[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

2020-07-13 Thread Amy Kwan via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG62f5ba624bfb: [PowerPC][Power10] Implement Test LSB by Byte 
Builtins in LLVM/Clang (authored by amyk).

Changed prior to commit:
  https://reviews.llvm.org/D82431?vs=274667=277646#toc

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; These test cases aims to test the builtins for the Power10 VSX vector
+; instructions introduced in ISA 3.1.
+
+declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i1)
+
+define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) {
+; CHECK-LABEL: test_vec_test_lsbb_all_ones:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xvtlsbb cr0, v2
+; CHECK-NEXT:mfocrf r3, 128
+; CHECK-NEXT:srwi r3, r3, 31
+; CHECK-NEXT:extsw r3, r3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 1)
+  ret i32 %0
+}
+
+define signext i32 @test_vec_test_lsbb_all_zeros(<16 x i8> %vuca) {
+; CHECK-LABEL: test_vec_test_lsbb_all_zeros:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xvtlsbb cr0, v2
+; CHECK-NEXT:mfocrf r3, 128
+; CHECK-NEXT:rlwinm r3, r3, 3, 31, 31
+; CHECK-NEXT:extsw r3, r3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 0)
+  ret i32 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -396,6 +396,25 @@
   let Inst{63} = XT{5};
 }
 
+// [PO BF / XO2 B XO BX /]
+class XX2_BF3_XO5_XB6_XO9 opcode, bits<5> xo2, bits<9> xo, dag OOL,
+  dag IOL, string asmstr, InstrItinClass itin,
+  list pattern>
+  : I {
+  bits<3> BF;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}   = BF;
+  let Inst{9-10}  = 0;
+  let Inst{11-15} = xo2;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}= XB{5};
+  let Inst{31}= 0;
+}
+
 multiclass MLS_DForm_R_SI34_RTA5_MEM_p opcode, dag OOL, dag IOL,
dag PCRel_IOL, string asmstr,
InstrItinClass itin> {
@@ -943,6 +962,9 @@
  [(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
 
+  def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
+"xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
+
   // The XFormMemOp flag for the following 8 instructions is set on
   // the instruction format.
   let mayLoad = 1, mayStore = 0 in {
@@ -960,8 +982,6 @@
   }
 }
 
-
-
 // Anonymous Patterns //
 let Predicates = [IsISA3_1] in {
   def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)),
@@ -972,6 +992,10 @@
 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
+  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, -1)),
+(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
+  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
+(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
 }
 
 let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1067,6 +1067,9 @@
   PowerPC_VSX_Intrinsic<"xxinsertw",[llvm_v4i32_ty],
 [llvm_v4i32_ty,llvm_v2i64_ty,llvm_i32_ty],
 [IntrNoMem]>;
+def int_ppc_vsx_xvtlsbb :
+  PowerPC_VSX_Intrinsic<"xvtlsbb", [llvm_i32_ty],
+[llvm_v16i8_ty, llvm_i1_ty], [IntrNoMem]>;
 def int_ppc_vsx_xxeval :
   PowerPC_VSX_Intrinsic<"xxeval", [llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_v2i64_ty,
Index:

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

2020-06-30 Thread Lei Huang via Phabricator via cfe-commits 
lei accepted this revision.
lei added a comment.

LGTM thx!


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[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

2020-06-30 Thread Amy Kwan via Phabricator via cfe-commits 
amyk updated this revision to Diff 274667.
amyk added a comment.

Update patch to:

- place MC tests in correct files


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
  llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

Index: llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
===
--- llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -357,3 +357,6 @@
 # CHECK-BE: vsrdbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x23,0x56]
 # CHECK-LE: vsrdbi 2, 3, 4, 5 # encoding: [0x56,0x23,0x43,0x10]
 vsrdbi 2, 3, 4, 5
+# CHECK-BE: xvtlsbb 1, 7  # encoding: [0xf0,0x82,0x3f,0x6c]
+# CHECK-LE: xvtlsbb 1, 7  # encoding: [0x6c,0x3f,0x82,0xf0]
+xvtlsbb 1, 7
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
===
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -230,3 +230,6 @@
 
 # CHECK: vsrdbi 2, 3, 4, 5
 0x10 0x43 0x23 0x56
+
+# CHECK: xvtlsbb 1, 7
+0xf0 0x82 0x3f 0x6c
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; These test cases aims to test the builtins for the Power10 VSX vector
+; instructions introduced in ISA 3.1.
+
+declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i1)
+
+define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) {
+; CHECK-LABEL: test_vec_test_lsbb_all_ones:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xvtlsbb cr0, v2
+; CHECK-NEXT:mfocrf r3, 128
+; CHECK-NEXT:srwi r3, r3, 31
+; CHECK-NEXT:extsw r3, r3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 1)
+  ret i32 %0
+}
+
+define signext i32 @test_vec_test_lsbb_all_zeros(<16 x i8> %vuca) {
+; CHECK-LABEL: test_vec_test_lsbb_all_zeros:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xvtlsbb cr0, v2
+; CHECK-NEXT:mfocrf r3, 128
+; CHECK-NEXT:rlwinm r3, r3, 3, 31, 31
+; CHECK-NEXT:extsw r3, r3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 0)
+  ret i32 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -356,6 +356,25 @@
   let Inst{63} = XT{5};
 }
 
+// [PO BF / XO2 B XO BX /]
+class XX2_BF3_XO5_XB6_XO9 opcode, bits<5> xo2, bits<9> xo, dag OOL,
+  dag IOL, string asmstr, InstrItinClass itin,
+  list pattern>
+  : I {
+  bits<3> BF;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}   = BF;
+  let Inst{9-10}  = 0;
+  let Inst{11-15} = xo2;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}= XB{5};
+  let Inst{31}= 0;
+}
+
 multiclass MLS_DForm_R_SI34_RTA5_MEM_p opcode, dag OOL, dag IOL,
dag PCRel_IOL, string asmstr,
InstrItinClass itin> {
@@ -809,6 +828,8 @@
  "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
  [(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
+   def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
+ "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
 }
 
 // Anonymous Patterns //
@@ -821,4 +842,8 @@
 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
+  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, -1)),
+(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
+  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
+(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
 }
Index:

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

2020-06-30 Thread Lei Huang via Phabricator via cfe-commits 
lei added a comment.

encoding tests need to be placed in corresponding `ppc64-encoding-ISA31*` files


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[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

2020-06-29 Thread Qing Shan Zhang via Phabricator via cfe-commits 
steven.zhang added inline comments.



Comment at: llvm/test/MC/Disassembler/PowerPC/vsx.txt:2
 # RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu -mcpu=pwr7 
| FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu \
+# RUN:   -mcpu=pwr10 | FileCheck %s --check-prefix=CHECK-P10

So, this is for bigendian, where is the little endian disassemble tests ...


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[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

2020-06-29 Thread Amy Kwan via Phabricator via cfe-commits 
amyk updated this revision to Diff 274239.
amyk added a comment.

Updated revision to:

- add the MC test cases into `vsx.s` and `vsx.txt`.
- create a test file called `builtins-ppc-p10vsx.ll` to place all Power10 VSX 
builtins tests.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
  llvm/test/MC/Disassembler/PowerPC/vsx.txt
  llvm/test/MC/PowerPC/vsx.s

Index: llvm/test/MC/PowerPC/vsx.s
===
--- llvm/test/MC/PowerPC/vsx.s
+++ llvm/test/MC/PowerPC/vsx.s
@@ -1001,3 +1001,10 @@
 # CHECK-BE: xvtstdcsp 63, 63, 34   # encoding: [0xf3,0xe2,0xfe,0xaf]
 # CHECK-LE: xvtstdcsp 63, 63, 34   # encoding: [0xaf,0xfe,0xe2,0xf3]
 xvtstdcsp 63, 63, 34
+
+# Power 10 Instructions:
+
+# Test LSB Byte by Byte
+# CHECK-BE: xvtlsbb 1, 7   # encoding: [0xf0,0x82,0x3f,0x6c]
+# CHECK-LE: xvtlsbb 1, 7   # encoding: [0x6c,0x3f,0x82,0xf0]
+xvtlsbb 1, 7
Index: llvm/test/MC/Disassembler/PowerPC/vsx.txt
===
--- llvm/test/MC/Disassembler/PowerPC/vsx.txt
+++ llvm/test/MC/Disassembler/PowerPC/vsx.txt
@@ -1,4 +1,6 @@
 # RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu \
+# RUN:   -mcpu=pwr10 | FileCheck %s --check-prefix=CHECK-P10
 
 # CHECK: lxsdx 7, 5, 31
 0x7c 0xe5 0xfc 0x98
@@ -874,3 +876,6 @@
 
 # CHECK: xvtstdcsp 63, 63, 34
 0xf3 0xe2 0xfe 0xaf
+
+# CHECK-P10: xvtlsbb 1, 7
+0xf0 0x82 0x3f 0x6c
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; These test cases aims to test the builtins for the Power10 VSX vector
+; instructions introduced in ISA 3.1.
+
+declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i1)
+
+define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) {
+; CHECK-LABEL: test_vec_test_lsbb_all_ones:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xvtlsbb cr0, v2
+; CHECK-NEXT:mfocrf r3, 128
+; CHECK-NEXT:srwi r3, r3, 31
+; CHECK-NEXT:extsw r3, r3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 1)
+  ret i32 %0
+}
+
+define signext i32 @test_vec_test_lsbb_all_zeros(<16 x i8> %vuca) {
+; CHECK-LABEL: test_vec_test_lsbb_all_zeros:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xvtlsbb cr0, v2
+; CHECK-NEXT:mfocrf r3, 128
+; CHECK-NEXT:rlwinm r3, r3, 3, 31, 31
+; CHECK-NEXT:extsw r3, r3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 0)
+  ret i32 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -177,6 +177,25 @@
   let Inst{31} = XT{5};
 }
 
+// [PO BF / XO2 B XO BX /]
+class XX2_BF3_XO5_XB6_XO9 opcode, bits<5> xo2, bits<9> xo, dag OOL,
+  dag IOL, string asmstr, InstrItinClass itin,
+  list pattern>
+  : I {
+  bits<3> BF;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}   = BF;
+  let Inst{9-10}  = 0;
+  let Inst{11-15} = xo2;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}= XB{5};
+  let Inst{31}= 0;
+}
+
 multiclass MLS_DForm_R_SI34_RTA5_MEM_p opcode, dag OOL, dag IOL,
dag PCRel_IOL, string asmstr,
InstrItinClass itin> {
@@ -552,6 +571,8 @@
  "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
  [(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
+   def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
+ "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
 }
 
 // Anonymous Patterns //
@@ -564,4 +585,8 @@
 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

2020-06-29 Thread Amy Kwan via Phabricator via cfe-commits 
amyk added a comment.

@lei Could you please take another look at this to see if this change is OK?


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[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

2020-06-26 Thread Lei Huang via Phabricator via cfe-commits 
lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

2020-06-26 Thread Amy Kwan via Phabricator via cfe-commits 
amyk updated this revision to Diff 273745.
amyk added a comment.

Updated to the correct indentation for the functions in `altivec.h`.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll
  llvm/test/MC/Disassembler/PowerPC/p10insts.txt
  llvm/test/MC/PowerPC/p10.s

Index: llvm/test/MC/PowerPC/p10.s
===
--- llvm/test/MC/PowerPC/p10.s
+++ llvm/test/MC/PowerPC/p10.s
@@ -33,3 +33,6 @@
 # CHECK-BE: vclrrb 1, 4, 3# encoding: [0x10,0x24,0x19,0xcd]
 # CHECK-LE: vclrrb 1, 4, 3# encoding: [0xcd,0x19,0x24,0x10]
 vclrrb 1, 4, 3
+# CHECK-BE: xvtlsbb 1, 7  # encoding: [0xf0,0x82,0x3f,0x6c]
+# CHECK-LE: xvtlsbb 1, 7  # encoding: [0x6c,0x3f,0x82,0xf0]
+xvtlsbb 1, 7
Index: llvm/test/MC/Disassembler/PowerPC/p10insts.txt
===
--- llvm/test/MC/Disassembler/PowerPC/p10insts.txt
+++ llvm/test/MC/Disassembler/PowerPC/p10insts.txt
@@ -30,3 +30,6 @@
 
 # CHECK: vclrrb 1, 4, 3
 0x10 0x24 0x19 0xcd
+
+# CHECK: xvtlsbb 1, 7
+0xf0 0x82 0x3f 0x6c
Index: llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; This test case aims to test the builtins for VSX vector instructions
+; on Power10.
+
+declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i1)
+
+define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) {
+; CHECK-LABEL: test_vec_test_lsbb_all_ones:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xvtlsbb cr0, v2
+; CHECK-NEXT:mfocrf r3, 128
+; CHECK-NEXT:srwi r3, r3, 31
+; CHECK-NEXT:extsw r3, r3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 1)
+  ret i32 %0
+}
+
+define signext i32 @test_vec_test_lsbb_all_zeros(<16 x i8> %vuca) {
+; CHECK-LABEL: test_vec_test_lsbb_all_zeros:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xvtlsbb cr0, v2
+; CHECK-NEXT:mfocrf r3, 128
+; CHECK-NEXT:rlwinm r3, r3, 3, 31, 31
+; CHECK-NEXT:extsw r3, r3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 0)
+  ret i32 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -177,6 +177,25 @@
   let Inst{31} = XT{5};
 }
 
+// [PO BF / XO2 B XO BX /]
+class XX2_BF3_XO5_XB6_XO9 opcode, bits<5> xo2, bits<9> xo, dag OOL,
+  dag IOL, string asmstr, InstrItinClass itin,
+  list pattern>
+  : I {
+  bits<3> BF;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}   = BF;
+  let Inst{9-10}  = 0;
+  let Inst{11-15} = xo2;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}= XB{5};
+  let Inst{31}= 0;
+}
+
 multiclass MLS_DForm_R_SI34_RTA5_MEM_p opcode, dag OOL, dag IOL,
dag PCRel_IOL, string asmstr,
InstrItinClass itin> {
@@ -552,6 +571,8 @@
  "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
  [(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
+   def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
+ "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
 }
 
 // Anonymous Patterns //
@@ -564,4 +585,8 @@
 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
+  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, -1)),
+(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
+  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
+(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
 }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

2020-06-23 Thread Amy Kwan via Phabricator via cfe-commits 
amyk created this revision.
amyk added reviewers: nemanjai, lei, saghir, hfinkel, power-llvm-team, PowerPC.
amyk added projects: LLVM, clang, PowerPC.
Herald added subscribers: shchenz, hiraditya.

This patch implements builtins for the following prototypes:

  int vec_test_lsbb_all_ones (vector unsigned char a);  
  int vec_test_lsbb_all_zeros (vector unsigned char a);  


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82431

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll
  llvm/test/MC/Disassembler/PowerPC/p10insts.txt
  llvm/test/MC/PowerPC/p10.s

Index: llvm/test/MC/PowerPC/p10.s
===
--- llvm/test/MC/PowerPC/p10.s
+++ llvm/test/MC/PowerPC/p10.s
@@ -33,3 +33,6 @@
 # CHECK-BE: vclrrb 1, 4, 3# encoding: [0x10,0x24,0x19,0xcd]
 # CHECK-LE: vclrrb 1, 4, 3# encoding: [0xcd,0x19,0x24,0x10]
 vclrrb 1, 4, 3
+# CHECK-BE: xvtlsbb 1, 7  # encoding: [0xf0,0x82,0x3f,0x6c]
+# CHECK-LE: xvtlsbb 1, 7  # encoding: [0x6c,0x3f,0x82,0xf0]
+xvtlsbb 1, 7
Index: llvm/test/MC/Disassembler/PowerPC/p10insts.txt
===
--- llvm/test/MC/Disassembler/PowerPC/p10insts.txt
+++ llvm/test/MC/Disassembler/PowerPC/p10insts.txt
@@ -30,3 +30,6 @@
 
 # CHECK: vclrrb 1, 4, 3
 0x10 0x24 0x19 0xcd
+
+# CHECK: xvtlsbb 1, 7
+0xf0 0x82 0x3f 0x6c
Index: llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; This test case aims to test the builtins for VSX vector instructions
+; on Power10.
+
+declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i1)
+
+define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) {
+; CHECK-LABEL: test_vec_test_lsbb_all_ones:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xvtlsbb cr0, v2
+; CHECK-NEXT:mfocrf r3, 128
+; CHECK-NEXT:srwi r3, r3, 31
+; CHECK-NEXT:extsw r3, r3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 1)
+  ret i32 %0
+}
+
+define signext i32 @test_vec_test_lsbb_all_zeros(<16 x i8> %vuca) {
+; CHECK-LABEL: test_vec_test_lsbb_all_zeros:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xvtlsbb cr0, v2
+; CHECK-NEXT:mfocrf r3, 128
+; CHECK-NEXT:rlwinm r3, r3, 3, 31, 31
+; CHECK-NEXT:extsw r3, r3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 0)
+  ret i32 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -177,6 +177,25 @@
   let Inst{31} = XT{5};
 }
 
+// [PO BF / XO2 B XO BX /]
+class XX2_BF3_XO5_XB6_XO9 opcode, bits<5> xo2, bits<9> xo, dag OOL,
+  dag IOL, string asmstr, InstrItinClass itin,
+  list pattern>
+  : I {
+  bits<3> BF;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}   = BF;
+  let Inst{9-10}  = 0;
+  let Inst{11-15} = xo2;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}= XB{5};
+  let Inst{31}= 0;
+}
+
 multiclass MLS_DForm_R_SI34_RTA5_MEM_p opcode, dag OOL, dag IOL,
dag PCRel_IOL, string asmstr,
InstrItinClass itin> {
@@ -552,6 +571,8 @@
  "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
  [(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
+   def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
+ "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
 }
 
 // Anonymous Patterns //
@@ -564,4 +585,8 @@
 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
+  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, -1)),
+(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
+  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
+(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
 }