[PATCH] D82501: [sve][acle] Add reinterpret intrinsics for brain float.
fpetrogalli added a comment. Reverted in https://github.com/llvm/llvm-project/commit/ff5ccf258e297df29f32d6b5e4fa0a7b95c44f9c Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82501/new/ https://reviews.llvm.org/D82501 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82501: [sve][acle] Add reinterpret intrinsics for brain float.
fpetrogalli added a comment. Ops, I accidentally removed the C tests... I'll revert, add the tests and recommit. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82501/new/ https://reviews.llvm.org/D82501 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82501: [sve][acle] Add reinterpret intrinsics for brain float.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa15722c5ce47: [sve][acle] Add reinterpret intrinsics for
brain float. (authored by fpetrogalli).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82501/new/
https://reviews.llvm.org/D82501
Files:
clang/utils/TableGen/SveEmitter.cpp
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-bitcast.ll
Index: llvm/test/CodeGen/AArch64/sve-bitcast.ll
===
--- llvm/test/CodeGen/AArch64/sve-bitcast.ll
+++ llvm/test/CodeGen/AArch64/sve-bitcast.ll
@@ -340,3 +340,118 @@
%bc = bitcast %v to
ret %bc
}
+
+define @bitcast_bfloat_to_i8( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i16( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i32( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i64( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_half( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_half:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_float( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_float:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_double( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_double:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i8_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_i8_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i16_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_i16_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i32_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_i32_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i64_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_i64_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_half_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_half_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_float_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_float_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_double_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_double_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+; +bf16 is required for the bfloat version.
+attributes #0 = { "target-features"="+sve,+bf16" }
Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1464,7 +1464,6 @@
def : Pat<(nxv8f16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8f16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8f16 ZPR:$src)>;
-def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8f16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
@@ -1485,6 +1484,24 @@
def : Pat<(nxv2f64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2f64 ZPR:$src)>;
}
+ let Predicates = [IsLE, HasSVE, HasBF16] in {
+def : Pat<(nxv8bf16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv8f16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+
+def : Pat<(nxv16i8 (bitconvert (nxv8bf16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
+def : Pat<(nxv8i16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8i16 ZPR:$src)>;
+def : Pat<(nxv4i32 (bitconvert (nxv8bf16 ZPR:$src))), (nxv4i32 ZPR:$src)>;
+def : Pat<(nxv2i64 (bitconvert (nxv8bf16 ZPR:$src))),
[PATCH] D82501: [sve][acle] Add reinterpret intrinsics for brain float.
fpetrogalli updated this revision to Diff 273737.
fpetrogalli marked an inline comment as done.
fpetrogalli added a comment.
I removed the duplicate tests.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82501/new/
https://reviews.llvm.org/D82501
Files:
clang/utils/TableGen/SveEmitter.cpp
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-bitcast.ll
Index: llvm/test/CodeGen/AArch64/sve-bitcast.ll
===
--- llvm/test/CodeGen/AArch64/sve-bitcast.ll
+++ llvm/test/CodeGen/AArch64/sve-bitcast.ll
@@ -340,3 +340,118 @@
%bc = bitcast %v to
ret %bc
}
+
+define @bitcast_bfloat_to_i8( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i16( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i32( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i64( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_half( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_half:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_float( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_float:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_double( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_double:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i8_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_i8_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i16_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_i16_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i32_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_i32_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i64_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_i64_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_half_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_half_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_float_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_float_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_double_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_double_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+; +bf16 is required for the bfloat version.
+attributes #0 = { "target-features"="+sve,+bf16" }
Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1464,7 +1464,6 @@
def : Pat<(nxv8f16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8f16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8f16 ZPR:$src)>;
-def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8f16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
@@ -1485,6 +1484,24 @@
def : Pat<(nxv2f64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2f64 ZPR:$src)>;
}
+ let Predicates = [IsLE, HasSVE, HasBF16] in {
+def : Pat<(nxv8bf16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv8f16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+
+def : Pat<(nxv16i8 (bitconvert (nxv8bf16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
+def : Pat<(nxv8i16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8i16 ZPR:$src)>;
+def : Pat<(nxv4i32 (bitconvert (nxv8bf16 ZPR:$src))), (nxv4i32 ZPR:$src)>;
+def : Pat<(nxv2i64 (bitconvert (nxv8bf16 ZPR:$src))), (nxv2i64 ZPR:$src)>;
+def :
[PATCH] D82501: [sve][acle] Add reinterpret intrinsics for brain float.
fpetrogalli marked 2 inline comments as done.
fpetrogalli added inline comments.
Comment at: llvm/test/CodeGen/AArch64/sve-bitcast-bfloat.ll:8
+
+define @bitcast_bfloat_to_i8( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_i8:
david-arm wrote:
> Aren't these tests all duplicates of ones in
> llvm/test/CodeGen/AArch64/sve-bitcast.ll? Looks like you can remove this file
> completely.
(facepalm). yes, I remember thinking "I have to remove them before updating the
patch", and then I forgot... I will do it before submitting. Thank you for
pointing this out.
Repository:
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[PATCH] D82501: [sve][acle] Add reinterpret intrinsics for brain float.
david-arm accepted this revision.
david-arm added a comment.
This revision is now accepted and ready to land.
Can you remove the duplicate tests before submitting? Otherwise LGTM!
Comment at: llvm/test/CodeGen/AArch64/sve-bitcast-bfloat.ll:8
+
+define @bitcast_bfloat_to_i8( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_i8:
Aren't these tests all duplicates of ones in
llvm/test/CodeGen/AArch64/sve-bitcast.ll? Looks like you can remove this file
completely.
Repository:
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[PATCH] D82501: [sve][acle] Add reinterpret intrinsics for brain float.
fpetrogalli updated this revision to Diff 273399.
fpetrogalli marked an inline comment as done.
fpetrogalli added a comment.
@david-arm, at the end I decided to add the `ASM-NOT` test, it was easy and
came for free.
Also, I have moved the IR tests in the file with all other bitcasts, using a
funcion attribute to enable the bf16 feature only for those functions that deal
with bfloats.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82501/new/
https://reviews.llvm.org/D82501
Files:
clang/utils/TableGen/SveEmitter.cpp
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-bitcast-bfloat.ll
llvm/test/CodeGen/AArch64/sve-bitcast.ll
Index: llvm/test/CodeGen/AArch64/sve-bitcast.ll
===
--- llvm/test/CodeGen/AArch64/sve-bitcast.ll
+++ llvm/test/CodeGen/AArch64/sve-bitcast.ll
@@ -340,3 +340,118 @@
%bc = bitcast %v to
ret %bc
}
+
+define @bitcast_bfloat_to_i8( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i16( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i32( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i64( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_half( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_half:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_float( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_float:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_double( %v) #0 {
+; CHECK-LABEL: bitcast_bfloat_to_double:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i8_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_i8_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i16_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_i16_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i32_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_i32_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i64_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_i64_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_half_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_half_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_float_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_float_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_double_to_bfloat( %v) #0 {
+; CHECK-LABEL: bitcast_double_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+; +bf16 is required for the bfloat version.
+attributes #0 = { "target-features"="+sve,+bf16" }
Index: llvm/test/CodeGen/AArch64/sve-bitcast-bfloat.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-bitcast-bfloat.ll
@@ -0,0 +1,119 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s 2>%t | FileCheck %s
+; RUN: not --crash llc -mtriple=aarch64_be -mattr=+sve,+bf16 < %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; WARN-NOT: warning
+
+define @bitcast_bfloat_to_i8( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i16( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i32( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i64( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_half( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_half:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_float( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_float:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc =
[PATCH] D82501: [sve][acle] Add reinterpret intrinsics for brain float.
fpetrogalli marked 2 inline comments as done. fpetrogalli added inline comments. Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c:5 + +#include + david-arm wrote: > Hi @fpetrogalli, in the same way that you asked @kmclaughlin if she could add > the ASM-NOT check line in her patch, are you able to do that here? You'd need > to add an additional RUN line though to compile to assembly. Don't worry if > it's not possible though! It is possible, but my understanding is that we anyway decided to do this work as a separate patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82501/new/ https://reviews.llvm.org/D82501 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82501: [sve][acle] Add reinterpret intrinsics for brain float.
david-arm added inline comments. Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c:5 + +#include + Hi @fpetrogalli, in the same way that you asked @kmclaughlin if she could add the ASM-NOT check line in her patch, are you able to do that here? You'd need to add an additional RUN line though to compile to assembly. Don't worry if it's not possible though! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82501/new/ https://reviews.llvm.org/D82501 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82501: [sve][acle] Add reinterpret intrinsics for brain float.
fpetrogalli created this revision.
fpetrogalli added reviewers: kmclaughlin, efriedma, ctetreau, sdesmalen,
david-arm.
Herald added subscribers: llvm-commits, cfe-commits, psnobl, rkruppe,
hiraditya, tschuett.
Herald added projects: clang, LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D82501
Files:
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c
clang/utils/TableGen/SveEmitter.cpp
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-bitcast-bfloat.ll
Index: llvm/test/CodeGen/AArch64/sve-bitcast-bfloat.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-bitcast-bfloat.ll
@@ -0,0 +1,119 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s 2>%t | FileCheck %s
+; RUN: not --crash llc -mtriple=aarch64_be -mattr=+sve,+bf16 < %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; WARN-NOT: warning
+
+define @bitcast_bfloat_to_i8( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i16( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i32( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_i64( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_half( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_half:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_float( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_float:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_bfloat_to_double( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_double:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i8_to_bfloat( %v) {
+; CHECK-LABEL: bitcast_i8_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i16_to_bfloat( %v) {
+; CHECK-LABEL: bitcast_i16_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i32_to_bfloat( %v) {
+; CHECK-LABEL: bitcast_i32_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_i64_to_bfloat( %v) {
+; CHECK-LABEL: bitcast_i64_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_half_to_bfloat( %v) {
+; CHECK-LABEL: bitcast_half_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_float_to_bfloat( %v) {
+; CHECK-LABEL: bitcast_float_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
+define @bitcast_double_to_bfloat( %v) {
+; CHECK-LABEL: bitcast_double_to_bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ret
+ %bc = bitcast %v to
+ ret %bc
+}
+
Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1435,7 +1435,6 @@
def : Pat<(nxv8f16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8f16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8f16 ZPR:$src)>;
-def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8f16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
@@ -1456,6 +1455,24 @@
def : Pat<(nxv2f64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2f64 ZPR:$src)>;
}
+ let Predicates = [IsLE, HasSVE, HasBF16] in {
+def : Pat<(nxv8bf16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv8f16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+
+def : Pat<(nxv16i8 (bitconvert (nxv8bf16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
+def : Pat<(nxv8i16 (bitconvert
