[PATCH] D89102: [X86] Add HRESET instruction.

2020-10-12 Thread Pengfei Wang via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG412cdcf2edf2: [X86] Add HRESET instruction. (authored by 
pengfei).

Changed prior to commit:
  https://reviews.llvm.org/D89102?vs=297402=297732#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89102/new/

https://reviews.llvm.org/D89102

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/hresetintrin.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/x86-hreset-intrin.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -2014,3 +2014,7 @@
 // CHECK: tdcall
 // CHECK: encoding: [0x66,0x0f,0x01,0xcc]
 tdcall
+
+// CHECK: hreset
+// CHECK: encoding: [0xf3,0x0f,0x3a,0xf0,0xc0,0x01]
+hreset $1
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10891,4 +10891,8 @@
 
 // CHECK: tdcall
 // CHECK: encoding: [0x66,0x0f,0x01,0xcc]
-tdcall
\ No newline at end of file
+tdcall
+
+// CHECK: hreset
+// CHECK: encoding: [0xf3,0x0f,0x3a,0xf0,0xc0,0x01]
+hreset $1
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -712,3 +712,6 @@
 
 #CHECK: tdcall
 0x66 0x0f 0x01 0xcc
+
+# CHECK: hreset $1
+0xf3 0x0f 0x3a 0xf0 0xc0 0x01
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -1000,3 +1000,6 @@
 
 #CHECK: tdcall
 0x66 0x0f 0x01 0xcc
+
+# CHECK: hreset $1
+0xf3 0x0f 0x3a 0xf0 0xc0 0x01
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -401,6 +401,9 @@
   /// Processor support key locker wide instructions
   bool HasWIDEKL = false;
 
+  /// Processor supports HRESET instruction
+  bool HasHRESET = false;
+
   /// Processor supports SERIALIZE instruction
   bool HasSERIALIZE = false;
 
@@ -736,6 +739,7 @@
   bool hasENQCMD() const { return HasENQCMD; }
   bool hasKL() const { return HasKL; }
   bool hasWIDEKL() const { return HasWIDEKL; }
+  bool hasHRESET() const { return HasHRESET; }
   bool hasSERIALIZE() const { return HasSERIALIZE; }
   bool hasTSXLDTRK() const { return HasTSXLDTRK; }
   bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
Index: llvm/lib/Target/X86/X86InstrInfo.td
===
--- llvm/lib/Target/X86/X86InstrInfo.td
+++ llvm/lib/Target/X86/X86InstrInfo.td
@@ -972,6 +972,7 @@
 def HasENQCMD: Predicate<"Subtarget->hasENQCMD()">;
 def HasKL: Predicate<"Subtarget->hasKL()">;
 def HasWIDEKL: Predicate<"Subtarget->hasWIDEKL()">;
+def HasHRESET: Predicate<"Subtarget->hasHRESET()">;
 def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">;
 def HasTSXLDTRK  : Predicate<"Subtarget->hasTSXLDTRK()">;
 def HasAMXTILE   : Predicate<"Subtarget->hasAMXTILE()">;
@@ -2913,6 +2914,13 @@
 def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>;
 def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>;
 
+//===--===//
+// HRESET Instruction
+//
+let Uses = [EAX], SchedRW = [WriteSystem] in
+  def HRESET : Ii8<0xF0, MRM_C0, (outs), (ins i32u8imm:$imm), "hreset\t$imm", []>,
+   Requires<[HasHRESET]>, TAXS;
+
 //===--===//
 // SERIALIZE Instruction
 //
Index: llvm/lib/Target/X86/X86InstrFormats.td
===
--- llvm/lib/Target/X86/X86InstrFormats.td
+++ llvm/lib/Target/X86/X86InstrFormats.td
@@ -216,6 +216,7 @@
 class TAPS : TA { Prefix OpPrefix = PS;

[PATCH] D89102: [X86] Add HRESET instruction.

2020-10-12 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

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[PATCH] D89102: [X86] Add HRESET instruction.

2020-10-10 Thread Pengfei Wang via Phabricator via cfe-commits 
pengfei updated this revision to Diff 297402.
pengfei added a comment.

Rebased.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89102/new/

https://reviews.llvm.org/D89102

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/hresetintrin.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/x86-hreset-intrin.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -2014,3 +2014,7 @@
 // CHECK: tdcall
 // CHECK: encoding: [0x66,0x0f,0x01,0xcc]
 tdcall
+
+// CHECK: hreset
+// CHECK: encoding: [0xf3,0x0f,0x3a,0xf0,0xc0,0x01]
+hreset $1
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10891,4 +10891,8 @@
 
 // CHECK: tdcall
 // CHECK: encoding: [0x66,0x0f,0x01,0xcc]
-tdcall
\ No newline at end of file
+tdcall
+
+// CHECK: hreset
+// CHECK: encoding: [0xf3,0x0f,0x3a,0xf0,0xc0,0x01]
+hreset $1
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -712,3 +712,6 @@
 
 #CHECK: tdcall
 0x66 0x0f 0x01 0xcc
+
+# CHECK: hreset $1
+0xf3 0x0f 0x3a 0xf0 0xc0 0x01
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -1000,3 +1000,6 @@
 
 #CHECK: tdcall
 0x66 0x0f 0x01 0xcc
+
+# CHECK: hreset $1
+0xf3 0x0f 0x3a 0xf0 0xc0 0x01
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -401,6 +401,9 @@
   /// Processor support key locker wide instructions
   bool HasWIDEKL = false;
 
+  /// Processor supports HRESET instruction
+  bool HasHRESET = false;
+
   /// Processor supports SERIALIZE instruction
   bool HasSERIALIZE = false;
 
@@ -736,6 +739,7 @@
   bool hasENQCMD() const { return HasENQCMD; }
   bool hasKL() const { return HasKL; }
   bool hasWIDEKL() const { return HasWIDEKL; }
+  bool hasHRESET() const { return HasHRESET; }
   bool hasSERIALIZE() const { return HasSERIALIZE; }
   bool hasTSXLDTRK() const { return HasTSXLDTRK; }
   bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
Index: llvm/lib/Target/X86/X86InstrInfo.td
===
--- llvm/lib/Target/X86/X86InstrInfo.td
+++ llvm/lib/Target/X86/X86InstrInfo.td
@@ -971,6 +971,7 @@
 def HasENQCMD: Predicate<"Subtarget->hasENQCMD()">;
 def HasKL: Predicate<"Subtarget->hasKL()">;
 def HasWIDEKL: Predicate<"Subtarget->hasWIDEKL()">;
+def HasHRESET: Predicate<"Subtarget->hasHRESET()">;
 def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">;
 def HasTSXLDTRK  : Predicate<"Subtarget->hasTSXLDTRK()">;
 def HasAMXTILE   : Predicate<"Subtarget->hasAMXTILE()">;
@@ -2911,6 +2912,13 @@
 def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>;
 def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>;
 
+//===--===//
+// HRESET Instruction
+//
+let Uses = [EAX], SchedRW = [WriteSystem] in
+  def HRESET : Ii8<0xF0, MRM_C0, (outs), (ins i32u8imm:$imm), "hreset\t$imm", []>,
+   Requires<[HasHRESET]>, TAXS;
+
 //===--===//
 // SERIALIZE Instruction
 //
Index: llvm/lib/Target/X86/X86InstrFormats.td
===
--- llvm/lib/Target/X86/X86InstrFormats.td
+++ llvm/lib/Target/X86/X86InstrFormats.td
@@ -216,6 +216,7 @@
 class TAPS : TA { Prefix OpPrefix = PS; }
 class TAPD : TA { Prefix OpPrefix = PD; }
 class TAXD : TA { Prefix OpPrefix = XD; }
+class TAXS : TA { Prefix OpPrefix = XS; }
 class VEX{ Encoding OpEnc = EncVEX; }
 class VEX_W{ bit HasVEX_W = 1; }

[PATCH] D89102: [X86] Add HRESET instruction.

2020-10-09 Thread Pengfei Wang via Phabricator via cfe-commits 
pengfei updated this revision to Diff 297234.
pengfei added a comment.

Address review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89102/new/

https://reviews.llvm.org/D89102

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/hresetintrin.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/x86-hreset-intrin.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -2014,3 +2014,7 @@
 // CHECK: tdcall
 // CHECK: encoding: [0x66,0x0f,0x01,0xcc]
 tdcall
+
+// CHECK: hreset
+// CHECK: encoding: [0xf3,0x0f,0x3a,0xf0,0xc0,0x01]
+hreset $1
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10891,4 +10891,8 @@
 
 // CHECK: tdcall
 // CHECK: encoding: [0x66,0x0f,0x01,0xcc]
-tdcall
\ No newline at end of file
+tdcall
+
+// CHECK: hreset
+// CHECK: encoding: [0xf3,0x0f,0x3a,0xf0,0xc0,0x01]
+hreset $1
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -712,3 +712,6 @@
 
 #CHECK: tdcall
 0x66 0x0f 0x01 0xcc
+
+# CHECK: hreset $1
+0xf3 0x0f 0x3a 0xf0 0xc0 0x01
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -1000,3 +1000,6 @@
 
 #CHECK: tdcall
 0x66 0x0f 0x01 0xcc
+
+# CHECK: hreset $1
+0xf3 0x0f 0x3a 0xf0 0xc0 0x01
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -401,6 +401,9 @@
   /// Processor support key locker wide instructions
   bool HasWIDEKL = false;
 
+  /// Processor supports HRESET instruction
+  bool HasHRESET = false;
+
   /// Processor supports SERIALIZE instruction
   bool HasSERIALIZE = false;
 
@@ -736,6 +739,7 @@
   bool hasENQCMD() const { return HasENQCMD; }
   bool hasKL() const { return HasKL; }
   bool hasWIDEKL() const { return HasWIDEKL; }
+  bool hasHRESET() const { return HasHRESET; }
   bool hasSERIALIZE() const { return HasSERIALIZE; }
   bool hasTSXLDTRK() const { return HasTSXLDTRK; }
   bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
Index: llvm/lib/Target/X86/X86InstrInfo.td
===
--- llvm/lib/Target/X86/X86InstrInfo.td
+++ llvm/lib/Target/X86/X86InstrInfo.td
@@ -971,6 +971,7 @@
 def HasENQCMD: Predicate<"Subtarget->hasENQCMD()">;
 def HasKL: Predicate<"Subtarget->hasKL()">;
 def HasWIDEKL: Predicate<"Subtarget->hasWIDEKL()">;
+def HasHRESET: Predicate<"Subtarget->hasHRESET()">;
 def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">;
 def HasTSXLDTRK  : Predicate<"Subtarget->hasTSXLDTRK()">;
 def HasAMXTILE   : Predicate<"Subtarget->hasAMXTILE()">;
@@ -2911,6 +2912,13 @@
 def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>;
 def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>;
 
+//===--===//
+// HRESET Instruction
+//
+let Uses = [EAX], SchedRW = [WriteSystem] in
+  def HRESET : Ii8<0xF0, MRM_C0, (outs), (ins i32u8imm:$imm), "hreset\t$imm", []>,
+   Requires<[HasHRESET]>, TAXS;
+
 //===--===//
 // SERIALIZE Instruction
 //
Index: llvm/lib/Target/X86/X86InstrFormats.td
===
--- llvm/lib/Target/X86/X86InstrFormats.td
+++ llvm/lib/Target/X86/X86InstrFormats.td
@@ -216,6 +216,7 @@
 class TAPS : TA { Prefix OpPrefix = PS; }
 class TAPD : TA { Prefix OpPrefix = PD; }
 class TAXD : TA { Prefix OpPrefix = XD; }
+class TAXS : TA { Prefix OpPrefix = XS; }
 class VEX{ Encoding OpEnc = EncVEX; }
 class VEX_W{ bit

[PATCH] D89102: [X86] Add HRESET instruction.

2020-10-09 Thread Pengfei Wang via Phabricator via cfe-commits 
pengfei marked an inline comment as done.
pengfei added a comment.

Thanks for the review.


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[PATCH] D89102: [X86] Add HRESET instruction.

2020-10-09 Thread Simon Pilgrim via Phabricator via cfe-commits 
RKSimon added a comment.

Please can you add a mention in the 12.0 release notes?




Comment at: llvm/lib/Target/X86/X86InstrInfo.td:2920
+  def HRESET : Ii8<0xF0, MRM_C0, (outs), (ins i32u8imm:$imm), "hreset\t$imm", 
[]>,
+   Requires<[HasHRESET]>, TAXS;
+

Put this under the WriteSystem SchedRW class? 


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[PATCH] D89102: [X86] Add HRESET instruction.

2020-10-09 Thread Pengfei Wang via Phabricator via cfe-commits 
pengfei created this revision.
pengfei added reviewers: craig.topper, RKSimon, LuoYuanke.
Herald added subscribers: llvm-commits, cfe-commits, dang, hiraditya, mgorny.
Herald added projects: clang, LLVM.
pengfei requested review of this revision.

For more details about these instructions, please refer to the latest ISE 
document: 
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D89102

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/hresetintrin.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/x86-hreset-intrin.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -2014,3 +2014,7 @@
 // CHECK: tdcall
 // CHECK: encoding: [0x66,0x0f,0x01,0xcc]
 tdcall
+
+// CHECK: hreset
+// CHECK: encoding: [0xf3,0x0f,0x3a,0xf0,0xc0,0x01]
+hreset $1
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10891,4 +10891,8 @@
 
 // CHECK: tdcall
 // CHECK: encoding: [0x66,0x0f,0x01,0xcc]
-tdcall
\ No newline at end of file
+tdcall
+
+// CHECK: hreset
+// CHECK: encoding: [0xf3,0x0f,0x3a,0xf0,0xc0,0x01]
+hreset $1
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -712,3 +712,6 @@
 
 #CHECK: tdcall
 0x66 0x0f 0x01 0xcc
+
+# CHECK: hreset $1
+0xf3 0x0f 0x3a 0xf0 0xc0 0x01
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -1000,3 +1000,6 @@
 
 #CHECK: tdcall
 0x66 0x0f 0x01 0xcc
+
+# CHECK: hreset $1
+0xf3 0x0f 0x3a 0xf0 0xc0 0x01
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -401,6 +401,9 @@
   /// Processor support key locker wide instructions
   bool HasWIDEKL = false;
 
+  /// Processor supports HRESET instruction
+  bool HasHRESET = false;
+
   /// Processor supports SERIALIZE instruction
   bool HasSERIALIZE = false;
 
@@ -736,6 +739,7 @@
   bool hasENQCMD() const { return HasENQCMD; }
   bool hasKL() const { return HasKL; }
   bool hasWIDEKL() const { return HasWIDEKL; }
+  bool hasHRESET() const { return HasHRESET; }
   bool hasSERIALIZE() const { return HasSERIALIZE; }
   bool hasTSXLDTRK() const { return HasTSXLDTRK; }
   bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
Index: llvm/lib/Target/X86/X86InstrInfo.td
===
--- llvm/lib/Target/X86/X86InstrInfo.td
+++ llvm/lib/Target/X86/X86InstrInfo.td
@@ -971,6 +971,7 @@
 def HasENQCMD: Predicate<"Subtarget->hasENQCMD()">;
 def HasKL: Predicate<"Subtarget->hasKL()">;
 def HasWIDEKL: Predicate<"Subtarget->hasWIDEKL()">;
+def HasHRESET: Predicate<"Subtarget->hasHRESET()">;
 def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">;
 def HasTSXLDTRK  : Predicate<"Subtarget->hasTSXLDTRK()">;
 def HasAMXTILE   : Predicate<"Subtarget->hasAMXTILE()">;
@@ -2911,6 +2912,13 @@
 def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>;
 def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>;
 
+//===--===//
+// HRESET Instruction
+//
+let Uses = [EAX] in
+  def HRESET : Ii8<0xF0, MRM_C0, (outs), (ins i32u8imm:$imm), "hreset\t$imm", []>,
+   Requires<[HasHRESET]>, TAXS;
+
 //===--===//
 // SERIALIZE Instruction
 //
Index: llvm/lib/Target/X86/X86InstrFormats.td
===
--- llvm/lib/Target/X86/X86InstrFormats.td
+++ llvm/lib/Target/X86/X86InstrFormats.td
@@ -216,6 +216,7 @@
 class TAPS