[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG776f92e06759: [X86] Add support for vex, vex2, vex3, and
evex for MASM (authored by LiuChen3).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D90441
Files:
clang/lib/AST/Stmt.cpp
clang/test/CodeGen/X86/ms-inline-asm-prefix.c
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3064,7 +3064,26 @@
}
continue;
}
+// Parse MASM style pseudo prefixes.
+if (isParsingMSInlineAsm()) {
+ if (Name.equals_lower("vex"))
+ForcedVEXEncoding = VEXEncoding_VEX;
+ else if (Name.equals_lower("vex2"))
+ForcedVEXEncoding = VEXEncoding_VEX2;
+ else if (Name.equals_lower("vex3"))
+ForcedVEXEncoding = VEXEncoding_VEX3;
+ else if (Name.equals_lower("evex"))
+ForcedVEXEncoding = VEXEncoding_EVEX;
+ if (ForcedVEXEncoding != VEXEncoding_Default) {
+if (getLexer().isNot(AsmToken::Identifier))
+ return Error(Parser.getTok().getLoc(), "Expected identifier");
+// FIXME: The mnemonic won't match correctly if its not in lower case.
+Name = Parser.getTok().getString();
+NameLoc = Parser.getTok().getLoc();
+Parser.Lex();
+ }
+}
break;
}
@@ -4370,10 +4389,16 @@
MCInst Inst;
- // If VEX3 encoding is forced, we need to pass the USE_VEX3 flag to the
- // encoder.
- if (ForcedVEXEncoding == VEXEncoding_VEX3)
+ // If VEX/EVEX encoding is forced, we need to pass the USE_* flag to the
+ // encoder and printer.
+ if (ForcedVEXEncoding == VEXEncoding_VEX)
+Prefixes |= X86::IP_USE_VEX;
+ else if (ForcedVEXEncoding == VEXEncoding_VEX2)
+Prefixes |= X86::IP_USE_VEX2;
+ else if (ForcedVEXEncoding == VEXEncoding_VEX3)
Prefixes |= X86::IP_USE_VEX3;
+ else if (ForcedVEXEncoding == VEXEncoding_EVEX)
+Prefixes |= X86::IP_USE_EVEX;
// Set encoded flags for {disp8} and {disp32}.
if (ForcedDispEncoding == DispEncoding_Disp8)
Index: clang/test/CodeGen/X86/ms-inline-asm-prefix.c
===
--- /dev/null
+++ clang/test/CodeGen/X86/ms-inline-asm-prefix.c
@@ -0,0 +1,14 @@
+// REQUIRES: x86-registered-target
+// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-windows-msvc -target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl -fasm-blocks -mllvm -x86-asm-syntax=intel -S -emit-llvm -o - | FileCheck %s -check-prefix=INTEL
+// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-windows-msvc -target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl -fasm-blocks -mllvm -x86-asm-syntax=att -S -emit-llvm -o - | FileCheck %s -check-prefix=ATT
+
+void check_inline_prefix(void) {
+ __asm {
+// INTEL: call void asm sideeffect inteldialect "{vex} vcvtps2pd xmm0, xmm1\0A\09{vex2} vcvtps2pd xmm0, xmm1\0A\09{vex3} vcvtps2pd xmm0, xmm1\0A\09{evex} vcvtps2pd xmm0, xmm1", "~{xmm0},~{dirflag},~{fpsr},~{flags}"()
+// ATT: call void asm sideeffect inteldialect "{vex} vcvtps2pd xmm0, xmm1\0A\09{vex2} vcvtps2pd xmm0, xmm1\0A\09{vex3} vcvtps2pd xmm0, xmm1\0A\09{evex} vcvtps2pd xmm0, xmm1", "~{xmm0},~{dirflag},~{fpsr},~{flags}"()
+vex vcvtps2pd xmm0, xmm1
+vex2 vcvtps2pd xmm0, xmm1
+vex3 vcvtps2pd xmm0, xmm1
+evex vcvtps2pd xmm0, xmm1
+ }
+}
Index: clang/lib/AST/Stmt.cpp
===
--- clang/lib/AST/Stmt.cpp
+++ clang/lib/AST/Stmt.cpp
@@ -791,7 +791,27 @@
/// Assemble final IR asm string (MS-style).
std::string MSAsmStmt::generateAsmString(const ASTContext ) const {
// FIXME: This needs to be translated into the IR string representation.
- return std::string(AsmStr);
+ SmallVector Pieces;
+ AsmStr.split(Pieces, "\n\t");
+ std::string MSAsmString;
+ for (size_t I = 0, E = Pieces.size(); I < E; ++I) {
+StringRef Instruction = Pieces[I];
+// For vex/vex2/vex3/evex masm style prefix, convert it to att style
+// since we don't support masm style prefix in backend.
+if (Instruction.startswith("vex "))
+ MSAsmString += '{' + Instruction.substr(0, 3).str() + '}' +
+ Instruction.substr(3).str();
+else if (Instruction.startswith("vex2 ") ||
+ Instruction.startswith("vex3 ") || Instruction.startswith("evex "))
+ MSAsmString += '{' + Instruction.substr(0, 4).str() + '}' +
+ Instruction.substr(4).str();
+else
+ MSAsmString += Instruction.str();
+// If this is not the last instruction, adding back the '\n\t'.
+if (I < E - 1)
+ MSAsmString += "\n\t";
+ }
+ return
[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
pengfei accepted this revision. pengfei added a comment. This revision is now accepted and ready to land. LGTM. Thanks. You'd better wait one or two days to see if other people objects. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D90441/new/ https://reviews.llvm.org/D90441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
LiuChen3 marked an inline comment as done.
LiuChen3 added a comment.
> It allows more than two, right? like `{vex}{vex2}{vex3} instruction`. I think
> it should be a bug for att.
Yes, My previous statement is incorrect, it should be ‘two more’. Thanks for
your correction.
We might need another patch to fix it.
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3079
+ if (ForcedVEXEncoding != VEXEncoding_Default) {
+if (getLexer().isNot(AsmToken::Identifier))
+ return Error(Parser.getTok().getLoc(), "Expected identifier");
pengfei wrote:
> Do you need to eat the prefix here?
No. The prefix has been eat.
For example: vex vcvtps2pd xmm0, xmm1 .
Current token is 'vex' and the rest is 'vcvtps2pd xmm0, xmm1'. 'vcvtps2pd' is
the next token which will be eat in line 3082.
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[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
pengfei added a comment.
> 2. Delete IsPrefix parameter, and delete 'break', so that we won't check
> prefix again. I am not sure if this is right. Att format can allow two prefix
> and using the last one as the finally encoding prefix. I think this may not
> be the original intention of the design.
It allows more than two, right? like `{vex}{vex2}{vex3} instruction`. I think
it should be a bug for att.
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3079
+ if (ForcedVEXEncoding != VEXEncoding_Default) {
+if (getLexer().isNot(AsmToken::Identifier))
+ return Error(Parser.getTok().getLoc(), "Expected identifier");
Do you need to eat the prefix here?
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[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
LiuChen3 marked an inline comment as done.
LiuChen3 added a comment.
> 2. Delete IsPrefix parameter, and delete 'break'
It should be 'continue'. Sorry for this mistake.
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3083
+ }
+ if (IsPrefix) {
+NameLoc = Parser.getTok().getLoc();
pengfei wrote:
> You just need to check `ForcedVEXEncoding != VEXEncoding_Default`.
I think this is better. Multi vex/evex prefix doesn't make sense.
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3084
+ if (IsPrefix) {
+NameLoc = Parser.getTok().getLoc();
+if (getLexer().isNot(AsmToken::Identifier))
pengfei wrote:
> Unused assignment. It may suppose to be used on line 3086.
This would be used later. However, this should only be updated when there is
prefix. I put it in wrong place.
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[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
LiuChen3 updated this revision to Diff 305959.
LiuChen3 added a comment.
1. Check prefix, ignoring case
2. Delete IsPrefix parameter, and delete 'break', so that we won't check prefix
again. I am not sure if this is right. Att format can allow two prefix and
using the last one as the finally encoding prefix. I think this may not be the
original intention of the design.
3. Change the test: checking the IR istead of checking the assembly.
4. Made some format adjustments.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D90441
Files:
clang/lib/AST/Stmt.cpp
clang/test/CodeGen/X86/ms-inline-asm-prefix.c
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3064,7 +3064,26 @@
}
continue;
}
+// Parse MASM style pseudo prefixes.
+if (isParsingMSInlineAsm()) {
+ if (Name.equals_lower("vex"))
+ForcedVEXEncoding = VEXEncoding_VEX;
+ else if (Name.equals_lower("vex2"))
+ForcedVEXEncoding = VEXEncoding_VEX2;
+ else if (Name.equals_lower("vex3"))
+ForcedVEXEncoding = VEXEncoding_VEX3;
+ else if (Name.equals_lower("evex"))
+ForcedVEXEncoding = VEXEncoding_EVEX;
+ if (ForcedVEXEncoding != VEXEncoding_Default) {
+if (getLexer().isNot(AsmToken::Identifier))
+ return Error(Parser.getTok().getLoc(), "Expected identifier");
+// FIXME: The mnemonic won't match correctly if its not in lower case.
+Name = Parser.getTok().getString();
+NameLoc = Parser.getTok().getLoc();
+Parser.Lex();
+ }
+}
break;
}
@@ -4370,10 +4389,16 @@
MCInst Inst;
- // If VEX3 encoding is forced, we need to pass the USE_VEX3 flag to the
- // encoder.
- if (ForcedVEXEncoding == VEXEncoding_VEX3)
+ // If VEX/EVEX encoding is forced, we need to pass the USE_* flag to the
+ // encoder and printer.
+ if (ForcedVEXEncoding == VEXEncoding_VEX)
+Prefixes |= X86::IP_USE_VEX;
+ else if (ForcedVEXEncoding == VEXEncoding_VEX2)
+Prefixes |= X86::IP_USE_VEX2;
+ else if (ForcedVEXEncoding == VEXEncoding_VEX3)
Prefixes |= X86::IP_USE_VEX3;
+ else if (ForcedVEXEncoding == VEXEncoding_EVEX)
+Prefixes |= X86::IP_USE_EVEX;
// Set encoded flags for {disp8} and {disp32}.
if (ForcedDispEncoding == DispEncoding_Disp8)
Index: clang/test/CodeGen/X86/ms-inline-asm-prefix.c
===
--- /dev/null
+++ clang/test/CodeGen/X86/ms-inline-asm-prefix.c
@@ -0,0 +1,14 @@
+// REQUIRES: x86-registered-target
+// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-windows-msvc -target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl -fasm-blocks -mllvm -x86-asm-syntax=intel -S -emit-llvm -o - | FileCheck %s -check-prefix=INTEL
+// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-windows-msvc -target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl -fasm-blocks -mllvm -x86-asm-syntax=att -S -emit-llvm -o - | FileCheck %s -check-prefix=ATT
+
+void check_inline_prefix(void) {
+ __asm {
+// INTEL: call void asm sideeffect inteldialect "{vex} vcvtps2pd xmm0, xmm1\0A\09{vex2} vcvtps2pd xmm0, xmm1\0A\09{vex3} vcvtps2pd xmm0, xmm1\0A\09{evex} vcvtps2pd xmm0, xmm1", "~{xmm0},~{dirflag},~{fpsr},~{flags}"()
+// ATT: call void asm sideeffect inteldialect "{vex} vcvtps2pd xmm0, xmm1\0A\09{vex2} vcvtps2pd xmm0, xmm1\0A\09{vex3} vcvtps2pd xmm0, xmm1\0A\09{evex} vcvtps2pd xmm0, xmm1", "~{xmm0},~{dirflag},~{fpsr},~{flags}"()
+vex vcvtps2pd xmm0, xmm1
+vex2 vcvtps2pd xmm0, xmm1
+vex3 vcvtps2pd xmm0, xmm1
+evex vcvtps2pd xmm0, xmm1
+ }
+}
Index: clang/lib/AST/Stmt.cpp
===
--- clang/lib/AST/Stmt.cpp
+++ clang/lib/AST/Stmt.cpp
@@ -791,7 +791,27 @@
/// Assemble final IR asm string (MS-style).
std::string MSAsmStmt::generateAsmString(const ASTContext ) const {
// FIXME: This needs to be translated into the IR string representation.
- return std::string(AsmStr);
+ SmallVector Pieces;
+ AsmStr.split(Pieces, "\n\t");
+ std::string MSAsmString;
+ for (size_t I = 0, E = Pieces.size(); I < E; ++I) {
+StringRef Instruction = Pieces[I];
+// For vex/vex2/vex3/evex masm style prefix, convert it to att style
+// since we don't support masm style prefix in backend.
+if (Instruction.startswith("vex "))
+ MSAsmString += '{' + Instruction.substr(0, 3).str() + '}' +
+ Instruction.substr(3).str();
+else if (Instruction.startswith("vex2 ") ||
+ Instruction.startswith("vex3 ") || Instruction.startswith("evex "))
+ MSAsmString += '{' + Instruction.substr(0, 4).str() + '}' +
+
[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
LiuChen3 added inline comments. Comment at: clang/lib/AST/Stmt.cpp:795 + SmallVector Pieces; + AsmStr.split(Pieces, "\n\t"); + std::string MSAsmString; pengfei wrote: > Can we always assume the separator is `\n\t`? I think so. From the code, we can see '\n\t' will be added to each end of statement: ``` case AOK_EndOfStatement: OS << "\n\t"; break; ``` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D90441/new/ https://reviews.llvm.org/D90441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
pengfei added inline comments.
Comment at: clang/lib/AST/Stmt.cpp:795
+ SmallVector Pieces;
+ AsmStr.split(Pieces, "\n\t");
+ std::string MSAsmString;
Can we always assume the separator is `\n\t`?
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3083
+ }
+ if (IsPrefix) {
+NameLoc = Parser.getTok().getLoc();
You just need to check `ForcedVEXEncoding != VEXEncoding_Default`.
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3084
+ if (IsPrefix) {
+NameLoc = Parser.getTok().getLoc();
+if (getLexer().isNot(AsmToken::Identifier))
Unused assignment. It may suppose to be used on line 3086.
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[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
LiuChen3 added a comment. Ping? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D90441/new/ https://reviews.llvm.org/D90441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
LiuChen3 added inline comments.
Comment at: clang/lib/AST/Stmt.cpp:801
+// since we don't support masm style prefix in backend.
+if (Instruction.startswith("vex "))
+ MSAsmString += '{' + Instruction.substr(0, 3).str() + '}' +
From X86AsmParser, the vex/evex prefix must be the begin of the instructions.
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[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
LiuChen3 updated this revision to Diff 304730.
LiuChen3 added a comment.
Rebase.
Adding the '{}' to prefix when generate IR.
Repository:
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Files:
clang/lib/AST/Stmt.cpp
clang/test/CodeGen/X86/ms-inline-asm-prefix.c
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3064,7 +3064,32 @@
}
continue;
}
-
+// Parse MASM style pseudo prefixes.
+if (isParsingMSInlineAsm()) {
+ bool IsPrefix = false;
+ if (Name == "vex") {
+ForcedVEXEncoding = VEXEncoding_VEX;
+IsPrefix = true;
+ } else if (Name == "vex2") {
+ForcedVEXEncoding = VEXEncoding_VEX2;
+IsPrefix = true;
+ } else if (Name == "vex3") {
+ForcedVEXEncoding = VEXEncoding_VEX3;
+IsPrefix = true;
+ } else if (Name == "evex") {
+ForcedVEXEncoding = VEXEncoding_EVEX;
+IsPrefix = true;
+ }
+ if (IsPrefix) {
+NameLoc = Parser.getTok().getLoc();
+if (getLexer().isNot(AsmToken::Identifier))
+ return Error(Parser.getTok().getLoc(), "Expected identifier");
+// FIXME: The mnemonic won't match correctly if its not in lower case.
+Name = Parser.getTok().getString();
+Parser.Lex();
+continue;
+ }
+}
break;
}
@@ -4370,10 +4395,16 @@
MCInst Inst;
- // If VEX3 encoding is forced, we need to pass the USE_VEX3 flag to the
- // encoder.
- if (ForcedVEXEncoding == VEXEncoding_VEX3)
+ // If VEX/EVEX encoding is forced, we need to pass the USE_* flag to the
+ // encoder and printer.
+ if (ForcedVEXEncoding == VEXEncoding_VEX)
+Prefixes |= X86::IP_USE_VEX;
+ else if (ForcedVEXEncoding == VEXEncoding_VEX2)
+Prefixes |= X86::IP_USE_VEX2;
+ else if (ForcedVEXEncoding == VEXEncoding_VEX3)
Prefixes |= X86::IP_USE_VEX3;
+ else if (ForcedVEXEncoding == VEXEncoding_EVEX)
+Prefixes |= X86::IP_USE_EVEX;
// Set encoded flags for {disp8} and {disp32}.
if (ForcedDispEncoding == DispEncoding_Disp8)
Index: clang/test/CodeGen/X86/ms-inline-asm-prefix.c
===
--- /dev/null
+++ clang/test/CodeGen/X86/ms-inline-asm-prefix.c
@@ -0,0 +1,20 @@
+// REQUIRES: x86-registered-target
+// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-windows-msvc -target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl -fasm-blocks -mllvm -x86-asm-syntax=intel -S -o - | FileCheck %s -check-prefix=INTEL
+// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-windows-msvc -target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl -fasm-blocks -mllvm -x86-asm-syntax=att -S -o - | FileCheck %s -check-prefix=ATT
+
+void check_inline_prefix(void) {
+ __asm {
+// INTEL: {vex} vcvtps2pd xmm0, xmm1
+// INTEL: {vex2}vcvtps2pd xmm0, xmm1
+// INTEL: {vex3}vcvtps2pd xmm0, xmm1
+// INTEL: {evex}vcvtps2pd xmm0, xmm1
+// ATT: {vex} vcvtps2pd %xmm1, %xmm0
+// ATT: {vex2} vcvtps2pd %xmm1, %xmm0
+// ATT: {vex3} vcvtps2pd %xmm1, %xmm0
+// ATT: {evex} vcvtps2pd %xmm1, %xmm0
+vex vcvtps2pd xmm0, xmm1
+vex2 vcvtps2pd xmm0, xmm1
+vex3 vcvtps2pd xmm0, xmm1
+evex vcvtps2pd xmm0, xmm1
+ }
+}
Index: clang/lib/AST/Stmt.cpp
===
--- clang/lib/AST/Stmt.cpp
+++ clang/lib/AST/Stmt.cpp
@@ -791,7 +791,27 @@
/// Assemble final IR asm string (MS-style).
std::string MSAsmStmt::generateAsmString(const ASTContext ) const {
// FIXME: This needs to be translated into the IR string representation.
- return std::string(AsmStr);
+ SmallVector Pieces;
+ AsmStr.split(Pieces, "\n\t");
+ std::string MSAsmString;
+ for (size_t i = 0, e = Pieces.size(); i < e; ++i) {
+StringRef Instruction = Pieces[i];
+// For vex/vex2/vex3/evex masm style prefix, convert it to att style
+// since we don't support masm style prefix in backend.
+if (Instruction.startswith("vex "))
+ MSAsmString += '{' + Instruction.substr(0, 3).str() + '}' +
+ Instruction.substr(3).str();
+else if (Instruction.startswith("vex2 ") ||
+ Instruction.startswith("vex3 ") || Instruction.startswith("evex "))
+ MSAsmString += '{' + Instruction.substr(0, 4).str() + '}' +
+ Instruction.substr(4).str();
+else
+ MSAsmString += Instruction.str();
+// If this is not the last instruction, adding back the '\n\t'.
+if (i < e - 1)
+ MSAsmString += "\n\t";
+ }
+ return MSAsmString;
}
Expr *MSAsmStmt::getOutputExpr(unsigned i) {
[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
LiuChen3 added inline comments.
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:2851
+// Parse MASM style pseudo prefixes.
+// FIXME: This prefix should only be used for MASM, not for intel-syntax.
+if (isParsingIntelSyntax()) {
craig.topper wrote:
> epastor wrote:
> > LiuChen3 wrote:
> > > I tried to limit to MASM. But I found that the 'isParsingMSInlineAsm()'
> > > is not accurate. And then I tried to transmit 'ParsingMSInlineAsm'
> > > information correctly in AsmPrinterInlineAsm.cpp (according to the
> > > '-fasm-blocks' option). But I was surprised to find that
> > > isParsingMSInlineAsm() is actually used as the argument of
> > > 'MatchingInlineAsm' in 'MatchAndEmitInstruction()'. This makes me
> > > confused. Should that 'MatchingInlineAsm' be 'MatchingMSInlineAsm' ?Is
> > > this MatchingInlineAsm only used by llvm-ml.
> > > It difficult to limit this to MASM at the moment.
> > llvm-ml attempts not to touch **anything** involving inline assembly so
> > far. The signal that MasmParser.cpp is involved is
> > `Parser.isParsingMasm()`. However... while I can't answer the majority of
> > this without more research, I suspect you're correct that
> > `MatchingInlineAsm` is misnamed. We need to check this, and if so, we
> > should rename it to avoid confusion.
> MS inline assembly is parsed twice. Once by clang to find names of C/C++
> variables. And again in the backend. GNU inline assembly is only parsed in
> the backend since variable names are bound explicitly and not referenced in
> the assembly text.
>
> IsParsingInlineAsm is set during the clang parsing.
Thanks. That's make sense.
So 'MatchingInlineAsm' in MatchAndEmitInstruction() more like
'MatchingMSInlineAsm' and can only be set when parsing the instructions first
time. And the second time parser can not set 'setParsingMSInlineAsm(true)'.
That's make difficult to limit the scope to MASM for now.
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[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
craig.topper added inline comments.
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:2851
+// Parse MASM style pseudo prefixes.
+// FIXME: This prefix should only be used for MASM, not for intel-syntax.
+if (isParsingIntelSyntax()) {
epastor wrote:
> LiuChen3 wrote:
> > I tried to limit to MASM. But I found that the 'isParsingMSInlineAsm()' is
> > not accurate. And then I tried to transmit 'ParsingMSInlineAsm'
> > information correctly in AsmPrinterInlineAsm.cpp (according to the
> > '-fasm-blocks' option). But I was surprised to find that
> > isParsingMSInlineAsm() is actually used as the argument of
> > 'MatchingInlineAsm' in 'MatchAndEmitInstruction()'. This makes me confused.
> > Should that 'MatchingInlineAsm' be 'MatchingMSInlineAsm' ?Is this
> > MatchingInlineAsm only used by llvm-ml.
> > It difficult to limit this to MASM at the moment.
> llvm-ml attempts not to touch **anything** involving inline assembly so far.
> The signal that MasmParser.cpp is involved is `Parser.isParsingMasm()`.
> However... while I can't answer the majority of this without more research, I
> suspect you're correct that `MatchingInlineAsm` is misnamed. We need to check
> this, and if so, we should rename it to avoid confusion.
MS inline assembly is parsed twice. Once by clang to find names of C/C++
variables. And again in the backend. GNU inline assembly is only parsed in the
backend since variable names are bound explicitly and not referenced in the
assembly text.
IsParsingInlineAsm is set during the clang parsing.
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[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
epastor added inline comments.
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:2851
+// Parse MASM style pseudo prefixes.
+// FIXME: This prefix should only be used for MASM, not for intel-syntax.
+if (isParsingIntelSyntax()) {
LiuChen3 wrote:
> I tried to limit to MASM. But I found that the 'isParsingMSInlineAsm()' is
> not accurate. And then I tried to transmit 'ParsingMSInlineAsm' information
> correctly in AsmPrinterInlineAsm.cpp (according to the '-fasm-blocks'
> option). But I was surprised to find that isParsingMSInlineAsm() is actually
> used as the argument of 'MatchingInlineAsm' in 'MatchAndEmitInstruction()'.
> This makes me confused. Should that 'MatchingInlineAsm' be
> 'MatchingMSInlineAsm' ?Is this MatchingInlineAsm only used by llvm-ml.
> It difficult to limit this to MASM at the moment.
llvm-ml attempts not to touch **anything** involving inline assembly so far.
The signal that MasmParser.cpp is involved is `Parser.isParsingMasm()`.
However... while I can't answer the majority of this without more research, I
suspect you're correct that `MatchingInlineAsm` is misnamed. We need to check
this, and if so, we should rename it to avoid confusion.
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[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
LiuChen3 added inline comments.
Comment at: clang/test/CodeGen/X86/ms-inline-asm-prefix.c:1
+// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-widows-msvc
-target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl
-fasm-blocks -mllvm -x86-asm-syntax=intel -S -o - | FileCheck %s -check-prefix
CHECK
+
LiuChen3 wrote:
> epastor wrote:
> > epastor wrote:
> > > pengfei wrote:
> > > > pengfei wrote:
> > > > > pengfei wrote:
> > > > > > Maybe need `// REQUIRES: x86-registered-target`
> > > > > You may need add att check too since you modified the att code.
> > > > Should it be avalible only when `-fms-compatibility`
> > > The triple is misspelled; it should be `x86_64-pc-windows-msvc` (the "n"
> > > in windows is missing)
> > A broader question: As written, this applies to anything in Intel syntax.
> > Is this an Intel syntax feature, or a MASM feature?
> Thanks for your review. After checking with the people of MSVC, I found that
> prefix without braces is not intel syntax. Actually, we don't know if there
> any document says what the prefix should be. At least, gcc does have the "{}"
> in intel syntax, so does clang. We currently decide to only support parsing
> the prefix without MSVC.
I am not sure. But I think -fasm-blocks, -fms-extensions also support MASM.
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:2851
+// Parse MASM style pseudo prefixes.
+// FIXME: This prefix should only be used for MASM, not for intel-syntax.
+if (isParsingIntelSyntax()) {
I tried to limit to MASM. But I found that the 'isParsingMSInlineAsm()' is not
accurate. And then I tried to transmit 'ParsingMSInlineAsm' information
correctly in AsmPrinterInlineAsm.cpp (according to the '-fasm-blocks' option).
But I was surprised to find that isParsingMSInlineAsm() is actually used as the
argument of 'MatchingInlineAsm' in 'MatchAndEmitInstruction()'. This makes me
confused. Should that 'MatchingInlineAsm' be 'MatchingMSInlineAsm' ?Is this
MatchingInlineAsm only used by llvm-ml.
It difficult to limit this to MASM at the moment.
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[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
LiuChen3 updated this revision to Diff 302769.
LiuChen3 added a comment.
1. Address comments;
2. Only support parsing vex/vex2/vex3/evex prefix for MASM
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Files:
clang/test/CodeGen/X86/ms-inline-asm-prefix.c
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2847,7 +2847,33 @@
}
continue;
}
-
+// Parse MASM style pseudo prefixes.
+// FIXME: This prefix should only be used for MASM, not for intel-syntax.
+if (isParsingIntelSyntax()) {
+ bool IsPrefix = false;
+ if (Name == "vex") {
+ForcedVEXEncoding = VEXEncoding_VEX;
+IsPrefix = true;
+ } else if (Name == "vex2") {
+ForcedVEXEncoding = VEXEncoding_VEX2;
+IsPrefix = true;
+ } else if (Name == "vex3") {
+ForcedVEXEncoding = VEXEncoding_VEX3;
+IsPrefix = true;
+ } else if (Name == "evex") {
+ForcedVEXEncoding = VEXEncoding_EVEX;
+IsPrefix = true;
+ }
+ if (IsPrefix) {
+NameLoc = Parser.getTok().getLoc();
+if (getLexer().isNot(AsmToken::Identifier))
+ return Error(Parser.getTok().getLoc(), "Expected identifier");
+// FIXME: The mnemonic won't match correctly if its not in lower case.
+Name = Parser.getTok().getString();
+Parser.Lex();
+continue;
+ }
+}
break;
}
@@ -4153,10 +4179,16 @@
MCInst Inst;
- // If VEX3 encoding is forced, we need to pass the USE_VEX3 flag to the
- // encoder.
- if (ForcedVEXEncoding == VEXEncoding_VEX3)
+ // If VEX/EVEX encoding is forced, we need to pass the USE_* flag to the
+ // encoder and printer.
+ if (ForcedVEXEncoding == VEXEncoding_VEX)
+Prefixes |= X86::IP_USE_VEX;
+ else if (ForcedVEXEncoding == VEXEncoding_VEX2)
+Prefixes |= X86::IP_USE_VEX2;
+ else if (ForcedVEXEncoding == VEXEncoding_VEX3)
Prefixes |= X86::IP_USE_VEX3;
+ else if (ForcedVEXEncoding == VEXEncoding_EVEX)
+Prefixes |= X86::IP_USE_EVEX;
// Set encoded flags for {disp8} and {disp32}.
if (ForcedDispEncoding == DispEncoding_Disp8)
Index: clang/test/CodeGen/X86/ms-inline-asm-prefix.c
===
--- /dev/null
+++ clang/test/CodeGen/X86/ms-inline-asm-prefix.c
@@ -0,0 +1,20 @@
+// REQUIRES: x86-registered-target
+// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-windows-msvc
-target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl
-fasm-blocks -mllvm -x86-asm-syntax=intel -S -o - | FileCheck %s
-check-prefix=INTEL
+// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-windows-msvc
-target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl
-fasm-blocks -mllvm -x86-asm-syntax=att -S -o - | FileCheck %s
-check-prefix=ATT
+
+void check_inline_prefix(void) {
+ __asm {
+// INTEL: {vex} vcvtps2pd xmm0, xmm1
+// INTEL: {vex2}vcvtps2pd xmm0, xmm1
+// INTEL: {vex3}vcvtps2pd xmm0, xmm1
+// INTEL: {evex}vcvtps2pd xmm0, xmm1
+// ATT: {vex} vcvtps2pd %xmm1, %xmm0
+// ATT: {vex2} vcvtps2pd %xmm1, %xmm0
+// ATT: {vex3} vcvtps2pd %xmm1, %xmm0
+// ATT: {evex} vcvtps2pd %xmm1, %xmm0
+vex vcvtps2pd xmm0, xmm1
+vex2 vcvtps2pd xmm0, xmm1
+vex3 vcvtps2pd xmm0, xmm1
+evex vcvtps2pd xmm0, xmm1
+ }
+}
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2847,7 +2847,33 @@
}
continue;
}
-
+// Parse MASM style pseudo prefixes.
+// FIXME: This prefix should only be used for MASM, not for intel-syntax.
+if (isParsingIntelSyntax()) {
+ bool IsPrefix = false;
+ if (Name == "vex") {
+ForcedVEXEncoding = VEXEncoding_VEX;
+IsPrefix = true;
+ } else if (Name == "vex2") {
+ForcedVEXEncoding = VEXEncoding_VEX2;
+IsPrefix = true;
+ } else if (Name == "vex3") {
+ForcedVEXEncoding = VEXEncoding_VEX3;
+IsPrefix = true;
+ } else if (Name == "evex") {
+ForcedVEXEncoding = VEXEncoding_EVEX;
+IsPrefix = true;
+ }
+ if (IsPrefix) {
+NameLoc = Parser.getTok().getLoc();
+if (getLexer().isNot(AsmToken::Identifier))
+ return Error(Parser.getTok().getLoc(), "Expected identifier");
+// FIXME: The mnemonic won't match correctly if its not in lower case.
+Name = Parser.getTok().getString();
+Parser.Lex();
+continue;
+ }
+}
[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
LiuChen3 added inline comments.
Comment at: clang/test/CodeGen/X86/ms-inline-asm-prefix.c:1
+// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-widows-msvc
-target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl
-fasm-blocks -mllvm -x86-asm-syntax=intel -S -o - | FileCheck %s -check-prefix
CHECK
+
epastor wrote:
> epastor wrote:
> > pengfei wrote:
> > > pengfei wrote:
> > > > pengfei wrote:
> > > > > Maybe need `// REQUIRES: x86-registered-target`
> > > > You may need add att check too since you modified the att code.
> > > Should it be avalible only when `-fms-compatibility`
> > The triple is misspelled; it should be `x86_64-pc-windows-msvc` (the "n" in
> > windows is missing)
> A broader question: As written, this applies to anything in Intel syntax. Is
> this an Intel syntax feature, or a MASM feature?
Thanks for your review. After checking with the people of MSVC, I found that
prefix without braces is not intel syntax. Actually, we don't know if there any
document says what the prefix should be. At least, gcc does have the "{}" in
intel syntax, so does clang. We currently decide to only support parsing the
prefix without MSVC.
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[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
epastor added inline comments. Comment at: clang/test/CodeGen/X86/ms-inline-asm-prefix.c:1 +// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-widows-msvc -target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl -fasm-blocks -mllvm -x86-asm-syntax=intel -S -o - | FileCheck %s -check-prefix CHECK + pengfei wrote: > pengfei wrote: > > pengfei wrote: > > > Maybe need `// REQUIRES: x86-registered-target` > > You may need add att check too since you modified the att code. > Should it be avalible only when `-fms-compatibility` The triple is misspelled; it should be `x86_64-pc-windows-msvc` (the "n" in windows is missing) Comment at: clang/test/CodeGen/X86/ms-inline-asm-prefix.c:1 +// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-widows-msvc -target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl -fasm-blocks -mllvm -x86-asm-syntax=intel -S -o - | FileCheck %s -check-prefix CHECK + epastor wrote: > pengfei wrote: > > pengfei wrote: > > > pengfei wrote: > > > > Maybe need `// REQUIRES: x86-registered-target` > > > You may need add att check too since you modified the att code. > > Should it be avalible only when `-fms-compatibility` > The triple is misspelled; it should be `x86_64-pc-windows-msvc` (the "n" in > windows is missing) A broader question: As written, this applies to anything in Intel syntax. Is this an Intel syntax feature, or a MASM feature? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D90441/new/ https://reviews.llvm.org/D90441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
pengfei added inline comments. Comment at: clang/test/CodeGen/X86/ms-inline-asm-prefix.c:1 +// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-widows-msvc -target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl -fasm-blocks -mllvm -x86-asm-syntax=intel -S -o - | FileCheck %s -check-prefix CHECK + Maybe need `// REQUIRES: x86-registered-target` Comment at: clang/test/CodeGen/X86/ms-inline-asm-prefix.c:1 +// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-widows-msvc -target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl -fasm-blocks -mllvm -x86-asm-syntax=intel -S -o - | FileCheck %s -check-prefix CHECK + pengfei wrote: > Maybe need `// REQUIRES: x86-registered-target` You may need add att check too since you modified the att code. Comment at: clang/test/CodeGen/X86/ms-inline-asm-prefix.c:1 +// RUN:%clang_cc1 %s -ferror-limit 0 -triple=x86_64-pc-widows-msvc -target-feature +avx512f -target-feature +avx2 -target-feature +avx512vl -fasm-blocks -mllvm -x86-asm-syntax=intel -S -o - | FileCheck %s -check-prefix CHECK + pengfei wrote: > pengfei wrote: > > Maybe need `// REQUIRES: x86-registered-target` > You may need add att check too since you modified the att code. Should it be avalible only when `-fms-compatibility` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D90441/new/ https://reviews.llvm.org/D90441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM
LiuChen3 created this revision.
Herald added subscribers: llvm-commits, cfe-commits, hiraditya.
Herald added projects: clang, LLVM.
LiuChen3 requested review of this revision.
For MASM syntax, the prefixes are not enclosed in braces.
The assembly code should like:
"evex vcvtps2pd xmm0, xmm1"
There are still some avx512 tests need to be improved with 'evex'
prefix. But I think it's better to discuss this syntax first.
Repository:
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Files:
clang/test/CodeGen/X86/ms-inline-asm-prefix.c
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
Index: llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
===
--- llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
@@ -42,6 +42,17 @@
raw_ostream ) {
printInstFlags(MI, OS);
+ unsigned Flags = MI->getFlags();
+ // These all require a pseudo prefix
+ if (Flags & X86::IP_USE_VEX)
+OS << "\tvex";
+ else if (Flags & X86::IP_USE_VEX2)
+OS << "\tvex2";
+ else if (Flags & X86::IP_USE_VEX3)
+OS << "\tvex3";
+ else if (Flags & X86::IP_USE_EVEX)
+OS << "\tevex";
+
// In 16-bit mode, print data16 as data32.
if (MI->getOpcode() == X86::DATA16_PREFIX &&
STI.getFeatureBits()[X86::Mode16Bit]) {
Index: llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
===
--- llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
@@ -346,21 +346,6 @@
O << "\trepne\t";
else if (Flags & X86::IP_HAS_REPEAT)
O << "\trep\t";
-
- // These all require a pseudo prefix
- if (Flags & X86::IP_USE_VEX)
-O << "\t{vex}";
- else if (Flags & X86::IP_USE_VEX2)
-O << "\t{vex2}";
- else if (Flags & X86::IP_USE_VEX3)
-O << "\t{vex3}";
- else if (Flags & X86::IP_USE_EVEX)
-O << "\t{evex}";
-
- if (Flags & X86::IP_USE_DISP8)
-O << "\t{disp8}";
- else if (Flags & X86::IP_USE_DISP32)
-O << "\t{disp32}";
}
void X86InstPrinterCommon::printVKPair(const MCInst *MI, unsigned OpNo,
Index: llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
===
--- llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
@@ -48,6 +48,22 @@
printInstFlags(MI, OS);
+ unsigned Flags = MI->getFlags();
+ // These all require a pseudo prefix
+ if (Flags & X86::IP_USE_VEX)
+OS << "\t{vex}";
+ else if (Flags & X86::IP_USE_VEX2)
+OS << "\t{vex2}";
+ else if (Flags & X86::IP_USE_VEX3)
+OS << "\t{vex3}";
+ else if (Flags & X86::IP_USE_EVEX)
+OS << "\t{evex}";
+
+ if (Flags & X86::IP_USE_DISP8)
+OS << "\t{disp8}";
+ else if (Flags & X86::IP_USE_DISP32)
+OS << "\t{disp32}";
+
// Output CALLpcrel32 as "callq" in 64-bit mode.
// In Intel annotation it's always emitted as "call".
//
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2847,7 +2847,30 @@
}
continue;
}
-
+// Parse MASM style pseudo prefixes.
+if (isParsingIntelSyntax()) {
+ bool IsPrefix = false;
+ if (Name == "vex" || Name == "vex2") {
+ForcedVEXEncoding = VEXEncoding_VEX;
+IsPrefix = true;
+ }
+ else if (Name == "vex3") {
+ForcedVEXEncoding = VEXEncoding_VEX3;
+IsPrefix = true;
+ }
+ else if (Name == "evex") {
+ForcedVEXEncoding = VEXEncoding_EVEX;
+IsPrefix = true;
+ }
+ if (IsPrefix) {
+NameLoc = Parser.getTok().getLoc();
+if (getLexer().isNot(AsmToken::Identifier))
+ return Error(Parser.getTok().getLoc(), "Expected identifier");
+// FIXME: The mnemonic won't match correctly if its not in lower case.
+Name = Parser.getTok().getString();
+Parser.Lex();
+ }
+}
break;
}
@@ -4146,10 +4169,16 @@
MCInst Inst;
- // If VEX3 encoding is forced, we need to pass the USE_VEX3 flag to the
- // encoder.
- if (ForcedVEXEncoding == VEXEncoding_VEX3)
+ // If VEX/EVEX encoding is forced, we need to pass the USE_* flag to the
+ // encoder and printer.
+ if (ForcedVEXEncoding == VEXEncoding_VEX)
+Prefixes |= X86::IP_USE_VEX;
+ else if (ForcedVEXEncoding == VEXEncoding_VEX2)
+Prefixes |= X86::IP_USE_VEX2;
+ else if (ForcedVEXEncoding == VEXEncoding_VEX3)
Prefixes |= X86::IP_USE_VEX3;
+ else if (ForcedVEXEncoding == VEXEncoding_EVEX)
+
