[PATCH] D91974: [PowerPC] Rename the vector pair intrinsics and builtins to replace the _mma_ prefix by _vsx_

2020-12-17 Thread Albion Fung via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc2892978e919: [PowerPC] Rename the vector pair intrinsics 
and builtins to replace the _mma_… (authored by bsaleil, committed by Conanap).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91974/new/

https://reviews.llvm.org/D91974

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-mma.c
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-mma-types.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-mma-types.cpp
  clang/test/SemaCXX/ppc-pair-mma-types.cpp
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
  llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/mma-outer-product.ll
  llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
  llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics-without-mma.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll

Index: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -0,0 +1,357 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-NOMMA
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-BE-NOMMA
+
+; This test also checks that the paired vector intrinsics are available even
+; when MMA is disabled.
+
+; assemble_pair
+declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
+define void @ass_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
+; CHECK-LABEL: ass_pair:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmr v3, v2
+; CHECK-NEXT:stxv v2, 16(r3)
+; CHECK-NEXT:stxv v3, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: ass_pair:
+; CHECK-NOMMA:   # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:vmr v3, v2
+; CHECK-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-NOMMA-NEXT:stxv v3, 0(r3)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: ass_pair:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:vmr v3, v2
+; CHECK-BE-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: ass_pair:
+; CHECK-BE-NOMMA:   # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:vmr v3, v2
+; CHECK-BE-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NOMMA-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NOMMA-NEXT:blr
+entry:
+  %0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
+  store <256 x i1> %0, <256 x i1>* %ptr, align 32
+  ret void
+}
+
+; disassemble_pair
+declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
+define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
+; CHECK-LABEL: disass_pair:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:lxv vs1, 0(r3)
+; CHECK-NEXT:lxv vs0, 16(r3)
+; CHECK-NEXT:stxv vs1, 0(r4)
+; CHECK-NEXT:stxv vs0, 0(r5)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: disass_pair:
+; CHECK-NOMMA:   # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:lxv vs1, 0(r3)
+; CHECK-NOMMA-NEXT:lxv vs0, 16(r3)
+; CHECK-NOMMA-NEXT:stxv vs1, 0(r4)
+; CHECK-NOMMA-NEXT:stxv vs0, 0(r5)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: disass_pair:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lxv vs1, 16(r3)
+; CHECK-BE-NEXT:lxv vs0, 0(r3)
+; CHECK-BE-NEXT:stxv vs0, 0(r4)
+; CHECK-BE-NEXT:stxv vs1, 0(r5)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: disass_pair:
+; CHECK-BE-NOMMA:   # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:lxv vs1, 16(r3)
+; CHECK-BE-NOMMA-NEXT:lxv vs0, 0(r3)
+; CHECK-BE-NOMMA-NEXT:stxv vs0, 0(r4)
+; CHECK-BE-NOMMA-NEXT:stxv vs1, 0(r5)
+; CHECK-BE-NOMMA-NEXT:blr

[PATCH] D91974: [PowerPC] Rename the vector pair intrinsics and builtins to replace the _mma_ prefix by _vsx_

2020-12-16 Thread Baptiste Saleil via Phabricator via cfe-commits 
bsaleil updated this revision to Diff 312238.
bsaleil added a comment.

Rebase and fix comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91974/new/

https://reviews.llvm.org/D91974

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-mma.c
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-mma-types.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-mma-types.cpp
  clang/test/SemaCXX/ppc-pair-mma-types.cpp
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
  llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/mma-outer-product.ll
  llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
  llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics-without-mma.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll

Index: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -0,0 +1,357 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-NOMMA
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-BE-NOMMA
+
+; This test also checks that the paired vector intrinsics are available even
+; when MMA is disabled.
+
+; assemble_pair
+declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
+define void @ass_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
+; CHECK-LABEL: ass_pair:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmr v3, v2
+; CHECK-NEXT:stxv v2, 16(r3)
+; CHECK-NEXT:stxv v3, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: ass_pair:
+; CHECK-NOMMA:   # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:vmr v3, v2
+; CHECK-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-NOMMA-NEXT:stxv v3, 0(r3)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: ass_pair:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:vmr v3, v2
+; CHECK-BE-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: ass_pair:
+; CHECK-BE-NOMMA:   # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:vmr v3, v2
+; CHECK-BE-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NOMMA-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NOMMA-NEXT:blr
+entry:
+  %0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
+  store <256 x i1> %0, <256 x i1>* %ptr, align 32
+  ret void
+}
+
+; disassemble_pair
+declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
+define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
+; CHECK-LABEL: disass_pair:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:lxv vs1, 0(r3)
+; CHECK-NEXT:lxv vs0, 16(r3)
+; CHECK-NEXT:stxv vs1, 0(r4)
+; CHECK-NEXT:stxv vs0, 0(r5)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: disass_pair:
+; CHECK-NOMMA:   # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:lxv vs1, 0(r3)
+; CHECK-NOMMA-NEXT:lxv vs0, 16(r3)
+; CHECK-NOMMA-NEXT:stxv vs1, 0(r4)
+; CHECK-NOMMA-NEXT:stxv vs0, 0(r5)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: disass_pair:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lxv vs1, 16(r3)
+; CHECK-BE-NEXT:lxv vs0, 0(r3)
+; CHECK-BE-NEXT:stxv vs0, 0(r4)
+; CHECK-BE-NEXT:stxv vs1, 0(r5)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: disass_pair:
+; CHECK-BE-NOMMA:   # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:lxv vs1, 16(r3)
+; CHECK-BE-NOMMA-NEXT:lxv vs0, 0(r3)
+; CHECK-BE-NOMMA-NEXT:stxv vs0, 0(r4)
+; CHECK-BE-NOMMA-NEXT:stxv vs1, 0(r5)
+; CHECK-BE-NOMMA-NEXT:blr
+entry:
+  %0 = load <256 x i1>, <256 x i1>* %ptr1, align 32
+  %1 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %0)
+  %2 = extractvalue { <16 x i8>, <16 x i8> }

[PATCH] D91974: [PowerPC] Rename the vector pair intrinsics and builtins to replace the _mma_ prefix by _vsx_

2020-12-15 Thread Ahsan Saghir via Phabricator via cfe-commits 
saghir accepted this revision.
saghir added a comment.

LGTM. A minor nit regarding an incomplete comment in 
`llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll` which can be addressed 
when committing the patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91974/new/

https://reviews.llvm.org/D91974

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D91974: [PowerPC] Rename the vector pair intrinsics and builtins to replace the _mma_ prefix by _vsx_

2020-12-04 Thread Amy Kwan via Phabricator via cfe-commits 
amyk accepted this revision as: amyk.
amyk added a comment.
This revision is now accepted and ready to land.

Just a minor comment but LGTM overall.




Comment at: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll:15
+
+; This test is to check that the paired vector intrinsics are available even
+

Unfinished comment?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91974/new/

https://reviews.llvm.org/D91974

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits