[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd6a0560bf258: [Clang][RISCV] Add custom TableGen backend for 
riscv-vector intrinsics. (authored by khchen).

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  https://reviews.llvm.org/D95016?vs=328533=329819#toc

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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:58-62
+  bool IsPointer = false;
+  // IsConstant indices are "int", but have the constant expression.
+  bool IsImmediate = false;
+  // const qualifier.
+  bool IsConstant = false;

craig.topper wrote:
> craig.topper wrote:
> > jrtc27 wrote:
> > > This isn't expressive enough for the grammar you defined. `PCPCec` is 
> > > supposed to give `const i8 * const i8 *`, whereas this will interpret it 
> > > as `const i8 *`. Given such types are presumably not needed you need to 
> > > tighten the rules of your grammar.
> > @jrtc, are you asking for RVVType::applyModifier to verify that that C 
> > doesn't appear twice for example?
> Oops I meant to write @jrtc27 above. Are you asking for 
> RVVType::applyModifier to verify that that C doesn't appear twice for example?
That P and C don't appear twice, and that C appears in the "right" order wrt P 
(i.e. it's always PC never CP).


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM. I think we can address any remaining issues post-commit. I'd like to see 
us start adding the intrinsics that use this.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

@jrtc27, please advise if there is anything more should to be changed, thanks.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

LGTM. @jrtc27 are you ok with this?


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 328533.
khchen added a comment.

rebase.


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:58-62
+  bool IsPointer = false;
+  // IsConstant indices are "int", but have the constant expression.
+  bool IsImmediate = false;
+  // const qualifier.
+  bool IsConstant = false;

craig.topper wrote:
> jrtc27 wrote:
> > This isn't expressive enough for the grammar you defined. `PCPCec` is 
> > supposed to give `const i8 * const i8 *`, whereas this will interpret it as 
> > `const i8 *`. Given such types are presumably not needed you need to 
> > tighten the rules of your grammar.
> @jrtc, are you asking for RVVType::applyModifier to verify that that C 
> doesn't appear twice for example?
Oops I meant to write @jrtc27 above. Are you asking for RVVType::applyModifier 
to verify that that C doesn't appear twice for example?


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

t




Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:58-62
+  bool IsPointer = false;
+  // IsConstant indices are "int", but have the constant expression.
+  bool IsImmediate = false;
+  // const qualifier.
+  bool IsConstant = false;

jrtc27 wrote:
> This isn't expressive enough for the grammar you defined. `PCPCec` is 
> supposed to give `const i8 * const i8 *`, whereas this will interpret it as 
> `const i8 *`. Given such types are presumably not needed you need to tighten 
> the rules of your grammar.
@jrtc, are you asking for RVVType::applyModifier to verify that that C doesn't 
appear twice for example?


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 327363.
khchen marked 11 inline comments as done.
khchen added a comment.

address @jrtc27's comments, thanks!


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:50
+Boolean,
+SignInteger,
+UnsignedInteger,

Signed



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:58-62
+  bool IsPointer = false;
+  // IsConstant indices are "int", but have the constant expression.
+  bool IsImmediate = false;
+  // const qualifier.
+  bool IsConstant = false;

This isn't expressive enough for the grammar you defined. `PCPCec` is supposed 
to give `const i8 * const i8 *`, whereas this will interpret it as `const i8 
*`. Given such types are presumably not needed you need to tighten the rules of 
your grammar.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:127
+
+enum RISCV_Extension : uint8_t {
+  Basic = 0,

No underscores in names



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:173
+  StringRef getIRName() const { return IRName; }
+  uint8_t getRISCV_Extensions() const { return RISCV_Extensions; }
+

No underscores in names



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:354-356
+  }
+
+  switch (ScalarType) {

Combine the two switch statements



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:419
+  ClangBuiltinStr = "__rvv_";
+  if (isBoolean()) {
+ClangBuiltinStr += "bool" + utostr(64 / Scale.getValue()) + "_t";

Combine this with the switch



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:441
+  assert(isValid() && "RVVType is invalid");
+  assert(ScalarType != ScalarTypeKind::Invalid && "ScalarType is invalid");
+  switch (ScalarType) {

Combine this with the switch



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:452-467
+  default:
+break;
+  }
+
+  if (IsConstant)
+Str += "const ";
+

This should be able to be tidied up so there's only one switch



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:627
+case 'W':
+  assert(isVector() && "'W' type transformer cannot be used on vectors");
+  ElementBitwidth *= 2;

This looks wrong



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:259-260
+
+LMULType ::operator*=(unsigned RHS) {
+  this->Log2LMUL = this->Log2LMUL + RHS;
+  return *this;

khchen wrote:
> craig.topper wrote:
> > jrtc27 wrote:
> > > That's not how multiplication works. This is exponentiation. 
> > > Multiplication would be `Log2LMul + log2(RHS)`. Please don't abuse 
> > > operators like this.
> > This seems like it must be broken, but since we don't do widening or 
> > narrowing in this patch we didn't notice?
> Yes, thanks for point out. In my original plan is fixing that in followup 
> patches. 
> I also add more bug fixes into this patch.
Probably worth adding an an `assert(isPowerOf2_32(RHS));` too


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:56
+//
+//   e: type of "t" as is (identity)
+//   v: computes a vector type whose element type is "t" for the current LMUL

jrtc27 wrote:
> khchen wrote:
> > jrtc27 wrote:
> > > Do we really need to invent an esoteric DSL?
> > I think this is different design choose.
> > Current design is based on 
> > https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi/-/blob/EPI/clang/include/clang/Basic/epi_builtins.td,
> >  personally I think it makes td file more simpler.
> > 
> > Of course we can make td file more complex little bit and list all legal 
> > type and combination like 
> > https://github.com/isrc-cas/rvv-llvm/blob/rvv-iscas/clang/include/clang/Basic/riscv_vector.td
> >  did.
> > 
> > In fact, I don't have a strong opinion on which one is better
> > 
> > ps. current approach is similar to arm_sve.td design, maybe they know the 
> > some critical reason.
> I just find it really obfuscates things when we have all these magic 
> character sequences.
Sorry, what do you mean?



Comment at: clang/include/clang/Basic/riscv_vector.td:66
+//  element type which is bool
+//   0: void type, ignores "t"
+//   z: size_t, ignores "t"

craig.topper wrote:
> jrtc27 wrote:
> > craig.topper wrote:
> > > jrtc27 wrote:
> > > > khchen wrote:
> > > > > jrtc27 wrote:
> > > > > > Then why aren't these just base types? We don't have to follow the 
> > > > > > brain-dead nature of printf.
> > > > > Basically builtin interface is instantiated by the "base type + LMUL" 
> > > > > with type transformers. But in some intrinsic function we need a 
> > > > > specific type regardless "base type + LMUL"
> > > > > ex. `vuint32m2_t vssrl_vx_u32m2_vl (vuint32m2_t op1, uint8_t op2, 
> > > > > size_t vl);`
> > > > Then fix the way you define these? This is just bad design IMO.
> > > For each signature there is effectively a single key type that is a 
> > > vector. The type transformer is a list of rules for how to derive all of 
> > > the other operands from that one key type. Conceptually similar to 
> > > LLVMScalarOrSameVectorWidth or LLVMHalfElementsVectorType in 
> > > Intrinsics.td. Some types are fixed and don't vary by the key type. Like 
> > > the size_t vl operand or a store intrinsic returning void.  There is no 
> > > separate place to put a base type.
> > Oh I see, I hadn't appreciated that TypeRange got split up and each 
> > character was a whole separate intrinsic, I had misinterpreted it as it 
> > being a list of the types of arguments, i.e. an N-character string for an 
> > (N-1)-argument (plus return type) intrinsic that you could then use as a 
> > base and apply transformations too (e.g. "if" for a float-to-int intrinsic, 
> > with "vv" etc giving you a vectorised versions) and so was confused as to 
> > why the void/size_t/ptrdiff_t/uint8_t/bool-ness couldn't just be pushed 
> > into the TypeRange and the corresponding transforms left as "e". But, how 
> > _would_ you define vector float-to-int (and back) conversions with this 
> > scheme then?
> > 
> > On a related note, I feel one way to make this less obfuscated is change 
> > v/w/q/o to be v1/v2/v4/v8 (maybe with the 1 being optional, don't really 
> > care), and is also more extensible in future rather than ending up with yet 
> > more alphabet soup, though it does change the parsing from being a list of 
> > characters to a list of strings.
> I think these transforms are used for the float-to-int and int-to-float. 
> 
> //   I: given a vector type, compute the vector type with integer type
> //  elements of the same width
> //   F: given a vector type, compute the vector type with floating-point type
> //  elements of the same width
> 
> The float and integer types for conversion are always the same size or one 
> lmul up or one lmul down. So combining I and F with v or w should cover it.
Yes, thanks for Craig's comments, I and U are used to implement conversion.

void/size_t/ptrdiff_t/uint8_t are not related to basic type so it's why they 
are no transformed from transforms left as `e`.

> On a related note, I feel one way to make this less obfuscated is change 
> v/w/q/o to be v1/v2/v4/v8 (maybe with the 1 being optional, don't really 
> care), and is also more extensible in future rather than ending up with yet 
> more alphabet soup, though it does change the parsing from being a list of 
> characters to a list of strings.

In the downstream we define a "complex" transformer which is not included in 
this patch. It  uses a string and encode additional information for some 
special type, like indexed operand of indexed load/store (its type is using EEW 
encoded in the instruction with EMUL=(EEW/SEW)*LMUL).
I have considered to use list of string, but personally I still prefer to use a 
list of characters because it's not often to use "complex" transformer and 
overall looking at the riscv_vector.td I 

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 326980.
khchen marked 17 inline comments as done.
khchen added a comment.

1. address @jrtc27's suggestions, thanks.
2. fix several bugs.


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:66
+//  element type which is bool
+//   0: void type, ignores "t"
+//   z: size_t, ignores "t"

jrtc27 wrote:
> craig.topper wrote:
> > jrtc27 wrote:
> > > khchen wrote:
> > > > jrtc27 wrote:
> > > > > Then why aren't these just base types? We don't have to follow the 
> > > > > brain-dead nature of printf.
> > > > Basically builtin interface is instantiated by the "base type + LMUL" 
> > > > with type transformers. But in some intrinsic function we need a 
> > > > specific type regardless "base type + LMUL"
> > > > ex. `vuint32m2_t vssrl_vx_u32m2_vl (vuint32m2_t op1, uint8_t op2, 
> > > > size_t vl);`
> > > Then fix the way you define these? This is just bad design IMO.
> > For each signature there is effectively a single key type that is a vector. 
> > The type transformer is a list of rules for how to derive all of the other 
> > operands from that one key type. Conceptually similar to 
> > LLVMScalarOrSameVectorWidth or LLVMHalfElementsVectorType in Intrinsics.td. 
> > Some types are fixed and don't vary by the key type. Like the size_t vl 
> > operand or a store intrinsic returning void.  There is no separate place to 
> > put a base type.
> Oh I see, I hadn't appreciated that TypeRange got split up and each character 
> was a whole separate intrinsic, I had misinterpreted it as it being a list of 
> the types of arguments, i.e. an N-character string for an (N-1)-argument 
> (plus return type) intrinsic that you could then use as a base and apply 
> transformations too (e.g. "if" for a float-to-int intrinsic, with "vv" etc 
> giving you a vectorised versions) and so was confused as to why the 
> void/size_t/ptrdiff_t/uint8_t/bool-ness couldn't just be pushed into the 
> TypeRange and the corresponding transforms left as "e". But, how _would_ you 
> define vector float-to-int (and back) conversions with this scheme then?
> 
> On a related note, I feel one way to make this less obfuscated is change 
> v/w/q/o to be v1/v2/v4/v8 (maybe with the 1 being optional, don't really 
> care), and is also more extensible in future rather than ending up with yet 
> more alphabet soup, though it does change the parsing from being a list of 
> characters to a list of strings.
I think these transforms are used for the float-to-int and int-to-float. 

//   I: given a vector type, compute the vector type with integer type
//  elements of the same width
//   F: given a vector type, compute the vector type with floating-point type
//  elements of the same width

The float and integer types for conversion are always the same size or one lmul 
up or one lmul down. So combining I and F with v or w should cover it.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:66
+//  element type which is bool
+//   0: void type, ignores "t"
+//   z: size_t, ignores "t"

craig.topper wrote:
> jrtc27 wrote:
> > khchen wrote:
> > > jrtc27 wrote:
> > > > Then why aren't these just base types? We don't have to follow the 
> > > > brain-dead nature of printf.
> > > Basically builtin interface is instantiated by the "base type + LMUL" 
> > > with type transformers. But in some intrinsic function we need a specific 
> > > type regardless "base type + LMUL"
> > > ex. `vuint32m2_t vssrl_vx_u32m2_vl (vuint32m2_t op1, uint8_t op2, size_t 
> > > vl);`
> > Then fix the way you define these? This is just bad design IMO.
> For each signature there is effectively a single key type that is a vector. 
> The type transformer is a list of rules for how to derive all of the other 
> operands from that one key type. Conceptually similar to 
> LLVMScalarOrSameVectorWidth or LLVMHalfElementsVectorType in Intrinsics.td. 
> Some types are fixed and don't vary by the key type. Like the size_t vl 
> operand or a store intrinsic returning void.  There is no separate place to 
> put a base type.
Oh I see, I hadn't appreciated that TypeRange got split up and each character 
was a whole separate intrinsic, I had misinterpreted it as it being a list of 
the types of arguments, i.e. an N-character string for an (N-1)-argument (plus 
return type) intrinsic that you could then use as a base and apply 
transformations too (e.g. "if" for a float-to-int intrinsic, with "vv" etc 
giving you a vectorised versions) and so was confused as to why the 
void/size_t/ptrdiff_t/uint8_t/bool-ness couldn't just be pushed into the 
TypeRange and the corresponding transforms left as "e". But, how _would_ you 
define vector float-to-int (and back) conversions with this scheme then?

On a related note, I feel one way to make this less obfuscated is change 
v/w/q/o to be v1/v2/v4/v8 (maybe with the 1 being optional, don't really care), 
and is also more extensible in future rather than ending up with yet more 
alphabet soup, though it does change the parsing from being a list of 
characters to a list of strings.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:259-260
+
+LMULType ::operator*=(unsigned RHS) {
+  this->Log2LMUL = this->Log2LMUL + RHS;
+  return *this;

jrtc27 wrote:
> That's not how multiplication works. This is exponentiation. Multiplication 
> would be `Log2LMul + log2(RHS)`. Please don't abuse operators like this.
This seems like it must be broken, but since we don't do widening or narrowing 
in this patch we didn't notice?


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[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:567
+  // Compute type transformers
+  for (char I : Transformer.take_front(Transformer.size() - 1)) {
+switch (I) {

craig.topper wrote:
> jrtc27 wrote:
> > craig.topper wrote:
> > > Can we do Transformer = Transformer.drop_back() right before this loop. 
> > > That take_front code is harder to think about.
> > Or would it be better as a pop_back in the switch above?
> I don't think StringRef has a pop_back.
Right, and it's an immutable data structure anyway so you'd need to have to 
deal with two return values. Never mind then.


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Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:567
+  // Compute type transformers
+  for (char I : Transformer.take_front(Transformer.size() - 1)) {
+switch (I) {

jrtc27 wrote:
> craig.topper wrote:
> > Can we do Transformer = Transformer.drop_back() right before this loop. 
> > That take_front code is harder to think about.
> Or would it be better as a pop_back in the switch above?
I don't think StringRef has a pop_back.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper requested changes to this revision.
craig.topper added a comment.
This revision now requires changes to proceed.

Dropping my approval pending @jrtc27 comments.


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jrtc27 added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:116
+  D = 1 << 2,
+  ZFH = 1 << 3
+};

Zfh



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:241
+  case 8:
+ExpResult = Log2LMUL + 3;
+break;

Please be consistent and use Log2 rather than Exp



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:259-260
+
+LMULType ::operator*=(unsigned RHS) {
+  this->Log2LMUL = this->Log2LMUL + RHS;
+  return *this;

That's not how multiplication works. This is exponentiation. Multiplication 
would be `Log2LMul + log2(RHS)`. Please don't abuse operators like this.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:325
+  std::string  = BuiltinStr;
+  if (IsVoid) {
+S = "v";

This really needs to be an enum not a bunch of mutually-exclusive booleans, 
which I though I suggested in the past?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:450-451
+  S += "uint";
+// Vector bool is special case, the formulate is `vbool_t =
+// MVT::nxv<64/N>i1` ex. vbool16_t = MVT::
+if (IsBool && isVector())

Please try and avoid wrapping code across lines



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:624
+  }
+  // Init RISCV_Extensions
+  for (const auto  : OutInTypes) {

Blank line



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:685
+  OS << "};\n";
+  OS << "break;\n";
+}

This is missing indentation?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:870
+PrevDef = Def.get();
+OS << "case RISCV::BI__builtin_rvv_" << Def->getName() << ":\n";
+  }

Needs indentation?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:567
+  // Compute type transformers
+  for (char I : Transformer.take_front(Transformer.size() - 1)) {
+switch (I) {

craig.topper wrote:
> Can we do Transformer = Transformer.drop_back() right before this loop. That 
> take_front code is harder to think about.
Or would it be better as a pop_back in the switch above?


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craig.topper added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:66
+//  element type which is bool
+//   0: void type, ignores "t"
+//   z: size_t, ignores "t"

jrtc27 wrote:
> khchen wrote:
> > jrtc27 wrote:
> > > Then why aren't these just base types? We don't have to follow the 
> > > brain-dead nature of printf.
> > Basically builtin interface is instantiated by the "base type + LMUL" with 
> > type transformers. But in some intrinsic function we need a specific type 
> > regardless "base type + LMUL"
> > ex. `vuint32m2_t vssrl_vx_u32m2_vl (vuint32m2_t op1, uint8_t op2, size_t 
> > vl);`
> Then fix the way you define these? This is just bad design IMO.
For each signature there is effectively a single key type that is a vector. The 
type transformer is a list of rules for how to derive all of the other operands 
from that one key type. Conceptually similar to LLVMScalarOrSameVectorWidth or 
LLVMHalfElementsVectorType in Intrinsics.td. Some types are fixed and don't 
vary by the key type. Like the size_t vl operand or a store intrinsic returning 
void.  There is no separate place to put a base type.


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[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:56
+//
+//   e: type of "t" as is (identity)
+//   v: computes a vector type whose element type is "t" for the current LMUL

khchen wrote:
> jrtc27 wrote:
> > Do we really need to invent an esoteric DSL?
> I think this is different design choose.
> Current design is based on 
> https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi/-/blob/EPI/clang/include/clang/Basic/epi_builtins.td,
>  personally I think it makes td file more simpler.
> 
> Of course we can make td file more complex little bit and list all legal type 
> and combination like 
> https://github.com/isrc-cas/rvv-llvm/blob/rvv-iscas/clang/include/clang/Basic/riscv_vector.td
>  did.
> 
> In fact, I don't have a strong opinion on which one is better
> 
> ps. current approach is similar to arm_sve.td design, maybe they know the 
> some critical reason.
I just find it really obfuscates things when we have all these magic character 
sequences.



Comment at: clang/include/clang/Basic/riscv_vector.td:66
+//  element type which is bool
+//   0: void type, ignores "t"
+//   z: size_t, ignores "t"

khchen wrote:
> jrtc27 wrote:
> > Then why aren't these just base types? We don't have to follow the 
> > brain-dead nature of printf.
> Basically builtin interface is instantiated by the "base type + LMUL" with 
> type transformers. But in some intrinsic function we need a specific type 
> regardless "base type + LMUL"
> ex. `vuint32m2_t vssrl_vx_u32m2_vl (vuint32m2_t op1, uint8_t op2, size_t vl);`
Then fix the way you define these? This is just bad design IMO.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM




Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:908
+
+// Compute Buitlin types
+SmallVector ProtoMaskSeq = ProtoSeq;

Buitlin->Builtin


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 326585.
khchen marked 10 inline comments as done.
khchen added a comment.

1. address Craig's comments.
2. use ListSeparator in some code snippet.


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  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:678
+else
+  OS << ", Ops[" << Twine(static_cast(Idx)) << "]->getType()";
+  }

We don't need Twine here



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:684
+  if (hasVL())
+OS << ", Ops[" + utostr(getNumOperand() - 1) + "]->getType()";
+  OS << "};\n";

Replace + with << and drop utostr



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:691
+  if (getNumOperand() > 0) {
+OS << "op" << Twine(CTypeOrder[0]);
+for (unsigned i = 1; i < CTypeOrder.size(); ++i)

Drop Twine



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:693
+for (unsigned i = 1; i < CTypeOrder.size(); ++i)
+  OS << ", op" << Twine(CTypeOrder[i]);
+  }

Drop Twine



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:700
+for (unsigned i = 1; i < InputTypes.size(); ++i)
+  OS << ", (" << InputTypes[i]->getTypeStr() + ")(op" << Twine(i) << ")";
+  }

Drop Twine



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:710
+  if (getNumOperand() > 0) {
+OS << InputTypes[CTypeOrder[0]]->getTypeStr() + " op0";
+for (unsigned i = 1; i < CTypeOrder.size(); ++i)

Replace + with <<



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:713
+  OS << ", " << InputTypes[CTypeOrder[i]]->getTypeStr() << " op"
+ << Twine(i);
+  }

Drop Twine



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:789
+auto T = computeType('h', Log2LMUL, "v");
+// first.
+if (T.hasValue())

This comment looks incomplete



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:872
+  PrevDef->emitCodeGenSwitchBody(OS);
+  OS << "break;\n";
+}

Should we sink the printing of break; into emitCodeGenSwitchBody so its not 
repeated after the other call to emitCodeGenSwitchBody?


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

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khchen updated this revision to Diff 326309.
khchen added a comment.

refine comment


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  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
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  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:873
+  // Dump switch body when the ir name changes from previous iteration.
+  RVVIntrinsic *PrevDef = Defs.begin()->get();
+  for (auto  : Defs) {

khchen wrote:
> craig.topper wrote:
> > Can we remember the PrevIRName StringRef instead?
> I don't think so. We need `PrevDef` to emitCodeGenSwitchBody.
Of course we do. Sorry about that.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:270
+  IsPointer(false), IsSize_t(false), IsPtrdiff_t(false),
+  ElementBitwidth(~0U), Scale(0) {
+  applyBasicType();

craig.topper wrote:
> Why is ElementBitwidth default ~0. Wouldn't 0 also be an invalid value?
I followed SVE did, but you are right, 0 is better.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:714
+  // Emit function arguments
+  if (CTypeOrder.size() > 1) {
+OS << InputTypes[CTypeOrder[0]]->type_str() + " op0";

craig.topper wrote:
> Why is this > 1 and not >= 1 or !CTypeOrder.empty()?
Thanks, it's bug when I refactor code from output input vector to input only 
vector...



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:757
+  OS << "#error \"Vector intrinsics require the vector extension.\"\n";
+  OS << "#else\n\n";
+

craig.topper wrote:
> Can we just #endif here instead of the #else? If the error is emitted the 
> preprocessor should stop and not process the rest of the file. Then we don't 
> need to close it at the bottom of the file.
Good point. Thanks. I should think more when I copied code from SVE.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:873
+  // Dump switch body when the ir name changes from previous iteration.
+  RVVIntrinsic *PrevDef = Defs.begin()->get();
+  for (auto  : Defs) {

craig.topper wrote:
> Can we remember the PrevIRName StringRef instead?
I don't think so. We need `PrevDef` to emitCodeGenSwitchBody.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1027
+return false;
+  bool NeedOR = false;
+  OS << "#if";

craig.topper wrote:
> I think you can use ListSeparator for this. It keeps track of the separator 
> string and whether the first item has been printed. It's most often used with 
> loops, but it should work here. I think there are many examples uses in 
> llvm/utils/TableGen
thanks, it's more elegant.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 326300.
khchen marked 21 inline comments as done.
khchen added a comment.

1. Rename Dump to Print.
2. Address Craig's comments, thanks for your patient.


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  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:70
+  // passing to the BUILTIN() macro in Builtins.def.
+  const std::string _str() const { return BuiltinStr; }
+

These method names should use CamelCase and start with "get"



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:102
+  // Compute and record a string for legal type.
+  void compute_builtin_str();
+  // Compute and record a builtin RVV vector type string.

These should use CamelCase per llvm coding style.

Might be better named init*Str instead of compute. compute makes me think they 
are going to return something, but that might just be me.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:267
+RVVType::RVVType(BasicType BT, int Log2LMUL, StringRef prototype)
+: BT(BT), LMUL(LMULType(Log2LMUL)), IsFloat(false), IsBool(false),
+  IsSigned(true), IsImmediate(false), IsVoid(false), IsConstant(false),

You can initialize the bools to false with " = false" where they are declared 
in the class body then you don't need to mention them all here. Similar for 
Scale and ElementBitWidth.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:270
+  IsPointer(false), IsSize_t(false), IsPtrdiff_t(false),
+  ElementBitwidth(~0U), Scale(0) {
+  applyBasicType();

Why is ElementBitwidth default ~0. Wouldn't 0 also be an invalid value?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:333
+return;
+  } else if (IsSize_t) {
+S = "z";

You drop the else since the if above returned.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:618
+  if (NewMangledName.empty())
+MangledName = Twine(NewName.split("_").first).str();
+  else

I don't think we need to go through Twine here. We should be able to call str() 
directly on first.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:621
+MangledName = NewMangledName.str();
+  if (Suffix.size())
+Name += "_" + Suffix.str();

!Suffix.empty()



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:640
+  InputTypes.assign(OutInTypes.begin() + 1, OutInTypes.end());
+  for (unsigned i = 0; i < InputTypes.size(); ++i)
+CTypeOrder.push_back(i);

CTypeOrder.resize(InputTypes.size());
std::iota(CTypeOrder.begin(), CTypeOrder.end(), 0);



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:710
+void RVVIntrinsic::emitMangledFuncDef(raw_ostream ) const {
+  OS << Twine(OutputType->type_str() + Twine(" ")).str();
+  OS << getMangledName();

Can't we just print OutputType->type_str() and " " to OS separately? We 
shouldn't need to concat them into a Twine first.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:714
+  // Emit function arguments
+  if (CTypeOrder.size() > 1) {
+OS << InputTypes[CTypeOrder[0]]->type_str() + " op0";

Why is this > 1 and not >= 1 or !CTypeOrder.empty()?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:720
+  OS << "){\n";
+  OS << "  return " + getName() + "(";
+  // Emit parameter variables

Replace the + operators with <<



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:722
+  // Emit parameter variables
+  if (CTypeOrder.size() > 1) {
+OS << "op0";

Same here, why is this >1 and not >=1 or !CTypeOrder.empty()?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:749
+
+  OS << "#ifndef _RISCV_VECTOR_H\n";
+  OS << "#define _RISCV_VECTOR_H\n\n";

Looks like other headers use 2 underscores at the beginning of their include 
guard.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:757
+  OS << "#error \"Vector intrinsics require the vector extension.\"\n";
+  OS << "#else\n\n";
+

Can we just #endif here instead of the #else? If the error is emitted the 
preprocessor should stop and not process the rest of the file. Then we don't 
need to close it at the bottom of the file.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:767
+  // Dump RVV boolean types.
+  auto dumpType = [&](auto T) {
+OS << "typedef " << T->clang_builtin_str() << " " << T->type_str() << 
";\n";

I'd recommend calling this printType.  dump made me think it was printing for 
debug like the dump() functions found in many LLVM classes.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:799
+  // D implies F
+  OS << "#if defined(__riscv_f) || defined(__riscv_d)\n";
+  for (int Log2LMUL : Log2LMULs) {

I think we only need to check __riscv_f here?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:836
+  return;
+OS << StringRef(
+"static inline 

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 326107.
khchen marked 2 inline comments as done.
khchen added a comment.

address https://reviews.llvm.org/D95016?id=324197#inline-912573


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:899
+// (operand) in ProtoSeq. ProtoSeq[0] is output operand.
+SmallVector ProtoSeq;
+const StringRef Primaries("evwqom0ztc");

craig.topper wrote:
> I think this is something like
> 
> ```
> while (!Prototypes.empty()) {
>  auto Idx = Prototypes.find_first_of(Primaries);
>  assert(Idx != StringRef::npos);
>  ProtoSeq.push_back(Prototypes.slice(0, Idx+1).str());
>  Prototypes = Prototypes.drop_front(Idx+1);
> }
> ```
> 
> Which might be easier to understand.
Thanks, it's clear.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1016
+  SmallVector ExtVector;
+  // D implies F
+  if (Extents & RISCV_Extension::F) {

craig.topper wrote:
> I don't understand this. It says D implies F but we're checking for F. So 
> that seems like F implies D.
Remove extension implying rule. 
I thought we don't need to consider implying rule because it's clang's 
responsibility. 
The original thinking was when predecessor "only" defines `__riscv_d`, and 
floating instruction also need to supported. But in fact,  when enabling 
__riscv_d predecessor will also define `__riscv_f`.



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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 326104.
khchen marked 10 inline comments as done.
khchen added a comment.

1. Rebase
2. Address Craig's comments.
3. Change the operand orders of builtin to the same order of IR intrinsics.


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:567
+  // Compute type transformers
+  for (char I : Transformer.take_front(Transformer.size() - 1)) {
+switch (I) {

Can we do Transformer = Transformer.drop_back() right before this loop. That 
take_front code is harder to think about.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:148
+  // If HasMask, this flag states that this builtin has a maskedoff operand. It
+  // is always the first operand.
+  bit HasMaskedOffOperand = true;

Isn't mask the first operand maskedoff the second operand?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:157
+  ArrayRef getIntrinsicTypes() const { return IntrinsicTypes; }
+  std::string getIRName() const { return IRName; }
+  uint8_t getRISCV_Extensions() const { return RISCV_Extensions; }

Return by const reference or use StringRef.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:175
+
+using TypeString = std::string;
+class RVVEmitter {

Why not just use std::string in the one place this is used?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:862
+
+  // The same intrinsic name has the same switch body.
+  llvm::StringMap, 128>> DefsSet;

Might be better to just sort the vector by the IR name and then walk the vector 
looking for the boundaries where the name changes from the previous iteration.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:899
+// (operand) in ProtoSeq. ProtoSeq[0] is output operand.
+SmallVector ProtoSeq;
+const StringRef Primaries("evwqom0ztc");

I think this is something like

```
while (!Prototypes.empty()) {
 auto Idx = Prototypes.find_first_of(Primaries);
 assert(Idx != StringRef::npos);
 ProtoSeq.push_back(Prototypes.slice(0, Idx+1).str());
 Prototypes = Prototypes.drop_front(Idx+1);
}
```

Which might be easier to understand.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:970
+  if (It != LegalTypes.end())
+return Optional(&(It->second));
+  if (IllegalTypes.count(Idx))

Why does this need to explicitly create an Optional? Shouldn't we just be able 
to return &(It->second)?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:990
+  // Collect the same extension intrinsic in the one set for arch guard marco.
+  DenseMap, 256>> DefsSet;
+  for (auto  : Defs) {

Could we maybe just sort the original vector by extension and just loop over 
it. Keep track of the extensions from previous iteration and emit the guard 
when this iteration doesn't match the previous iteration.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1012
+
+SmallVector RVVEmitter::getExtStrings(uint8_t Extents) {
+  if (Extents == 0)

This is only called in one place which immediate loops over and prints the 
contents. Could we just pass the raw_ostream in here and do the printing 
directly?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1015
+return {};
+  SmallVector ExtVector;
+  // D implies F

Even if we don't print directly. This can be a vector of StringRef. These are 
all string literals.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1016
+  SmallVector ExtVector;
+  // D implies F
+  if (Extents & RISCV_Extension::F) {

I don't understand this. It says D implies F but we're checking for F. So that 
seems like F implies D.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 324197.
khchen added a comment.

remove float32_t and float64_t to avoid collisions with other project.


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:2
 
-RISCVV_BUILTIN(vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_m_vl, "q4Ssq4bq4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_vl, "q2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_m_vl, "q2Siq2bq2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_vl, "q1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_vl, "q16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_m_vl, "q16Scq16bq16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_vl, "q8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_m_vl, "q8Ssq8bq8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_vl, "q4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_m_vl, "q4Siq4bq4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_vl, "q2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_vl, "q32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_m_vl, "q32Scq32bq32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_vl, "q16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_m_vl, "q16Ssq16bq16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_vl, "q8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_m_vl, "q8Siq8bq8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_vl, "q4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_vl, "q64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_m_vl, "q64Scq64bq64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_vl, "q32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_m_vl, "q32Ssq32bq32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_vl, "q16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_m_vl, "q16Siq16bq16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_vl, "q8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_vl, "q4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_m_vl, "q4Scq4bq4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_vl, "q2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_m_vl, "q2Ssq2bq2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_vl, "q1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_m_vl, "q1Siq1bq1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_vl, "q2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_m_vl, "q2Scq2bq2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_vl, "q1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_m_vl, "q1Ssq1bq1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_vl, "q1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_m_vl, "q1Scq1bq1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_vl, "q8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_m_vl, "q8Scq8bq8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_vl, "q4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_m_vl, "q4Ssq4bq4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_vl, "q2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_m_vl, "q2Siq2bq2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_vl, "q1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_vl, "q16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_m_vl, "q16Scq16bq16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_vl, "q8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_m_vl, "q8Ssq8bq8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_vl, "q4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_m_vl, "q4Siq4bq4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_vl, "q2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_vl, "q32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_m_vl, "q32Scq32bq32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_vl, "q16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_m_vl, "q16Ssq16bq16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_vl, "q8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_m_vl, "q8Siq8bq8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_vl, "q4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_vl, "q64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_m_vl, "q64Scq64bq64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_vl, "q32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_m_vl, "q32Ssq32bq32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_vl, "q16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_m_vl, "q16Siq16bq16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_vl, "q8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_vl, "q4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_m_vl, "q4Scq4bq4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_vl, "q2Ssq2SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_m_vl, 

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 322300.
khchen added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95016/new/

https://reviews.llvm.org/D95016

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:2
 
-RISCVV_BUILTIN(vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_m_vl, "q4Ssq4bq4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_vl, "q2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_m_vl, "q2Siq2bq2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_vl, "q1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_vl, "q16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_m_vl, "q16Scq16bq16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_vl, "q8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_m_vl, "q8Ssq8bq8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_vl, "q4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_m_vl, "q4Siq4bq4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_vl, "q2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_vl, "q32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_m_vl, "q32Scq32bq32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_vl, "q16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_m_vl, "q16Ssq16bq16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_vl, "q8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_m_vl, "q8Siq8bq8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_vl, "q4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_vl, "q64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_m_vl, "q64Scq64bq64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_vl, "q32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_m_vl, "q32Ssq32bq32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_vl, "q16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_m_vl, "q16Siq16bq16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_vl, "q8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_vl, "q4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_m_vl, "q4Scq4bq4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_vl, "q2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_m_vl, "q2Ssq2bq2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_vl, "q1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_m_vl, "q1Siq1bq1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_vl, "q2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_m_vl, "q2Scq2bq2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_vl, "q1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_m_vl, "q1Ssq1bq1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_vl, "q1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_m_vl, "q1Scq1bq1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_vl, "q8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_m_vl, "q8Scq8bq8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_vl, "q4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_m_vl, "q4Ssq4bq4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_vl, "q2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_m_vl, "q2Siq2bq2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_vl, "q1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_vl, "q16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_m_vl, "q16Scq16bq16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_vl, "q8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_m_vl, "q8Ssq8bq8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_vl, "q4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_m_vl, "q4Siq4bq4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_vl, "q2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_vl, "q32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_m_vl, "q32Scq32bq32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_vl, "q16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_m_vl, "q16Ssq16bq16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_vl, "q8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_m_vl, "q8Siq8bq8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_vl, "q4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_vl, "q64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_m_vl, "q64Scq64bq64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_vl, "q32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_m_vl, "q32Ssq32bq32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_vl, "q16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_m_vl, "q16Siq16bq16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_vl, "q8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_vl, "q4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_m_vl, "q4Scq4bq4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_vl, "q2Ssq2SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_m_vl, 

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 322297.
khchen marked 3 inline comments as done.
khchen added a comment.

1. address Jim's comment.
2. remove suffix `_vl` according by 
https://github.com/riscv/rvv-intrinsic-doc/pull/64


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95016/new/

https://reviews.llvm.org/D95016

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/docs/CommandGuide/tblgen.rst:141
 
-  Generate RISCV compressed instructions.
+  Generate RISC-V compressed instructions.
 

It is typo fix. Could you fix it in a separate patch?


Repository:
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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:2
 
-RISCVV_BUILTIN(vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_m_vl, "q4Ssq4bq4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_vl, "q2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_m_vl, "q2Siq2bq2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_vl, "q1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_vl, "q16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_m_vl, "q16Scq16bq16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_vl, "q8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_m_vl, "q8Ssq8bq8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_vl, "q4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_m_vl, "q4Siq4bq4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_vl, "q2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_vl, "q32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_m_vl, "q32Scq32bq32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_vl, "q16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_m_vl, "q16Ssq16bq16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_vl, "q8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_m_vl, "q8Siq8bq8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_vl, "q4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_vl, "q64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_m_vl, "q64Scq64bq64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_vl, "q32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_m_vl, "q32Ssq32bq32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_vl, "q16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_m_vl, "q16Siq16bq16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_vl, "q8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_vl, "q4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_m_vl, "q4Scq4bq4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_vl, "q2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_m_vl, "q2Ssq2bq2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_vl, "q1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_m_vl, "q1Siq1bq1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_vl, "q2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_m_vl, "q2Scq2bq2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_vl, "q1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_m_vl, "q1Ssq1bq1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_vl, "q1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_m_vl, "q1Scq1bq1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_vl, "q8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_m_vl, "q8Scq8bq8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_vl, "q4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_m_vl, "q4Ssq4bq4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_vl, "q2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_m_vl, "q2Siq2bq2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_vl, "q1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_vl, "q16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_m_vl, "q16Scq16bq16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_vl, "q8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_m_vl, "q8Ssq8bq8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_vl, "q4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_m_vl, "q4Siq4bq4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_vl, "q2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_vl, "q32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_m_vl, "q32Scq32bq32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_vl, "q16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_m_vl, "q16Ssq16bq16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_vl, "q8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_m_vl, "q8Siq8bq8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_vl, "q4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_vl, "q64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_m_vl, "q64Scq64bq64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_vl, "q32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_m_vl, "q32Ssq32bq32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_vl, "q16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_m_vl, "q16Siq16bq16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_vl, "q8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_vl, "q4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_m_vl, "q4Scq4bq4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_vl, "q2Ssq2SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_m_vl, 

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added inline comments.



Comment at: clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c:10
+
+// ASM-NOT: warning
+#include 

jrtc27 wrote:
> Asm checks are discouraged in Clang. If you want to check for Clang warnings, 
> use -verify, and in this case you want `// expected-no-diagnostics`.
RVV is the scalable vector type similar to SVE, so I added this check.
please see https://reviews.llvm.org/D82943.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:48-55
+  bool Float, Bool, Signed;
+  // Constant indices are "int", but have the constant expression.
+  bool Immediate;
+  bool Void;
+  // const qualifier.
+  bool Constant;
+  bool Pointer;

jrtc27 wrote:
> These are poor names; many of them don't sound like bools, and are some of 
> them not mutually exclusive? If so, an enum would be better.
Those variables are used to descript the property of RVVType, I think maybe 
rename as IsXXX could become more clear.
ps. I implement RVVType similar to SveType [[ 
https://github.com/llvm/llvm-project/blob/main/clang/utils/TableGen/SveEmitter.cpp#L68-L70
 | did ]].
Do you mean only mutually exclusive property should be represented in an enum?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:308
+return false;
+  if (Float && ElementBitwidth == 8)
+return false;

jrtc27 wrote:
> or 1? Clearer to move this into the switch below IMO.
This checks illegal type float8_t .


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 319488.
khchen marked 21 inline comments as done.
khchen added a comment.

1. address @jrtc27's comments. I really appreciate your help very much.
2. use downstream test generator and move all tests to rvv-intrinsics-generic 
and rvv-intrinsics.


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  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:161
+  // This builtin is valid for the given exponental LMULs.
+  list ELMUL = [0, 1, 2, 3, -1, -2, -3];
+

khchen wrote:
> HsiangKai wrote:
> > EMUL according to specification.
> Here ELMUL means  exponental LMUL
Log2LMUL would be a clearer name and more consistent with how things like this 
are named elsewhere in LLVM


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.



Comment at: clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c:7-8
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d 
-target-feature +experimental-v \
+// RUN:   -target-feature +experimental-zfh -Werror -Wall -o - %s >/dev/null 
2>%t
+// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
+

This is poor style, but should be unnecessary per my comment below



Comment at: clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c:10
+
+// ASM-NOT: warning
+#include 

Asm checks are discouraged in Clang. If you want to check for Clang warnings, 
use -verify, and in this case you want `// expected-no-diagnostics`.



Comment at: clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c:38
+vint8m1_t test_vadd_vv_i8m1_m_vl(vbool8_t arg_1, vint8m1_t arg_2, vint8m1_t 
arg_3, vint8m1_t arg_4, size_t arg_5) {
+//
+  return vadd_m_vl(arg_1, arg_2, arg_3, arg_4, arg_5);

Delete



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:36
+public:
+  ELMULType() : ELMULType(0) {}
+  ELMULType(int ELMUL);

Surely being uninitialised is an error and we expect to always have it 
specified in the source?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:48-55
+  bool Float, Bool, Signed;
+  // Constant indices are "int", but have the constant expression.
+  bool Immediate;
+  bool Void;
+  // const qualifier.
+  bool Constant;
+  bool Pointer;

These are poor names; many of them don't sound like bools, and are some of them 
not mutually exclusive? If so, an enum would be better.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:55
+  bool Pointer;
+  bool SIZE_T, PtrDiff_T;
+  unsigned ElementBitwidth;

Capitalisation.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:56
+  bool SIZE_T, PtrDiff_T;
+  unsigned ElementBitwidth;
+  VScaleVal Vscale;

Capital W.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:57
+  unsigned ElementBitwidth;
+  VScaleVal Vscale;
+  bool Valid;

VScale. Or just drop the V and use Scale?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:87-95
+  bool isHalfVector() const {
+return isVector() && Float && ElementBitwidth == 16;
+  }
+  bool isFloatVector() const {
+return isVector() && Float && ElementBitwidth == 32;
+  }
+  bool isDoubleVector() const {

though at that point the wrappers are a bit unnecessary as they only seem to be 
used once.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:109
+  // Compute and record a string for legal type.
+  void compute_builtin_str();
+  // Compute and record a builtin RVV vector type string.

Camel-case?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:121
+
+enum class RISCV_Extension : uint8_t {
+  Basic = 0,

Using an `enum class` for a bitmask doesn't make much sense.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:294
+
+// type\lmul |1/8|1/4  |1/2 |1   |2   |4|8
+//   |-- | |--- |--- || |

Please make sure there's at least 1 space around things



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:308
+return false;
+  if (Float && ElementBitwidth == 8)
+return false;

or 1? Clearer to move this into the switch below IMO.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:315
+// Check Vscale is 1,2,4,8,16,32,64
+return (V <= 64 && countPopulation(V) == 1);
+  case 16:

isPowerOf2_32 from llvm/Support/MathExtras.h



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:380
+  }
+  if (!Float && !Bool) {
+if (Signed)

Move into the !Float above



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:386
+  }
+  if (Immediate) {
+assert(!Float && "fp immediates are not supported");

Move into the !Float above



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:512
+
+void RVVType::applyModifier(StringRef transformer) {
+  if (transformer.empty())

Capital T



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:693
+
+void RVVIntrinsic::emitFuncDelc(raw_ostream , bool IsMangled) const {
+  // Index 0 is output type

Decl?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:714
+  OS << "{\n";
+  OS << Twine("  return " + getName() + "(").str();
+  // Emit parameter variables

This is odd, why not `OS << "  return " + getName() + "(";` or `OS << "  return 
" << getName() << "(";`



Comment at: 

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:161
+  // This builtin is valid for the given exponental LMULs.
+  list ELMUL = [0, 1, 2, 3, -1, -2, -3];
+

HsiangKai wrote:
> EMUL according to specification.
Here ELMUL means  exponental LMUL


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 319000.
khchen marked 7 inline comments as done.
khchen added a comment.

1. address @HsiangKai's comments
2. remove test generator to make td simpler.
3. remove MangledSuffix, it should be MangledName


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  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:128
+  // after an underscore (_). It is instantiated like Prototype.
+  string MangledSuffix = managed_suffix;
+

mangled_suffix



Comment at: clang/include/clang/Basic/riscv_vector.td:147
+
+  // If HasMask, this flag states that this builtin has a merge operand. It is
+  // always the first operand.

"has a maskedoff operand"



Comment at: clang/include/clang/Basic/riscv_vector.td:149
+  // always the first operand.
+  bit HasMergeOperand = true;
+

Propose to use HasMaskedOffOperand.



Comment at: clang/include/clang/Basic/riscv_vector.td:161
+  // This builtin is valid for the given exponental LMULs.
+  list ELMUL = [0, 1, 2, 3, -1, -2, -3];
+

EMUL according to specification.



Comment at: clang/include/clang/Basic/riscv_vector.td:191
+multiclass GenRVVBuiltin {
+ if !or(!eq(gen_all, true), !eq(gen, true))  then {

mangled_suffix


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 318447.
khchen marked 2 inline comments as done.
khchen added a comment.

1. do not need to manually define new op in gen-rvv-tests.py.
2. do not need to manually add new op define in ALL marco.


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  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  clang/utils/TestUtils/gen-rvv-tests.py
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen marked 7 inline comments as done.
khchen added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:191
+defvar suffix = s_p[1];
+defvar prototype = s_p[2];
+

Paul-C-Anagnostopoulos wrote:
> Well now, thanks for highlighting an inconsistency I did not know about. The 
> documentation says that x[0] produces a list of the 0th element of x, which 
> is why I suggested using !head. But that is true only in certain contexts, 
> such as when x is a defvar. Otherwise it produces the single element. Ouch.
I also thanks for your suggestion. When I was trying to use `!head(s_p[1])` but 
it didn't work, and then I found giving the index is clearer.



Comment at: clang/include/clang/Basic/riscv_vector.td:204
+// op_list in gen-riscv-v-tests.sh.
+#ifdef ALL
+#define VADD

jrtc27 wrote:
> Probably nicer to have a notion of a builtin group and allow the records to 
> be filtered (with the default being to process all of them). Depending on 
> what's still to come you could even use NAME automatically as the group for 
> RVVBinBuiltinSet's RVV(Bin)Builtins given that's always the lowercase version 
> of the macro guarding the definitions at the moment.
@jrtc27 Sorry, I still have no idea to do that, could you please elaborate it 
more?
In our downstream implementation, some builtins inherit `RVVBuiltin` class 
directly. Does your solution still work in this situation?


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 318423.
khchen added a comment.

1. address @craig.topper's comment.
2. rewrite script as python.

I'm still have no idea to make generating tests mechanism be more elegant...


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  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  clang/utils/TestUtils/gen-riscv-v-tests.sh
  clang/utils/TestUtils/gen-rvv-tests.py
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:772
+  // Parse records
+  SmallVector, 512> Defs;
+  std::vector RV = Records.getAllDerivedDefinitions("RVVBuiltin");

This getAllDerivedDefinitions, loop, call createRVVIntrinsic is repeated in 4 
places. I realize it was copied from the NeonEmitter to the SveEmitter, but I 
don't think we should repeat that.

Maybe just sink the loop and getAllDerivedDefinitions into createRVVIntrinsic, 
rename it createRVVIntrinsics and have it return the Defs vector?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:772
+  // Parse records
+  SmallVector, 512> Defs;
+  std::vector RV = Records.getAllDerivedDefinitions("RVVBuiltin");

craig.topper wrote:
> This getAllDerivedDefinitions, loop, call createRVVIntrinsic is repeated in 4 
> places. I realize it was copied from the NeonEmitter to the SveEmitter, but I 
> don't think we should repeat that.
> 
> Maybe just sink the loop and getAllDerivedDefinitions into 
> createRVVIntrinsic, rename it createRVVIntrinsics and have it return the Defs 
> vector?
Given what I know about the namer of builtins we need, there's no way we're 
going to fit in this 512 right? Except if we're only generate a subset of 
tests? If that's the case probably should just use a std::vector.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:772
+  // Parse records
+  SmallVector, 512> Defs;
+  std::vector RV = Records.getAllDerivedDefinitions("RVVBuiltin");

craig.topper wrote:
> craig.topper wrote:
> > This getAllDerivedDefinitions, loop, call createRVVIntrinsic is repeated in 
> > 4 places. I realize it was copied from the NeonEmitter to the SveEmitter, 
> > but I don't think we should repeat that.
> > 
> > Maybe just sink the loop and getAllDerivedDefinitions into 
> > createRVVIntrinsic, rename it createRVVIntrinsics and have it return the 
> > Defs vector?
> Given what I know about the namer of builtins we need, there's no way we're 
> going to fit in this 512 right? Except if we're only generate a subset of 
> tests? If that's the case probably should just use a std::vector.
Oops that should have said "number of builtins we need"


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Paul C. Anagnostopoulos via Phabricator via cfe-commits]

Paul-C-Anagnostopoulos added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:191
+defvar suffix = s_p[1];
+defvar prototype = s_p[2];
+

Well now, thanks for highlighting an inconsistency I did not know about. The 
documentation says that x[0] produces a list of the 0th element of x, which is 
why I suggested using !head. But that is true only in certain contexts, such as 
when x is a defvar. Otherwise it produces the single element. Ouch.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

marked some inline comments as done except the test generator related part.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 318102.
khchen marked 74 inline comments as done.
khchen added a comment.

1. use exponent LMUL.
2. address @Paul-C-Anagnostopoulos 's comment.


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  clang/utils/TestUtils/gen-riscv-v-tests.sh
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:881
+if (!Def->hasSideEffects())
+  OS << "\"n\")\n";
+else

"n" refers to "nothrow" which means the builtin doesn't throw a C++ exception. 
None of our builtins throw a C++ exceptions so they should all have "n" as far 
as I know.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Liao Chunyu via Phabricator via cfe-commits]

liaolucy added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:157
+  // Reads or writes "memory" or has other side-effects.
+  bit HasSideEffects = 0;
+

 Where will it be used？Will just marking sideeffect in the 
llvm/include/llvm/IR/IntrinsicsRISCV.td file not meet the requirement? Thanks.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Paul C. Anagnostopoulos via Phabricator via cfe-commits]

Paul-C-Anagnostopoulos added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:144
+  // This builtin has a masked form.
+  bit HasMask = 1;
+

May I recommend that you use 'true' and 'false' for boolean literals.



Comment at: clang/include/clang/Basic/riscv_vector.td:190
+defvar suffix = !head(!tail(s_p));
+defvar prototype = !head(!tail(!tail(s_p)));
+

If you find it clearer, you can code !head(s_p[1]) and !head(s_p[2]).

TableGen needs an !element() operator.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 317919.
khchen added a comment.

apply clang-format


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  clang/utils/TestUtils/gen-riscv-v-tests.sh
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 317916.
khchen added a comment.

address reviewer's suggestion, do not include test generator related part.


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  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  clang/utils/TestUtils/gen-riscv-v-tests.sh
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

Really thanks for @jrtc27 and @craig.topper 's review suggestions.
Before I upload the patch, I would want to discuss about the test generator, 
because if we don't want to upstream it, I don't need to fix some issues which 
are addressed by reivewers.

@asb @jrtc27 @craig.topper @evandro @HsiangKai : 
What's your opinion about the intrinsic test generator, should we really need 
to upstream it?
I'm just afraid when any community people want to contribute this part, they 
need to rewrite it again by themselves.
In the future we can remove test generator when all intrinsic are upstreamed.

However, I'm also ok to remove test generator if more people prefer on removing 
it.




Comment at: clang/include/clang/Basic/riscv_vector.td:56
+//
+//   e: type of "t" as is (identity)
+//   v: computes a vector type whose element type is "t" for the current LMUL

jrtc27 wrote:
> Do we really need to invent an esoteric DSL?
I think this is different design choose.
Current design is based on 
https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi/-/blob/EPI/clang/include/clang/Basic/epi_builtins.td,
 personally I think it makes td file more simpler.

Of course we can make td file more complex little bit and list all legal type 
and combination like 
https://github.com/isrc-cas/rvv-llvm/blob/rvv-iscas/clang/include/clang/Basic/riscv_vector.td
 did.

In fact, I don't have a strong opinion on which one is better

ps. current approach is similar to arm_sve.td design, maybe they know the some 
critical reason.



Comment at: clang/include/clang/Basic/riscv_vector.td:66
+//  element type which is bool
+//   0: void type, ignores "t"
+//   z: size_t, ignores "t"

jrtc27 wrote:
> Then why aren't these just base types? We don't have to follow the brain-dead 
> nature of printf.
Basically builtin interface is instantiated by the "base type + LMUL" with type 
transformers. But in some intrinsic function we need a specific type regardless 
"base type + LMUL"
ex. `vuint32m2_t vssrl_vx_u32m2_vl (vuint32m2_t op1, uint8_t op2, size_t vl);`



Comment at: clang/utils/TestUtils/gen-riscv-v-tests.sh:22
+# op_list have marco name used in riscv_vector.td
+  local op_list="VADD VFADD"
+  local option="$1"

craig.topper wrote:
> It feels a little weird that this list is in the script and not derived from 
> the td file automatically somehow. Ideally we wouldn't have to update the 
> script every time a new set of intrinsics is added.
In tablegen interface `EmitRVVTest(RecordKeeper , raw_ostream )` can 
only emit one file. Currently I only found this stupid way to control 
`clang-tblgen` to generate one op in different files. 
Do you think it is acceptable to have a huge test file?
or maybe we can generate the same category op (ex. integer ops, floating ops) 
in the same file and predefined the all category first.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:687
+  [this](const std::vector ) {
+std::string S = "  ID = Intrinsic::riscv_" + getIRName() + ";\n";
+

Might be better to use raw_string_ostream here so you can use stream operators 
and not keep creating temporary std::strings and then appending them.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:707
+return getIntrinsicTypesString(getIntrinsicTypes());
+  } else {
+// IntrinsicTypes is ummasked version index

Drop else since previous if returned.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:70
+  // passing to the BUILTIN() macro in Builtins.def.
+  std::string builtin_str() const { return BuiltinStr; }
+

Return a const std::string & or a StringRef.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:85
+  bool isScalar() const {
+return (Vscale.hasValue() && Vscale.getValue() == 0);
+  }

Drop parentheses



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:154
+  // Return the architecture preprocessor definitions.
+  static SmallVector getExtStrings(uint8_t Extensions);
+

Does this need to be in Intrinsic? Can it just be in the emitter class?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:984
+  StringRef MangledSuffix = R->getValueAsString("MangledSuffix");
+  std::string Prototypes = R->getValueAsString("Prototype").data();
+  StringRef TypeRange = R->getValueAsString("TypeRange");

Use str() not data().

But I'm not sure why it can't just a be StringRef?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:997
+
+  // Parse prototype and create a list of primitve type with transformers
+  // (operand) in ProtoSeq. ProtoSeq[0] is output operand.

primitive*



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1070
+  // search first
+  if (LegalTypes.count(Idx)) {
+return Optional(LegalTypes[Idx]);

Use LegalTypes.find() so you don't have to two look ups.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1076
+  // compute type and record the result
+  auto T = std::make_shared(BT, LMUL, Proto);
+  if (T->isValid()) {

Does this need to be shared_ptr? Can we just arrange for LegalTypes to own the 
types and give every one else a pointer? LegalTypes would just need to outlive 
the references to the types.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1102
+if (ExtStrings.size()) {
+  std::string ArchMacro = std::accumulate(
+  ExtStrings.begin() + 1, ExtStrings.end(), "(" + ExtStrings[0] + ")",

Can we just stream this out to OS instead of accumulating a string before 
streaming?


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:9
+//
+// This file defines builtins for RISCV-V V-extension. See:
+//

"the"



Comment at: clang/include/clang/Basic/riscv_vector.td:23
+// The elements of this collection are defined by an instantiation process the
+// range of which is specified by cross product of the LMUL attribute and every
+// element in the attribute TypeRange. By default builtins have LMUL = [1, 2,

Missing "the"



Comment at: clang/include/clang/Basic/riscv_vector.td:25
+// element in the attribute TypeRange. By default builtins have LMUL = [1, 2,
+// 4, 8, -2, -4, -8] so the process is repeated 7 times. A negative LMUL -x
+// in that list is used to represent the fractional LMUL 1/x.

Why not just make it an exponent instead? Then that falls out naturally rather 
than having this weird split interpretation.



Comment at: clang/include/clang/Basic/riscv_vector.td:42
+//   i: int (32-bit)
+//   l: long (64-bit)
+//   h: half (16-bit)

If this is a C long, that's not true for RV32. If it's not a C long, call all 
these something else.

Though either way it'd be better to use the architectural names or LLVM-ish 
names for these things rather than something approximating the C language-level 
names.



Comment at: clang/include/clang/Basic/riscv_vector.td:47
+//
+// This way, given an LMUL, a record with a TypeRange "sil" will cause the
+// definition of 3 builtins. Each type "t" in the TypeRange (in this example

Strings that are really lists is a bit gross. I'd use TableGen sequences of 
LLVM types.



Comment at: clang/include/clang/Basic/riscv_vector.td:56
+//
+//   e: type of "t" as is (identity)
+//   v: computes a vector type whose element type is "t" for the current LMUL

Do we really need to invent an esoteric DSL?



Comment at: clang/include/clang/Basic/riscv_vector.td:66
+//  element type which is bool
+//   0: void type, ignores "t"
+//   z: size_t, ignores "t"

Then why aren't these just base types? We don't have to follow the brain-dead 
nature of printf.



Comment at: clang/include/clang/Basic/riscv_vector.td:116
+class RVVBuiltin
+{

Curly braces almost always go on the same line in .td files.



Comment at: clang/include/clang/Basic/riscv_vector.td:118
+{
+  // Base name that will be prepended __builtin_rvv_ and appended the computed
+  // Suffix.

Grammar



Comment at: clang/include/clang/Basic/riscv_vector.td:123
+  // If not empty, each instantiated builtin will have this appended after an
+  // underscore (_). Suffix is instantiated like Prototype.
+  string Suffix = suffix;

Don't need to repeat the field name.



Comment at: clang/include/clang/Basic/riscv_vector.td:130
+
+  // For each type described in TypeRange we instantiate this Prototype.
+  string Prototype = prototype;

Could do with a better explanation (you don't instantiate the prototype, you 
use the prototype to instantiate a specific element of the set of builtins 
being defined).



Comment at: clang/include/clang/Basic/riscv_vector.td:139
+
+  // If HasMask == 1, this flag states that this builtin has a first merge
+  // operand.

What's a "first merge" operand? Is the first important? Because the field 
itself is called HasMergeOperand, no mention of first. If merge operands are 
always first then rephrase the comment to not make it sound like coming first 
is special.



Comment at: clang/include/clang/Basic/riscv_vector.td:146
+
+  // This builtin supprot function overloading and has a mangled name
+  bit HasGeneric = 1;

support



Comment at: clang/include/clang/Basic/riscv_vector.td:149
+
+  // Reads or writes "memory".
+  bit HasSideEffects = 0;

If it's solely memory then call the field something to do with that. If there 
can be other side effects then don't make the comment so specific.



Comment at: clang/include/clang/Basic/riscv_vector.td:152
+
+  // This builtin is valid for the given LMUL.
+  list LMUL = [1, 2, 4, 8, -2, -4, -8];

Plural



Comment at: clang/include/clang/Basic/riscv_vector.td:155-161
+  // emit the automatic clang codegen. It describes
+  // what types we have to use to obtain the specific LLVM intrinsic.
+  //
+  // -1 means the return type,
+  // otherwise, k >= 0 meaning the k-th operand (counting from zero) of the
+  // codegen'd parameter of the unmasked version. k can't be the mask operand's
+  // position.

This needs proper formatting and capitalisation.



Comment at: 

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

This is a very incomplete review, but I need to go eat dinner




Comment at: clang/include/clang/Basic/riscv_vector.td:201
+// gen-riscv-vector-test.
+// gen-riscv-v-tests.sh will define each marco to generate each intrinsic test
+// in different files. It mean adding the new definition also need to update

marco->macro



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:124
+
+// TODO rafactor Intrinsic class design after support all intrinsic 
combination.
+class Intrinsic {

rafactor->refactor



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1000
+  SmallVector ProtoSeq;
+  const StringRef Pirmaries("evwqom0ztc");
+  size_t start = 0;

Is this supposed to be Primaries or some other word?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1055
+  RVVTypes Types;
+  for (std::string Proto : PrototypeSeq) {
+auto T = computeType(BT, LMUL, Proto);

Can Proto be a const std::string & ?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1057
+auto T = computeType(BT, LMUL, Proto);
+if (!T.hasValue()) {
+  return llvm::None;

Drop curly braces



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1068
+ StringRef Proto) {
+  TypeString Idx = Twine(BT + utostr(LMUL) + Proto).str();
+  // search first

Use Twine(LMUL)  instead of utostr. That should avoid creating std::string



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1112
+}
+if (ExtStrings.size())
+  OS << "#endif\n\n";

!ExtStrings.empty()



Comment at: clang/utils/TestUtils/gen-riscv-v-tests.sh:21
+gen_tests(){
+# op_list have marco name used in riscv_vector.td
+  local op_list="VADD VFADD"

marco->macro



Comment at: clang/utils/TestUtils/gen-riscv-v-tests.sh:22
+# op_list have marco name used in riscv_vector.td
+  local op_list="VADD VFADD"
+  local option="$1"

It feels a little weird that this list is in the script and not derived from 
the td file automatically somehow. Ideally we wouldn't have to update the 
script every time a new set of intrinsics is added.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, HsiangKai, 
evandro, liaolucy, arcbbb, monkchiang.
Herald added subscribers: dexonsmith, NickHung, luismarques, apazos, 
sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb, kristof.beyls, mgorny.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Demonstrate how to generate vadd/vfadd intrinsic functions
(explicitly api) and tests.

1. add -gen-riscv-vector-builtins for clang builtins.
2. add -gen-riscv-vector-builtin-codegen for clang codegen.
3. add -gen-riscv-vector-header for riscv_vector.h. It also generates

ifdef directives with extension checking, base on D94403 
.

4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h.

Generate overloading version Header for generic api.
https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface

5. add -gen-riscv-vector-test and -gen-riscv-vector-generic-test for clang

tests. I think using the same td file to generate tests can avoid duplicate 
works
but there is no test generator are writen in tablengen backend now. (ArmNeonTest
was deprecated). In order to generate separated test files, I need modify
clang_generate_header function of CMake to support passing more arguments.

6. add gen-riscv-v-tests.sh which generates all clang tests and use

'update_cc_test_checks.py' to update expected result.

7. update tblgen doc for riscv related options.

riscv_vector.td also defines some unused type transformers for vadd,
because I think it could demonstrate how tranfer type work and we need them
for whole intrinsic functions implementation in the future.

Authored-by: Roger Ferrer Ibanez 
Co-Authored-by: Zakk Cehn 


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  clang/utils/TestUtils/gen-riscv-v-tests.sh
  llvm/docs/CommandGuide/tblgen.rst

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