subject:"\[PATCH\] D95680\: \[RISCV\] Update the version number to v0.10 for vector."

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

2021-01-29 Thread Hsiangkai Wang via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG282aca10aeb0: [RISCV] Update the version number to v0.10 for 
vector. (authored by HsiangKai).

Changed prior to commit:
  https://reviews.llvm.org/D95680?vs=320125=320226#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95680/new/

https://reviews.llvm.org/D95680

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -40,7 +40,7 @@
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v1p0"
+# CHECK: attribute  5, "rv32i2p0_v0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba0p93"
@@ -79,7 +79,7 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 
-.attribute arch, "rv32iv_zvamo1p0_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+.attribute arch, "rv32iv_zvamo0p10_zvlsseg"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -47,7 +47,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
-; RV32V: .attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
@@ -60,7 +60,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -80,8 +80,8 @@
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: .attribute 5, "rv64i2p0_v1p0_zvamo1p0_zvlsseg1p0"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
+; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
 
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -7,7 +7,7 @@
 //===--===//
 ///
 /// This file describes the RISC-V instructions from the standard 'V' Vector
-/// extension, version 0.9.
+/// extension, version 0.10.
 /// This version is still experimental as the 'V' extension hasn't been
 /// ratified yet.
 ///
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -63,7 +63,7 @@
   if (STI.hasFeature(RISCV::FeatureStdExtB))
 Arch += "_b0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtV))
-Arch += "_v1p0";
+Arch += "_v0p10";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
 Arch += "_zfh0p1";
   if (STI.hasFeature(RISCV::FeatureExtZba))
@@ -89,9 +89,9 @@
   if (STI.hasFeature(RISCV::FeatureExtZbt))
 Arch += "_zbt0p93";
   if (STI.hasFeature(RISCV::FeatureExtZvamo))
-Arch += "_zvamo1p0";
+Arch += "_zvamo0p10";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
-Arch += "_zvlsseg1p0";
+Arch += "_zvlsseg0p10";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

2021-01-29 Thread Hsiangkai Wang via Phabricator via cfe-commits

HsiangKai added a comment.

In D95680#2530775 , @asb wrote:

> LGTM modulo one additional request: please update the comment at the top of 
> RISCVInstrInfoV.td to say "0.10" rather than "0.9".

Thanks for pointing it out. I will do it.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

2021-01-29 Thread Fraser Cormack via Phabricator via cfe-commits

frasercrmck accepted this revision.
frasercrmck added a comment.

LGTM


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[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

2021-01-29 Thread Alex Bradbury via Phabricator via cfe-commits

asb accepted this revision.
asb added a comment.

LGTM modulo one additional request: please update the comment at the top of 
RISCVInstrInfoV.td to say "0.10" rather than "0.9".


Repository:
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[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

2021-01-29 Thread Jessica Clarke via Phabricator via cfe-commits

jrtc27 accepted this revision.
jrtc27 added a comment.
This revision is now accepted and ready to land.

\o/


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[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

2021-01-29 Thread Hsiangkai Wang via Phabricator via cfe-commits

HsiangKai created this revision.
HsiangKai added reviewers: craig.topper, jrtc27, rogfer01, frasercrmck, evandro.
Herald added subscribers: vkmr, NickHung, jdoerfert, luismarques, apazos, 
sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
HsiangKai requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

v0.10 is tagged in V specification. Update the version to v0.10.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95680

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -40,7 +40,7 @@
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v1p0"
+# CHECK: attribute  5, "rv32i2p0_v0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba0p93"
@@ -79,7 +79,7 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 
-.attribute arch, "rv32iv_zvamo1p0_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+.attribute arch, "rv32iv_zvamo0p10_zvlsseg"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -47,7 +47,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
-; RV32V: .attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
@@ -60,7 +60,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -80,8 +80,8 @@
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: .attribute 5, "rv64i2p0_v1p0_zvamo1p0_zvlsseg1p0"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
+; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
 
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -63,7 +63,7 @@
   if (STI.hasFeature(RISCV::FeatureStdExtB))
 Arch += "_b0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtV))
-Arch += "_v1p0";
+Arch += "_v0p10";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
 Arch += "_zfh0p1";
   if (STI.hasFeature(RISCV::FeatureExtZba))
@@ -89,9 +89,9 @@
   if (STI.hasFeature(RISCV::FeatureExtZbt))
 Arch += "_zbt0p93";
   if (STI.hasFeature(RISCV::FeatureExtZvamo))
-Arch += "_zvamo1p0";
+Arch += "_zvamo0p10";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
-Arch += "_zvlsseg1p0";
+Arch += "_zvlsseg0p10";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2126,7 +2126,7 @@
   if (getFeatureBits(RISCV::FeatureStdExtB))
 formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
   if (getFeatureBits(RISCV::FeatureStdExtV))
-formalArchStr = (Twine(formalArchStr) + "_v1p0").str();

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

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