[clang] [ARM64EC] Fix arm_neon.h on ARM64EC. (PR #88572)

2024-04-16 Thread Eli Friedman via cfe-commits 

https://github.com/efriedma-quic closed 
https://github.com/llvm/llvm-project/pull/88572
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[clang] [ARM64EC] Fix arm_neon.h on ARM64EC. (PR #88572)

2024-04-15 Thread Jacek Caban via cfe-commits 

https://github.com/cjacek approved this pull request.


https://github.com/llvm/llvm-project/pull/88572
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[clang] [ARM64EC] Fix arm_neon.h on ARM64EC. (PR #88572)

2024-04-12 Thread Daniel Paoliello via cfe-commits 

https://github.com/dpaoliello approved this pull request.


https://github.com/llvm/llvm-project/pull/88572
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[clang] [ARM64EC] Fix arm_neon.h on ARM64EC. (PR #88572)

2024-04-12 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Eli Friedman (efriedma-quic)


Changes

Since 97fe519d, in ARM64EC mode, we don't define `__aarch64__`. Fix various 
preprocessor guards to account for this.

---
Full diff: https://github.com/llvm/llvm-project/pull/88572.diff


3 Files Affected:

- (modified) clang/include/clang/Basic/arm_fp16.td (+1-1) 
- (modified) clang/include/clang/Basic/arm_neon.td (+29-29) 
- (modified) clang/utils/TableGen/NeonEmitter.cpp (+4-4) 


``diff
diff --git a/clang/include/clang/Basic/arm_fp16.td 
b/clang/include/clang/Basic/arm_fp16.td
index cb2a09303e8e12..d36b4617bef5d2 100644
--- a/clang/include/clang/Basic/arm_fp16.td
+++ b/clang/include/clang/Basic/arm_fp16.td
@@ -14,7 +14,7 @@
 include "arm_neon_incl.td"
 
 // ARMv8.2-A FP16 intrinsics.
-let ArchGuard = "defined(__aarch64__)", TargetGuard = "fullfp16" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = 
"fullfp16" in {
 
   // Negate
   def VNEGSH  : SInst<"vneg", "11", "Sh">;
diff --git a/clang/include/clang/Basic/arm_neon.td 
b/clang/include/clang/Basic/arm_neon.td
index 7edac5afafaa99..6d655c39360d3b 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -605,11 +605,11 @@ def VQDMULL_LANE  : SOpInst<"vqdmull_lane", "(>Q)..I", 
"si", OP_QDMULL_LN>;
 def VQDMULH_N : SOpInst<"vqdmulh_n", "..1", "siQsQi", OP_QDMULH_N>;
 def VQRDMULH_N: SOpInst<"vqrdmulh_n", "..1", "siQsQi", OP_QRDMULH_N>;
 
-let ArchGuard = "!defined(__aarch64__)" in {
+let ArchGuard = "!defined(__aarch64__) && !defined(__arm64ec__)" in {
 def VQDMULH_LANE  : SOpInst<"vqdmulh_lane", "..qI", "siQsQi", OP_QDMULH_LN>;
 def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "..qI", "siQsQi", OP_QRDMULH_LN>;
 }
-let ArchGuard = "defined(__aarch64__)" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)" in {
 def A64_VQDMULH_LANE  : SInst<"vqdmulh_lane", "..(!q)I", "siQsQi">;
 def A64_VQRDMULH_LANE : SInst<"vqrdmulh_lane", "..(!q)I", "siQsQi">;
 }
@@ -686,7 +686,7 @@ multiclass REINTERPRET_CROSS_TYPES {
 
 // E.3.31 Vector reinterpret cast operations
 def VREINTERPRET : 
REINTERPRET_CROSS_SELF<"csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs"> {
-  let ArchGuard = "!defined(__aarch64__)";
+  let ArchGuard = "!defined(__aarch64__) && !defined(__arm64ec__)";
   let BigEndianSafe = 1;
 }
 
@@ -714,7 +714,7 @@ def VADDP   : WInst<"vadd", "...", "PcPsPlQPcQPsQPl">;
 

 // AArch64 Intrinsics
 
-let ArchGuard = "defined(__aarch64__)" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)" in {
 
 

 // Load/Store
@@ -1091,14 +1091,14 @@ let isLaneQ = 1 in {
 def VQDMULH_LANEQ  : SInst<"vqdmulh_laneq", "..QI", "siQsQi">;
 def VQRDMULH_LANEQ : SInst<"vqrdmulh_laneq", "..QI", "siQsQi">;
 }
-let ArchGuard = "defined(__aarch64__)", TargetGuard = "v8.1a" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = 
"v8.1a" in {
 def VQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "...QI", "siQsQi", 
OP_QRDMLAH_LN> {
   let isLaneQ = 1;
 }
 def VQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "...QI", "siQsQi", 
OP_QRDMLSH_LN> {
   let isLaneQ = 1;
 }
-} // ArchGuard = "defined(__aarch64__)", TargetGuard = "v8.1a"
+} // ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = 
"v8.1a"
 
 // Note: d type implemented by SCALAR_VMULX_LANE
 def VMULX_LANE : IOpInst<"vmulx_lane", "..qI", "fQfQd", OP_MULX_LN>;
@@ -1143,7 +1143,7 @@ def SHA256H2 : SInst<"vsha256h2", "", "QUi">;
 def SHA256SU1 : SInst<"vsha256su1", "", "QUi">;
 }
 
-let ArchGuard = "defined(__aarch64__)", TargetGuard = "sha3" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = 
"sha3" in {
 def BCAX : SInst<"vbcax", "", "QUcQUsQUiQUlQcQsQiQl">;
 def EOR3 : SInst<"veor3", "", "QUcQUsQUiQUlQcQsQiQl">;
 def RAX1 : SInst<"vrax1", "...", "QUl">;
@@ -1153,14 +1153,14 @@ def XAR :  SInst<"vxar", "...I", "QUl">;
 }
 }
 
-let ArchGuard = "defined(__aarch64__)", TargetGuard = "sha3" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = 
"sha3" in {
 def SHA512SU0 : SInst<"vsha512su0", "...", "QUl">;
 def SHA512su1 : SInst<"vsha512su1", "", "QUl">;
 def SHA512H : SInst<"vsha512h", "", "QUl">;
 def SHA512H2 : SInst<"vsha512h2", "", "QUl">;
 }
 
-let ArchGuard = "defined(__aarch64__)", TargetGuard = "sm4" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = 
"sm4" in {
 def SM3SS1 : SInst<"vsm3ss1", "", "QUi">;
 def SM3TT1A : SInst<"vsm3tt1a", "I", "QUi">;
 def SM3TT1B : SInst<"vsm3tt1b", "I", "QUi">;
@@ -1170,7 +1170,7 @@ def SM3PARTW1 : SInst<"vsm3partw1", "", "QUi">;
 def SM3PARTW2 : SInst<"vsm3partw2", "", "QUi">;
 }
 
-let ArchGuard = "defined(__aarch64__)", TargetGuard =

[clang] [ARM64EC] Fix arm_neon.h on ARM64EC. (PR #88572)

2024-04-12 Thread Eli Friedman via cfe-commits 

https://github.com/efriedma-quic created 
https://github.com/llvm/llvm-project/pull/88572

Since 97fe519d, in ARM64EC mode, we don't define `__aarch64__`. Fix various 
preprocessor guards to account for this.

>From 1931103205e566ef49bbfa96272b3304c89f7d2d Mon Sep 17 00:00:00 2001
From: Eli Friedman 
Date: Fri, 12 Apr 2024 13:10:14 -0700
Subject: [PATCH] [ARM64EC] Fix arm_neon.h on ARM64EC.

Since 97fe519d, in ARM64EC mode, we don't define __aarch64__. Fix
various preprocessor guards to account for this.
---
 clang/include/clang/Basic/arm_fp16.td |  2 +-
 clang/include/clang/Basic/arm_neon.td | 58 +--
 clang/utils/TableGen/NeonEmitter.cpp  |  8 ++--
 3 files changed, 34 insertions(+), 34 deletions(-)

diff --git a/clang/include/clang/Basic/arm_fp16.td 
b/clang/include/clang/Basic/arm_fp16.td
index cb2a09303e8e12..d36b4617bef5d2 100644
--- a/clang/include/clang/Basic/arm_fp16.td
+++ b/clang/include/clang/Basic/arm_fp16.td
@@ -14,7 +14,7 @@
 include "arm_neon_incl.td"
 
 // ARMv8.2-A FP16 intrinsics.
-let ArchGuard = "defined(__aarch64__)", TargetGuard = "fullfp16" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = 
"fullfp16" in {
 
   // Negate
   def VNEGSH  : SInst<"vneg", "11", "Sh">;
diff --git a/clang/include/clang/Basic/arm_neon.td 
b/clang/include/clang/Basic/arm_neon.td
index 7edac5afafaa99..6d655c39360d3b 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -605,11 +605,11 @@ def VQDMULL_LANE  : SOpInst<"vqdmull_lane", "(>Q)..I", 
"si", OP_QDMULL_LN>;
 def VQDMULH_N : SOpInst<"vqdmulh_n", "..1", "siQsQi", OP_QDMULH_N>;
 def VQRDMULH_N: SOpInst<"vqrdmulh_n", "..1", "siQsQi", OP_QRDMULH_N>;
 
-let ArchGuard = "!defined(__aarch64__)" in {
+let ArchGuard = "!defined(__aarch64__) && !defined(__arm64ec__)" in {
 def VQDMULH_LANE  : SOpInst<"vqdmulh_lane", "..qI", "siQsQi", OP_QDMULH_LN>;
 def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "..qI", "siQsQi", OP_QRDMULH_LN>;
 }
-let ArchGuard = "defined(__aarch64__)" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)" in {
 def A64_VQDMULH_LANE  : SInst<"vqdmulh_lane", "..(!q)I", "siQsQi">;
 def A64_VQRDMULH_LANE : SInst<"vqrdmulh_lane", "..(!q)I", "siQsQi">;
 }
@@ -686,7 +686,7 @@ multiclass REINTERPRET_CROSS_TYPES {
 
 // E.3.31 Vector reinterpret cast operations
 def VREINTERPRET : 
REINTERPRET_CROSS_SELF<"csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs"> {
-  let ArchGuard = "!defined(__aarch64__)";
+  let ArchGuard = "!defined(__aarch64__) && !defined(__arm64ec__)";
   let BigEndianSafe = 1;
 }
 
@@ -714,7 +714,7 @@ def VADDP   : WInst<"vadd", "...", "PcPsPlQPcQPsQPl">;
 

 // AArch64 Intrinsics
 
-let ArchGuard = "defined(__aarch64__)" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)" in {
 
 

 // Load/Store
@@ -1091,14 +1091,14 @@ let isLaneQ = 1 in {
 def VQDMULH_LANEQ  : SInst<"vqdmulh_laneq", "..QI", "siQsQi">;
 def VQRDMULH_LANEQ : SInst<"vqrdmulh_laneq", "..QI", "siQsQi">;
 }
-let ArchGuard = "defined(__aarch64__)", TargetGuard = "v8.1a" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = 
"v8.1a" in {
 def VQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "...QI", "siQsQi", 
OP_QRDMLAH_LN> {
   let isLaneQ = 1;
 }
 def VQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "...QI", "siQsQi", 
OP_QRDMLSH_LN> {
   let isLaneQ = 1;
 }
-} // ArchGuard = "defined(__aarch64__)", TargetGuard = "v8.1a"
+} // ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = 
"v8.1a"
 
 // Note: d type implemented by SCALAR_VMULX_LANE
 def VMULX_LANE : IOpInst<"vmulx_lane", "..qI", "fQfQd", OP_MULX_LN>;
@@ -1143,7 +1143,7 @@ def SHA256H2 : SInst<"vsha256h2", "", "QUi">;
 def SHA256SU1 : SInst<"vsha256su1", "", "QUi">;
 }
 
-let ArchGuard = "defined(__aarch64__)", TargetGuard = "sha3" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = 
"sha3" in {
 def BCAX : SInst<"vbcax", "", "QUcQUsQUiQUlQcQsQiQl">;
 def EOR3 : SInst<"veor3", "", "QUcQUsQUiQUlQcQsQiQl">;
 def RAX1 : SInst<"vrax1", "...", "QUl">;
@@ -1153,14 +1153,14 @@ def XAR :  SInst<"vxar", "...I", "QUl">;
 }
 }
 
-let ArchGuard = "defined(__aarch64__)", TargetGuard = "sha3" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = 
"sha3" in {
 def SHA512SU0 : SInst<"vsha512su0", "...", "QUl">;
 def SHA512su1 : SInst<"vsha512su1", "", "QUl">;
 def SHA512H : SInst<"vsha512h", "", "QUl">;
 def SHA512H2 : SInst<"vsha512h2", "", "QUl">;
 }
 
-let ArchGuard = "defined(__aarch64__)", TargetGuard = "sm4" in {
+let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = 
"sm4" in {
 def SM3SS1 : SInst<"vsm3ss1", "", "QUi">;
 def SM3TT1A : SInst<"vsm3tt1a", "I", "QUi">;