[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-06-10 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-06-10 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From 9ab05b9f68def57e9abb9d5ac65293b84aacc95a Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c   |  5 -
 clang/test/Preprocessor/riscv-target-features.c  | 12 
 llvm/docs/RISCVUsage.rst |  1 +
 llvm/docs/ReleaseNotes.rst   |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td   |  8 
 llvm/test/CodeGen/RISCV/attributes.ll|  4 
 llvm/unittests/TargetParser/RISCVISAInfoTest.cpp |  9 ++---
 7 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index ddf617bbb6237..ffd92e1f398c4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 09b9ad0a160bb..91307141e0406 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -194,6 +195,17 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 35115e67ecf92..ef06f80c747f9 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 8cdb9db087c77..b46994bbcd66d 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -152,6 +152,7 @@ Changes to the RISC-V Backend
 * Zaamo and Zalrsc are no longer experimental.
 * Processors that enable post reg-alloc scheduling (PostMachineScheduler) by 
default should use the `UsePostRAScheduler` subtarget feature. Setting 
`PostRAScheduler = 1` in the scheduler model will have no effect on the 
enabling of the PostMachineScheduler.
 * Zabha is no longer experimental.
+* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9bf06850483d8..011edca019fd6 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -477,6 +477,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureStdExtB
+: RISCVExtension<"b", 1, 0,
+ "'B' (the collection of the Zba, Zbb, Zbs extensions)",
+ [FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
+def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
+   AssemblerPredicate<(all_of FeatureStdExtB),
+   "'B' (the collection of the Zba, Zbb, Zbs 
extensions)">;
+
 def FeatureStdExtZbkb
 : RISCVExtension<"zbkb", 1, 0,
  "'Z

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-06-05 Thread Craig Topper via cfe-commits 

https://github.com/topperc approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-06-05 Thread Pengcheng Wang via cfe-commits 


@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
 }
 
 static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"},  {"zks"},   {"zvkn"},  {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"},  {"zks"},   {"zvkn"},

wangpc-pp wrote:

> Remove this from `CombineIntoExts` may cause `__riscv_b` become less useful I 
> think?

Yeah, but I think @topperc's concern makes sense as well. Will binutils 
complain or just ignore unknown extensions?

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-06-05 Thread Kito Cheng via cfe-commits 


@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
 }
 
 static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"},  {"zks"},   {"zvkn"},  {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"},  {"zks"},   {"zvkn"},

kito-cheng wrote:

Remove this from `CombineIntoExts` may cause `__riscv_b` become less useful I 
think?

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-06-05 Thread Pengcheng Wang via cfe-commits 


@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
 }
 
 static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"},  {"zks"},   {"zvkn"},  {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"},  {"zks"},   {"zvkn"},

wangpc-pp wrote:

I removed this part.
We can support combination of B extension in a separate patch if we need it.

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-06-05 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From ac2c10240160783ebbd65332230c8c294fef2442 Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c|  5 -
 .../test/Preprocessor/riscv-target-features.c | 20 +++
 llvm/docs/RISCVUsage.rst  |  1 +
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/test/CodeGen/RISCV/attributes.ll |  4 
 .../TargetParser/RISCVISAInfoTest.cpp |  9 ++---
 7 files changed, 36 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index ddf617bbb6237..ffd92e1f398c4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 09b9ad0a160bb..5d578a02b20fb 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -194,6 +195,25 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32i_zba_zbb_zbs -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64i_zba_zbb_zbs -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
+// CHECK-COMBINE-INTO-B: __riscv_b 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 35115e67ecf92..ef06f80c747f9 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 393b97efa5470..2aee464cdaf2d 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -142,6 +142,7 @@ Changes to the RISC-V Backend
 * Zaamo and Zalrsc are no longer experimental.
 * Processors that enable post reg-alloc scheduling (PostMachineScheduler) by 
default should use the `UsePostRAScheduler` subtarget feature. Setting 
`PostRAScheduler = 1` in the scheduler model will have no effect on the 
enabling of the PostMachineScheduler.
 * Zabha is no longer experimental.
+* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9bf06850483d8..011edca019fd6 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -477,6 +477,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureStdExtB
+: RISCVExtension<"b", 1, 0,
+ "'B' (the collection of the Zba, Zbb, Zbs extensions)",
+

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-05-30 Thread Pengcheng Wang via cfe-commits 


@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
 }
 
 static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"},  {"zks"},   {"zvkn"},  {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"},  {"zks"},   {"zvkn"},

wangpc-pp wrote:

@kito-cheng WDYT?

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-05-30 Thread Craig Topper via cfe-commits 


@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
 }
 
 static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"},  {"zks"},   {"zvkn"},  {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"},  {"zks"},   {"zvkn"},

topperc wrote:

I'm concerned this will make us not interoperate with older versions of 
binutils that don't know about B.

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-05-30 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

Ping. The B extension has been ratified and I hava rebased this PR.

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-05-30 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From a780efe3e297fe59c5521ea5387dda12905a4423 Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c|  5 -
 .../test/Preprocessor/riscv-target-features.c | 20 +++
 llvm/docs/RISCVUsage.rst  |  1 +
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  4 ++--
 llvm/test/CodeGen/RISCV/attributes.ll | 18 ++---
 .../TargetParser/RISCVISAInfoTest.cpp |  9 ++---
 8 files changed, 45 insertions(+), 21 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index ddf617bbb6237..ffd92e1f398c4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 0865add7e8fb8..ff3f31ec67c1c 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -194,6 +195,25 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32i_zba_zbb_zbs -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64i_zba_zbb_zbs -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
+// CHECK-COMBINE-INTO-B: __riscv_b 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 5ecee2a480f7d..34c2b967a4111 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 1e1ccb495c366..6e96545c739e3 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -132,6 +132,7 @@ Changes to the RISC-V Backend
 * Added smstateen extension to -march. CSR names for smstateen were already 
supported.
 * Zaamo and Zalrsc are no longer experimental.
 * Processors that enable post reg-alloc scheduling (PostMachineScheduler) by 
default should use the `UsePostRAScheduler` subtarget feature. Setting 
`PostRAScheduler = 1` in the scheduler model will have no effect on the 
enabling of the PostMachineScheduler.
+* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a78d78946be31..6acb147330d62 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -477,6 +477,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureSt

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-04-12 Thread Kito Cheng via cfe-commits 

kito-cheng wrote:

Jeff told me it's still need wait TSC vote for the ratification, anyway it will 
ratify this month.

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-04-11 Thread Alex Bradbury via cfe-commits 

asb wrote:

> It passed public review[1] and merged into riscv-isa-manual[2], so I think 
> it's time to mark it as 1.0 and moving forward :)
> 
> [1] 
> https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/KetVUCQkfK4/m/Y3Dbd2pvAAAJ?utm_medium=email&utm_source=footer
>  [2] 
> [riscv/riscv-isa-manual@cdb2585](https://github.com/riscv/riscv-isa-manual/commit/cdb25859bcce5a6edbdc34914c1f86f079b3fddd)

That's probably true - though historically I've been using 
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions to determine 
if a spec is ratified or not, now moved to 
https://wiki.riscv.org/display/HOME/Ratified+Extensions seemingly. B doesn't 
seem to be listed yet. @jjscheel - is it just not added to the wiki page yet, 
or is it technically not yet ratified?

(I know it's really a trivial "extension" so might be a special case)

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-04-11 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From 169ef33f585b964d9af7a7628919271245f318fc Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH 1/3] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c  |  5 -
 clang/test/Preprocessor/riscv-target-features.c | 12 
 llvm/docs/RISCVUsage.rst|  1 +
 llvm/lib/Support/RISCVISAInfo.cpp   |  3 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td  |  8 
 llvm/test/CodeGen/RISCV/attributes.ll   |  4 
 llvm/unittests/Support/RISCVISAInfoTest.cpp |  6 ++
 7 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 8399b4e97f86d5..8e48ed9160992d 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index ec7764bb538189..dfdef72cb1e755 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -191,6 +192,17 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 6f5eba263def43..232604788f9972 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 7a19d24d1ff483..99962501153b0e 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -52,6 +52,7 @@ static const char *RISCVGImplications[] = {
 // NOTE: This table should be sorted alphabetically by extension name.
 static const RISCVSupportedExtension SupportedExtensions[] = {
 {"a", {2, 1}},
+{"b", {1, 0}},
 {"c", {2, 0}},
 {"d", {2, 2}},
 {"e", {2, 0}},
@@ -1106,6 +1107,7 @@ Error RISCVISAInfo::checkDependency() {
   return Error::success();
 }
 
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1181,6 +1183,7 @@ struct ImpliedExtsEntry {
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
 {{"d"}, {ImpliedExtsD}},
 {{"f"}, {ImpliedExtsF}},
 {{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 794455aa730400..33541be37537df 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -430,6 +430,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureStdExtB
+: SubtargetFeature<"b", "HasStdExtB", "true",
+   "'B' (the collection of the Zba, Zbb, Zbs e

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-04-11 Thread Kito Cheng via cfe-commits 

kito-cheng wrote:

Could you add `B` into CombinedExtsEntry and added a test for that?

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-04-11 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From 169ef33f585b964d9af7a7628919271245f318fc Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH 1/2] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c  |  5 -
 clang/test/Preprocessor/riscv-target-features.c | 12 
 llvm/docs/RISCVUsage.rst|  1 +
 llvm/lib/Support/RISCVISAInfo.cpp   |  3 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td  |  8 
 llvm/test/CodeGen/RISCV/attributes.ll   |  4 
 llvm/unittests/Support/RISCVISAInfoTest.cpp |  6 ++
 7 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 8399b4e97f86d5..8e48ed9160992d 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index ec7764bb538189..dfdef72cb1e755 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -191,6 +192,17 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 6f5eba263def43..232604788f9972 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 7a19d24d1ff483..99962501153b0e 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -52,6 +52,7 @@ static const char *RISCVGImplications[] = {
 // NOTE: This table should be sorted alphabetically by extension name.
 static const RISCVSupportedExtension SupportedExtensions[] = {
 {"a", {2, 1}},
+{"b", {1, 0}},
 {"c", {2, 0}},
 {"d", {2, 2}},
 {"e", {2, 0}},
@@ -1106,6 +1107,7 @@ Error RISCVISAInfo::checkDependency() {
   return Error::success();
 }
 
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1181,6 +1183,7 @@ struct ImpliedExtsEntry {
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
 {{"d"}, {ImpliedExtsD}},
 {{"f"}, {ImpliedExtsF}},
 {{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 794455aa730400..33541be37537df 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -430,6 +430,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureStdExtB
+: SubtargetFeature<"b", "HasStdExtB", "true",
+   "'B' (the collection of the Zba, Zbb, Zbs e

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-04-11 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From 169ef33f585b964d9af7a7628919271245f318fc Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c  |  5 -
 clang/test/Preprocessor/riscv-target-features.c | 12 
 llvm/docs/RISCVUsage.rst|  1 +
 llvm/lib/Support/RISCVISAInfo.cpp   |  3 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td  |  8 
 llvm/test/CodeGen/RISCV/attributes.ll   |  4 
 llvm/unittests/Support/RISCVISAInfoTest.cpp |  6 ++
 7 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 8399b4e97f86d5..8e48ed9160992d 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index ec7764bb538189..dfdef72cb1e755 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -191,6 +192,17 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 6f5eba263def43..232604788f9972 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 7a19d24d1ff483..99962501153b0e 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -52,6 +52,7 @@ static const char *RISCVGImplications[] = {
 // NOTE: This table should be sorted alphabetically by extension name.
 static const RISCVSupportedExtension SupportedExtensions[] = {
 {"a", {2, 1}},
+{"b", {1, 0}},
 {"c", {2, 0}},
 {"d", {2, 2}},
 {"e", {2, 0}},
@@ -1106,6 +1107,7 @@ Error RISCVISAInfo::checkDependency() {
   return Error::success();
 }
 
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1181,6 +1183,7 @@ struct ImpliedExtsEntry {
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
 {{"d"}, {ImpliedExtsD}},
 {{"f"}, {ImpliedExtsF}},
 {{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 794455aa730400..33541be37537df 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -430,6 +430,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureStdExtB
+: SubtargetFeature<"b", "HasStdExtB", "true",
+   "'B' (the collection of the Zba, Zbb, Zbs exten

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-04-11 Thread Kito Cheng via cfe-commits 

kito-cheng wrote:

It passed public review[1] and merged into riscv-isa-manual[2], so I think it's 
time to mark it as 1.0 and moving forward :)

[1]  
https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/KetVUCQkfK4/m/Y3Dbd2pvAAAJ?utm_medium=email&utm_source=footer
[2] 
https://github.com/riscv/riscv-isa-manual/commit/cdb25859bcce5a6edbdc34914c1f86f079b3fddd

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-01-19 Thread Wang Pengcheng via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From c4f7441b2809dfbb6ed4b6d97d581e3d736819fe Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.

Though it hasn't been ratified, I set its version to `1.0`.
---
 clang/test/Driver/riscv-arch.c  |  5 -
 clang/test/Preprocessor/riscv-target-features.c | 12 
 llvm/docs/RISCVUsage.rst|  1 +
 llvm/lib/Support/RISCVISAInfo.cpp   |  5 -
 llvm/lib/Target/RISCV/RISCVFeatures.td  |  8 
 llvm/test/CodeGen/RISCV/attributes.ll   |  4 
 llvm/unittests/Support/RISCVISAInfoTest.cpp |  6 ++
 7 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 0ac81ea982f1b61..7c9f880c74035ba 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -233,11 +233,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 8dc02f7efefbd6f..6acd7b1f2d6d6ad 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -159,6 +160,17 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN: -march=rv32ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index fc4d97b13437153..bfdceb81ce2dc76 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  ExtensionStatus
  ===  =
  ``A``Supported
+ ``B``Supported
  ``C``Supported
  ``D``Supported
  ``F``Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 8c9eb1bddb3cb52..1f194851d0681e4 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -46,6 +46,7 @@ static const char *RISCVGImplications[] = {
 // NOTE: This table should be sorted alphabetically by extension name.
 static const RISCVSupportedExtension SupportedExtensions[] = {
 {"a", {2, 1}},
+{"b", {1, 0}},
 {"c", {2, 0}},
 {"d", {2, 2}},
 {"e", {2, 0}},
@@ -848,7 +849,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool 
EnableExperimentalExtension,
 }
 
 // The order is OK, then push it into features.
-// Currently LLVM supports only "mafdcvh".
+// Currently LLVM supports only "mafdcbvh".
 if (!isSupportedExtension(StringRef(&C, 1))) {
   if (IgnoreUnknown) {
 GoToNextExt(I, ConsumeLength, Exts.end());
@@ -998,6 +999,7 @@ Error RISCVISAInfo::checkDependency() {
   return Error::success();
 }
 
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1072,6 +1074,7 @@ struct ImpliedExtsEntry {
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
 {{"d"}, {ImpliedExtsD}},
 {{"f"}, {ImpliedExtsF}},
 {{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Tar

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-01-17 Thread Kito Cheng via cfe-commits 

kito-cheng wrote:

It tagged with 0.1 now :)
https://github.com/riscv/riscv-b/releases/tag/v0.1

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-01-04 Thread Craig Topper via cfe-commits 

topperc wrote:

> Thanks!
> 
> 
> 
> If someone sets zba_zbb_zbs, should b be inferred?
> 
> 
> 

Yes, but it will break `-march=rv64i_zba_zbb_zbs -fno-integrated-as` with 
versions of the external assembler that don't know about B. We'll infer B and 
pass it to the assembler -march.

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-01-04 Thread Alex Bradbury via cfe-commits 

asb wrote:

Thanks!

If someone sets zba_zbb_zbs, should b be inferred?

This patch needs an LLVM release note as well, and agreed we should await on a 
versioning decision.

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-01-03 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Wang Pengcheng (wangpc-pp)


Changes

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.

Though it hasn't been ratified, I set its version to `1.0`.


---
Full diff: https://github.com/llvm/llvm-project/pull/76893.diff


5 Files Affected:

- (modified) clang/test/Preprocessor/riscv-target-features.c (+12) 
- (modified) llvm/docs/RISCVUsage.rst (+1) 
- (modified) llvm/lib/Support/RISCVISAInfo.cpp (+3) 
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+8) 
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+4) 


``diff
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 02d8d34116f804..783edfe7301a5f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -5,6 +5,7 @@
 
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -150,6 +151,17 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN: -march=rv32ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 99c7146825f5ee..05634702595018 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  ExtensionStatus
  ===  =
  ``A``Supported
+ ``B``Supported
  ``C``Supported
  ``D``Supported
  ``F``Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index a9b7e209915a13..f9c5bd2eb2bdbb 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -51,6 +51,7 @@ static const char *RISCVGImplications[] = {
 // NOTE: This table should be sorted alphabetically by extension name.
 static const RISCVSupportedExtension SupportedExtensions[] = {
 {"a", RISCVExtensionVersion{2, 1}},
+{"b", RISCVExtensionVersion{1, 0}},
 {"c", RISCVExtensionVersion{2, 0}},
 {"d", RISCVExtensionVersion{2, 2}},
 {"e", RISCVExtensionVersion{2, 0}},
@@ -997,6 +998,7 @@ Error RISCVISAInfo::checkDependency() {
   return Error::success();
 }
 
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1071,6 +1073,7 @@ struct ImpliedExtsEntry {
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
 {{"d"}, {ImpliedExtsD}},
 {{"f"}, {ImpliedExtsF}},
 {{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 59b202606dadaf..0201f4837733a0 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -202,6 +202,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
  AssemblerPredicate<(all_of FeatureStdExtZbs),
  "'Zbs' (Single-Bit Instructions)">;
 
+def FeatureStdExtB
+: SubtargetFeature<"b", "HasStdExtB", "true",
+   "'B' (the collection of the Zba, Zbb, Zbs extensions)",
+   [FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
+def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
+   AssemblerPredicate<(all_of FeatureStdExtB),
+   "'B' (the collection of the Zba, Zbb, Zbs 
extensions)">;
+
 def FeatureStdExtZbkb
 : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
"'Zbkb' (Bitmanip instructions for Cryptography)">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll 
b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3..522e2c8a30e1e6 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -5,6 +5,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zmmul %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZMMUL %s
 ; RUN: llc

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-01-03 Thread Wang Pengcheng via cfe-commits 

https://github.com/wangpc-pp created 
https://github.com/llvm/llvm-project/pull/76893

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.

Though it hasn't been ratified, I set its version to `1.0`.


>From 52ed8e07f759546454798b6590ba01cbb6a08651 Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.

Though it hasn't been ratified, I set its version to `1.0`.
---
 clang/test/Preprocessor/riscv-target-features.c | 12 
 llvm/docs/RISCVUsage.rst|  1 +
 llvm/lib/Support/RISCVISAInfo.cpp   |  3 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td  |  8 
 llvm/test/CodeGen/RISCV/attributes.ll   |  4 
 5 files changed, 28 insertions(+)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 02d8d34116f804..783edfe7301a5f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -5,6 +5,7 @@
 
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -150,6 +151,17 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN: -march=rv32ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 99c7146825f5ee..05634702595018 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  ExtensionStatus
  ===  =
  ``A``Supported
+ ``B``Supported
  ``C``Supported
  ``D``Supported
  ``F``Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index a9b7e209915a13..f9c5bd2eb2bdbb 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -51,6 +51,7 @@ static const char *RISCVGImplications[] = {
 // NOTE: This table should be sorted alphabetically by extension name.
 static const RISCVSupportedExtension SupportedExtensions[] = {
 {"a", RISCVExtensionVersion{2, 1}},
+{"b", RISCVExtensionVersion{1, 0}},
 {"c", RISCVExtensionVersion{2, 0}},
 {"d", RISCVExtensionVersion{2, 2}},
 {"e", RISCVExtensionVersion{2, 0}},
@@ -997,6 +998,7 @@ Error RISCVISAInfo::checkDependency() {
   return Error::success();
 }
 
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1071,6 +1073,7 @@ struct ImpliedExtsEntry {
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
 {{"d"}, {ImpliedExtsD}},
 {{"f"}, {ImpliedExtsF}},
 {{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 59b202606dadaf..0201f4837733a0 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -202,6 +202,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
  AssemblerPredicate<(all_of FeatureStdExtZbs),
  "'Zbs' (Single-Bit Instructions)">;
 
+def FeatureStdExtB
+: SubtargetFeature<"b", "HasStdExtB", "true",
+   "'B' (the collection of the Zba, Zbb, Zbs extensions)",
+   [FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
+def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
+   AssemblerPredicate<(all_of FeatureStdExtB),
+   "'B' (the collection of the Zba, Zbb, Zbs 
extensions)">;
+
 def FeatureStdExtZbkb
 : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
"'Zbkb' (Bitmanip instructions for Cryptography)