[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)

2024-04-01 Thread Nathan Sidwell via cfe-commits 

urnathan wrote:

#65742 is committed, so MIPS' TargetInfo will need adjusting to propagate the 
unaligned capability. See 7df79ababee8

https://github.com/llvm/llvm-project/pull/85174
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[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)

2024-03-20 Thread YunQiang Su via cfe-commits 

https://github.com/wzssyqa closed 
https://github.com/llvm/llvm-project/pull/85174
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[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)

2024-03-16 Thread YunQiang Su via cfe-commits 

https://github.com/wzssyqa updated 
https://github.com/llvm/llvm-project/pull/85174

>From 7e1cf74f4fc9271e88b62462ea9a38826fd3ee38 Mon Sep 17 00:00:00 2001
From: YunQiang Su 
Date: Thu, 14 Mar 2024 11:48:36 +0800
Subject: [PATCH] MIPS: Support -m(no-)strict-align for r6

MIPSr6 ISA requires normal load/store instructions support
misunaligned memory access, while it is not always do so
by hardware. On some microarchitectures or some corner cases
it may need support by OS.

Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't
support them, instead, r6 requires lw instruction support
misunaligned memory access. So, if -mstrict-align is used for
pre-R6, lwl/lwr won't be disabled.

If -mstrict-align is used for r6 and the access is not well
aligned, some lb/lh instructions will be used to replace lw.
This is useful for OS kernels.

To be back-compatible with GCC, -m(no-)unaligned-access are also
added as Neg-Alias of -m(no-)strict-align.
---
 clang/include/clang/Driver/Options.td |  4 +-
 clang/lib/Driver/ToolChains/Arch/Mips.cpp |  9 +++
 clang/test/Driver/mips-features.c | 26 +++
 llvm/lib/Target/Mips/Mips.td  |  4 ++
 llvm/lib/Target/Mips/MipsISelLowering.cpp | 16 -
 llvm/lib/Target/Mips/MipsSEISelLowering.cpp   | 11 ++-
 llvm/lib/Target/Mips/MipsSubtarget.cpp|  2 +-
 llvm/lib/Target/Mips/MipsSubtarget.h  |  7 +-
 llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll | 10 +--
 .../CodeGen/Mips/no-unaligned-access-r6.ll| 69 +++
 10 files changed, 145 insertions(+), 13 deletions(-)
 create mode 100644 llvm/test/CodeGen/Mips/no-unaligned-access-r6.ll

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index acb7592e98100a..6567e7a7a9a745 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4704,9 +4704,9 @@ def mrvv_vector_bits_EQ : Joined<["-"], 
"mrvv-vector-bits=">, Group,
 " (RISC-V only)")>;
 
 def munaligned_access : Flag<["-"], "munaligned-access">, Group,
-  HelpText<"Allow memory accesses to be unaligned (AArch32 only)">;
+  HelpText<"Allow memory accesses to be unaligned (AArch32/MIPSr6 only)">;
 def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group,
-  HelpText<"Force all memory accesses to be aligned (AArch32 only)">;
+  HelpText<"Force all memory accesses to be aligned (AArch32/MIPSr6 only)">;
 def munaligned_symbols : Flag<["-"], "munaligned-symbols">, Group,
   HelpText<"Expect external char-aligned symbols to be without ABI alignment 
(SystemZ only)">;
 def mno_unaligned_symbols : Flag<["-"], "mno-unaligned-symbols">, 
Group,
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp 
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index fe9d112b8800b1..74a8874a3ea2b7 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -341,6 +341,15 @@ void mips::getMIPSTargetFeatures(const Driver , const 
llvm::Triple ,
"dspr2");
   AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
"msa");
+  if (Arg *A = Args.getLastArg(
+  options::OPT_mstrict_align, options::OPT_mno_strict_align,
+  options::OPT_mno_unaligned_access, options::OPT_munaligned_access)) {
+if (A->getOption().matches(options::OPT_mstrict_align) ||
+A->getOption().matches(options::OPT_mno_unaligned_access))
+  Features.push_back(Args.MakeArgString("+strict-align"));
+else
+  Features.push_back(Args.MakeArgString("-strict-align"));
+  }
 
   // Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
   // pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
diff --git a/clang/test/Driver/mips-features.c 
b/clang/test/Driver/mips-features.c
index fd06b1400c3123..5e92dccaa02abb 100644
--- a/clang/test/Driver/mips-features.c
+++ b/clang/test/Driver/mips-features.c
@@ -462,3 +462,29 @@
 // RUN: -mrelax-pic-calls -mno-relax-pic-calls 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-NO-RELAX-PIC-CALLS %s
 // CHECK-NO-RELAX-PIC-CALLS: "-mllvm" "-mips-jalr-reloc=0"
+//
+// -mno-unaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -munaligned-access -mno-strict-align \
+// RUN: -mno-unaligned-access 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-STRICT-ALIGN %s
+// CHECK-STRICT-ALIGN: "-target-feature" "+strict-align"
+//
+// -munaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -mno-unaligned-access -mstrict-align \
+// RUN: -munaligned-access 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-STRICT-ALIGN %s
+// CHECK-NO-STRICT-ALIGN: "-target-feature" "-strict-align"
+//
+// -mstrict-align
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -munaligned-access -mno-strict-align \
+// RUN: -mstrict-align 2>&1 \
+// RUN:   | FileCheck

[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)

2024-03-16 Thread YunQiang Su via cfe-commits 

https://github.com/wzssyqa edited 
https://github.com/llvm/llvm-project/pull/85174
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[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)

2024-03-16 Thread YunQiang Su via cfe-commits 

https://github.com/wzssyqa updated 
https://github.com/llvm/llvm-project/pull/85174

>From e75523f5ab1bb58a495afdd30203a0c7c93c7ec4 Mon Sep 17 00:00:00 2001
From: YunQiang Su 
Date: Thu, 14 Mar 2024 11:48:36 +0800
Subject: [PATCH] MIPS: Support -m(no-)strict-align for r6

MIPSr6 ISA requires normal load/store instructions support
misunaligned memory access, while it is not always do so
by hardware. On some microarchitectures or some corner cases
it may need support by OS.

Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't
support them, instead, r6 requires lw instruction support
misunaligned memory access. So, if -mstrict-align is used for
pre-R6, lwl/lwr won't be disabled.

If -mstrict-align is used for r6 and the access is not well
aligned, some lb/lh instructions will be used to replace lw.
This is useful for OS kernels.

To be back-compatible with GCC, -m(no-)unaligned-access are also
added as Neg-Alias of -m(no-)strict-align.
---
 clang/include/clang/Driver/Options.td |  4 +-
 clang/lib/Driver/ToolChains/Arch/Mips.cpp | 13 
 clang/test/Driver/mips-features.c | 26 +++
 llvm/lib/Target/Mips/Mips.td  |  4 ++
 llvm/lib/Target/Mips/MipsISelLowering.cpp | 16 -
 llvm/lib/Target/Mips/MipsSEISelLowering.cpp   | 11 ++-
 llvm/lib/Target/Mips/MipsSubtarget.cpp|  2 +-
 llvm/lib/Target/Mips/MipsSubtarget.h  |  7 +-
 llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll | 10 +--
 .../CodeGen/Mips/no-unaligned-access-r6.ll| 69 +++
 10 files changed, 149 insertions(+), 13 deletions(-)
 create mode 100644 llvm/test/CodeGen/Mips/no-unaligned-access-r6.ll

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index acb7592e98100a..6567e7a7a9a745 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4704,9 +4704,9 @@ def mrvv_vector_bits_EQ : Joined<["-"], 
"mrvv-vector-bits=">, Group,
 " (RISC-V only)")>;
 
 def munaligned_access : Flag<["-"], "munaligned-access">, Group,
-  HelpText<"Allow memory accesses to be unaligned (AArch32 only)">;
+  HelpText<"Allow memory accesses to be unaligned (AArch32/MIPSr6 only)">;
 def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group,
-  HelpText<"Force all memory accesses to be aligned (AArch32 only)">;
+  HelpText<"Force all memory accesses to be aligned (AArch32/MIPSr6 only)">;
 def munaligned_symbols : Flag<["-"], "munaligned-symbols">, Group,
   HelpText<"Expect external char-aligned symbols to be without ABI alignment 
(SystemZ only)">;
 def mno_unaligned_symbols : Flag<["-"], "mno-unaligned-symbols">, 
Group,
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp 
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index fe9d112b8800b1..b6c8a897106f20 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -341,6 +341,19 @@ void mips::getMIPSTargetFeatures(const Driver , const 
llvm::Triple ,
"dspr2");
   AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
"msa");
+  AddTargetFeature(Args, Features, options::OPT_mstrict_align,
+   options::OPT_mno_strict_align, "strict-align");
+  AddTargetFeature(Args, Features, options::OPT_mno_unaligned_access,
+   options::OPT_munaligned_access, "strict-align");
+  if (Arg *A = Args.getLastArg(
+  options::OPT_mstrict_align, options::OPT_mno_strict_align,
+  options::OPT_mno_unaligned_access, options::OPT_munaligned_access)) {
+if (A->getOption().matches(options::OPT_mstrict_align) ||
+A->getOption().matches(options::OPT_mno_unaligned_access))
+  Features.push_back(Args.MakeArgString("+strict-align"));
+else
+  Features.push_back(Args.MakeArgString("-strict-align"));
+  }
 
   // Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
   // pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
diff --git a/clang/test/Driver/mips-features.c 
b/clang/test/Driver/mips-features.c
index fd06b1400c3123..5e92dccaa02abb 100644
--- a/clang/test/Driver/mips-features.c
+++ b/clang/test/Driver/mips-features.c
@@ -462,3 +462,29 @@
 // RUN: -mrelax-pic-calls -mno-relax-pic-calls 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-NO-RELAX-PIC-CALLS %s
 // CHECK-NO-RELAX-PIC-CALLS: "-mllvm" "-mips-jalr-reloc=0"
+//
+// -mno-unaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -munaligned-access -mno-strict-align \
+// RUN: -mno-unaligned-access 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-STRICT-ALIGN %s
+// CHECK-STRICT-ALIGN: "-target-feature" "+strict-align"
+//
+// -munaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -mno-unaligned-access -mstrict-align \
+// RUN: -munaligned-access 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-STRICT-ALIGN %s
+//

[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)

2024-03-13 Thread via cfe-commits 

github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff 437fcc6eed99694a9f9486d29ead6a3d3275ede9 
a74a9bbd2ff2c6589db4c9756cf809c22e98fa64 -- 
clang/lib/Driver/ToolChains/Arch/Mips.cpp clang/test/Driver/mips-features.c 
llvm/lib/Target/Mips/MipsISelLowering.cpp 
llvm/lib/Target/Mips/MipsSEISelLowering.cpp 
llvm/lib/Target/Mips/MipsSubtarget.cpp llvm/lib/Target/Mips/MipsSubtarget.h
``





View the diff from clang-format here.


``diff
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp 
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 0a0d40751f..e089eb79e1 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -366,11 +366,11 @@ MipsTargetLowering::MipsTargetLowering(const 
MipsTargetMachine ,
 setOperationAction(ISD::ConstantPool,   MVT::i64,   Custom);
 setOperationAction(ISD::SELECT, MVT::i64,   Custom);
 if (Subtarget.hasMips64r6()) {
-  setOperationAction(ISD::LOAD,   MVT::i64,   Legal);
-  setOperationAction(ISD::STORE,  MVT::i64,   Legal);
+  setOperationAction(ISD::LOAD, MVT::i64, Legal);
+  setOperationAction(ISD::STORE, MVT::i64, Legal);
 } else {
-  setOperationAction(ISD::LOAD,   MVT::i64,   Custom);
-  setOperationAction(ISD::STORE,  MVT::i64,   Custom);
+  setOperationAction(ISD::LOAD, MVT::i64, Custom);
+  setOperationAction(ISD::STORE, MVT::i64, Custom);
 }
 setOperationAction(ISD::FP_TO_SINT, MVT::i64,   Custom);
 setOperationAction(ISD::SHL_PARTS,  MVT::i64,   Custom);
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp 
b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
index 5c8d64e3b6..ebaf0746d6 100644
--- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -198,11 +198,11 @@ MipsSETargetLowering::MipsSETargetLowering(const 
MipsTargetMachine ,
   setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
   setOperationAction(ISD::ATOMIC_FENCE,   MVT::Other, Custom);
   if (Subtarget.hasMips32r6()) {
-setOperationAction(ISD::LOAD,   MVT::i32, Legal);
-setOperationAction(ISD::STORE,  MVT::i32, Legal);
+setOperationAction(ISD::LOAD, MVT::i32, Legal);
+setOperationAction(ISD::STORE, MVT::i32, Legal);
   } else {
-setOperationAction(ISD::LOAD,   MVT::i32, Custom);
-setOperationAction(ISD::STORE,  MVT::i32, Custom);
+setOperationAction(ISD::LOAD, MVT::i32, Custom);
+setOperationAction(ISD::STORE, MVT::i32, Custom);
   }
 
   setTargetDAGCombine(ISD::MUL);
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp 
b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 29b277f5f3..3c67d156a6 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -79,11 +79,11 @@ MipsSubtarget::MipsSubtarget(const Triple , StringRef 
CPU, StringRef FS,
   HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
   HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
   InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), 
HasDSP(false),
-  HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 || 
Mips_Os16),
-  Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
-  HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
-  HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false),
-  NoUnalignedAccess(false),
+  HasDSPR2(false), HasDSPR3(false),
+  AllowMixed16_32(Mixed16_32 || Mips_Os16), Os16(Mips_Os16), HasMSA(false),
+  UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
+  HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false),
+  UseIndirectJumpsHazard(false), NoUnalignedAccess(false),
   StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
   TSInfo(), InstrInfo(MipsInstrInfo::create(
 initializeSubtargetDependencies(CPU, FS, TM))),

``




https://github.com/llvm/llvm-project/pull/85174
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[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)

2024-03-13 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: YunQiang Su (wzssyqa)


Changes

MIPSr6 ISA requires normal load/store instructions support misunaligned memory 
access, while it is not always do so by hardware. On some microarchitectures or 
some corner cases it may need support by OS.

Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't support them, 
instead, r6 requires lw instruction support misunaligned memory access. So, if 
-mno-unaligned-access is used for pre-R6, lwl/lwr won't be disabled.

If -mno-unaligned-access is used for r6 and the access is not well aligned, 
some lb/lh instructions will be used to replace lw. This is useful for OS 
kernels.

---
Full diff: https://github.com/llvm/llvm-project/pull/85174.diff


10 Files Affected:

- (modified) clang/include/clang/Driver/Options.td (+2-2) 
- (modified) clang/lib/Driver/ToolChains/Arch/Mips.cpp (+2) 
- (modified) clang/test/Driver/mips-features.c (+26) 
- (modified) llvm/lib/Target/Mips/Mips.td (+4) 
- (modified) llvm/lib/Target/Mips/MipsISelLowering.cpp (+13-3) 
- (modified) llvm/lib/Target/Mips/MipsSEISelLowering.cpp (+9-2) 
- (modified) llvm/lib/Target/Mips/MipsSubtarget.cpp (+1) 
- (modified) llvm/lib/Target/Mips/MipsSubtarget.h (+6-1) 
- (modified) llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll (+6-4) 
- (added) llvm/test/CodeGen/Mips/no-unaligned-access-r6.ll (+69) 


``diff
diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 1fac7b6f0093d8..6d3645f0a66828 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4696,9 +4696,9 @@ def mrvv_vector_bits_EQ : Joined<["-"], 
"mrvv-vector-bits=">, Group,
 " (RISC-V only)")>;
 
 def munaligned_access : Flag<["-"], "munaligned-access">, Group,
-  HelpText<"Allow memory accesses to be unaligned 
(AArch32/AArch64/LoongArch/RISC-V only)">;
+  HelpText<"Allow memory accesses to be unaligned 
(AArch32/AArch64/LoongArch/MIPS/RISC-V only)">;
 def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group,
-  HelpText<"Force all memory accesses to be aligned 
(AArch32/AArch64/LoongArch/RISC-V only)">;
+  HelpText<"Force all memory accesses to be aligned 
(AArch32/AArch64/LoongArch/MIPS/RISC-V only)">;
 def munaligned_symbols : Flag<["-"], "munaligned-symbols">, Group,
   HelpText<"Expect external char-aligned symbols to be without ABI alignment 
(SystemZ only)">;
 def mno_unaligned_symbols : Flag<["-"], "mno-unaligned-symbols">, 
Group,
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp 
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index fe9d112b8800b1..1de11811dccbc1 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -341,6 +341,8 @@ void mips::getMIPSTargetFeatures(const Driver , const 
llvm::Triple ,
"dspr2");
   AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
"msa");
+  AddTargetFeature(Args, Features, options::OPT_mno_unaligned_access,
+   options::OPT_munaligned_access, "no-unaligned-access");
 
   // Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
   // pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
diff --git a/clang/test/Driver/mips-features.c 
b/clang/test/Driver/mips-features.c
index fd06b1400c3123..9e724b34e869d4 100644
--- a/clang/test/Driver/mips-features.c
+++ b/clang/test/Driver/mips-features.c
@@ -462,3 +462,29 @@
 // RUN: -mrelax-pic-calls -mno-relax-pic-calls 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-NO-RELAX-PIC-CALLS %s
 // CHECK-NO-RELAX-PIC-CALLS: "-mllvm" "-mips-jalr-reloc=0"
+//
+// -mno-unaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -munaligned-access -mno-strict-align \
+// RUN: -mno-unaligned-access 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-UNALIGNED-ACCESS %s
+// CHECK-NO-UNALIGNED-ACCESS: "-target-feature" "+no-unaligned-access"
+//
+// -munaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -mno-unaligned-access -mstrict-align \
+// RUN: -munaligned-access 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-UNALIGNED-ACCESS %s
+// CHECK-UNALIGNED-ACCESS: "-target-feature" "-no-unaligned-access"
+//
+// -mstrict-align
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -munaligned-access -mno-strict-align \
+// RUN: -mstrict-align 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-UNALIGNED-ACCESS %s
+//
+// -mno-strict-align
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -mno-unaligned-access -mstrict-align \
+// RUN: -mno-strict-align 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-UNALIGNED-ACCESS %s
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index dbff25dfa0f36c..e768394dbc8192 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -208,6 +208,10

[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)

2024-03-13 Thread YunQiang Su via cfe-commits 

https://github.com/wzssyqa created 
https://github.com/llvm/llvm-project/pull/85174

MIPSr6 ISA requires normal load/store instructions support misunaligned memory 
access, while it is not always do so by hardware. On some microarchitectures or 
some corner cases it may need support by OS.

Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't support them, 
instead, r6 requires lw instruction support misunaligned memory access. So, if 
-mno-unaligned-access is used for pre-R6, lwl/lwr won't be disabled.

If -mno-unaligned-access is used for r6 and the access is not well aligned, 
some lb/lh instructions will be used to replace lw. This is useful for OS 
kernels.

>From a74a9bbd2ff2c6589db4c9756cf809c22e98fa64 Mon Sep 17 00:00:00 2001
From: YunQiang Su 
Date: Thu, 14 Mar 2024 11:48:36 +0800
Subject: [PATCH] MIPS: Support -m(no-)unaligned-access for r6

MIPSr6 ISA requires normal load/store instructions support
misunaligned memory access, while it is not always do so
by hardware. On some microarchitectures or some corner cases
it may need support by OS.

Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't
support them, instead, r6 requires lw instruction support
misunaligned memory access. So, if -mno-unaligned-access is
used for pre-R6, lwl/lwr won't be disabled.

If -mno-unaligned-access is used for r6 and the access is
not well aligned, some lb/lh instructions will be used to replace
lw. This is useful for OS kernels.
---
 clang/include/clang/Driver/Options.td |  4 +-
 clang/lib/Driver/ToolChains/Arch/Mips.cpp |  2 +
 clang/test/Driver/mips-features.c | 26 +++
 llvm/lib/Target/Mips/Mips.td  |  4 ++
 llvm/lib/Target/Mips/MipsISelLowering.cpp | 16 -
 llvm/lib/Target/Mips/MipsSEISelLowering.cpp   | 11 ++-
 llvm/lib/Target/Mips/MipsSubtarget.cpp|  1 +
 llvm/lib/Target/Mips/MipsSubtarget.h  |  7 +-
 llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll | 10 +--
 .../CodeGen/Mips/no-unaligned-access-r6.ll| 69 +++
 10 files changed, 138 insertions(+), 12 deletions(-)
 create mode 100644 llvm/test/CodeGen/Mips/no-unaligned-access-r6.ll

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 1fac7b6f0093d8..6d3645f0a66828 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4696,9 +4696,9 @@ def mrvv_vector_bits_EQ : Joined<["-"], 
"mrvv-vector-bits=">, Group,
 " (RISC-V only)")>;
 
 def munaligned_access : Flag<["-"], "munaligned-access">, Group,
-  HelpText<"Allow memory accesses to be unaligned 
(AArch32/AArch64/LoongArch/RISC-V only)">;
+  HelpText<"Allow memory accesses to be unaligned 
(AArch32/AArch64/LoongArch/MIPS/RISC-V only)">;
 def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group,
-  HelpText<"Force all memory accesses to be aligned 
(AArch32/AArch64/LoongArch/RISC-V only)">;
+  HelpText<"Force all memory accesses to be aligned 
(AArch32/AArch64/LoongArch/MIPS/RISC-V only)">;
 def munaligned_symbols : Flag<["-"], "munaligned-symbols">, Group,
   HelpText<"Expect external char-aligned symbols to be without ABI alignment 
(SystemZ only)">;
 def mno_unaligned_symbols : Flag<["-"], "mno-unaligned-symbols">, 
Group,
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp 
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index fe9d112b8800b1..1de11811dccbc1 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -341,6 +341,8 @@ void mips::getMIPSTargetFeatures(const Driver , const 
llvm::Triple ,
"dspr2");
   AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
"msa");
+  AddTargetFeature(Args, Features, options::OPT_mno_unaligned_access,
+   options::OPT_munaligned_access, "no-unaligned-access");
 
   // Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
   // pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
diff --git a/clang/test/Driver/mips-features.c 
b/clang/test/Driver/mips-features.c
index fd06b1400c3123..9e724b34e869d4 100644
--- a/clang/test/Driver/mips-features.c
+++ b/clang/test/Driver/mips-features.c
@@ -462,3 +462,29 @@
 // RUN: -mrelax-pic-calls -mno-relax-pic-calls 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-NO-RELAX-PIC-CALLS %s
 // CHECK-NO-RELAX-PIC-CALLS: "-mllvm" "-mips-jalr-reloc=0"
+//
+// -mno-unaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -munaligned-access -mno-strict-align \
+// RUN: -mno-unaligned-access 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-UNALIGNED-ACCESS %s
+// CHECK-NO-UNALIGNED-ACCESS: "-target-feature" "+no-unaligned-access"
+//
+// -munaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -mno-unaligned-access -mstrict-align \
+// RUN: -munaligned-access 2>&1 \
+// RUN:   | FileCheck