[clang-tools-extra] [clang] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)

[Simon Pilgrim via cfe-commits]

https://github.com/RKSimon commented:

Please can you confirm we have tests for underaligned pointers?

https://github.com/llvm/llvm-project/pull/74275
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[clang-tools-extra] [clang] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)

[James Y Knight via cfe-commits]

jyknight wrote:

Ping!

https://github.com/llvm/llvm-project/pull/74275
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[clang-tools-extra] [clang] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)

[James Y Knight via cfe-commits]

@@ -228,87 +228,86 @@ define void @widen_broadcast_unaligned(ptr %p0, i32 %v) {
 }
 
 define i128 @load_i128(ptr %ptr) {
-; CHECK-O0-LABEL: load_i128:
-; CHECK-O0:   # %bb.0:
-; CHECK-O0-NEXT:pushq %rbx
-; CHECK-O0-NEXT:.cfi_def_cfa_offset 16
-; CHECK-O0-NEXT:.cfi_offset %rbx, -16
-; CHECK-O0-NEXT:xorl %eax, %eax
-; CHECK-O0-NEXT:movl %eax, %ebx
-; CHECK-O0-NEXT:movq %rbx, %rax
-; CHECK-O0-NEXT:movq %rbx, %rdx
-; CHECK-O0-NEXT:movq %rbx, %rcx
-; CHECK-O0-NEXT:lock cmpxchg16b (%rdi)
-; CHECK-O0-NEXT:popq %rbx
-; CHECK-O0-NEXT:.cfi_def_cfa_offset 8
-; CHECK-O0-NEXT:retq
-;
-; CHECK-O3-LABEL: load_i128:
-; CHECK-O3:   # %bb.0:
-; CHECK-O3-NEXT:pushq %rbx
-; CHECK-O3-NEXT:.cfi_def_cfa_offset 16
-; CHECK-O3-NEXT:.cfi_offset %rbx, -16
-; CHECK-O3-NEXT:xorl %eax, %eax
-; CHECK-O3-NEXT:xorl %edx, %edx
-; CHECK-O3-NEXT:xorl %ecx, %ecx
-; CHECK-O3-NEXT:xorl %ebx, %ebx
-; CHECK-O3-NEXT:lock cmpxchg16b (%rdi)
-; CHECK-O3-NEXT:popq %rbx
-; CHECK-O3-NEXT:.cfi_def_cfa_offset 8
-; CHECK-O3-NEXT:retq
+; CHECK-O0-CUR-LABEL: load_i128:

jyknight wrote:

Done.

https://github.com/llvm/llvm-project/pull/74275
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[clang-tools-extra] [clang] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)

[Philip Reames via cfe-commits]

@@ -30115,12 +30126,16 @@ 
X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
   // If this a 64 bit atomic load on a 32-bit target and SSE2 is enabled, we
   // can use movq to do the load. If we have X87 we can load into an 80-bit
   // X87 register and store it to a stack temporary.

preames wrote:

Can you move the comment down to the case it applies to (inside the outer if).  
Currently, it binds to both cases which is misleading.

https://github.com/llvm/llvm-project/pull/74275
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[clang-tools-extra] [clang] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)

[Philip Reames via cfe-commits]

@@ -31259,14 +31274,23 @@ static SDValue LowerATOMIC_STORE(SDValue Op, 
SelectionDAG &DAG,
   if (!IsSeqCst && IsTypeLegal)
 return Op;
 
-  if (VT == MVT::i64 && !IsTypeLegal) {
+  if (!IsTypeLegal && !Subtarget.useSoftFloat() &&
+  !DAG.getMachineFunction().getFunction().hasFnAttribute(
+  Attribute::NoImplicitFloat)) {
+SDValue Chain;
+// For illegal i128 atomic_store, when AVX is enabled, we can simply emit a
+// vector store.
+if (VT == MVT::i128) {
+  if (Subtarget.is64Bit() && Subtarget.hasAVX()) {

preames wrote:

Looks like you can collapse one level of if clause here.

https://github.com/llvm/llvm-project/pull/74275
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