[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
jacquesguan wrote: > > > I think the conclusion from the LLVM sync-up call was that everyone happy > > > to move in this direction, so please add the release note and we can do a > > > final review. Thanks! > > > > > > Done, added release note. > > > > Thanks! Sorry I wasn't specific about this, but we need a Clang release note > as well. Done, added Clang release note too. https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73489 >From 4e5442531d5412e83399eb918ba405dcd580b227 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Mon, 27 Nov 2023 16:14:04 +0800 Subject: [PATCH] [clang][RISCV] Change default abi with f extension but without d extension Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is different with riscv-gnu-toolchain. In https://github.com/riscv-collab/riscv-gnu-toolchain/blob/8e9fb09a0c4b1e566492ee6f42e8c1fa5ef7e0c2/configure#L3385 when have f but not, it prefers lp64f/ilp32f but no soft float. This patch tries to make their behaviors consistent. --- clang/docs/ReleaseNotes.rst| 3 +++ clang/test/Driver/riscv-abi.c | 14 +- clang/test/Driver/riscv-cpus.c | 6 +++--- llvm/docs/ReleaseNotes.rst | 1 + llvm/lib/Support/RISCVISAInfo.cpp | 4 llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll | 4 ++-- llvm/test/CodeGen/RISCV/calling-conv-half.ll | 4 ++-- .../CodeGen/RISCV/calling-conv-rv32f-ilp32.ll | 2 +- .../CodeGen/RISCV/calling-conv-vector-float.ll | 2 +- .../RISCV/float-bitmanip-dagcombines.ll| 8 llvm/test/CodeGen/RISCV/float-frem.ll | 7 +-- llvm/test/CodeGen/RISCV/float-select-verify.ll | 2 +- .../CodeGen/RISCV/half-bitmanip-dagcombines.ll | 18 +- llvm/test/CodeGen/RISCV/half-fcmp.ll | 8 14 files changed, 45 insertions(+), 38 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 28f9393e28437..317b1f7fdeca9 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -954,6 +954,9 @@ RISC-V Support - Unaligned memory accesses can be toggled by ``-m[no-]unaligned-access`` or the aliases ``-m[no-]strict-align``. +- Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f + for RV64. + CUDA/HIP Language Changes ^ diff --git a/clang/test/Driver/riscv-abi.c b/clang/test/Driver/riscv-abi.c index e67f790e0de0e..16568271564c7 100644 --- a/clang/test/Driver/riscv-abi.c +++ b/clang/test/Driver/riscv-abi.c @@ -4,8 +4,6 @@ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s -// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \ @@ -24,6 +22,10 @@ // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -mabi=ilp32f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s // CHECK-ILP32F: "-target-abi" "ilp32f" @@ -51,8 +53,6 @@ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s -// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \ @@ -60,7 +60,11 @@ // CHECK-LP64: "-target-abi" "lp64" -// RUN: not %clang --target=riscv64-unknown-elf %s -### -march=rv64f -mabi=lp64f 2>&1 \ +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64F %s // CHECK-LP64F: "-target-abi" "lp64f" diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 6c31282d0c8d4..d7fa7c9854a48 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -113,7 +113,7 @@ // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E24: "-target-feature" "+c" // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E24: "-target-abi" "ilp32" +// MCPU-SIFIVE-E24: "-target-abi" "ilp32f" // mcpu with default march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s @@ -121,7 +121,7 @@ //
[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
jacquesguan wrote: > I think the conclusion from the LLVM sync-up call was that everyone happy to > move in this direction, so please add the release note and we can do a final > review. Thanks! Done, added release note. https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73489 >From dcc71641695128e117b290cd1e63879e0beeb796 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Mon, 27 Nov 2023 16:14:04 +0800 Subject: [PATCH] [clang][RISCV] Change default abi with f extension but without d extension Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is different with riscv-gnu-toolchain. In https://github.com/riscv-collab/riscv-gnu-toolchain/blob/8e9fb09a0c4b1e566492ee6f42e8c1fa5ef7e0c2/configure#L3385 when have f but not, it prefers lp64f/ilp32f but no soft float. This patch tries to make their behaviors consistent. --- clang/test/Driver/riscv-abi.c | 14 +- clang/test/Driver/riscv-cpus.c | 6 +++--- llvm/docs/ReleaseNotes.rst | 1 + llvm/lib/Support/RISCVISAInfo.cpp | 4 llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll | 4 ++-- llvm/test/CodeGen/RISCV/calling-conv-half.ll | 4 ++-- .../CodeGen/RISCV/calling-conv-rv32f-ilp32.ll | 2 +- .../CodeGen/RISCV/calling-conv-vector-float.ll | 2 +- .../RISCV/float-bitmanip-dagcombines.ll| 8 llvm/test/CodeGen/RISCV/float-frem.ll | 7 +-- llvm/test/CodeGen/RISCV/float-select-verify.ll | 2 +- .../CodeGen/RISCV/half-bitmanip-dagcombines.ll | 18 +- llvm/test/CodeGen/RISCV/half-fcmp.ll | 8 13 files changed, 42 insertions(+), 38 deletions(-) diff --git a/clang/test/Driver/riscv-abi.c b/clang/test/Driver/riscv-abi.c index e67f790e0de0e..16568271564c7 100644 --- a/clang/test/Driver/riscv-abi.c +++ b/clang/test/Driver/riscv-abi.c @@ -4,8 +4,6 @@ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s -// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \ @@ -24,6 +22,10 @@ // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -mabi=ilp32f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s // CHECK-ILP32F: "-target-abi" "ilp32f" @@ -51,8 +53,6 @@ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s -// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \ @@ -60,7 +60,11 @@ // CHECK-LP64: "-target-abi" "lp64" -// RUN: not %clang --target=riscv64-unknown-elf %s -### -march=rv64f -mabi=lp64f 2>&1 \ +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64F %s // CHECK-LP64F: "-target-abi" "lp64f" diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 6c31282d0c8d4..d7fa7c9854a48 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -113,7 +113,7 @@ // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E24: "-target-feature" "+c" // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E24: "-target-abi" "ilp32" +// MCPU-SIFIVE-E24: "-target-abi" "ilp32f" // mcpu with default march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s @@ -121,7 +121,7 @@ // MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E34: "-target-feature" "+c" // MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E34: "-target-abi" "ilp32" +// MCPU-SIFIVE-E34: "-target-abi" "ilp32f" // mcpu with mabi option // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s @@ -178,7 +178,7 @@ // MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature"
[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
asb wrote: This is a user-facing change that definitely needs to be acknowledged in the release notes (clang/docs/ReleaseNotes.rst) I agree with you that it seems more intuitive that a -march=rv32imaf invocation should default to ilp32f just as -march=rv32imafd defaults to ilp32d. I slightly disagree that this patch aligns us to GCC, because as I understood Kito's comment the GCC behaviour is really depending on what default ABI the toolchain was configured with. For a toolchain that defaults to ilp32d, presumably -march=rv32imaf still ends up with ilp32? That said, with the GCC cross-compilation model being so different to clang I don't think we necessarily need to match precisely, so I'm not opposed to a more intuitive default. https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
@@ -1,4 +1,4 @@ -// Check target CPUs are correctly passed. +ยท// Check target CPUs are correctly passed. jacquesguan wrote: Fixed https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
https://github.com/jacquesguan edited https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
