[llvm] [clang] [clang-tools-extra] DAG: Implement promotion for strict_fp_round (PR #74332)

[Craig Topper via cfe-commits]

@@ -2621,6 +2642,29 @@ SDValue 
DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(SDNode *N) {
   return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, Round);
 }
 
+// Explicit operation to reduce precision.  Reduce the value to half precision
+// and promote it back to the legal type.
+SDValue DAGTypeLegalizer::PromoteFloatRes_STRICT_FP_ROUND(SDNode *N) {

topperc wrote:

There are two promotion legalizers, Promote and SoftPromoteHalf. X86 and RISC-V 
use SoftPromoteHalf. Other targets use Promote. Promote doesn't convert back to 
fp16 in the right places in my opinion. If I recall correctly Promote doesn't 
convert to fp16 between two promoted fadds for example so it keeps extra 
precision.

https://github.com/llvm/llvm-project/pull/74332
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[llvm] [clang] [clang-tools-extra] DAG: Implement promotion for strict_fp_round (PR #74332)

[Matt Arsenault via cfe-commits]

https://github.com/arsenm closed https://github.com/llvm/llvm-project/pull/74332
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[llvm] [clang] [clang-tools-extra] DAG: Implement promotion for strict_fp_round (PR #74332)

[Matt Arsenault via cfe-commits]

@@ -2621,6 +2642,29 @@ SDValue 
DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(SDNode *N) {
   return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, Round);
 }
 
+// Explicit operation to reduce precision.  Reduce the value to half precision
+// and promote it back to the legal type.
+SDValue DAGTypeLegalizer::PromoteFloatRes_STRICT_FP_ROUND(SDNode *N) {
+  SDLoc DL(N);
+
+  SDValue Chain = N->getOperand(0);
+  SDValue Op = N->getOperand(1);
+  EVT VT = N->getValueType(0);
+  EVT OpVT = Op->getValueType(0);
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
+
+  // Round promoted float to desired precision
+  SDValue Round = DAG.getNode(GetPromotionOpcodeStrict(OpVT, VT), DL,
+  DAG.getVTList(IVT, MVT::Other), Chain, Op);
+  // Promote it back to the legal output type
+  SDValue Res =
+  DAG.getNode(GetPromotionOpcodeStrict(VT, NVT), DL,

arsenm wrote:

They all need updating at some point 

https://github.com/llvm/llvm-project/pull/74332
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[llvm] [clang] [clang-tools-extra] DAG: Implement promotion for strict_fp_round (PR #74332)

[Andy Kaylor via cfe-commits]

@@ -2621,6 +2642,29 @@ SDValue 
DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(SDNode *N) {
   return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, Round);
 }
 
+// Explicit operation to reduce precision.  Reduce the value to half precision
+// and promote it back to the legal type.
+SDValue DAGTypeLegalizer::PromoteFloatRes_STRICT_FP_ROUND(SDNode *N) {
+  SDLoc DL(N);
+
+  SDValue Chain = N->getOperand(0);
+  SDValue Op = N->getOperand(1);
+  EVT VT = N->getValueType(0);
+  EVT OpVT = Op->getValueType(0);
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
+
+  // Round promoted float to desired precision
+  SDValue Round = DAG.getNode(GetPromotionOpcodeStrict(OpVT, VT), DL,
+  DAG.getVTList(IVT, MVT::Other), Chain, Op);
+  // Promote it back to the legal output type
+  SDValue Res =
+  DAG.getNode(GetPromotionOpcodeStrict(VT, NVT), DL,

andykaylor wrote:

GetPromotionOpcode() is used in a lot more places. Are those not needed for 
strict or are they coming in later patches?

https://github.com/llvm/llvm-project/pull/74332
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