[clang] [clang] Default to -fno-sized-deallocation for AIX (PR #97076)

2024-06-30 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/97076
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[clang] [clang-tools-extra] [llvm] [NFC][RISCV] Simplify the dynamic linker construction logic (PR #97383)

2024-07-01 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/97383
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[clang] [clang-tools-extra] [llvm] [NFC][RISCV] Simplify the dynamic linker construction logic (PR #97383)

2024-07-01 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/97383
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[clang] [llvm] [RISCV] Remove SeenExtMap from RISCVISAInfo::parseArchString. (PR #97506)

2024-07-02 Thread Pengcheng Wang via cfe-commits 


@@ -306,7 +306,7 @@
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_ -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XSEP %s
 // RV32-XSEP: error: invalid arch name 'rv32ixabc_',
-// RV32-XSEP: extension name missing after separator '_'
+// RV32-XSEP: unsupported non-standard user-level extension 'xabc'

wangpc-pp wrote:

So there is no test coverage for `extension name missing after separator` now? 
Or is this error in a dead code path now?

https://github.com/llvm/llvm-project/pull/97506
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[clang] [llvm] [RISCV] Remove SeenExtMap from RISCVISAInfo::parseArchString. (PR #97506)

2024-07-02 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/97506
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[clang] [libcxx] [llvm] [mlir] [openmp] [CodeGen] Add dump() to MachineTraceMetrics.h (PR #97799)

2024-07-05 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/97799
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[clang] [libcxx] [llvm] [mlir] [openmp] [CodeGen] Add dump() to MachineTraceMetrics.h (PR #97799)

2024-07-05 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/97799
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[clang] [llvm] [RISCV] Remove experimental for bf16 extensions (PR #97996)

2024-07-08 Thread Pengcheng Wang via cfe-commits 


@@ -271,7 +271,7 @@ The primary goal of experimental support is to assist in 
the process of ratifica
 ``experimental-zalasr``
   LLVM implements the `0.0.5 draft specification 
`__.
 
-``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
+``zfbfmin``, ``zvfbfmin``, ``zvfbfwma``

wangpc-pp wrote:

We should not just remove the `experimental` prefix, these extensions still 
belong to `Experimental Extensions` section.

https://github.com/llvm/llvm-project/pull/97996
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[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

2024-09-03 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

> @JinjinLi868 are you still working on this?

I can ask him. Is this PR blocking some of your works on float16/bf16?

https://github.com/llvm/llvm-project/pull/89051
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[clang] [RISCV] Allow -mcmodel= to accept large for RV64 (PR #107817)

2024-09-09 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

> What's the status of backend support for the large code model? That would 
> presumably be a prerequisite to landing this.

It was just merged: https://github.com/llvm/llvm-project/pull/70308.

https://github.com/llvm/llvm-project/pull/107817
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[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

2024-09-09 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/89051
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

2024-08-14 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp created 
https://github.com/llvm/llvm-project/pull/103709

These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.

Please see https://github.com/riscv/riscv-isa-manual/pull/1306.


>From 0bdc302fb5b4dd7369d2f16a6da32412adbe7d7f Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Wed, 14 Aug 2024 15:14:36 +0800
Subject: [PATCH] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs

These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.

Please see https://github.com/riscv/riscv-isa-manual/pull/1306.
---
 .../Driver/print-supported-extensions-riscv.c |  2 ++
 .../test/Preprocessor/riscv-target-features.c | 18 
 llvm/docs/RISCVUsage.rst  |  3 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td| 19 +
 llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td| 12 +--
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  9 ++--
 llvm/test/CodeGen/RISCV/attributes.ll |  8 +++
 llvm/test/MC/RISCV/rvv/zvbc.s | 17 +++
 llvm/test/MC/RISCV/rvv/zvkgs.s| 21 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  2 ++
 10 files changed, 103 insertions(+), 8 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rvv/zvkgs.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 91f12b8416b2a4..132422393170a9 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -172,6 +172,8 @@
 // CHECK-NEXT: zicfiss  1.0   'Zicfiss' (Shadow stack)
 // CHECK-NEXT: zacas1.0   'Zacas' (Atomic 
Compare-And-Swap Instructions)
 // CHECK-NEXT: zalasr   0.1   'Zalasr' (Load-Acquire and 
Store-Release Instructions)
+// CHECK-NEXT: zvbc32e  0.7   'Zvbc32e' (Vector Carryless 
Multiplication with 32-bits elements)
+// CHECK-NEXT: zvkgs0.7   'Zvkgs' (Vector-Scalar GCM 
instructions for Cryptography)
 // CHECK-NEXT: smmpm1.0   'Smmpm' (Machine-level 
Pointer Masking for M-mode)
 // CHECK-NEXT: smnpm1.0   'Smnpm' (Machine-level 
Pointer Masking for next lower privilege mode)
 // CHECK-NEXT: ssnpm1.0   'Ssnpm' (Supervisor-level 
Pointer Masking for next lower privilege mode)
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 72131108cb5f6a..517702fab5b919 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -187,8 +187,10 @@
 // CHECK-NOT: __riscv_zicfilp {{.*$}}
 // CHECK-NOT: __riscv_zicfiss {{.*$}}
 // CHECK-NOT: __riscv_ztso {{.*$}}
+// CHECK-NOT: __riscv_zvbc32e {{.*$}}
 // CHECK-NOT: __riscv_zvfbfmin {{.*$}}
 // CHECK-NOT: __riscv_zvfbfwma {{.*$}}
+// CHECK-NOT: __riscv_zvkgs {{.*$}}
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ia -E -dM %s \
@@ -1658,6 +1660,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
 // CHECK-ZTSO-EXT: __riscv_ztso 100{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_zve32x_zvbc32e0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_zve32x_zvbc32e0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s
+// CHECK-ZVBC32E-EXT: __riscv_zvbc32e 7000{{$}}
+
 // RUN: %clang --target=riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32ifzvfbfmin1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s
@@ -1674,6 +1684,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
 // CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 100{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_zve32x_zvkgs0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_zve32x_zvkgs0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s
+// CHECK-ZVKGS-EXT: __riscv_zvkgs 7000{{$}}
+
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32izicfiss1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index b3c7b0e3883d01..3af1428138c021 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -302,6 +302,9 @@ The primary goal of experimental support is to assist in 
the process of ratifica
 ``ex

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

2024-08-14 Thread Pengcheng Wang via cfe-commits 


@@ -302,6 +302,9 @@ The primary goal of experimental support is to assist in 
the process of ratifica
 ``experimental-zicfilp``, ``experimental-zicfiss``
   LLVM implements the `1.0 release specification 
`__.
 
+``experimental-zvbc32e``, ``experimental-zvkgs``
+  LLVM implements the `0.7 release specification 
`__.

wangpc-pp wrote:

Actually, there is no repo&tag. They are in a pull request.

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

2024-08-14 Thread Pengcheng Wang via cfe-commits 


@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = 
NoConstraint in {
  SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;
 } // Predicates = [HasStdExtZvkg]
 
+let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

wangpc-pp wrote:

Oops, I think we should set this for `vghsh.vv` and `vgmul.vv` as well. cc 
@4vtomat 

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

2024-08-14 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/102155
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

2024-08-14 Thread Pengcheng Wang via cfe-commits 


@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = 
NoConstraint in {
  SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;
 } // Predicates = [HasStdExtZvkg]
 
+let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

wangpc-pp wrote:

Why? I was thinking it should be the same case?

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

2024-08-14 Thread Pengcheng Wang via cfe-commits 


@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = 
NoConstraint in {
  SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;
 } // Predicates = [HasStdExtZvkg]
 
+let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

wangpc-pp wrote:

I made a comment in https://github.com/riscv/riscv-isa-manual/pull/1306. We may 
not need this constraint to keep the consistency between `.vv` and `.vs`.

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

2024-08-14 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

2024-08-14 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

2024-08-15 Thread Pengcheng Wang via cfe-commits 


@@ -754,6 +754,17 @@ def HasStdExtZvbc : 
Predicate<"Subtarget->hasStdExtZvbc()">,
 AssemblerPredicate<(all_of FeatureStdExtZvbc),
 "'Zvbc' (Vector Carryless Multiplication)">;
 
+def FeatureStdExtZvbc32e
+: RISCVExperimentalExtension<"zvbc32e", 0, 7,
+ "'Zvbc32e' (Vector Carryless Multiplication 
with 32-bits elements)">;
+def HasStdExtZvbc32e : Predicate<"Subtarget->hasStdExtZvbc32e()">,

wangpc-pp wrote:

Currently no, I will remove it.

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

2024-08-15 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/103709

>From 0bdc302fb5b4dd7369d2f16a6da32412adbe7d7f Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Wed, 14 Aug 2024 15:14:36 +0800
Subject: [PATCH 1/2] [RISCV][MC] Support experimental extensions Zvbc32e and
 Zvkgs

These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.

Please see https://github.com/riscv/riscv-isa-manual/pull/1306.
---
 .../Driver/print-supported-extensions-riscv.c |  2 ++
 .../test/Preprocessor/riscv-target-features.c | 18 
 llvm/docs/RISCVUsage.rst  |  3 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td| 19 +
 llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td| 12 +--
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  9 ++--
 llvm/test/CodeGen/RISCV/attributes.ll |  8 +++
 llvm/test/MC/RISCV/rvv/zvbc.s | 17 +++
 llvm/test/MC/RISCV/rvv/zvkgs.s| 21 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  2 ++
 10 files changed, 103 insertions(+), 8 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rvv/zvkgs.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 91f12b8416b2a4..132422393170a9 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -172,6 +172,8 @@
 // CHECK-NEXT: zicfiss  1.0   'Zicfiss' (Shadow stack)
 // CHECK-NEXT: zacas1.0   'Zacas' (Atomic 
Compare-And-Swap Instructions)
 // CHECK-NEXT: zalasr   0.1   'Zalasr' (Load-Acquire and 
Store-Release Instructions)
+// CHECK-NEXT: zvbc32e  0.7   'Zvbc32e' (Vector Carryless 
Multiplication with 32-bits elements)
+// CHECK-NEXT: zvkgs0.7   'Zvkgs' (Vector-Scalar GCM 
instructions for Cryptography)
 // CHECK-NEXT: smmpm1.0   'Smmpm' (Machine-level 
Pointer Masking for M-mode)
 // CHECK-NEXT: smnpm1.0   'Smnpm' (Machine-level 
Pointer Masking for next lower privilege mode)
 // CHECK-NEXT: ssnpm1.0   'Ssnpm' (Supervisor-level 
Pointer Masking for next lower privilege mode)
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 72131108cb5f6a..517702fab5b919 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -187,8 +187,10 @@
 // CHECK-NOT: __riscv_zicfilp {{.*$}}
 // CHECK-NOT: __riscv_zicfiss {{.*$}}
 // CHECK-NOT: __riscv_ztso {{.*$}}
+// CHECK-NOT: __riscv_zvbc32e {{.*$}}
 // CHECK-NOT: __riscv_zvfbfmin {{.*$}}
 // CHECK-NOT: __riscv_zvfbfwma {{.*$}}
+// CHECK-NOT: __riscv_zvkgs {{.*$}}
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ia -E -dM %s \
@@ -1658,6 +1660,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
 // CHECK-ZTSO-EXT: __riscv_ztso 100{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_zve32x_zvbc32e0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_zve32x_zvbc32e0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s
+// CHECK-ZVBC32E-EXT: __riscv_zvbc32e 7000{{$}}
+
 // RUN: %clang --target=riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32ifzvfbfmin1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s
@@ -1674,6 +1684,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
 // CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 100{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_zve32x_zvkgs0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_zve32x_zvkgs0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s
+// CHECK-ZVKGS-EXT: __riscv_zvkgs 7000{{$}}
+
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32izicfiss1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index b3c7b0e3883d01..3af1428138c021 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -302,6 +302,9 @@ The primary goal of experimental support is to assist in 
the process of ratifica
 ``experimental-zicfilp``, ``experimental-zicfiss``
   LLVM implements the `1.0 release specification 
`__.
 
+``experimental-zvbc32e``, ``experimen

[clang] [llvm] [RISCV] Zimop/Zcmop are ratified (PR #87966)

2024-04-08 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp created 
https://github.com/llvm/llvm-project/pull/87966

Remove them from experimental.

See also:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc


>From 5b312a80cdc3396e3e35d906176f56349392d437 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Mon, 8 Apr 2024 15:33:19 +0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
 =?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6-beta.1
---
 clang/test/Driver/riscv-profiles.c| 26 +++---
 .../test/Preprocessor/riscv-target-features.c | 36 +--
 llvm/docs/RISCVUsage.rst  |  6 
 llvm/lib/Support/RISCVISAInfo.cpp | 26 +++---
 llvm/lib/Target/RISCV/RISCVFeatures.td|  4 +--
 llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td  |  2 --
 llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td  |  2 --
 llvm/test/CodeGen/RISCV/attributes.ll | 16 -
 .../test/CodeGen/RISCV/rv32zimop-intrinsic.ll |  2 +-
 .../test/CodeGen/RISCV/rv64zimop-intrinsic.ll |  2 +-
 llvm/test/MC/RISCV/attribute-arch.s   |  2 +-
 llvm/test/MC/RISCV/compressed-zicfiss.s   | 12 +++
 llvm/test/MC/RISCV/rv32zcmop-invalid.s|  2 +-
 llvm/test/MC/RISCV/rv32zimop-invalid.s|  2 +-
 llvm/test/MC/RISCV/rvzcmop-valid.s| 12 +++
 llvm/test/MC/RISCV/rvzimop-valid.s| 12 +++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   |  4 +--
 17 files changed, 78 insertions(+), 90 deletions(-)

diff --git a/clang/test/Driver/riscv-profiles.c 
b/clang/test/Driver/riscv-profiles.c
index ec9206f2f45370..647567d4c971f4 100644
--- a/clang/test/Driver/riscv-profiles.c
+++ b/clang/test/Driver/riscv-profiles.c
@@ -111,7 +111,7 @@
 // RVA22S64: "-target-feature" "+svinval"
 // RVA22S64: "-target-feature" "+svpbmt"
 
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 
-menable-experimental-extensions \
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 \
 // RUN:   | FileCheck -check-prefix=RVA23U64 %s
 // RVA23U64: "-target-feature" "+m"
 // RVA23U64: "-target-feature" "+a"
@@ -133,13 +133,13 @@
 // RVA23U64: "-target-feature" "+zihintntl"
 // RVA23U64: "-target-feature" "+zihintpause"
 // RVA23U64: "-target-feature" "+zihpm"
-// RVA23U64: "-target-feature" "+experimental-zimop"
+// RVA23U64: "-target-feature" "+zimop"
 // RVA23U64: "-target-feature" "+za64rs"
 // RVA23U64: "-target-feature" "+zawrs"
 // RVA23U64: "-target-feature" "+zfa"
 // RVA23U64: "-target-feature" "+zfhmin"
 // RVA23U64: "-target-feature" "+zcb"
-// RVA23U64: "-target-feature" "+experimental-zcmop"
+// RVA23U64: "-target-feature" "+zcmop"
 // RVA23U64: "-target-feature" "+zba"
 // RVA23U64: "-target-feature" "+zbb"
 // RVA23U64: "-target-feature" "+zbs"
@@ -172,13 +172,13 @@
 // RVA23S64: "-target-feature" "+zihintntl"
 // RVA23S64: "-target-feature" "+zihintpause"
 // RVA23S64: "-target-feature" "+zihpm"
-// RVA23S64: "-target-feature" "+experimental-zimop"
+// RVA23S64: "-target-feature" "+zimop"
 // RVA23S64: "-target-feature" "+za64rs"
 // RVA23S64: "-target-feature" "+zawrs"
 // RVA23S64: "-target-feature" "+zfa"
 // RVA23S64: "-target-feature" "+zfhmin"
 // RVA23S64: "-target-feature" "+zcb"
-// RVA23S64: "-target-feature" "+experimental-zcmop"
+// RVA23S64: "-target-feature" "+zcmop"
 // RVA23S64: "-target-feature" "+zba"
 // RVA23S64: "-target-feature" "+zbb"
 // RVA23S64: "-target-feature" "+zbs"
@@ -207,7 +207,7 @@
 // RVA23S64: "-target-feature" "+svnapot"
 // RVA23S64: "-target-feature" "+svpbmt"
 
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23u64 
-menable-experimental-extensions \
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23u64 \
 // RUN:   | FileCheck -check-prefix=RVB23U64 %s
 // RVB23U64: "-target-feature" "+m"
 // RVB23U64: "-target-feature" "+a"
@@ -228,12 +228,12 @@
 // RVB23U64: "-target-feature" "+zihintntl"
 // RVB23U64: "-target-feature" "+zihintpause"
 // RVB23U64: "-target-feature" "+zihpm"
-// RVB23U64: "-target-feature" "+experimental-zimop"
+// RVB23U64: "-target-feature" "+zimop"
 // RVB23U64: "-target-feature" "+za64rs"
 // RVB23U64: "-target-feature" "+zawrs"
 // RVB23U64: "-target-feature" "+zfa"
 // RVB23U64: "-target-feature" "+zcb"
-// RVB23U64: "-target-feature" "+experimental-zcmop"
+// RVB23U64: "-target-feature" "+zcmop"
 // RVB23U64: "-target-feature" "+zba"
 // RVB23U64: "-target-feature" "+zbb"
 // RVB23U64: "-target-feature" "+zbs"
@@ -261,12 +261,12 @@
 // RVB23S64: "-target-feature" "+zihintntl"
 // RVB23S64: "-target-feature" "+zihintpause"
 // RVB23S64: "-target-feature" "+zihpm"
-// RVB23S64: "-target-feature" "+experimental-zimop"
+// RVB23S64: "-target-feature" "+zimop"
 // RVB23S64: "-target-feature" "+za64rs"
 // RVB23S64: "-target-feature" "+zawrs"
 // RVB23S64: "-target-feature" "+zfa"
 // RVB23S64: "-target-feature" "+zcb"
-// RVB23S64:

[clang] [llvm] [RISCV] Zimop/Zcmop are ratified (PR #87966)

2024-04-08 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/87966
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[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

2024-04-09 Thread Pengcheng Wang via cfe-commits 


@@ -7238,10 +7238,15 @@ void Clang::ConstructJob(Compilation &C, const 
JobAction &JA,
   Args.addOptInFlag(CmdArgs, options::OPT_frelaxed_template_template_args,
 options::OPT_fno_relaxed_template_template_args);
 
-  // -fsized-deallocation is off by default, as it is an ABI-breaking change 
for
-  // most platforms.
-  Args.addOptInFlag(CmdArgs, options::OPT_fsized_deallocation,
-options::OPT_fno_sized_deallocation);
+  // -fsized-deallocation is on by default in C++14 onwards and otherwise off
+  // by default.
+  if (Arg *A = Args.getLastArg(options::OPT_fsized_deallocation,
+   options::OPT_fno_sized_deallocation)) {
+if (A->getOption().matches(options::OPT_fno_sized_deallocation))
+  CmdArgs.push_back("-fno-sized-deallocation");

wangpc-pp wrote:

I don't know if I understand correctly, but I think we need both clang and cc1 
options for `sized_deallocation`. Please see `aligned_allocation` case, which 
is the same as `sized_deallocation`:
https://github.com/llvm/llvm-project/blob/24e8c6a09b7d226dbe706aeae7aebf479a1e5087/clang/include/clang/Driver/Options.td#L3355-L3358
And there are a lot of tests assumed we have cc1 options 
`-fno-sized-deallocation` and `-fsized-deallocation` like 
[`clang/test/SemaCXX/builtin-operator-new-delete.cpp`](https://github.com/llvm/llvm-project/blob/main/clang/test/SemaCXX/builtin-operator-new-delete.cpp).

https://github.com/llvm/llvm-project/pull/83774
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[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

2024-04-09 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/83774

>From 1e556e00e59377c76c168293d6c2678f7a874742 Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/2] [clang] Enable sized deallocation by default in C++14
 onwards

Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.

Differential Revision: https://reviews.llvm.org/D112921
---
 .../clangd/unittests/FindTargetTests.cpp  |   4 +-
 .../checkers/misc/new-delete-overloads.cpp|  10 -
 clang/docs/ReleaseNotes.rst   |   5 +
 clang/include/clang/Driver/Options.td |   7 +-
 clang/lib/Driver/ToolChains/Clang.cpp |  13 +-
 clang/lib/Driver/ToolChains/Darwin.cpp|  58 -
 clang/lib/Driver/ToolChains/Darwin.h  |   4 +
 clang/lib/Driver/ToolChains/ZOS.cpp   |   6 +
 clang/test/AST/ast-dump-expr-json.cpp |   2 +-
 clang/test/AST/ast-dump-expr.cpp  |   2 +-
 clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
 clang/test/Analysis/cxxnewexpr-callback.cpp   |   4 +-
 .../basic.stc.dynamic.deallocation/p2.cpp |   2 +-
 clang/test/CXX/drs/dr292.cpp  |  17 +-
 .../test/CXX/expr/expr.unary/expr.new/p14.cpp |   2 +-
 .../CodeGenCXX/cxx1y-sized-deallocation.cpp   |  10 +-
 .../CodeGenCXX/cxx1z-aligned-allocation.cpp   |   6 +-
 .../CodeGenCXX/cxx2a-destroying-delete.cpp|   4 +-
 clang/test/CodeGenCXX/delete-two-arg.cpp  |   4 +-
 clang/test/CodeGenCXX/delete.cpp  |  12 +-
 clang/test/CodeGenCXX/dllimport.cpp   |   4 +-
 clang/test/CodeGenCXX/new.cpp |   6 +-
 .../coro-aligned-alloc-2.cpp  |   2 -
 .../CodeGenCoroutines/coro-aligned-alloc.cpp  |   6 +-
 clang/test/CodeGenCoroutines/coro-alloc.cpp   |   6 +-
 clang/test/CodeGenCoroutines/coro-cleanup.cpp |   6 +-
 clang/test/CodeGenCoroutines/coro-dealloc.cpp |   2 -
 clang/test/CodeGenCoroutines/coro-gro.cpp |   3 +-
 clang/test/CodeGenCoroutines/pr56919.cpp  |   9 +-
 clang/test/Lexer/cxx-features.cpp |  20 +-
 clang/test/PCH/cxx1z-aligned-alloc.cpp|  10 +-
 clang/test/SemaCXX/MicrosoftExtensions.cpp|   8 +-
 .../SemaCXX/builtin-operator-new-delete.cpp   |   2 +-
 .../test/SemaCXX/cxx1y-sized-deallocation.cpp |   2 +-
 .../unavailable_aligned_allocation.cpp|  15 +-
 clang/tools/clang-repl/CMakeLists.txt |  59 +
 clang/unittests/Interpreter/CMakeLists.txt|  59 +
 .../StaticAnalyzer/CallEventTest.cpp  |   2 +-
 clang/www/cxx_status.html |  11 +-
 .../support.dynamic/libcpp_deallocate.sh.cpp  |   3 +
 .../sized_delete_array14.pass.cpp |   8 +-
 .../new.delete.single/sized_delete14.pass.cpp |   8 +-
 42 files changed, 555 insertions(+), 112 deletions(-)

diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp 
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 0af6036734ba53..1b7b96281dfaa5 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
   [[delete]] x;
 }
   )cpp";
-  EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+  // Sized deallocation is enabled by default in C++14 onwards.
+  EXPECT_DECLS("CXXDeleteExpr",
+   "void operator delete(void *, unsigned long) noexcept");
 }
 
 TEST_F(TargetDeclTest, DependentExprs) {
diff --git 
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp 
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e19..f86fe8a4c5b14f 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
 // CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has 
no matching declaration of 'operator delete' at the same scope
 void *operator new(size_t size) noexcept(false);
 
-struct T {
-  // Sized deallocations are not enabled by default, and so this new/delete 
pair
-  // does not match. However, we expect only one warning, for the new, because
-  // the operator delete is a placement delete and we do not warn on 
mismatching
-  // placement operations.
-  // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new' 
has no matching declaration of 'operator delete' at the same scope
-  void *operator new(size_t size) noexcept;
-  void operator delete(void *ptr, size_t) noexcept; // ok only if sized 
deallocation is enabled
-};
-
 struct U {
   void *operator new(size_t size) noexcept;
   void operator delete(void *ptr) noexcept;
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 8fc925350849

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-04-11 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From 169ef33f585b964d9af7a7628919271245f318fc Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c  |  5 -
 clang/test/Preprocessor/riscv-target-features.c | 12 
 llvm/docs/RISCVUsage.rst|  1 +
 llvm/lib/Support/RISCVISAInfo.cpp   |  3 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td  |  8 
 llvm/test/CodeGen/RISCV/attributes.ll   |  4 
 llvm/unittests/Support/RISCVISAInfoTest.cpp |  6 ++
 7 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 8399b4e97f86d5..8e48ed9160992d 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index ec7764bb538189..dfdef72cb1e755 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -191,6 +192,17 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 6f5eba263def43..232604788f9972 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 7a19d24d1ff483..99962501153b0e 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -52,6 +52,7 @@ static const char *RISCVGImplications[] = {
 // NOTE: This table should be sorted alphabetically by extension name.
 static const RISCVSupportedExtension SupportedExtensions[] = {
 {"a", {2, 1}},
+{"b", {1, 0}},
 {"c", {2, 0}},
 {"d", {2, 2}},
 {"e", {2, 0}},
@@ -1106,6 +1107,7 @@ Error RISCVISAInfo::checkDependency() {
   return Error::success();
 }
 
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1181,6 +1183,7 @@ struct ImpliedExtsEntry {
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
 {{"d"}, {ImpliedExtsD}},
 {{"f"}, {ImpliedExtsF}},
 {{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 794455aa730400..33541be37537df 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -430,6 +430,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureStdExtB
+: SubtargetFeature<"b", "HasStdExtB", "true",
+   "'B' (the collection of the Zba, Zbb, Zbs exten

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-04-11 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From 169ef33f585b964d9af7a7628919271245f318fc Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH 1/2] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c  |  5 -
 clang/test/Preprocessor/riscv-target-features.c | 12 
 llvm/docs/RISCVUsage.rst|  1 +
 llvm/lib/Support/RISCVISAInfo.cpp   |  3 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td  |  8 
 llvm/test/CodeGen/RISCV/attributes.ll   |  4 
 llvm/unittests/Support/RISCVISAInfoTest.cpp |  6 ++
 7 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 8399b4e97f86d5..8e48ed9160992d 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index ec7764bb538189..dfdef72cb1e755 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -191,6 +192,17 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 6f5eba263def43..232604788f9972 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 7a19d24d1ff483..99962501153b0e 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -52,6 +52,7 @@ static const char *RISCVGImplications[] = {
 // NOTE: This table should be sorted alphabetically by extension name.
 static const RISCVSupportedExtension SupportedExtensions[] = {
 {"a", {2, 1}},
+{"b", {1, 0}},
 {"c", {2, 0}},
 {"d", {2, 2}},
 {"e", {2, 0}},
@@ -1106,6 +1107,7 @@ Error RISCVISAInfo::checkDependency() {
   return Error::success();
 }
 
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1181,6 +1183,7 @@ struct ImpliedExtsEntry {
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
 {{"d"}, {ImpliedExtsD}},
 {{"f"}, {ImpliedExtsF}},
 {{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 794455aa730400..33541be37537df 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -430,6 +430,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureStdExtB
+: SubtargetFeature<"b", "HasStdExtB", "true",
+   "'B' (the collection of the Zba, Zbb, Zbs e

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-04-11 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From 169ef33f585b964d9af7a7628919271245f318fc Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH 1/3] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c  |  5 -
 clang/test/Preprocessor/riscv-target-features.c | 12 
 llvm/docs/RISCVUsage.rst|  1 +
 llvm/lib/Support/RISCVISAInfo.cpp   |  3 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td  |  8 
 llvm/test/CodeGen/RISCV/attributes.ll   |  4 
 llvm/unittests/Support/RISCVISAInfoTest.cpp |  6 ++
 7 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 8399b4e97f86d5..8e48ed9160992d 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index ec7764bb538189..dfdef72cb1e755 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -191,6 +192,17 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 6f5eba263def43..232604788f9972 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 7a19d24d1ff483..99962501153b0e 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -52,6 +52,7 @@ static const char *RISCVGImplications[] = {
 // NOTE: This table should be sorted alphabetically by extension name.
 static const RISCVSupportedExtension SupportedExtensions[] = {
 {"a", {2, 1}},
+{"b", {1, 0}},
 {"c", {2, 0}},
 {"d", {2, 2}},
 {"e", {2, 0}},
@@ -1106,6 +1107,7 @@ Error RISCVISAInfo::checkDependency() {
   return Error::success();
 }
 
+static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1181,6 +1183,7 @@ struct ImpliedExtsEntry {
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"b"}, {ImpliedExtsB}},
 {{"d"}, {ImpliedExtsD}},
 {{"f"}, {ImpliedExtsF}},
 {{"v"}, {ImpliedExtsV}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 794455aa730400..33541be37537df 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -430,6 +430,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureStdExtB
+: SubtargetFeature<"b", "HasStdExtB", "true",
+   "'B' (the collection of the Zba, Zbb, Zbs e

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

2024-04-11 Thread Pengcheng Wang via cfe-commits 


@@ -704,6 +705,12 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
 // CHECK-ZACAS-EXT: __riscv_zacas 100{{$}}
 
+// RUN: %clang --target=riscv32 -march=rv32izama16b -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZAMA16B-EXT %s

wangpc-pp wrote:

We need to indent 2 spaces here.

https://github.com/llvm/llvm-project/pull/88474
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[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

2024-06-05 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

> Filed https://gitlab.kitware.com/cmake/cmake/-/issues/26031

So this is a cmake bug, not clang's, right?


https://github.com/llvm/llvm-project/pull/90373
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[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)

2024-06-05 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

Spacemit K1 is the name of the product/SoC or whatever you call it. The 
processor definitions in the RISCV backend are focusing on the CPU core.
For Spacemit K1, its name should be `X60`? I don't know……

https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)

2024-06-05 Thread Pengcheng Wang via cfe-commits 


@@ -381,3 +381,14 @@ def XIANGSHAN_NANHU : 
RISCVProcessorModel<"xiangshan-nanhu",
 TuneZExtHFusion,
 TuneZExtWFusion,
 TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+   NoSchedModel,

wangpc-pp wrote:

Indent here.

https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-05 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp created 
https://github.com/llvm/llvm-project/pull/94578

`riscv_atomics.h` contains all builtins for atomics.


>From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Thu, 6 Jun 2024 13:48:34 +0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
 =?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6-beta.1
---
 clang/include/clang/Basic/BuiltinsRISCV.td|  18 ++
 clang/lib/CodeGen/CGBuiltin.cpp   |  22 ++
 clang/lib/Headers/CMakeLists.txt  |   1 +
 clang/lib/Headers/riscv_atomics.h |  36 +++
 clang/lib/Sema/SemaRISCV.cpp  |  10 +-
 .../RISCV/atomics-intrinsics/zalrsc-error.c   |  13 +
 .../CodeGen/RISCV/atomics-intrinsics/zalrsc.c | 222 ++
 .../CodeGen/RISCV/atomics-intrinsics/zawrs.c  |  42 
 llvm/include/llvm/IR/IntrinsicsRISCV.td   |  32 +++
 llvm/lib/Target/RISCV/RISCVInstrInfoA.td  |  25 ++
 llvm/lib/Target/RISCV/RISCVInstrInfoZa.td |   5 +-
 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll|  74 ++
 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll|  74 ++
 llvm/test/CodeGen/RISCV/zawrs.ll  |  33 +++
 14 files changed, 605 insertions(+), 2 deletions(-)
 create mode 100644 clang/lib/Headers/riscv_atomics.h
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zawrs.ll

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td 
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..458c755179417 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,21 @@ let Features = "zihintntl", Attributes = 
[CustomTypeChecking] in {
 def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===--===//
+// Zawrs extension.
+//===--===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
+
+//===--===//
+// Zalrsc extension.
+//===--===//
+let Features = "zalrsc" in {
+def lr_w : RISCVBuiltin<"int(int *, _Constant unsigned int)">;
+def lr_d : RISCVBuiltin<"int64_t(int64_t *, _Constant unsigned int)">;
+def sc_w : RISCVBuiltin<"int(int, int *, _Constant unsigned int)">;
+def sc_d : RISCVBuiltin<"int64_t(int64_t, int64_t *, _Constant unsigned int)">;
+} // Features = "zalrsc"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 37d0c478e0330..db48c69e10c86 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21769,6 +21769,28 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
 ID = Intrinsic::riscv_sm3p1;
 break;
 
+  // Zawrs
+  case RISCV::BI__builtin_riscv_wrs_nto:
+ID = Intrinsic::riscv_wrs_nto;
+break;
+  case RISCV::BI__builtin_riscv_wrs_sto:
+ID = Intrinsic::riscv_wrs_sto;
+break;
+
+  // Zalrsc
+  case RISCV::BI__builtin_riscv_lr_w:
+ID = Intrinsic::riscv_lr_w;
+break;
+  case RISCV::BI__builtin_riscv_lr_d:
+ID = Intrinsic::riscv_lr_d;
+break;
+  case RISCV::BI__builtin_riscv_sc_w:
+ID = Intrinsic::riscv_sc_w;
+break;
+  case RISCV::BI__builtin_riscv_sc_d:
+ID = Intrinsic::riscv_sc_d;
+break;
+
   // Zihintntl
   case RISCV::BI__builtin_riscv_ntl_load: {
 llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index d3090e488306f..cf2fbf1893772 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
   )
 
 set(riscv_files
+  riscv_atomics.h
   riscv_bitmanip.h
   riscv_crypto.h
   riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomics.h 
b/clang/lib/Headers/riscv_atomics.h
new file mode 100644
index 0..35db57fe36131
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomics.h
@@ -0,0 +1,36 @@
+/*=== riscv_atomics.h - RISC-V atomics intrinsics --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-05 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp converted_to_draft 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-05 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/94578

>From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Thu, 6 Jun 2024 13:48:34 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6-beta.1
---
 clang/include/clang/Basic/BuiltinsRISCV.td|  18 ++
 clang/lib/CodeGen/CGBuiltin.cpp   |  22 ++
 clang/lib/Headers/CMakeLists.txt  |   1 +
 clang/lib/Headers/riscv_atomics.h |  36 +++
 clang/lib/Sema/SemaRISCV.cpp  |  10 +-
 .../RISCV/atomics-intrinsics/zalrsc-error.c   |  13 +
 .../CodeGen/RISCV/atomics-intrinsics/zalrsc.c | 222 ++
 .../CodeGen/RISCV/atomics-intrinsics/zawrs.c  |  42 
 llvm/include/llvm/IR/IntrinsicsRISCV.td   |  32 +++
 llvm/lib/Target/RISCV/RISCVInstrInfoA.td  |  25 ++
 llvm/lib/Target/RISCV/RISCVInstrInfoZa.td |   5 +-
 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll|  74 ++
 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll|  74 ++
 llvm/test/CodeGen/RISCV/zawrs.ll  |  33 +++
 14 files changed, 605 insertions(+), 2 deletions(-)
 create mode 100644 clang/lib/Headers/riscv_atomics.h
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zawrs.ll

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td 
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..458c755179417 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,21 @@ let Features = "zihintntl", Attributes = 
[CustomTypeChecking] in {
 def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===--===//
+// Zawrs extension.
+//===--===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
+
+//===--===//
+// Zalrsc extension.
+//===--===//
+let Features = "zalrsc" in {
+def lr_w : RISCVBuiltin<"int(int *, _Constant unsigned int)">;
+def lr_d : RISCVBuiltin<"int64_t(int64_t *, _Constant unsigned int)">;
+def sc_w : RISCVBuiltin<"int(int, int *, _Constant unsigned int)">;
+def sc_d : RISCVBuiltin<"int64_t(int64_t, int64_t *, _Constant unsigned int)">;
+} // Features = "zalrsc"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 37d0c478e0330..db48c69e10c86 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21769,6 +21769,28 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
 ID = Intrinsic::riscv_sm3p1;
 break;
 
+  // Zawrs
+  case RISCV::BI__builtin_riscv_wrs_nto:
+ID = Intrinsic::riscv_wrs_nto;
+break;
+  case RISCV::BI__builtin_riscv_wrs_sto:
+ID = Intrinsic::riscv_wrs_sto;
+break;
+
+  // Zalrsc
+  case RISCV::BI__builtin_riscv_lr_w:
+ID = Intrinsic::riscv_lr_w;
+break;
+  case RISCV::BI__builtin_riscv_lr_d:
+ID = Intrinsic::riscv_lr_d;
+break;
+  case RISCV::BI__builtin_riscv_sc_w:
+ID = Intrinsic::riscv_sc_w;
+break;
+  case RISCV::BI__builtin_riscv_sc_d:
+ID = Intrinsic::riscv_sc_d;
+break;
+
   // Zihintntl
   case RISCV::BI__builtin_riscv_ntl_load: {
 llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index d3090e488306f..cf2fbf1893772 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
   )
 
 set(riscv_files
+  riscv_atomics.h
   riscv_bitmanip.h
   riscv_crypto.h
   riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomics.h 
b/clang/lib/Headers/riscv_atomics.h
new file mode 100644
index 0..35db57fe36131
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomics.h
@@ -0,0 +1,36 @@
+/*=== riscv_atomics.h - RISC-V atomics intrinsics --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===--

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-05 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-05 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp ready_for_review 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-05 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp unassigned 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-05 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp unassigned 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-06 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/94578

>From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Thu, 6 Jun 2024 13:48:34 +0800
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6-beta.1
---
 clang/include/clang/Basic/BuiltinsRISCV.td|  18 ++
 clang/lib/CodeGen/CGBuiltin.cpp   |  22 ++
 clang/lib/Headers/CMakeLists.txt  |   1 +
 clang/lib/Headers/riscv_atomics.h |  36 +++
 clang/lib/Sema/SemaRISCV.cpp  |  10 +-
 .../RISCV/atomics-intrinsics/zalrsc-error.c   |  13 +
 .../CodeGen/RISCV/atomics-intrinsics/zalrsc.c | 222 ++
 .../CodeGen/RISCV/atomics-intrinsics/zawrs.c  |  42 
 llvm/include/llvm/IR/IntrinsicsRISCV.td   |  32 +++
 llvm/lib/Target/RISCV/RISCVInstrInfoA.td  |  25 ++
 llvm/lib/Target/RISCV/RISCVInstrInfoZa.td |   5 +-
 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll|  74 ++
 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll|  74 ++
 llvm/test/CodeGen/RISCV/zawrs.ll  |  33 +++
 14 files changed, 605 insertions(+), 2 deletions(-)
 create mode 100644 clang/lib/Headers/riscv_atomics.h
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zawrs.ll

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td 
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..458c755179417 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,21 @@ let Features = "zihintntl", Attributes = 
[CustomTypeChecking] in {
 def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===--===//
+// Zawrs extension.
+//===--===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
+
+//===--===//
+// Zalrsc extension.
+//===--===//
+let Features = "zalrsc" in {
+def lr_w : RISCVBuiltin<"int(int *, _Constant unsigned int)">;
+def lr_d : RISCVBuiltin<"int64_t(int64_t *, _Constant unsigned int)">;
+def sc_w : RISCVBuiltin<"int(int, int *, _Constant unsigned int)">;
+def sc_d : RISCVBuiltin<"int64_t(int64_t, int64_t *, _Constant unsigned int)">;
+} // Features = "zalrsc"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 37d0c478e0330..db48c69e10c86 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21769,6 +21769,28 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
 ID = Intrinsic::riscv_sm3p1;
 break;
 
+  // Zawrs
+  case RISCV::BI__builtin_riscv_wrs_nto:
+ID = Intrinsic::riscv_wrs_nto;
+break;
+  case RISCV::BI__builtin_riscv_wrs_sto:
+ID = Intrinsic::riscv_wrs_sto;
+break;
+
+  // Zalrsc
+  case RISCV::BI__builtin_riscv_lr_w:
+ID = Intrinsic::riscv_lr_w;
+break;
+  case RISCV::BI__builtin_riscv_lr_d:
+ID = Intrinsic::riscv_lr_d;
+break;
+  case RISCV::BI__builtin_riscv_sc_w:
+ID = Intrinsic::riscv_sc_w;
+break;
+  case RISCV::BI__builtin_riscv_sc_d:
+ID = Intrinsic::riscv_sc_d;
+break;
+
   // Zihintntl
   case RISCV::BI__builtin_riscv_ntl_load: {
 llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index d3090e488306f..cf2fbf1893772 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
   )
 
 set(riscv_files
+  riscv_atomics.h
   riscv_bitmanip.h
   riscv_crypto.h
   riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomics.h 
b/clang/lib/Headers/riscv_atomics.h
new file mode 100644
index 0..35db57fe36131
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomics.h
@@ -0,0 +1,36 @@
+/*=== riscv_atomics.h - RISC-V atomics intrinsics --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===--

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-06 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/94578

>From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Thu, 6 Jun 2024 13:48:34 +0800
Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6-beta.1
---
 clang/include/clang/Basic/BuiltinsRISCV.td|  18 ++
 clang/lib/CodeGen/CGBuiltin.cpp   |  22 ++
 clang/lib/Headers/CMakeLists.txt  |   1 +
 clang/lib/Headers/riscv_atomics.h |  36 +++
 clang/lib/Sema/SemaRISCV.cpp  |  10 +-
 .../RISCV/atomics-intrinsics/zalrsc-error.c   |  13 +
 .../CodeGen/RISCV/atomics-intrinsics/zalrsc.c | 222 ++
 .../CodeGen/RISCV/atomics-intrinsics/zawrs.c  |  42 
 llvm/include/llvm/IR/IntrinsicsRISCV.td   |  32 +++
 llvm/lib/Target/RISCV/RISCVInstrInfoA.td  |  25 ++
 llvm/lib/Target/RISCV/RISCVInstrInfoZa.td |   5 +-
 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll|  74 ++
 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll|  74 ++
 llvm/test/CodeGen/RISCV/zawrs.ll  |  33 +++
 14 files changed, 605 insertions(+), 2 deletions(-)
 create mode 100644 clang/lib/Headers/riscv_atomics.h
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zawrs.ll

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td 
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..458c755179417 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,21 @@ let Features = "zihintntl", Attributes = 
[CustomTypeChecking] in {
 def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===--===//
+// Zawrs extension.
+//===--===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
+
+//===--===//
+// Zalrsc extension.
+//===--===//
+let Features = "zalrsc" in {
+def lr_w : RISCVBuiltin<"int(int *, _Constant unsigned int)">;
+def lr_d : RISCVBuiltin<"int64_t(int64_t *, _Constant unsigned int)">;
+def sc_w : RISCVBuiltin<"int(int, int *, _Constant unsigned int)">;
+def sc_d : RISCVBuiltin<"int64_t(int64_t, int64_t *, _Constant unsigned int)">;
+} // Features = "zalrsc"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 37d0c478e0330..db48c69e10c86 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21769,6 +21769,28 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
 ID = Intrinsic::riscv_sm3p1;
 break;
 
+  // Zawrs
+  case RISCV::BI__builtin_riscv_wrs_nto:
+ID = Intrinsic::riscv_wrs_nto;
+break;
+  case RISCV::BI__builtin_riscv_wrs_sto:
+ID = Intrinsic::riscv_wrs_sto;
+break;
+
+  // Zalrsc
+  case RISCV::BI__builtin_riscv_lr_w:
+ID = Intrinsic::riscv_lr_w;
+break;
+  case RISCV::BI__builtin_riscv_lr_d:
+ID = Intrinsic::riscv_lr_d;
+break;
+  case RISCV::BI__builtin_riscv_sc_w:
+ID = Intrinsic::riscv_sc_w;
+break;
+  case RISCV::BI__builtin_riscv_sc_d:
+ID = Intrinsic::riscv_sc_d;
+break;
+
   // Zihintntl
   case RISCV::BI__builtin_riscv_ntl_load: {
 llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index d3090e488306f..cf2fbf1893772 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
   )
 
 set(riscv_files
+  riscv_atomics.h
   riscv_bitmanip.h
   riscv_crypto.h
   riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomics.h 
b/clang/lib/Headers/riscv_atomics.h
new file mode 100644
index 0..35db57fe36131
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomics.h
@@ -0,0 +1,36 @@
+/*=== riscv_atomics.h - RISC-V atomics intrinsics --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===--

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-06 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

2024-06-06 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

The description needs to be revised.

https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-10 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

> lr/sc builtins are extremely fragile: there's no reasonable way for the 
> compiler to guarantee that the sc is placed in such a way that it will 
> eventually succeed.

I think the user should have enough knowledges about lr/sc to make the logic 
reasonable. If we don't provide these intrinsics, the user who wants to 
implement custom locks will use inline assemly instead.

>  (The equivalent intrinsics do exist on ARM, but ARM has significantly 
> stronger guarantees here. Even then, it's not completely reliable.)

I don't know much about there intrinsics on ARM, what are the `stronger 
guarantees`?

https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-10 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

If we are talking about the necessariness of adding these intrinsics, please 
refer to the ARM implementations in DPDK 
(https://github.com/DPDK/dpdk/blob/76cef1af8bdaeaf67a5c4ca5df3f221df994dc46/lib/eal/arm/include/rte_pause_64.h).We
 want to use 

https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)

2024-06-10 Thread Pengcheng Wang via cfe-commits 


@@ -86,8 +86,14 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const 
llvm::Triple &Triple,
   // and other features (ex. mirco architecture feature) from mcpu
   if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
 StringRef CPU = A->getValue();
-if (CPU == "native")
+if (CPU == "native") {
   CPU = llvm::sys::getHostCPUName();
+  llvm::StringMap HostFeatures;
+  if (llvm::sys::getHostCPUFeatures(HostFeatures))

wangpc-pp wrote:

Open discussion here: `CPU` may fail and return `generic`. Should we failback 
to use `getHostCPUFeatures` if `getHostCPUName` fails? Or we should use 
`getHostCPUFeatures` all the time?

https://github.com/llvm/llvm-project/pull/94352
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-06-10 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From 9ab05b9f68def57e9abb9d5ac65293b84aacc95a Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c   |  5 -
 clang/test/Preprocessor/riscv-target-features.c  | 12 
 llvm/docs/RISCVUsage.rst |  1 +
 llvm/docs/ReleaseNotes.rst   |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td   |  8 
 llvm/test/CodeGen/RISCV/attributes.ll|  4 
 llvm/unittests/TargetParser/RISCVISAInfoTest.cpp |  9 ++---
 7 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index ddf617bbb6237..ffd92e1f398c4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 09b9ad0a160bb..91307141e0406 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -194,6 +195,17 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 35115e67ecf92..ef06f80c747f9 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 8cdb9db087c77..b46994bbcd66d 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -152,6 +152,7 @@ Changes to the RISC-V Backend
 * Zaamo and Zalrsc are no longer experimental.
 * Processors that enable post reg-alloc scheduling (PostMachineScheduler) by 
default should use the `UsePostRAScheduler` subtarget feature. Setting 
`PostRAScheduler = 1` in the scheduler model will have no effect on the 
enabling of the PostMachineScheduler.
 * Zabha is no longer experimental.
+* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9bf06850483d8..011edca019fd6 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -477,6 +477,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureStdExtB
+: RISCVExtension<"b", 1, 0,
+ "'B' (the collection of the Zba, Zbb, Zbs extensions)",
+ [FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
+def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
+   AssemblerPredicate<(all_of FeatureStdExtB),
+   "'B' (the collection of the Zba, Zbb, Zbs 
extensions)">;
+
 def FeatureStdExtZbkb
 : RISCVExtension<"zbkb", 1, 0,
  "'Z

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-06-10 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/76893
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[clang] [clang-tools-extra] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

2024-06-10 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/94313
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[clang] [clang-tools-extra] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

2024-06-10 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/94313
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[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

2024-06-17 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

2024-06-17 Thread Pengcheng Wang via cfe-commits 


@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : 
RISCVProcessorModel<"xiangshan-nanhu",
 TuneZExtHFusion,
 TuneZExtWFusion,
 TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+   NoSchedModel,
+   !listconcat(RVA22S64Features,

wangpc-pp wrote:

I think you can just add `RVA22S64` feature here, no `!listconcat` is needed as 
profiles are subtarget features now.
```
[RVI20U32,
 FeatureStdExtV,
 FeatureStdExtSscofpmf,
 ...
```

https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

2024-06-17 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

2024-06-18 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/95953
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[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

2024-06-18 Thread Pengcheng Wang via cfe-commits 


@@ -358,3 +358,21 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s
+// MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+m" "-target-feature" "+c"

wangpc-pp wrote:

One `-target-feature` one line please.

https://github.com/llvm/llvm-project/pull/95953
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[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

2024-06-18 Thread Pengcheng Wang via cfe-commits 


@@ -358,3 +358,21 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s
+// MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+m" "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-abi" "ilp32"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV32 %s
+// MTUNE-SYNTACORE-SCR3-RV32: "-tune-cpu" "syntacore-scr3-rv32"

wangpc-pp wrote:

I think we don't need to test this, but I don't have a strong opinion here.

https://github.com/llvm/llvm-project/pull/95953
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[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

2024-06-18 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp approved this pull request.

LGTM with nits.

https://github.com/llvm/llvm-project/pull/95953
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[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

2024-06-19 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp approved this pull request.


https://github.com/llvm/llvm-project/pull/95953
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[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

2024-06-21 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs builtins (PR #96283)

2024-06-21 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp created 
https://github.com/llvm/llvm-project/pull/96283

`riscv_atomic.h` contains all builtins for atomics.

Currently, we suppoprt builtins for Zawrs extension.

Doc: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/79


>From 4b597ebf69de59d62e5587a27cedf2b12e831763 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Fri, 21 Jun 2024 16:09:13 +0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
 =?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6-beta.1
---
 clang/include/clang/Basic/BuiltinsRISCV.td|  8 
 clang/lib/CodeGen/CGBuiltin.cpp   |  8 
 clang/lib/Headers/CMakeLists.txt  |  1 +
 clang/lib/Headers/riscv_atomic.h  | 18 
 .../CodeGen/RISCV/atomics-intrinsics/zawrs.c  | 42 +++
 llvm/include/llvm/IR/IntrinsicsRISCV.td   | 10 +
 llvm/lib/Target/RISCV/RISCVInstrInfoZa.td |  5 ++-
 llvm/test/CodeGen/RISCV/zawrs-intrinsic.ll| 33 +++
 8 files changed, 124 insertions(+), 1 deletion(-)
 create mode 100644 clang/lib/Headers/riscv_atomic.h
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
 create mode 100644 llvm/test/CodeGen/RISCV/zawrs-intrinsic.ll

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td 
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..429f1356aa5fd 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,11 @@ let Features = "zihintntl", Attributes = 
[CustomTypeChecking] in {
 def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===--===//
+// Zawrs extension.
+//===--===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2516ed4508242..1e130cad6d00d 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21834,6 +21834,14 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
 ID = Intrinsic::riscv_sm3p1;
 break;
 
+  // Zawrs
+  case RISCV::BI__builtin_riscv_wrs_nto:
+ID = Intrinsic::riscv_wrs_nto;
+break;
+  case RISCV::BI__builtin_riscv_wrs_sto:
+ID = Intrinsic::riscv_wrs_sto;
+break;
+
   // Zihintntl
   case RISCV::BI__builtin_riscv_ntl_load: {
 llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 89fa0ecd45eb4..f8f430e6921cb 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
   )
 
 set(riscv_files
+  riscv_atomic.h
   riscv_bitmanip.h
   riscv_crypto.h
   riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomic.h b/clang/lib/Headers/riscv_atomic.h
new file mode 100644
index 0..4c548bdfa8253
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomic.h
@@ -0,0 +1,18 @@
+/*=== riscv_atomic.h - RISC-V atomic intrinsics ===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RISCV_ATOMIC_H
+#define __RISCV_ATOMIC_H
+
+#ifdef __riscv_zawrs
+#define __riscv_wrs_nto __builtin_riscv_wrs_nto
+#define __riscv_wrs_sto __builtin_riscv_wrs_sto
+#endif
+
+#endif
diff --git a/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c 
b/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
new file mode 100644
index 0..e3d4899244ca4
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
@@ -0,0 +1,42 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zawrs -disable-O0-optnone \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefixes=CHECK-RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zawrs -disable-O0-optnone \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV32-LABEL: define dso_local void @zawrs_nto
+// CHECK-RV32-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:call void @llvm.riscv.wrs.nto()
+// CHECK-RV32-NEXT:ret void
+//
+// CHECK-RV64-LABEL: define dso_local void @zawrs_nto
+// CHECK-RV64-SAME

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-05-30 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From a780efe3e297fe59c5521ea5387dda12905a4423 Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c|  5 -
 .../test/Preprocessor/riscv-target-features.c | 20 +++
 llvm/docs/RISCVUsage.rst  |  1 +
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  4 ++--
 llvm/test/CodeGen/RISCV/attributes.ll | 18 ++---
 .../TargetParser/RISCVISAInfoTest.cpp |  9 ++---
 8 files changed, 45 insertions(+), 21 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index ddf617bbb6237..ffd92e1f398c4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 0865add7e8fb8..ff3f31ec67c1c 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -194,6 +195,25 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32i_zba_zbb_zbs -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64i_zba_zbb_zbs -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
+// CHECK-COMBINE-INTO-B: __riscv_b 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 5ecee2a480f7d..34c2b967a4111 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 1e1ccb495c366..6e96545c739e3 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -132,6 +132,7 @@ Changes to the RISC-V Backend
 * Added smstateen extension to -march. CSR names for smstateen were already 
supported.
 * Zaamo and Zalrsc are no longer experimental.
 * Processors that enable post reg-alloc scheduling (PostMachineScheduler) by 
default should use the `UsePostRAScheduler` subtarget feature. Setting 
`PostRAScheduler = 1` in the scheduler model will have no effect on the 
enabling of the PostMachineScheduler.
+* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a78d78946be31..6acb147330d62 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -477,6 +477,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureSt

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-05-30 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

Ping. The B extension has been ratified and I hava rebased this PR.

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-05-30 Thread Pengcheng Wang via cfe-commits 


@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
 }
 
 static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"},  {"zks"},   {"zvkn"},  {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"},  {"zks"},   {"zvkn"},

wangpc-pp wrote:

@kito-cheng WDYT?

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add Smcsrind and Sscsrind extension (PR #93952)

2024-06-02 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

> Specification link: https://github.com/riscvarchive/riscv-indirect-csr-access

You may need to update link to 
https://github.com/riscv/riscv-isa-manual/blob/main/src/indirect-csr.adoc.

https://github.com/llvm/llvm-project/pull/93952
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[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

2024-06-04 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

> This broke building clang on Windows with PGO:
> 
> ```
> FAILED: bin/clang-repl.exe lib/clang-repl.lib 
> cmd.exe /C "cmd.exe /C "D:\task_171745452431588\fetches\cmake\bin\cmake.exe 
> -E __create_def 
> D:\task_171745452431588\fetches\llvm-project\build\stage2\build\tools\clang\tools\clang-repl\CMakeFiles\clang-repl.dir\.\exports.def
>  
> D:\task_171745452431588\fetches\llvm-project\build\stage2\build\tools\clang\tools\clang-repl\CMakeFiles\clang-repl.dir\.\exports.def.objs
>  --nm=D:\task_171745452431588\fetches\clang\bin\llvm-nm.exe && cd 
> D:\task_171745452431588\fetches\llvm-project\build\stage2\build" && 
> D:\task_171745452431588\fetches\cmake\bin\cmake.exe -E vs_link_exe 
> --intdir=tools\clang\tools\clang-repl\CMakeFiles\clang-repl.dir 
> --rc="D:\task_171745452431588\fetches\vs\Windows 
> Kits\10\bin\10.0.22621.0\x64\rc.exe" 
> --mt="D:\task_171745452431588\fetches\vs\Windows 
> Kits\10\bin\10.0.22621.0\x64\mt.exe" --manifests  -- 
> D:\task_171745452431588\fetches\clang\bin\lld-link.exe /nologo 
> @CMakeFiles\clang-repl.rsp  /out:bin\clang-repl.exe 
> /implib:lib\clang-repl.lib /pdb:bin\clang-repl.pdb /version:0.0 /machine:x64 
> /STACK:1000 
> /libpath:"D:/task_171745452431588/fetches/clang/lib/clang/19/lib/windows" 
> /INCREMENTAL:NO /subsystem:console   /EXPORT:??_7type_info@@6B@ 
> /EXPORT:?__type_info_root_node@@3U__type_info_node@@A 
> /EXPORT:?nothrow@std@@3Unothrow_t@1@B /EXPORT:_Init_thread_abort 
> /EXPORT:_Init_thread_epoch /EXPORT:_Init_thread_footer 
> /EXPORT:_Init_thread_header /EXPORT:_tls_index /EXPORT:??2@YAPEAX_K@Z 
> /EXPORT:??3@YAXPEAX@Z /EXPORT:??_U@YAPEAX_K@Z /EXPORT:??_V@YAXPEAX@Z 
> /EXPORT:??3@YAXPEAX_K@Z 
> /DEF:"D:/task_171745452431588/fetches/llvm-project/build/stage2/build/tools/clang/tools/clang-repl/clang-repl.def"
>   -Wl,--long-plt 
> /DEF:tools\clang\tools\clang-repl\CMakeFiles\clang-repl.dir\.\exports.def  && 
> cd ."
> LINK: command "D:\task_171745452431588\fetches\clang\bin\lld-link.exe /nologo 
> @CMakeFiles\clang-repl.rsp /out:bin\clang-repl.exe /implib:lib\clang-repl.lib 
> /pdb:bin\clang-repl.pdb /version:0.0 /machine:x64 /STACK:1000 
> /libpath:D:/task_171745452431588/fetches/clang/lib/clang/19/lib/windows 
> /INCREMENTAL:NO /subsystem:console /EXPORT:??_7type_info@@6B@ 
> /EXPORT:?__type_info_root_node@@3U__type_info_node@@A 
> /EXPORT:?nothrow@std@@3Unothrow_t@1@B /EXPORT:_Init_thread_abort 
> /EXPORT:_Init_thread_epoch /EXPORT:_Init_thread_footer 
> /EXPORT:_Init_thread_header /EXPORT:_tls_index /EXPORT:??2@YAPEAX_K@Z 
> /EXPORT:??3@YAXPEAX@Z /EXPORT:??_U@YAPEAX_K@Z /EXPORT:??_V@YAXPEAX@Z 
> /EXPORT:??3@YAXPEAX_K@Z 
> /DEF:D:/task_171745452431588/fetches/llvm-project/build/stage2/build/tools/clang/tools/clang-repl/clang-repl.def
>  -Wl,--long-plt 
> /DEF:tools\clang\tools\clang-repl\CMakeFiles\clang-repl.dir\.\exports.def 
> /MANIFEST /MANIFESTFILE:bin\clang-repl.exe.manifest" failed (exit code 1) 
> with the following output:
> lld-link: error: : undefined symbol: __profc_??$?0$$BY03DUdesc
> lld-link: error: : undefined symbol: __profc_??$?0$$BY04DW4OptionHidden
> lld-link: error: : undefined symbol: __profc_??$?0$$BY09DW4OptionHidden
> lld-link: error: : undefined symbol: __profc_??$?0$$BY0BC
> lld-link: error: : undefined symbol: __profc_??$?0$$BY0N
> lld-link: error: : undefined symbol: __profc_??$?0W4FormattingFlags
> lld-link: error: : undefined symbol: __profc_??$?4$$BY05D
> lld-link: error: : undefined symbol: __profc_??$?6PEBD
> lld-link: error: : undefined symbol: __profc_??$_Emplace_reallocate
> lld-link: error: : undefined symbol: __profc_??$_Reallocate_for
> lld-link: error: : undefined symbol: __profc_??$_Reallocate_grow_by
> lld-link: error: : undefined symbol: __profc_??$_Traits_find 
> lld-link: error: : undefined symbol: __profc_??$_Traits_rfind
> lld-link: error: : undefined symbol: __profc_??$_Uninitialized_move
> lld-link: error: : undefined symbol: __profc_??$addValue
> lld-link: error: : undefined symbol: __profc_??$handleErrors 
> lld-link: error: : undefined symbol: __profc_??$setValue
> lld-link: error: : undefined symbol: __profc_??0?$OptionValueCopy
> lld-link: error: : undefined symbol: __profc_??0Completion
> lld-link: error: : undefined symbol: __profc_??0ErrorList
> lld-link: error: too many errors emitted, stopping now (use /errorlimit:0 to 
> see all errors)
> ```

I don't have such environment, can you provide more details? And it seems these 
undefined symbols are not symbols for `delete`.

https://github.com/llvm/llvm-project/pull/90373
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[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)

2024-06-04 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

This seems to be a breaking change, do we need to create issue in 
https://github.com/riscv-non-isa/rvv-intrinsic-doc?

https://github.com/llvm/llvm-project/pull/94318
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[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)

2024-06-04 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/94318
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[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

2024-06-05 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

> What kind of detail are you looking for?

Mainly about the commands of cmake building. Does this failure bind to a 
buildbot?
And can @AaronBallman @vitalybuka @vgvassilev help me to figure this out?

https://github.com/llvm/llvm-project/pull/90373
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-06-05 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From ac2c10240160783ebbd65332230c8c294fef2442 Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c|  5 -
 .../test/Preprocessor/riscv-target-features.c | 20 +++
 llvm/docs/RISCVUsage.rst  |  1 +
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/test/CodeGen/RISCV/attributes.ll |  4 
 .../TargetParser/RISCVISAInfoTest.cpp |  9 ++---
 7 files changed, 36 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index ddf617bbb6237..ffd92e1f398c4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 09b9ad0a160bb..5d578a02b20fb 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -194,6 +195,25 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32i_zba_zbb_zbs -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64i_zba_zbb_zbs -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
+// CHECK-COMBINE-INTO-B: __riscv_b 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 35115e67ecf92..ef06f80c747f9 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 393b97efa5470..2aee464cdaf2d 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -142,6 +142,7 @@ Changes to the RISC-V Backend
 * Zaamo and Zalrsc are no longer experimental.
 * Processors that enable post reg-alloc scheduling (PostMachineScheduler) by 
default should use the `UsePostRAScheduler` subtarget feature. Setting 
`PostRAScheduler = 1` in the scheduler model will have no effect on the 
enabling of the PostMachineScheduler.
 * Zabha is no longer experimental.
+* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9bf06850483d8..011edca019fd6 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -477,6 +477,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureStdExtB
+: RISCVExtension<"b", 1, 0,
+ "'B' (the collection of the Zba, Zbb, Zbs extensions)",
+

[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-06-05 Thread Pengcheng Wang via cfe-commits 


@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
 }
 
 static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"},  {"zks"},   {"zvkn"},  {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"},  {"zks"},   {"zvkn"},

wangpc-pp wrote:

I removed this part.
We can support combination of B extension in a separate patch if we need it.

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

2024-06-05 Thread Pengcheng Wang via cfe-commits 


@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
 }
 
 static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"},  {"zks"},   {"zvkn"},  {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"},  {"zks"},   {"zvkn"},

wangpc-pp wrote:

> Remove this from `CombineIntoExts` may cause `__riscv_b` become less useful I 
> think?

Yeah, but I think @topperc's concern makes sense as well. Will binutils 
complain or just ignore unknown extensions?

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

2024-04-16 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

Can you add it to RVA23 profile?
https://github.com/llvm/llvm-project/blob/f71e25bb669d662f98823d6d81b3f918538c9239/llvm/lib/Support/RISCVISAInfo.cpp#L250-L284

https://github.com/llvm/llvm-project/pull/88474
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[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

2024-04-16 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

> Can you add it to RVA23 profile?
> 
> https://github.com/llvm/llvm-project/blob/f71e25bb669d662f98823d6d81b3f918538c9239/llvm/lib/Support/RISCVISAInfo.cpp#L250-L284

Never mind, it's an optional extension.

https://github.com/llvm/llvm-project/pull/88474
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[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

2024-04-16 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/88474
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[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

2024-04-16 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/84877

>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.4
---
 clang/test/Driver/riscv-cpus.c| 319 ++
 clang/test/Misc/target-invalid-cpu-note.c |   8 +-
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 224 ++-
 3 files changed, 539 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..a285f0f9c41f54 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -302,3 +302,322 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// Check profile CPUs
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s
+// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s
+// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s
+// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s
+// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s
+// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicb

[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

2024-04-16 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

Ping.

https://github.com/llvm/llvm-project/pull/84877
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[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

2024-04-17 Thread Pengcheng Wang via cfe-commits 


@@ -7238,10 +7238,15 @@ void Clang::ConstructJob(Compilation &C, const 
JobAction &JA,
   Args.addOptInFlag(CmdArgs, options::OPT_frelaxed_template_template_args,
 options::OPT_fno_relaxed_template_template_args);
 
-  // -fsized-deallocation is off by default, as it is an ABI-breaking change 
for
-  // most platforms.
-  Args.addOptInFlag(CmdArgs, options::OPT_fsized_deallocation,
-options::OPT_fno_sized_deallocation);
+  // -fsized-deallocation is on by default in C++14 onwards and otherwise off
+  // by default.
+  if (Arg *A = Args.getLastArg(options::OPT_fsized_deallocation,
+   options::OPT_fno_sized_deallocation)) {
+if (A->getOption().matches(options::OPT_fno_sized_deallocation))
+  CmdArgs.push_back("-fno-sized-deallocation");

wangpc-pp wrote:

Sorry for bothering you, but I'd like to know if it makes sense to you. 
@MaskRay 

https://github.com/llvm/llvm-project/pull/83774
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[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

2024-04-19 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

Has KunMingHu's RTl been finalized (IIRC, we have developing vector unit)? And 
can we have different doc for different generations of XiangShan?

https://github.com/llvm/llvm-project/pull/89359
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[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

2024-04-21 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

Ping.

https://github.com/llvm/llvm-project/pull/83774
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[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

2024-04-21 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/83774

>From f84c6c7a108d179ffa7f5ec423d852cb667e0f33 Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH] [clang] Enable sized deallocation by default in C++14 onwards

Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.

Differential Revision: https://reviews.llvm.org/D112921
---
 .../clangd/unittests/FindTargetTests.cpp  |   4 +-
 .../checkers/misc/new-delete-overloads.cpp|  10 -
 clang/docs/ReleaseNotes.rst   |   5 +
 clang/include/clang/Driver/Options.td |   8 +-
 clang/lib/Driver/ToolChains/Clang.cpp |  13 +-
 clang/lib/Driver/ToolChains/Darwin.cpp|  58 -
 clang/lib/Driver/ToolChains/Darwin.h  |   4 +
 clang/lib/Driver/ToolChains/ZOS.cpp   |   6 +
 clang/test/AST/ast-dump-expr-json.cpp |   2 +-
 clang/test/AST/ast-dump-expr.cpp  |   2 +-
 clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
 clang/test/Analysis/cxxnewexpr-callback.cpp   |   4 +-
 .../basic.stc.dynamic.deallocation/p2.cpp |   2 +-
 clang/test/CXX/drs/cwg292.cpp |  17 +-
 .../test/CXX/expr/expr.unary/expr.new/p14.cpp |   2 +-
 .../CodeGenCXX/cxx1y-sized-deallocation.cpp   |  10 +-
 .../CodeGenCXX/cxx1z-aligned-allocation.cpp   |   6 +-
 .../CodeGenCXX/cxx2a-destroying-delete.cpp|   4 +-
 clang/test/CodeGenCXX/delete-two-arg.cpp  |   4 +-
 clang/test/CodeGenCXX/delete.cpp  |  12 +-
 clang/test/CodeGenCXX/dllimport.cpp   |   4 +-
 clang/test/CodeGenCXX/new.cpp |   6 +-
 .../coro-aligned-alloc-2.cpp  |   2 -
 .../CodeGenCoroutines/coro-aligned-alloc.cpp  |   6 +-
 clang/test/CodeGenCoroutines/coro-alloc.cpp   |   6 +-
 clang/test/CodeGenCoroutines/coro-cleanup.cpp |   6 +-
 clang/test/CodeGenCoroutines/coro-dealloc.cpp |   2 -
 clang/test/CodeGenCoroutines/coro-gro.cpp |   3 +-
 clang/test/CodeGenCoroutines/pr56919.cpp  |   9 +-
 clang/test/Lexer/cxx-features.cpp |  20 +-
 clang/test/PCH/cxx1z-aligned-alloc.cpp|  10 +-
 clang/test/SemaCXX/MicrosoftExtensions.cpp|   8 +-
 .../SemaCXX/builtin-operator-new-delete.cpp   |   2 +-
 .../test/SemaCXX/cxx1y-sized-deallocation.cpp |   2 +-
 .../unavailable_aligned_allocation.cpp|  15 +-
 clang/tools/clang-repl/CMakeLists.txt |  59 +
 clang/unittests/Interpreter/CMakeLists.txt|  59 +
 .../StaticAnalyzer/CallEventTest.cpp  |   2 +-
 clang/www/cxx_status.html |  11 +-
 .../support.dynamic/libcpp_deallocate.sh.cpp  |   3 +
 .../sized_delete_array14.pass.cpp |   8 +-
 .../new.delete.single/sized_delete14.pass.cpp |   8 +-
 42 files changed, 555 insertions(+), 113 deletions(-)

diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp 
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 0af6036734ba53..1b7b96281dfaa5 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
   [[delete]] x;
 }
   )cpp";
-  EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+  // Sized deallocation is enabled by default in C++14 onwards.
+  EXPECT_DECLS("CXXDeleteExpr",
+   "void operator delete(void *, unsigned long) noexcept");
 }
 
 TEST_F(TargetDeclTest, DependentExprs) {
diff --git 
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp 
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e19..f86fe8a4c5b14f 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
 // CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has 
no matching declaration of 'operator delete' at the same scope
 void *operator new(size_t size) noexcept(false);
 
-struct T {
-  // Sized deallocations are not enabled by default, and so this new/delete 
pair
-  // does not match. However, we expect only one warning, for the new, because
-  // the operator delete is a placement delete and we do not warn on 
mismatching
-  // placement operations.
-  // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new' 
has no matching declaration of 'operator delete' at the same scope
-  void *operator new(size_t size) noexcept;
-  void operator delete(void *ptr, size_t) noexcept; // ok only if sized 
deallocation is enabled
-};
-
 struct U {
   void *operator new(size_t size) noexcept;
   void operator delete(void *ptr) noexcept;
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index c44f238e33846b..e

[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)

2024-04-22 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/89684
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[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)

2024-04-22 Thread Pengcheng Wang via cfe-commits 


@@ -1,12 +1,12 @@
-//===-- RISCVISAInfo.cpp - RISC-V Arch String Parser *- C++ 
-*-===//

wangpc-pp wrote:

We shouldn't remove `*- C++ -*` here I think, it's for editors like Emacs.

https://github.com/llvm/llvm-project/pull/89684
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[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)

2024-04-22 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp commented:

I think this patch doesn't need to be stacked on #89335.

https://github.com/llvm/llvm-project/pull/89684
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[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

2024-04-22 Thread Pengcheng Wang via cfe-commits 


@@ -0,0 +1,194 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 4
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -target-feature +fullbf16 
-S -emit-llvm %s -o - | FileCheck %s

wangpc-pp wrote:

```suggestion
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -target-feature +fullbf16 
-disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
```
We can run `mem2reg` to reduce CHECKs.

https://github.com/llvm/llvm-project/pull/89051
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[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)

2024-04-22 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/89684
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[clang] [NFC][clang] Fix typo of `riscv_rvv_vector_bits` in AttrDocs (PR #101046)

2024-07-29 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp approved this pull request.


https://github.com/llvm/llvm-project/pull/101046
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[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

2024-04-24 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/83774

>From 2ed73672a548b77a36675343b420ef57266e46ab Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH] [clang] Enable sized deallocation by default in C++14 onwards

Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.

Differential Revision: https://reviews.llvm.org/D112921
---
 .../clangd/unittests/FindTargetTests.cpp  |   4 +-
 .../checkers/misc/new-delete-overloads.cpp|  10 -
 clang/docs/ReleaseNotes.rst   |   5 +
 clang/include/clang/Driver/Options.td |   8 +-
 clang/lib/Driver/ToolChains/Clang.cpp |  13 +-
 clang/lib/Driver/ToolChains/Darwin.cpp|  58 -
 clang/lib/Driver/ToolChains/Darwin.h  |   4 +
 clang/lib/Driver/ToolChains/ZOS.cpp   |   6 +
 clang/test/AST/ast-dump-expr-json.cpp |   2 +-
 clang/test/AST/ast-dump-expr.cpp  |   2 +-
 clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
 clang/test/Analysis/cxxnewexpr-callback.cpp   |   4 +-
 .../basic.stc.dynamic.deallocation/p2.cpp |   2 +-
 clang/test/CXX/drs/cwg292.cpp |  17 +-
 .../test/CXX/expr/expr.unary/expr.new/p14.cpp |   2 +-
 .../CodeGenCXX/cxx1y-sized-deallocation.cpp   |  10 +-
 .../CodeGenCXX/cxx1z-aligned-allocation.cpp   |   6 +-
 .../CodeGenCXX/cxx2a-destroying-delete.cpp|   4 +-
 clang/test/CodeGenCXX/delete-two-arg.cpp  |   4 +-
 clang/test/CodeGenCXX/delete.cpp  |  12 +-
 clang/test/CodeGenCXX/dllimport.cpp   |   4 +-
 clang/test/CodeGenCXX/new.cpp |   6 +-
 .../coro-aligned-alloc-2.cpp  |   2 -
 .../CodeGenCoroutines/coro-aligned-alloc.cpp  |   6 +-
 clang/test/CodeGenCoroutines/coro-alloc.cpp   |   6 +-
 clang/test/CodeGenCoroutines/coro-cleanup.cpp |   6 +-
 clang/test/CodeGenCoroutines/coro-dealloc.cpp |   2 -
 clang/test/CodeGenCoroutines/coro-gro.cpp |   3 +-
 clang/test/CodeGenCoroutines/pr56919.cpp  |   9 +-
 clang/test/Lexer/cxx-features.cpp |  20 +-
 clang/test/PCH/cxx1z-aligned-alloc.cpp|  10 +-
 clang/test/SemaCXX/MicrosoftExtensions.cpp|   8 +-
 .../SemaCXX/builtin-operator-new-delete.cpp   |   2 +-
 .../test/SemaCXX/cxx1y-sized-deallocation.cpp |   2 +-
 .../unavailable_aligned_allocation.cpp|  15 +-
 clang/tools/clang-repl/CMakeLists.txt |  59 +
 clang/unittests/Interpreter/CMakeLists.txt|  59 +
 .../StaticAnalyzer/CallEventTest.cpp  |   2 +-
 clang/www/cxx_status.html |  11 +-
 .../support.dynamic/libcpp_deallocate.sh.cpp  |   3 +
 .../sized_delete_array14.pass.cpp |   8 +-
 .../new.delete.single/sized_delete14.pass.cpp |   8 +-
 42 files changed, 555 insertions(+), 113 deletions(-)

diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp 
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 799a549ff0816e..88aae2729904f4 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
   [[delete]] x;
 }
   )cpp";
-  EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+  // Sized deallocation is enabled by default in C++14 onwards.
+  EXPECT_DECLS("CXXDeleteExpr",
+   "void operator delete(void *, unsigned long) noexcept");
 }
 
 TEST_F(TargetDeclTest, DependentExprs) {
diff --git 
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp 
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e19..f86fe8a4c5b14f 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
 // CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has 
no matching declaration of 'operator delete' at the same scope
 void *operator new(size_t size) noexcept(false);
 
-struct T {
-  // Sized deallocations are not enabled by default, and so this new/delete 
pair
-  // does not match. However, we expect only one warning, for the new, because
-  // the operator delete is a placement delete and we do not warn on 
mismatching
-  // placement operations.
-  // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new' 
has no matching declaration of 'operator delete' at the same scope
-  void *operator new(size_t size) noexcept;
-  void operator delete(void *ptr, size_t) noexcept; // ok only if sized 
deallocation is enabled
-};
-
 struct U {
   void *operator new(size_t size) noexcept;
   void operator delete(void *ptr) noexcept;
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 7bea43ec64f062..5

[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

2024-04-24 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

Gentle ping.

https://github.com/llvm/llvm-project/pull/84877
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[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

2024-04-25 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

> Do you see any disadvantage to going back to adding a feature for the 
> profiles?

Of course not, I will revise this patch tomorrow. Thanks for discussing this!
(I missed the sync-up meeting because I forgot the daylight saving...)

https://github.com/llvm/llvm-project/pull/84877
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[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/84877
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[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/84877

>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.4
---
 clang/test/Driver/riscv-cpus.c| 319 ++
 clang/test/Misc/target-invalid-cpu-note.c |   8 +-
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 224 ++-
 3 files changed, 539 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..a285f0f9c41f54 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -302,3 +302,322 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// Check profile CPUs
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s
+// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s
+// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s
+// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s
+// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s
+// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicb

[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/84877

>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.4
---
 clang/test/Driver/riscv-cpus.c| 319 ++
 clang/test/Misc/target-invalid-cpu-note.c |   8 +-
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 224 ++-
 3 files changed, 539 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..a285f0f9c41f54 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -302,3 +302,322 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// Check profile CPUs
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s
+// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s
+// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s
+// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s
+// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s
+// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicb

[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Pengcheng Wang via cfe-commits 


@@ -138,6 +155,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   /// initializeProperties().
   RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
 
+  RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
+

wangpc-pp wrote:

Curently no, but we can support them in `RISCVISAInfo::updateCombination()`.
And I don't know if we need `getRISCVProfile` function, maybe we should remove 
it because there is no user.

https://github.com/llvm/llvm-project/pull/84877
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[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

2024-04-26 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/83774
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[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/84877

>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.4
---
 clang/test/Driver/riscv-cpus.c| 319 ++
 clang/test/Misc/target-invalid-cpu-note.c |   8 +-
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 224 ++-
 3 files changed, 539 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..a285f0f9c41f54 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -302,3 +302,322 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// Check profile CPUs
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s
+// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s
+// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s
+// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s
+// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s
+// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicb

[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

2024-04-26 Thread Pengcheng Wang via cfe-commits 


@@ -0,0 +1,165 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -disable-O0-optnone 
-emit-llvm \
+// RUN:   %s -o - | opt -S -passes=mem2reg | FileCheck %s
+
+// CHECK-LABEL: define dso_local half @test_convert_from_bf16_to_fp16(
+// CHECK-SAME: bfloat noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[FPEXT:%.*]] = fpext bfloat [[A]] to float
+// CHECK-NEXT:[[FPTRUNC:%.*]] = fptrunc float [[FPEXT]] to half
+// CHECK-NEXT:ret half [[FPTRUNC]]
+//
+_Float16 test_convert_from_bf16_to_fp16(__bf16 a) {
+return (_Float16)a;
+}
+
+// CHECK-LABEL: define dso_local bfloat @test_convert_from_fp16_to_bf16(
+// CHECK-SAME: half noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[FPEXT:%.*]] = fpext half [[A]] to float
+// CHECK-NEXT:[[FPTRUNC:%.*]] = fptrunc float [[FPEXT]] to bfloat
+// CHECK-NEXT:ret bfloat [[FPTRUNC]]
+//
+__bf16 test_convert_from_fp16_to_bf16(_Float16 a) {
+return (__bf16)a;
+}
+
+typedef _Float16 half2 __attribute__((ext_vector_type(2)));
+typedef _Float16 half4 __attribute__((ext_vector_type(4)));
+
+typedef __bf16 bfloat2 __attribute__((ext_vector_type(2)));
+typedef __bf16 bfloat4 __attribute__((ext_vector_type(4)));
+
+// CHECK-LABEL: define dso_local i32 @test_cast_from_half2_to_bfloat2(
+// CHECK-SAME: i32 noundef [[IN_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca <2 x bfloat>, align 4
+// CHECK-NEXT:[[IN:%.*]] = alloca <2 x half>, align 4
+// CHECK-NEXT:store i32 [[IN_COERCE]], ptr [[IN]], align 4
+// CHECK-NEXT:[[IN1:%.*]] = load <2 x half>, ptr [[IN]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <2 x half> [[IN1]] to <2 x bfloat>
+// CHECK-NEXT:store <2 x bfloat> [[TMP0]], ptr [[RETVAL]], align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4
+// CHECK-NEXT:ret i32 [[TMP1]]
+//
+bfloat2 test_cast_from_half2_to_bfloat2(half2 in) {
+  return (bfloat2)in;
+}
+
+
+// CHECK-LABEL: define dso_local double @test_cast_from_half4_to_bfloat4(
+// CHECK-SAME: double noundef [[IN_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca <4 x bfloat>, align 8
+// CHECK-NEXT:[[IN:%.*]] = alloca <4 x half>, align 8
+// CHECK-NEXT:store double [[IN_COERCE]], ptr [[IN]], align 8
+// CHECK-NEXT:[[IN1:%.*]] = load <4 x half>, ptr [[IN]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <4 x half> [[IN1]] to <4 x bfloat>
+// CHECK-NEXT:store <4 x bfloat> [[TMP0]], ptr [[RETVAL]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, ptr [[RETVAL]], align 8
+// CHECK-NEXT:ret double [[TMP1]]
+//
+bfloat4 test_cast_from_half4_to_bfloat4(half4 in) {
+  return (bfloat4)in;
+}
+
+// CHECK-LABEL: define dso_local i32 @test_cast_from_bfloat2_to_half2(
+// CHECK-SAME: i32 noundef [[IN_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca <2 x half>, align 4
+// CHECK-NEXT:[[IN:%.*]] = alloca <2 x bfloat>, align 4
+// CHECK-NEXT:store i32 [[IN_COERCE]], ptr [[IN]], align 4
+// CHECK-NEXT:[[IN1:%.*]] = load <2 x bfloat>, ptr [[IN]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <2 x bfloat> [[IN1]] to <2 x half>
+// CHECK-NEXT:store <2 x half> [[TMP0]], ptr [[RETVAL]], align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4
+// CHECK-NEXT:ret i32 [[TMP1]]
+//
+half2 test_cast_from_bfloat2_to_half2(bfloat2 in) {
+  return (half2)in;
+}
+
+
+// CHECK-LABEL: define dso_local double @test_cast_from_bfloat4_to_half4(
+// CHECK-SAME: double noundef [[IN_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca <4 x half>, align 8
+// CHECK-NEXT:[[IN:%.*]] = alloca <4 x bfloat>, align 8
+// CHECK-NEXT:store double [[IN_COERCE]], ptr [[IN]], align 8
+// CHECK-NEXT:[[IN1:%.*]] = load <4 x bfloat>, ptr [[IN]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <4 x bfloat> [[IN1]] to <4 x half>
+// CHECK-NEXT:store <4 x half> [[TMP0]], ptr [[RETVAL]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, ptr [[RETVAL]], align 8
+// CHECK-NEXT:ret double [[TMP1]]
+//
+half4 test_cast_from_bfloat4_to_half4(bfloat4 in) {
+  return (half4)in;
+}
+
+
+// CHECK-LABEL: define dso_local i32 @test_convertvector_from_half2_to_bfloat2(
+// CHECK-SAME: i32 noundef [[IN_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca <2 x bfloat>, align 4
+// CHECK-NEXT:[[IN:%.*]] = alloca <2 x half>, align 4
+// CHECK-NEXT:store i32 [[IN_COERCE]], ptr [[IN]], align 4
+// CHECK-NEXT:[[IN1:%.*]] = load <2 x half>, ptr [[IN]], align 4
+// CHECK-NEXT:[[FPEXT:%.*]] = fpext <2 x half> [[IN1]] to <2 x float>
+// CHECK-NEXT:[[FPTRUNC:%.*]] = fptrunc <2 x float> [[FPEXT]] to <2 x 
bfloat>
+// CHECK-NEXT:store <2 x bfloat> [[FPTRUNC]], ptr [[RETVAL]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load i32,

[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

2024-04-26 Thread Pengcheng Wang via cfe-commits 


@@ -0,0 +1,25 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -disable-O0-optnone 
-emit-llvm \
+// RUN:   %s -o - | opt -S -passes=mem2reg | FileCheck %s
+
+// CHECK-LABEL: define dso_local half @test_convert_from_bf16_to_fp16(
+// CHECK-SAME: bfloat noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[FPEXT:%.*]] = fpext bfloat [[A]] to float
+// CHECK-NEXT:[[FPTRUNC:%.*]] = fptrunc float [[FPEXT]] to half
+// CHECK-NEXT:ret half [[FPTRUNC]]
+//
+_Float16 test_convert_from_bf16_to_fp16(__bf16 a) {
+return (_Float16)a;
+}
+
+// CHECK-LABEL: define dso_local bfloat @test_convert_from_fp16_to_bf16(
+// CHECK-SAME: half noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[FPEXT:%.*]] = fpext half [[A]] to float
+// CHECK-NEXT:[[FPTRUNC:%.*]] = fptrunc float [[FPEXT]] to bfloat
+// CHECK-NEXT:ret bfloat [[FPTRUNC]]
+//
+__bf16 test_convert_from_fp16_to_bf16(_Float16 a) {
+return (__bf16)a;
+}
+

wangpc-pp wrote:

Vector tests are moved to HIP target now as the IRs are wierd in X86.

https://github.com/llvm/llvm-project/pull/89051
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[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

2024-04-26 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/89051
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[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

2024-04-27 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

> Lets revert #90299 to recover bots before the weekend.
> 

Many thanks for reverting it and fixing one of the failures!

https://github.com/llvm/llvm-project/pull/83774
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[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

2024-04-27 Thread Pengcheng Wang via cfe-commits 

wangpc-pp wrote:

> This change is also causing a failure on our internal Windows builder, and a 
> public Windows bot:
> https://lab.llvm.org/buildbot/#/builders/119/builds/17634
> ```
> 88.872 [191/66/4550] Linking CXX executable bin\clang-repl.exe
> FAILED: bin/clang-repl.exe 
> cmd.exe /C "cd . && "C:\Program Files\CMake\bin\cmake.exe" -E vs_link_exe 
> --intdir=tools\clang\tools\clang-repl\CMakeFiles\clang-repl.dir 
> --rc=C:\PROGRA~2\WINDOW~4\10\bin\100226~1.0\x64\rc.exe 
> --mt=C:\PROGRA~2\WINDOW~4\10\bin\100226~1.0\x64\mt.exe --manifests  -- 
> C:\PROGRA~1\MICROS~2\2022\COMMUN~1\VC\Tools\MSVC\1439~1.335\bin\Hostx64\x64\link.exe
>  /nologo @CMakeFiles\clang-repl.rsp  /out:bin\clang-repl.exe 
> /implib:lib\clang-repl.lib /pdb:bin\clang-repl.pdb /version:0.0 /machine:x64 
> /STACK:1000 /INCREMENTAL:NO /subsystem:console  
> /EXPORT:??_7type_info@@6B@ 
> /EXPORT:?__type_info_root_node@@3U__type_info_node@@A 
> /EXPORT:?nothrow@std@@3Unothrow_t@1@B /EXPORT:_Init_thread_abort 
> /EXPORT:_Init_thread_epoch /EXPORT:_Init_thread_footer 
> /EXPORT:_Init_thread_header /EXPORT:_tls_index /EXPORT:??2@YAPEAX_K@Z 
> /EXPORT:??3@YAXPEAX@Z /EXPORT:??_U@YAPEAX_K@Z /EXPORT:??_V@YAXPEAX@Z 
> /EXPORT:??3@YAXPEAX_K@Z 
> /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z 
> /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z 
> /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@N@Z 
> /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z 
> /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z
>  
> /EXPORT:??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z
>  
> /EXPORT:??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@PEBD@Z
>  /EXPORT:?_Facet_Register@std@@YAXPEAV_Facet_base@1@@Z  -Wl,--long-plt  && cd 
> ."
> LINK: command 
> "C:\PROGRA~1\MICROS~2\2022\COMMUN~1\VC\Tools\MSVC\1439~1.335\bin\Hostx64\x64\link.exe
>  /nologo @CMakeFiles\clang-repl.rsp /out:bin\clang-repl.exe 
> /implib:lib\clang-repl.lib /pdb:bin\clang-repl.pdb /version:0.0 /machine:x64 
> /STACK:1000 /INCREMENTAL:NO /subsystem:console /EXPORT:??_7type_info@@6B@ 
> /EXPORT:?__type_info_root_node@@3U__type_info_node@@A 
> /EXPORT:?nothrow@std@@3Unothrow_t@1@B /EXPORT:_Init_thread_abort 
> /EXPORT:_Init_thread_epoch /EXPORT:_Init_thread_footer 
> /EXPORT:_Init_thread_header /EXPORT:_tls_index /EXPORT:??2@YAPEAX_K@Z 
> /EXPORT:??3@YAXPEAX@Z /EXPORT:??_U@YAPEAX_K@Z /EXPORT:??_V@YAXPEAX@Z 
> /EXPORT:??3@YAXPEAX_K@Z 
> /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z 
> /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z 
> /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@N@Z 
> /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z 
> /EXPORT:??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z
>  
> /EXPORT:??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z
>  
> /EXPORT:??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@PEBD@Z
>  /EXPORT:?_Facet_Register@std@@YAXPEAV_Facet_base@1@@Z -Wl,--long-plt 
> /MANIFEST /MANIFESTFILE:bin\clang-repl.exe.manifest" failed (exit code 1120) 
> with the following output:
> LINK : warning LNK4044: unrecognized option '/Wl,--long-plt'; ignored
>Creating library lib\clang-repl.lib and object lib\clang-repl.exp
> LIBCMT.lib(initializers.obj) : warning LNK4098: defaultlib 'msvcrt.lib' 
> conflicts with use of other libs; use /NODEFAULTLIB:library
> LINK : warning LNK4217: symbol 'free' defined in 'libucrt.lib(free.obj)' is 
> imported by 'zlibstatic.lib(zutil.obj)' in function 'zcfree'
> LINK : warning LNK4217: symbol 'malloc' defined in 'libucrt.lib(malloc.obj)' 
> is imported by 'zlibstatic.lib(zutil.obj)' in function 'zcalloc'
> clang-repl.exp : error LNK2001: unresolved external symbol "public: class 
> std::basic_ostream > & __cdecl 
> std::basic_ostream >::operator<<(float)" 
> (??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z)
> clang-repl.exp : error LNK2001: unresolved external symbol "public: class 
> std::basic_ostream > & __cdecl 
> std::basic_ostream >::operator<<(class 
> std::basic_ostream > & (__cdecl*)(class 
> std::basic_ostream > &))" 
> (??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z)
> clang-repl.exp : error LNK2001: unresolved external symbol "public: class 
> std::basic_ostream > & __cdecl 
> std::basic_ostream >::operator<<(void 
> const *)" (??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z)
> bin\clang-repl.exe : fatal error LNK1120: 3 unresolved externals
> 
> ```

It seems that we need to remove these symbols from the CMakeLists.txt of 
clang-repl.

https://github.com/llvm/llvm-project/pull/83774
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cfe-commits mai

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