r331979 - This patch provides that bitfields are splitted even in case
Author: spetrovic Date: Thu May 10 05:31:12 2018 New Revision: 331979 URL: http://llvm.org/viewvc/llvm-project?rev=331979&view=rev Log: This patch provides that bitfields are splitted even in case when current field is not legal integer type. Differential Revision: https://reviews.llvm.org/D39053 Added: cfe/trunk/test/CodeGenCXX/finegrain-bitfield-type.cpp Modified: cfe/trunk/include/clang/Driver/Options.td cfe/trunk/lib/CodeGen/CGRecordLayoutBuilder.cpp Modified: cfe/trunk/include/clang/Driver/Options.td URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=331979&r1=331978&r2=331979&view=diff == --- cfe/trunk/include/clang/Driver/Options.td (original) +++ cfe/trunk/include/clang/Driver/Options.td Thu May 10 05:31:12 2018 @@ -1156,7 +1156,7 @@ def fxray_instrumentation_bundle : def ffine_grained_bitfield_accesses : Flag<["-"], "ffine-grained-bitfield-accesses">, Group, Flags<[CC1Option]>, - HelpText<"Use separate accesses for bitfields with legal widths and alignments.">; + HelpText<"Use separate accesses for consecutive bitfield runs with legal widths and alignments.">; def fno_fine_grained_bitfield_accesses : Flag<["-"], "fno-fine-grained-bitfield-accesses">, Group, Flags<[CC1Option]>, HelpText<"Use large-integer access for consecutive bitfield runs.">; Modified: cfe/trunk/lib/CodeGen/CGRecordLayoutBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGRecordLayoutBuilder.cpp?rev=331979&r1=331978&r2=331979&view=diff == --- cfe/trunk/lib/CodeGen/CGRecordLayoutBuilder.cpp (original) +++ cfe/trunk/lib/CodeGen/CGRecordLayoutBuilder.cpp Thu May 10 05:31:12 2018 @@ -404,19 +404,20 @@ CGRecordLowering::accumulateBitFields(Re return; } - // Check if current Field is better as a single field run. When current field + // Check if OffsetInRecord is better as a single field run. When OffsetInRecord // has legal integer width, and its bitfield offset is naturally aligned, it // is better to make the bitfield a separate storage component so as it can be // accessed directly with lower cost. - auto IsBetterAsSingleFieldRun = [&](RecordDecl::field_iterator Field) { + auto IsBetterAsSingleFieldRun = [&](uint64_t OffsetInRecord, + uint64_t StartBitOffset) { if (!Types.getCodeGenOpts().FineGrainedBitfieldAccesses) return false; -unsigned Width = Field->getBitWidthValue(Context); -if (!DataLayout.isLegalInteger(Width)) +if (!DataLayout.isLegalInteger(OffsetInRecord)) return false; -// Make sure Field is natually aligned if it is treated as an IType integer. -if (getFieldBitOffset(*Field) % -Context.toBits(getAlignment(getIntNType(Width))) != +// Make sure StartBitOffset is natually aligned if it is treated as an +// IType integer. + if (StartBitOffset % +Context.toBits(getAlignment(getIntNType(OffsetInRecord))) != 0) return false; return true; @@ -435,14 +436,15 @@ CGRecordLowering::accumulateBitFields(Re Run = Field; StartBitOffset = getFieldBitOffset(*Field); Tail = StartBitOffset + Field->getBitWidthValue(Context); -StartFieldAsSingleRun = IsBetterAsSingleFieldRun(Run); +StartFieldAsSingleRun = IsBetterAsSingleFieldRun(Tail - StartBitOffset, + StartBitOffset); } ++Field; continue; } // If the start field of a new run is better as a single run, or -// if current field is better as a single run, or +// if current field (or consecutive fields) is better as a single run, or // if current field has zero width bitfield and either // UseZeroLengthBitfieldAlignment or UseBitFieldTypeAlignment is set to // true, or @@ -451,7 +453,7 @@ CGRecordLowering::accumulateBitFields(Re // skip the block below and go ahead to emit the storage. // Otherwise, try to add bitfields to the run. if (!StartFieldAsSingleRun && Field != FieldEnd && -!IsBetterAsSingleFieldRun(Field) && +!IsBetterAsSingleFieldRun(Tail - StartBitOffset, StartBitOffset) && (!Field->isZeroLengthBitField(Context) || (!Context.getTargetInfo().useZeroLengthBitfieldAlignment() && !Context.getTargetInfo().useBitFieldTypeAlignment())) && Added: cfe/trunk/test/CodeGenCXX/finegrain-bitfield-type.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCXX/finegrain-bitfield-type.cpp?rev=331979&view=auto == --- cfe/trunk/test/CodeGenCXX/finegrain-bitfield-type.cpp (added) +++ cfe/trunk/test/CodeGenCXX/finegrain-bitfield-type.cpp Thu May 10 05:31:12 2018 @@ -0,0 +1,22 @@ +// RUN: %clan
r357466 - [PowerPC] Fix issue with inline asm - soft float mode
Author: spetrovic Date: Tue Apr 2 04:00:09 2019 New Revision: 357466 URL: http://llvm.org/viewvc/llvm-project?rev=357466&view=rev Log: [PowerPC] Fix issue with inline asm - soft float mode This patch prevents floating point register constraints in soft float mode. Differential Revision: https://reviews.llvm.org/D59310 Added: cfe/trunk/test/Driver/ppc-inlineasm-sf.c Modified: cfe/trunk/lib/Basic/Targets/PPC.cpp cfe/trunk/lib/Basic/Targets/PPC.h Modified: cfe/trunk/lib/Basic/Targets/PPC.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/PPC.cpp?rev=357466&r1=357465&r2=357466&view=diff == --- cfe/trunk/lib/Basic/Targets/PPC.cpp (original) +++ cfe/trunk/lib/Basic/Targets/PPC.cpp Tue Apr 2 04:00:09 2019 @@ -30,6 +30,7 @@ const Builtin::Info PPCTargetInfo::Built /// configured set of features. bool PPCTargetInfo::handleTargetFeatures(std::vector &Features, DiagnosticsEngine &Diags) { + FloatABI = HardFloat; for (const auto &Feature : Features) { if (Feature == "+altivec") { HasAltivec = true; @@ -53,6 +54,8 @@ bool PPCTargetInfo::handleTargetFeatures HasFloat128 = true; } else if (Feature == "+power9-vector") { HasP9Vector = true; +} else if (Feature == "-hard-float") { + FloatABI = SoftFloat; } // TODO: Finish this list and add an assert that we've handled them // all. Modified: cfe/trunk/lib/Basic/Targets/PPC.h URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/PPC.h?rev=357466&r1=357465&r2=357466&view=diff == --- cfe/trunk/lib/Basic/Targets/PPC.h (original) +++ cfe/trunk/lib/Basic/Targets/PPC.h Tue Apr 2 04:00:09 2019 @@ -53,6 +53,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetI static const char *const GCCRegNames[]; static const TargetInfo::GCCRegAlias GCCRegAliases[]; std::string CPU; + enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; // Target cpu features. bool HasAltivec = false; @@ -183,8 +184,11 @@ public: return false; case 'O': // Zero break; -case 'b': // Base register case 'f': // Floating point register + // Don't use floating point registers on soft float ABI. + if (FloatABI == SoftFloat) +return false; +case 'b': // Base register Info.setAllowsRegister(); break; // FIXME: The following are added to allow parsing. @@ -192,6 +196,10 @@ public: // Also, is more specific checking needed? I.e. specific registers? case 'd': // Floating point register (containing 64-bit value) case 'v': // Altivec vector register + // Don't use floating point and altivec vector registers + // on soft float ABI + if (FloatABI == SoftFloat) +return false; Info.setAllowsRegister(); break; case 'w': Added: cfe/trunk/test/Driver/ppc-inlineasm-sf.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/ppc-inlineasm-sf.c?rev=357466&view=auto == --- cfe/trunk/test/Driver/ppc-inlineasm-sf.c (added) +++ cfe/trunk/test/Driver/ppc-inlineasm-sf.c Tue Apr 2 04:00:09 2019 @@ -0,0 +1,16 @@ +// RUN: not %clang -target powerpc-unknown-linux -O2 -fPIC -m32 -msoft-float %s -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-ERRMSG %s +int foo () +{ + double x,y; + int a; + __asm__ ("fctiw %0,%1" : "=f"(x) : "f"(y)); + // CHECK-ERRMSG: error: invalid output constraint '=f' in asm + // CHECK-ERRMSG-NEXT: __asm__ ("fctiw %0,%1" : "=f"(x) : "f"(y)); + __asm__ ("fctiw %0,%1" : "=d"(x) : "d"(y)); + // CHECK-ERRMSG: error: invalid output constraint '=d' in asm + // CHECK-ERRMSG-NEXT: __asm__ ("fctiw %0,%1" : "=d"(x) : "d"(y)); + __asm__ ("vec_dss %0" : "=v"(a)); + // CHECK-ERRMSG: error: invalid output constraint '=v' in asm + // CHECK-ERRMSG-NEXT: __asm__ ("vec_dss %0" : "=v"(a)); +} + ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r313018 - [ARM] Option for reading thread pointer from coprocessor register
Author: spetrovic Date: Tue Sep 12 03:40:58 2017 New Revision: 313018 URL: http://llvm.org/viewvc/llvm-project?rev=313018&view=rev Log: [ARM] Option for reading thread pointer from coprocessor register This patch enables option for reading thread pointer directly from coprocessor register (-mtp=soft/cp15). Differential Revision: https://reviews.llvm.org/D34878 Modified: cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td cfe/trunk/include/clang/Driver/CC1Options.td cfe/trunk/include/clang/Driver/Options.td cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp cfe/trunk/lib/Driver/ToolChains/Arch/ARM.h cfe/trunk/test/Driver/clang-translation.c Modified: cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td?rev=313018&r1=313017&r2=313018&view=diff == --- cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td (original) +++ cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td Tue Sep 12 03:40:58 2017 @@ -101,6 +101,10 @@ def err_drv_force_crash : Error< "failing because %select{environment variable 'FORCE_CLANG_DIAGNOSTICS_CRASH' is set|'-gen-reproducer' is used}0">; def err_drv_invalid_mfloat_abi : Error< "invalid float ABI '%0'">; +def err_drv_invalid_mtp : Error< + "invalid thread pointer reading mode '%0'">; +def err_drv_missing_arg_mtp : Error< + "missing argument to '%0'">; def err_drv_invalid_libcxx_deployment : Error< "invalid deployment target for -stdlib=libc++ (requires %0 or later)">; def err_drv_invalid_argument_to_fdebug_prefix_map : Error< Modified: cfe/trunk/include/clang/Driver/CC1Options.td URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/CC1Options.td?rev=313018&r1=313017&r2=313018&view=diff == --- cfe/trunk/include/clang/Driver/CC1Options.td (original) +++ cfe/trunk/include/clang/Driver/CC1Options.td Tue Sep 12 03:40:58 2017 @@ -257,6 +257,8 @@ def menable_unsafe_fp_math : Flag<["-"], "precision">; def mfloat_abi : Separate<["-"], "mfloat-abi">, HelpText<"The float ABI to use">; +def mtp : Separate<["-"], "mtp">, + HelpText<"Mode for reading thread pointer">; def mlimit_float_precision : Separate<["-"], "mlimit-float-precision">, HelpText<"Limit float precision to the given value">; def split_stacks : Flag<["-"], "split-stacks">, Modified: cfe/trunk/include/clang/Driver/Options.td URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=313018&r1=313017&r2=313018&view=diff == --- cfe/trunk/include/clang/Driver/Options.td (original) +++ cfe/trunk/include/clang/Driver/Options.td Tue Sep 12 03:40:58 2017 @@ -1689,6 +1689,8 @@ def mexecute_only : Flag<["-"], "mexecut HelpText<"Disallow generation of data access to code sections (ARM only)">; def mno_execute_only : Flag<["-"], "mno-execute-only">, Group, HelpText<"Allow generation of data access to code sections (ARM only)">; +def mtp_mode_EQ : Joined<["-"], "mtp=">, Group, Values<"soft, cp15">, + HelpText<"Read thread pointer from coprocessor register (ARM only)">; def mpure_code : Flag<["-"], "mpure-code">, Alias; // Alias for GCC compatibility def mno_pure_code : Flag<["-"], "mno-pure-code">, Alias; def mtvos_version_min_EQ : Joined<["-"], "mtvos-version-min=">, Group; Modified: cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp?rev=313018&r1=313017&r2=313018&view=diff == --- cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp (original) +++ cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp Tue Sep 12 03:40:58 2017 @@ -131,6 +131,26 @@ bool arm::useAAPCSForMachO(const llvm::T T.getOS() == llvm::Triple::UnknownOS || isARMMProfile(T); } +// Select mode for reading thread pointer (-mtp=soft/cp15). +arm::ReadTPMode arm::getReadTPMode(const ToolChain &TC, const ArgList &Args) { + if (Arg *A = Args.getLastArg(options::OPT_mtp_mode_EQ)) { +const Driver &D = TC.getDriver(); +arm::ReadTPMode ThreadPointer = +llvm::StringSwitch(A->getValue()) +.Case("cp15", ReadTPMode::Cp15) +.Case("soft", ReadTPMode::Soft) +.Default(ReadTPMode::Invalid); +if (ThreadPointer != ReadTPMode::Invalid) + return ThreadPointer; +if (StringRef(A->getValue()).empty()) + D.Diag(diag::err_drv_missing_arg_mtp) << A->getAsString(Args); +else + D.Diag(diag::err_drv_invalid_mtp) << A->getAsString(Args); +return ReadTPMode::Invalid; + } + return ReadTPMode::Soft; +} + // Select the float ABI as determined by -msoft-float, -mhard-float, and // -mfloat-abi=. arm::FloatABI arm::getARMFloatABI
r329795 - [PowerPC] Option for secure plt mode
Author: spetrovic Date: Wed Apr 11 05:24:44 2018 New Revision: 329795 URL: http://llvm.org/viewvc/llvm-project?rev=329795&view=rev Log: [PowerPC] Option for secure plt mode This patch enables option for secure plt mode in clang (-msecure-plt). Differential Revision: https://reviews.llvm.org/D44921 Modified: cfe/trunk/include/clang/Driver/Options.td cfe/trunk/lib/Driver/ToolChains/Arch/PPC.cpp cfe/trunk/lib/Driver/ToolChains/Arch/PPC.h cfe/trunk/test/Driver/ppc-features.cpp Modified: cfe/trunk/include/clang/Driver/Options.td URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=329795&r1=329794&r2=329795&view=diff == --- cfe/trunk/include/clang/Driver/Options.td (original) +++ cfe/trunk/include/clang/Driver/Options.td Wed Apr 11 05:24:44 2018 @@ -1957,6 +1957,7 @@ def maltivec : Flag<["-"], "maltivec">, def mno_altivec : Flag<["-"], "mno-altivec">, Group; def mvsx : Flag<["-"], "mvsx">, Group; def mno_vsx : Flag<["-"], "mno-vsx">, Group; +def msecure_plt : Flag<["-"], "msecure-plt">, Group; def mpower8_vector : Flag<["-"], "mpower8-vector">, Group; def mno_power8_vector : Flag<["-"], "mno-power8-vector">, Modified: cfe/trunk/lib/Driver/ToolChains/Arch/PPC.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/PPC.cpp?rev=329795&r1=329794&r2=329795&view=diff == --- cfe/trunk/lib/Driver/ToolChains/Arch/PPC.cpp (original) +++ cfe/trunk/lib/Driver/ToolChains/Arch/PPC.cpp Wed Apr 11 05:24:44 2018 @@ -106,6 +106,16 @@ void ppc::getPPCTargetFeatures(const Dri ppc::FloatABI FloatABI = ppc::getPPCFloatABI(D, Args); if (FloatABI == ppc::FloatABI::Soft) Features.push_back("-hard-float"); + + ppc::ReadGOTPtrMode ReadGOT = ppc::getPPCReadGOTPtrMode(D, Args); + if (ReadGOT == ppc::ReadGOTPtrMode::SecurePlt) +Features.push_back("+secure-plt"); +} + +ppc::ReadGOTPtrMode ppc::getPPCReadGOTPtrMode(const Driver &D, const ArgList &Args) { + if (Args.getLastArg(options::OPT_msecure_plt)) +return ppc::ReadGOTPtrMode::SecurePlt; + return ppc::ReadGOTPtrMode::Bss; } ppc::FloatABI ppc::getPPCFloatABI(const Driver &D, const ArgList &Args) { Modified: cfe/trunk/lib/Driver/ToolChains/Arch/PPC.h URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/PPC.h?rev=329795&r1=329794&r2=329795&view=diff == --- cfe/trunk/lib/Driver/ToolChains/Arch/PPC.h (original) +++ cfe/trunk/lib/Driver/ToolChains/Arch/PPC.h Wed Apr 11 05:24:44 2018 @@ -29,10 +29,17 @@ enum class FloatABI { Hard, }; +enum class ReadGOTPtrMode { + Bss, + SecurePlt, +}; + FloatABI getPPCFloatABI(const Driver &D, const llvm::opt::ArgList &Args); std::string getPPCTargetCPU(const llvm::opt::ArgList &Args); const char *getPPCAsmModeForCPU(StringRef Name); +ReadGOTPtrMode getPPCReadGOTPtrMode(const Driver &D, + const llvm::opt::ArgList &Args); void getPPCTargetFeatures(const Driver &D, const llvm::Triple &Triple, const llvm::opt::ArgList &Args, Modified: cfe/trunk/test/Driver/ppc-features.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/ppc-features.cpp?rev=329795&r1=329794&r2=329795&view=diff == --- cfe/trunk/test/Driver/ppc-features.cpp (original) +++ cfe/trunk/test/Driver/ppc-features.cpp Wed Apr 11 05:24:44 2018 @@ -22,6 +22,10 @@ // RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -mhard-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTHARD %s // CHECK-SOFTHARD-NOT: "-target-feature" "-hard-float" +// check -msecure-plt option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu -msecure-plt %s -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SECUREPLT %s +// CHECK-SECUREPLT: "-target-feature" "+secure-plt" + // check -mfloat-abi=x option // RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=x -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-ERRMSG %s // CHECK-ERRMSG: error: invalid float ABI '-mfloat-abi=x' ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D13351: [Power PC] add soft float support for ppc32
spetrovic created this revision. spetrovic added a reviewer: hfinkel. spetrovic added a subscriber: cfe-commits. This patch enables soft float support for ppc32 architecture and fixes the ABI for variadic functions. This is first in set of patches for soft float support in LLVM. http://reviews.llvm.org/D13351 Files: include/clang/Basic/TargetInfo.h lib/Basic/Targets.cpp lib/CodeGen/TargetInfo.cpp lib/Driver/Tools.cpp lib/Driver/Tools.h test/CodeGen/ppc-sfvarargs.c test/Driver/ppc-features.cpp Index: test/Driver/ppc-features.cpp === --- test/Driver/ppc-features.cpp +++ test/Driver/ppc-features.cpp @@ -12,6 +12,10 @@ // RUN: not %clang -target mips64-linux-gnu -faltivec -fsyntax-only %s 2>&1 | FileCheck %s // RUN: not %clang -target sparc-unknown-solaris -faltivec -fsyntax-only %s 2>&1 | FileCheck %s +// check soft float option only for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT %s +// CHECK-SOFTFLOAT: "-target-feature" "+soft-float" + // CHECK: invalid argument '-faltivec' only allowed with 'ppc/ppc64/ppc64le' // Check that -fno-altivec and -mno-altivec correctly disable the altivec Index: test/CodeGen/ppc-sfvarargs.c === --- test/CodeGen/ppc-sfvarargs.c +++ test/CodeGen/ppc-sfvarargs.c @@ -0,0 +1,17 @@ +// RUN: %clang -O0 --target=powerpc-unknown-linux-gnu -EB -msoft-float -S -emit-llvm %s -o - | FileCheck %s + +#include +void test(char *fmt, ...) { + va_list ap; + va_start(ap, fmt); + va_arg(ap, double); + va_end(ap); +} + +void foo() { + double a; + test("test",a); +} +// CHECK: %{{[0-9]+}} = add i8 %numUsedRegs, 1 +// CHECK: %{{[0-9]+}} = and i8 %{{[0-9]+}}, -2 +// CHECK: %{{[0-9]+}} = mul i8 %{{[0-9]+}}, 4 \ No newline at end of file Index: lib/Driver/Tools.h === --- lib/Driver/Tools.h +++ lib/Driver/Tools.h @@ -728,6 +728,10 @@ FloatABI getARMFloatABI(const ToolChain &TC, const llvm::opt::ArgList &Args); } + +namespace ppc { + StringRef getPPCFloatABI(const llvm::opt::ArgList &Args); +} namespace XCore { // For XCore, we do not need to instantiate tools for PreProcess, PreCompile and // Compile. Index: lib/Driver/Tools.cpp === --- lib/Driver/Tools.cpp +++ lib/Driver/Tools.cpp @@ -1344,15 +1344,44 @@ // TODO: Change the LLVM backend option maybe? if (Name == "mfcrf") Name = "mfocrf"; - + Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name)); } + StringRef FloatABI = ppc::getPPCFloatABI(Args); + if (FloatABI == "soft") +Features.push_back("+soft-float"); + // Altivec is a bit weird, allow overriding of the Altivec feature here. AddTargetFeature(Args, Features, options::OPT_faltivec, options::OPT_fno_altivec, "altivec"); } +StringRef ppc::getPPCFloatABI(const ArgList &Args) { + StringRef FloatABI; + if (Arg *A = Args.getLastArg(options::OPT_msoft_float, + options::OPT_mhard_float, + options::OPT_mfloat_abi_EQ)) { +if (A->getOption().matches(options::OPT_msoft_float)) + FloatABI = "soft"; +else if (A->getOption().matches(options::OPT_mhard_float)) + FloatABI = "hard"; +else { + FloatABI = A->getValue(); + if (FloatABI != "soft" && FloatABI != "hard") { +FloatABI = "hard"; + } +} + } + + // If unspecified, choose the default based on the platform. + if (FloatABI.empty()) { +FloatABI = "hard"; + } + + return FloatABI; +} + void Clang::AddPPCTargetArgs(const ArgList &Args, ArgStringList &CmdArgs) const { // Select the ABI to use. @@ -1389,10 +1418,26 @@ if (StringRef(A->getValue()) != "altivec") ABIName = A->getValue(); + StringRef FloatABI = ppc::getPPCFloatABI(Args); + + if (FloatABI == "soft") { +// Floating point operations and argument passing are soft. +CmdArgs.push_back("-msoft-float"); +CmdArgs.push_back("-mfloat-abi"); +CmdArgs.push_back("soft"); + } + else { +// Floating point operations and argument passing are hard. +assert(FloatABI == "hard" && "Invalid float abi!"); +CmdArgs.push_back("-mfloat-abi"); +CmdArgs.push_back("hard"); + } + if (ABIName) { CmdArgs.push_back("-target-abi"); CmdArgs.push_back(ABIName); } + } bool ppc::hasPPCAbiArg(const ArgList &Args, const char *Value) { Index: lib/CodeGen/TargetInfo.cpp === --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -3422,6 +3422,8 @@ bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64; bool isInt = Ty->isIntegerType() || Ty->isPointerType()
Re: [PATCH] D13351: [Power PC] add soft float support for ppc32
spetrovic updated this revision to Diff 36763. http://reviews.llvm.org/D13351 Files: include/clang/Basic/TargetInfo.h lib/Basic/Targets.cpp lib/CodeGen/TargetInfo.cpp lib/Driver/Tools.cpp lib/Driver/Tools.h test/CodeGen/ppc-sfvarargs.c test/Driver/ppc-features.cpp Index: test/Driver/ppc-features.cpp === --- test/Driver/ppc-features.cpp +++ test/Driver/ppc-features.cpp @@ -12,6 +12,10 @@ // RUN: not %clang -target mips64-linux-gnu -faltivec -fsyntax-only %s 2>&1 | FileCheck %s // RUN: not %clang -target sparc-unknown-solaris -faltivec -fsyntax-only %s 2>&1 | FileCheck %s +// check soft float option only for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT %s +// CHECK-SOFTFLOAT: "-target-feature" "+soft-float" + // CHECK: invalid argument '-faltivec' only allowed with 'ppc/ppc64/ppc64le' // Check that -fno-altivec and -mno-altivec correctly disable the altivec Index: test/CodeGen/ppc-sfvarargs.c === --- test/CodeGen/ppc-sfvarargs.c +++ test/CodeGen/ppc-sfvarargs.c @@ -0,0 +1,17 @@ +// RUN: %clang -O0 --target=powerpc-unknown-linux-gnu -EB -msoft-float -S -emit-llvm %s -o - | FileCheck %s + +#include +void test(char *fmt, ...) { + va_list ap; + va_start(ap, fmt); + va_arg(ap, double); + va_end(ap); +} + +void foo() { + double a; + test("test",a); +} +// CHECK: %{{[0-9]+}} = add i8 %numUsedRegs, 1 +// CHECK: %{{[0-9]+}} = and i8 %{{[0-9]+}}, -2 +// CHECK: %{{[0-9]+}} = mul i8 %{{[0-9]+}}, 4 \ No newline at end of file Index: lib/Driver/Tools.h === --- lib/Driver/Tools.h +++ lib/Driver/Tools.h @@ -728,6 +728,10 @@ FloatABI getARMFloatABI(const ToolChain &TC, const llvm::opt::ArgList &Args); } + +namespace ppc { + StringRef getPPCFloatABI(const llvm::opt::ArgList &Args); +} namespace XCore { // For XCore, we do not need to instantiate tools for PreProcess, PreCompile and // Compile. Index: lib/Driver/Tools.cpp === --- lib/Driver/Tools.cpp +++ lib/Driver/Tools.cpp @@ -1344,15 +1344,44 @@ // TODO: Change the LLVM backend option maybe? if (Name == "mfcrf") Name = "mfocrf"; - + Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name)); } + StringRef FloatABI = ppc::getPPCFloatABI(Args); + if (FloatABI == "soft") +Features.push_back("+soft-float"); + // Altivec is a bit weird, allow overriding of the Altivec feature here. AddTargetFeature(Args, Features, options::OPT_faltivec, options::OPT_fno_altivec, "altivec"); } +StringRef ppc::getPPCFloatABI(const ArgList &Args) { + StringRef FloatABI; + if (Arg *A = Args.getLastArg(options::OPT_msoft_float, + options::OPT_mhard_float, + options::OPT_mfloat_abi_EQ)) { +if (A->getOption().matches(options::OPT_msoft_float)) + FloatABI = "soft"; +else if (A->getOption().matches(options::OPT_mhard_float)) + FloatABI = "hard"; +else { + FloatABI = A->getValue(); + if (FloatABI != "soft" && FloatABI != "hard") { +FloatABI = "hard"; + } +} + } + + // If unspecified, choose the default based on the platform. + if (FloatABI.empty()) { +FloatABI = "hard"; + } + + return FloatABI; +} + void Clang::AddPPCTargetArgs(const ArgList &Args, ArgStringList &CmdArgs) const { // Select the ABI to use. @@ -1389,6 +1418,21 @@ if (StringRef(A->getValue()) != "altivec") ABIName = A->getValue(); + StringRef FloatABI = ppc::getPPCFloatABI(Args); + + if (FloatABI == "soft") { +// Floating point operations and argument passing are soft. +CmdArgs.push_back("-msoft-float"); +CmdArgs.push_back("-mfloat-abi"); +CmdArgs.push_back("soft"); + } + else { +// Floating point operations and argument passing are hard. +assert(FloatABI == "hard" && "Invalid float abi!"); +CmdArgs.push_back("-mfloat-abi"); +CmdArgs.push_back("hard"); + } + if (ABIName) { CmdArgs.push_back("-target-abi"); CmdArgs.push_back(ABIName); Index: lib/CodeGen/TargetInfo.cpp === --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -3422,6 +3422,8 @@ bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64; bool isInt = Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType(); + bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64; + bool isSF = getTarget().isSoftFloatABI(); // All aggregates are passed indirectly? That doesn't seem consistent // with the argument-lowering code. @@ -3431,16 +3433,16 @@ // The calling convention
Re: [PATCH] D13351: [Power PC] add soft float support for ppc32
spetrovic updated this revision to Diff 38882. spetrovic marked 5 inline comments as done. spetrovic added a comment. Comments addressed. http://reviews.llvm.org/D13351 Files: lib/CodeGen/TargetInfo.cpp lib/Driver/Tools.cpp lib/Driver/Tools.h test/CodeGen/ppc-sfvarargs.c test/Driver/ppc-features.cpp Index: test/Driver/ppc-features.cpp === --- test/Driver/ppc-features.cpp +++ test/Driver/ppc-features.cpp @@ -12,6 +12,30 @@ // RUN: not %clang -target mips64-linux-gnu -faltivec -fsyntax-only %s 2>&1 | FileCheck %s // RUN: not %clang -target sparc-unknown-solaris -faltivec -fsyntax-only %s 2>&1 | FileCheck %s +// check -msoft-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT %s +// CHECK-SOFTFLOAT: "-target-feature" "+soft-float" + +// check -mfloat-abi=soft option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=soft -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT %s +// CHECK-FLOATABISOFT: "-target-feature" "+soft-float" + +// check -mhard-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mhard-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-HARDFLOAT %s +// CHECK-HARDFLOAT-NOT: "-target-feature" "+soft-float" + +// check -mfloat-abi=hard option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=hard -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABIHARD %s +// CHECK-FLOATABIHARD-NOT: "-target-feature" "+soft-float" + +// check combine -mhard-float -msoft-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mhard-float -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-HARDSOFT %s +// CHECK-HARDSOFT: "-target-feature" "+soft-float" + +// check combine -msoft-float -mhard-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -mhard-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTHARD %s +// CHECK-SOFTHARD-NOT: "-target-feature" "+soft-float" + // CHECK: invalid argument '-faltivec' only allowed with 'ppc/ppc64/ppc64le' // Check that -fno-altivec and -mno-altivec correctly disable the altivec Index: test/CodeGen/ppc-sfvarargs.c === --- test/CodeGen/ppc-sfvarargs.c +++ test/CodeGen/ppc-sfvarargs.c @@ -0,0 +1,17 @@ +// RUN: %clang -O0 --target=powerpc-unknown-linux-gnu -EB -msoft-float -S -emit-llvm %s -o - | FileCheck %s + +#include +void test(char *fmt, ...) { + va_list ap; + va_start(ap, fmt); + va_arg(ap, double); + va_end(ap); +} + +void foo() { + double a; + test("test",a); +} +// CHECK: %{{[0-9]+}} = add i8 %numUsedRegs, 1 +// CHECK: %{{[0-9]+}} = and i8 %{{[0-9]+}}, -2 +// CHECK: %{{[0-9]+}} = mul i8 %{{[0-9]+}}, 4 \ No newline at end of file Index: lib/Driver/Tools.h === --- lib/Driver/Tools.h +++ lib/Driver/Tools.h @@ -731,6 +731,16 @@ FloatABI getARMFloatABI(const ToolChain &TC, const llvm::opt::ArgList &Args); } + +namespace ppc { +enum class FloatABI { + Invalid, + Soft, + SoftFP, + Hard, +}; + ppc::FloatABI getPPCFloatABI(const Driver &D, const llvm::opt::ArgList &Args); +} namespace XCore { // For XCore, we do not need to instantiate tools for PreProcess, PreCompile and // Compile. Index: lib/Driver/Tools.cpp === --- lib/Driver/Tools.cpp +++ lib/Driver/Tools.cpp @@ -1325,7 +1325,7 @@ return ""; } -static void getPPCTargetFeatures(const ArgList &Args, +static void getPPCTargetFeatures(const Driver &D, const ArgList &Args, std::vector &Features) { for (const Arg *A : Args.filtered(options::OPT_m_ppc_Features_Group)) { StringRef Name = A->getOption().getName(); @@ -1345,15 +1345,48 @@ // TODO: Change the LLVM backend option maybe? if (Name == "mfcrf") Name = "mfocrf"; - + Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name)); } + ppc::FloatABI FloatABI = ppc::getPPCFloatABI(D, Args); + if (FloatABI == ppc::FloatABI::Soft) +Features.push_back("+soft-float"); + // Altivec is a bit weird, allow overriding of the Altivec feature here. AddTargetFeature(Args, Features, options::OPT_faltivec, options::OPT_fno_altivec, "altivec"); } +ppc::FloatABI ppc::getPPCFloatABI(const Driver &D, const ArgList &Args) { + ppc::FloatABI ABI = ppc::FloatABI::Invalid; + if (Arg *A = Args.getLastArg(options::OPT_msoft_float, + options::OPT_mhard_float, + options::OPT_mfloat_abi_EQ)) { +if (A->getOption().matches(options::OPT_msoft_float)) + ABI = ppc::FloatABI::Soft; +else if (A->getOption().matches(options::OPT_mhard_float)) + ABI =
Re: [PATCH] D13351: [Power PC] add soft float support for ppc32
spetrovic updated this revision to Diff 3. spetrovic added a comment. added test case http://reviews.llvm.org/D13351 Files: lib/CodeGen/TargetInfo.cpp lib/Driver/Tools.cpp lib/Driver/Tools.h test/CodeGen/ppc-sfvarargs.c test/Driver/ppc-features.cpp Index: test/Driver/ppc-features.cpp === --- test/Driver/ppc-features.cpp +++ test/Driver/ppc-features.cpp @@ -12,6 +12,34 @@ // RUN: not %clang -target mips64-linux-gnu -faltivec -fsyntax-only %s 2>&1 | FileCheck %s // RUN: not %clang -target sparc-unknown-solaris -faltivec -fsyntax-only %s 2>&1 | FileCheck %s +// check -msoft-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT %s +// CHECK-SOFTFLOAT: "-target-feature" "+soft-float" + +// check -mfloat-abi=soft option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=soft -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT %s +// CHECK-FLOATABISOFT: "-target-feature" "+soft-float" + +// check -mhard-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mhard-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-HARDFLOAT %s +// CHECK-HARDFLOAT-NOT: "-target-feature" "+soft-float" + +// check -mfloat-abi=hard option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=hard -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABIHARD %s +// CHECK-FLOATABIHARD-NOT: "-target-feature" "+soft-float" + +// check combine -mhard-float -msoft-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mhard-float -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-HARDSOFT %s +// CHECK-HARDSOFT: "-target-feature" "+soft-float" + +// check combine -msoft-float -mhard-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -mhard-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTHARD %s +// CHECK-SOFTHARD-NOT: "-target-feature" "+soft-float" + +// check -mfloat-abi=x option +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=x -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-ERRMSG %s +// CHECK-ERRMSG: clang: error: invalid float ABI '-mfloat-abi=x' + // CHECK: invalid argument '-faltivec' only allowed with 'ppc/ppc64/ppc64le' // Check that -fno-altivec and -mno-altivec correctly disable the altivec Index: test/CodeGen/ppc-sfvarargs.c === --- test/CodeGen/ppc-sfvarargs.c +++ test/CodeGen/ppc-sfvarargs.c @@ -0,0 +1,17 @@ +// RUN: %clang -O0 --target=powerpc-unknown-linux-gnu -EB -msoft-float -S -emit-llvm %s -o - | FileCheck %s + +#include +void test(char *fmt, ...) { + va_list ap; + va_start(ap, fmt); + va_arg(ap, double); + va_end(ap); +} + +void foo() { + double a; + test("test",a); +} +// CHECK: %{{[0-9]+}} = add i8 %numUsedRegs, 1 +// CHECK: %{{[0-9]+}} = and i8 %{{[0-9]+}}, -2 +// CHECK: %{{[0-9]+}} = mul i8 %{{[0-9]+}}, 4 \ No newline at end of file Index: lib/Driver/Tools.h === --- lib/Driver/Tools.h +++ lib/Driver/Tools.h @@ -731,6 +731,16 @@ FloatABI getARMFloatABI(const ToolChain &TC, const llvm::opt::ArgList &Args); } + +namespace ppc { +enum class FloatABI { + Invalid, + Soft, + SoftFP, + Hard, +}; + ppc::FloatABI getPPCFloatABI(const Driver &D, const llvm::opt::ArgList &Args); +} namespace XCore { // For XCore, we do not need to instantiate tools for PreProcess, PreCompile and // Compile. Index: lib/Driver/Tools.cpp === --- lib/Driver/Tools.cpp +++ lib/Driver/Tools.cpp @@ -1325,7 +1325,7 @@ return ""; } -static void getPPCTargetFeatures(const ArgList &Args, +static void getPPCTargetFeatures(const Driver &D, const ArgList &Args, std::vector &Features) { for (const Arg *A : Args.filtered(options::OPT_m_ppc_Features_Group)) { StringRef Name = A->getOption().getName(); @@ -1345,15 +1345,48 @@ // TODO: Change the LLVM backend option maybe? if (Name == "mfcrf") Name = "mfocrf"; - + Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name)); } + ppc::FloatABI FloatABI = ppc::getPPCFloatABI(D, Args); + if (FloatABI == ppc::FloatABI::Soft) +Features.push_back("+soft-float"); + // Altivec is a bit weird, allow overriding of the Altivec feature here. AddTargetFeature(Args, Features, options::OPT_faltivec, options::OPT_fno_altivec, "altivec"); } +ppc::FloatABI ppc::getPPCFloatABI(const Driver &D, const ArgList &Args) { + ppc::FloatABI ABI = ppc::FloatABI::Invalid; + if (Arg *A = Args.getLastArg(options::OPT_msoft_float, + options::OPT_mhard_float, + options::OPT_mfloat_ab
Re: [PATCH] D13351: [Power PC] add soft float support for ppc32
spetrovic added a comment. ping http://reviews.llvm.org/D13351 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D21022: [ARM] Fix linker emulation for arm 32 big endian
spetrovic created this revision. spetrovic added reviewers: rafael, petarj. spetrovic added subscribers: rankov, ivanbaev, cfe-commits. Herald added subscribers: rengolin, aemerson. This patch fixes target linker emulation for arm 32 big endian. As I saw in gcc only supported linker emulation is armelfb_linux_eabi. http://reviews.llvm.org/D21022 Files: lib/Driver/Tools.cpp test/Driver/linux-ld.c Index: test/Driver/linux-ld.c === --- test/Driver/linux-ld.c +++ test/Driver/linux-ld.c @@ -1561,13 +1561,13 @@ // RUN: | FileCheck --check-prefix=CHECK-ARMEB %s // CHECK-ARMEB: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-ARMEB-NOT: "--be8" -// CHECK-ARMEB: "-m" "armebelf_linux_eabi" +// CHECK-ARMEB: "-m" "armelfb_linux_eabi" // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ // RUN: --target=armebv7-unknown-linux \ // RUN: --gcc-toolchain="" \ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: | FileCheck --check-prefix=CHECK-ARMV7EB %s // CHECK-ARMV7EB: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-ARMV7EB: "--be8" -// CHECK-ARMV7EB: "-m" "armebelf_linux_eabi" +// CHECK-ARMV7EB: "-m" "armelfb_linux_eabi" Index: lib/Driver/Tools.cpp === --- lib/Driver/Tools.cpp +++ lib/Driver/Tools.cpp @@ -9095,7 +9095,7 @@ return "armelf_linux_eabi"; case llvm::Triple::armeb: case llvm::Triple::thumbeb: -return "armebelf_linux_eabi"; /* TODO: check which NAME. */ +return "armelfb_linux_eabi"; /* TODO: check which NAME. */ case llvm::Triple::ppc: return "elf32ppclinux"; case llvm::Triple::ppc64: Index: test/Driver/linux-ld.c === --- test/Driver/linux-ld.c +++ test/Driver/linux-ld.c @@ -1561,13 +1561,13 @@ // RUN: | FileCheck --check-prefix=CHECK-ARMEB %s // CHECK-ARMEB: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-ARMEB-NOT: "--be8" -// CHECK-ARMEB: "-m" "armebelf_linux_eabi" +// CHECK-ARMEB: "-m" "armelfb_linux_eabi" // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ // RUN: --target=armebv7-unknown-linux \ // RUN: --gcc-toolchain="" \ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: | FileCheck --check-prefix=CHECK-ARMV7EB %s // CHECK-ARMV7EB: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-ARMV7EB: "--be8" -// CHECK-ARMV7EB: "-m" "armebelf_linux_eabi" +// CHECK-ARMV7EB: "-m" "armelfb_linux_eabi" Index: lib/Driver/Tools.cpp === --- lib/Driver/Tools.cpp +++ lib/Driver/Tools.cpp @@ -9095,7 +9095,7 @@ return "armelf_linux_eabi"; case llvm::Triple::armeb: case llvm::Triple::thumbeb: -return "armebelf_linux_eabi"; /* TODO: check which NAME. */ +return "armelfb_linux_eabi"; /* TODO: check which NAME. */ case llvm::Triple::ppc: return "elf32ppclinux"; case llvm::Triple::ppc64: ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D21022: [ARM] Fix linker emulation for arm 32 big endian
spetrovic updated this revision to Diff 59870. spetrovic marked an inline comment as done. spetrovic added a comment. Comment addressed. http://reviews.llvm.org/D21022 Files: lib/Driver/Tools.cpp test/Driver/linux-ld.c Index: test/Driver/linux-ld.c === --- test/Driver/linux-ld.c +++ test/Driver/linux-ld.c @@ -1561,13 +1561,13 @@ // RUN: | FileCheck --check-prefix=CHECK-ARMEB %s // CHECK-ARMEB: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-ARMEB-NOT: "--be8" -// CHECK-ARMEB: "-m" "armebelf_linux_eabi" +// CHECK-ARMEB: "-m" "armelfb_linux_eabi" // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ // RUN: --target=armebv7-unknown-linux \ // RUN: --gcc-toolchain="" \ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: | FileCheck --check-prefix=CHECK-ARMV7EB %s // CHECK-ARMV7EB: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-ARMV7EB: "--be8" -// CHECK-ARMV7EB: "-m" "armebelf_linux_eabi" +// CHECK-ARMV7EB: "-m" "armelfb_linux_eabi" Index: lib/Driver/Tools.cpp === --- lib/Driver/Tools.cpp +++ lib/Driver/Tools.cpp @@ -9095,7 +9095,7 @@ return "armelf_linux_eabi"; case llvm::Triple::armeb: case llvm::Triple::thumbeb: -return "armebelf_linux_eabi"; /* TODO: check which NAME. */ +return "armelfb_linux_eabi"; case llvm::Triple::ppc: return "elf32ppclinux"; case llvm::Triple::ppc64: Index: test/Driver/linux-ld.c === --- test/Driver/linux-ld.c +++ test/Driver/linux-ld.c @@ -1561,13 +1561,13 @@ // RUN: | FileCheck --check-prefix=CHECK-ARMEB %s // CHECK-ARMEB: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-ARMEB-NOT: "--be8" -// CHECK-ARMEB: "-m" "armebelf_linux_eabi" +// CHECK-ARMEB: "-m" "armelfb_linux_eabi" // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ // RUN: --target=armebv7-unknown-linux \ // RUN: --gcc-toolchain="" \ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: | FileCheck --check-prefix=CHECK-ARMV7EB %s // CHECK-ARMV7EB: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-ARMV7EB: "--be8" -// CHECK-ARMV7EB: "-m" "armebelf_linux_eabi" +// CHECK-ARMV7EB: "-m" "armelfb_linux_eabi" Index: lib/Driver/Tools.cpp === --- lib/Driver/Tools.cpp +++ lib/Driver/Tools.cpp @@ -9095,7 +9095,7 @@ return "armelf_linux_eabi"; case llvm::Triple::armeb: case llvm::Triple::thumbeb: -return "armebelf_linux_eabi"; /* TODO: check which NAME. */ +return "armelfb_linux_eabi"; case llvm::Triple::ppc: return "elf32ppclinux"; case llvm::Triple::ppc64: ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r272402 - This patch fixes target linker emulation for ARM 32 big endian.
Author: spetrovic Date: Fri Jun 10 11:09:20 2016 New Revision: 272402 URL: http://llvm.org/viewvc/llvm-project?rev=272402&view=rev Log: This patch fixes target linker emulation for ARM 32 big endian. Modified: cfe/trunk/lib/Driver/Tools.cpp cfe/trunk/test/Driver/linux-ld.c Modified: cfe/trunk/lib/Driver/Tools.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=272402&r1=272401&r2=272402&view=diff == --- cfe/trunk/lib/Driver/Tools.cpp (original) +++ cfe/trunk/lib/Driver/Tools.cpp Fri Jun 10 11:09:20 2016 @@ -9119,7 +9119,7 @@ static const char *getLDMOption(const ll return "armelf_linux_eabi"; case llvm::Triple::armeb: case llvm::Triple::thumbeb: -return "armebelf_linux_eabi"; /* TODO: check which NAME. */ +return "armelfb_linux_eabi"; case llvm::Triple::ppc: return "elf32ppclinux"; case llvm::Triple::ppc64: Modified: cfe/trunk/test/Driver/linux-ld.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/linux-ld.c?rev=272402&r1=272401&r2=272402&view=diff == --- cfe/trunk/test/Driver/linux-ld.c (original) +++ cfe/trunk/test/Driver/linux-ld.c Fri Jun 10 11:09:20 2016 @@ -1561,7 +1561,7 @@ // RUN: | FileCheck --check-prefix=CHECK-ARMEB %s // CHECK-ARMEB: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-ARMEB-NOT: "--be8" -// CHECK-ARMEB: "-m" "armebelf_linux_eabi" +// CHECK-ARMEB: "-m" "armelfb_linux_eabi" // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ // RUN: --target=armebv7-unknown-linux \ @@ -1570,4 +1570,4 @@ // RUN: | FileCheck --check-prefix=CHECK-ARMV7EB %s // CHECK-ARMV7EB: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-ARMV7EB: "--be8" -// CHECK-ARMV7EB: "-m" "armebelf_linux_eabi" +// CHECK-ARMV7EB: "-m" "armelfb_linux_eabi" ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D21611: Fix small structures calling convention issue for some big endian architectures
spetrovic created this revision. spetrovic added reviewers: rjmccall, john.brawn, dsanders, petarj. spetrovic added subscribers: cfe-commits, rankov, ivanbaev. Herald added a reviewer: vkalintiris. Herald added a subscriber: aemerson. This patch fixes problem with passing structures and unions smaller than register as argument in variadic functions on big endian architectures. For example passing 3 chars in a structure as argument of variadic function LLVM is passing those chars left-adjusted in register and trying to read them like they are right-adjusted, and that makes the problem. I have changed reading of those arguments. Now LLVM reads them properly (left-adjusted). I detected this problem on ARM32 big endian, MIPS32 big endian and MIPS64 big endian. http://reviews.llvm.org/D21611 Files: lib/CodeGen/TargetInfo.cpp test/CodeGen/struct-union-BE.c Index: test/CodeGen/struct-union-BE.c === --- test/CodeGen/struct-union-BE.c +++ test/CodeGen/struct-union-BE.c @@ -0,0 +1,48 @@ +// RUN: %clang -O2 -target mips-linux-gnu -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS +// RUN: %clang -O2 -target mips64-linux-gnu -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64 +// RUN: %clang -O2 -target armeb-linux-gnueabihf -march=armv7a -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM + +#include +#include + +struct tiny { + char c; +}; + +union data { + char c; +}; + +void fstr(int n, ...) { + struct tiny x; + va_list ap; + va_start (ap,n); + x = va_arg (ap, struct tiny); + if (x.c != 10) +abort(); + va_end (ap); +// MIPS-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +// MIPS64-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i64 7 +// ARM-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +} + +void funi(int n, ...) { + union data x; + va_list ap; + va_start (ap,n); + x = va_arg (ap, union data); + if (x.c != 10) +abort(); + va_end (ap); +// MIPS-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +// MIPS64-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i64 7 +// ARM-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +} + +void foo() { + struct tiny x[3]; + union data y; + x[0].c = 10; + fstr(1, x[0]); + funi(1, y); +} Index: lib/CodeGen/TargetInfo.cpp === --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -272,7 +272,8 @@ // If the argument is smaller than a slot, and this is a big-endian // target, the argument will be right-adjusted in its slot. - if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian()) { + if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() && + !DirectTy->isStructTy()) { Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize); } Index: test/CodeGen/struct-union-BE.c === --- test/CodeGen/struct-union-BE.c +++ test/CodeGen/struct-union-BE.c @@ -0,0 +1,48 @@ +// RUN: %clang -O2 -target mips-linux-gnu -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS +// RUN: %clang -O2 -target mips64-linux-gnu -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64 +// RUN: %clang -O2 -target armeb-linux-gnueabihf -march=armv7a -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM + +#include +#include + +struct tiny { + char c; +}; + +union data { + char c; +}; + +void fstr(int n, ...) { + struct tiny x; + va_list ap; + va_start (ap,n); + x = va_arg (ap, struct tiny); + if (x.c != 10) +abort(); + va_end (ap); +// MIPS-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +// MIPS64-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i64 7 +// ARM-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +} + +void funi(int n, ...) { + union data x; + va_list ap; + va_start (ap,n); + x = va_arg (ap, union data); + if (x.c != 10) +abort(); + va_end (ap); +// MIPS-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +// MIPS64-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i64 7 +// ARM-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +} + +void foo() { + struct tiny x[3]; + union data y; + x[0].c = 10; + fstr(1, x[0]); + funi(1, y); +} Index: lib/CodeGen/TargetInfo.cpp === --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -272,7 +272,8 @@ // If the argument is smaller than a slot, and this is a big-endian // target, the argument will be right-adjusted in its slot. - if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian()) { + if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() && + !DirectTy->isStructTy()) { Addr = C
Re: [PATCH] D21611: Fix small structures calling convention issue for some big endian architectures
spetrovic added a comment. Yes, I tried all caller - callee combinations for ARM32 big endian and MIPS/MIPS64 big endian, and it works properly with this patch. http://reviews.llvm.org/D21611 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r273665 - This patch fixes problem with passing structures and unions
Author: spetrovic Date: Fri Jun 24 07:12:41 2016 New Revision: 273665 URL: http://llvm.org/viewvc/llvm-project?rev=273665&view=rev Log: This patch fixes problem with passing structures and unions smaller than register as argument in variadic functions on big endian architectures. Differential Revision: http://reviews.llvm.org/D21611 Added: cfe/trunk/test/CodeGen/struct-union-BE.c Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=273665&r1=273664&r2=273665&view=diff == --- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original) +++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Fri Jun 24 07:12:41 2016 @@ -272,7 +272,8 @@ static Address emitVoidPtrDirectVAArg(Co // If the argument is smaller than a slot, and this is a big-endian // target, the argument will be right-adjusted in its slot. - if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian()) { + if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() && + !DirectTy->isStructTy()) { Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize); } Added: cfe/trunk/test/CodeGen/struct-union-BE.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/struct-union-BE.c?rev=273665&view=auto == --- cfe/trunk/test/CodeGen/struct-union-BE.c (added) +++ cfe/trunk/test/CodeGen/struct-union-BE.c Fri Jun 24 07:12:41 2016 @@ -0,0 +1,48 @@ +// RUN: %clang -O2 -target mips-linux-gnu -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS +// RUN: %clang -O2 -target mips64-linux-gnu -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64 +// RUN: %clang -O2 -target armeb-linux-gnueabihf -march=armv7a -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM + +#include +#include + +struct tiny { + char c; +}; + +union data { + char c; +}; + +void fstr(int n, ...) { + struct tiny x; + va_list ap; + va_start (ap,n); + x = va_arg (ap, struct tiny); + if (x.c != 10) +abort(); + va_end (ap); +// MIPS-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +// MIPS64-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i64 7 +// ARM-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +} + +void funi(int n, ...) { + union data x; + va_list ap; + va_start (ap,n); + x = va_arg (ap, union data); + if (x.c != 10) +abort(); + va_end (ap); +// MIPS-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +// MIPS64-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i64 7 +// ARM-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +} + +void foo() { + struct tiny x[3]; + union data y; + x[0].c = 10; + fstr(1, x[0]); + funi(1, y); +} ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D21611: Fix small structures calling convention issue for some big endian architectures
This revision was automatically updated to reflect the committed changes. Closed by commit rL273665: This patch fixes problem with passing structures and unions (authored by spetrovic). Changed prior to commit: http://reviews.llvm.org/D21611?vs=61557&id=61777#toc Repository: rL LLVM http://reviews.llvm.org/D21611 Files: cfe/trunk/lib/CodeGen/TargetInfo.cpp cfe/trunk/test/CodeGen/struct-union-BE.c Index: cfe/trunk/test/CodeGen/struct-union-BE.c === --- cfe/trunk/test/CodeGen/struct-union-BE.c +++ cfe/trunk/test/CodeGen/struct-union-BE.c @@ -0,0 +1,48 @@ +// RUN: %clang -O2 -target mips-linux-gnu -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS +// RUN: %clang -O2 -target mips64-linux-gnu -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64 +// RUN: %clang -O2 -target armeb-linux-gnueabihf -march=armv7a -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM + +#include +#include + +struct tiny { + char c; +}; + +union data { + char c; +}; + +void fstr(int n, ...) { + struct tiny x; + va_list ap; + va_start (ap,n); + x = va_arg (ap, struct tiny); + if (x.c != 10) +abort(); + va_end (ap); +// MIPS-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +// MIPS64-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i64 7 +// ARM-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +} + +void funi(int n, ...) { + union data x; + va_list ap; + va_start (ap,n); + x = va_arg (ap, union data); + if (x.c != 10) +abort(); + va_end (ap); +// MIPS-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +// MIPS64-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i64 7 +// ARM-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +} + +void foo() { + struct tiny x[3]; + union data y; + x[0].c = 10; + fstr(1, x[0]); + funi(1, y); +} Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp === --- cfe/trunk/lib/CodeGen/TargetInfo.cpp +++ cfe/trunk/lib/CodeGen/TargetInfo.cpp @@ -272,7 +272,8 @@ // If the argument is smaller than a slot, and this is a big-endian // target, the argument will be right-adjusted in its slot. - if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian()) { + if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() && + !DirectTy->isStructTy()) { Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize); } Index: cfe/trunk/test/CodeGen/struct-union-BE.c === --- cfe/trunk/test/CodeGen/struct-union-BE.c +++ cfe/trunk/test/CodeGen/struct-union-BE.c @@ -0,0 +1,48 @@ +// RUN: %clang -O2 -target mips-linux-gnu -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS +// RUN: %clang -O2 -target mips64-linux-gnu -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64 +// RUN: %clang -O2 -target armeb-linux-gnueabihf -march=armv7a -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM + +#include +#include + +struct tiny { + char c; +}; + +union data { + char c; +}; + +void fstr(int n, ...) { + struct tiny x; + va_list ap; + va_start (ap,n); + x = va_arg (ap, struct tiny); + if (x.c != 10) +abort(); + va_end (ap); +// MIPS-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +// MIPS64-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i64 7 +// ARM-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +} + +void funi(int n, ...) { + union data x; + va_list ap; + va_start (ap,n); + x = va_arg (ap, union data); + if (x.c != 10) +abort(); + va_end (ap); +// MIPS-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +// MIPS64-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i64 7 +// ARM-NOT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %argp.cur, i32 3 +} + +void foo() { + struct tiny x[3]; + union data y; + x[0].c = 10; + fstr(1, x[0]); + funi(1, y); +} Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp === --- cfe/trunk/lib/CodeGen/TargetInfo.cpp +++ cfe/trunk/lib/CodeGen/TargetInfo.cpp @@ -272,7 +272,8 @@ // If the argument is smaller than a slot, and this is a big-endian // target, the argument will be right-adjusted in its slot. - if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian()) { + if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() && + !DirectTy->isStructTy()) { Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize); } ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r273675 - Fix make-check issues
Author: spetrovic Date: Fri Jun 24 08:11:15 2016 New Revision: 273675 URL: http://llvm.org/viewvc/llvm-project?rev=273675&view=rev Log: Fix make-check issues Fixing build issue for test test/CodeGen/struct-union-BE.c. Modified: cfe/trunk/test/CodeGen/struct-union-BE.c Modified: cfe/trunk/test/CodeGen/struct-union-BE.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/struct-union-BE.c?rev=273675&r1=273674&r2=273675&view=diff == --- cfe/trunk/test/CodeGen/struct-union-BE.c (original) +++ cfe/trunk/test/CodeGen/struct-union-BE.c Fri Jun 24 08:11:15 2016 @@ -1,9 +1,10 @@ -// RUN: %clang -O2 -target mips-linux-gnu -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS -// RUN: %clang -O2 -target mips64-linux-gnu -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64 -// RUN: %clang -O2 -target armeb-linux-gnueabihf -march=armv7a -EB -S -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM +// RUN: %clang_cc1 -triple mips-linux-gnu -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS +// RUN: %clang_cc1 -triple mips64-linux-gnu -S -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64 +// RUN: %clang_cc1 -triple armebv7-linux-gnueabihf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM #include -#include + +extern void abort() __attribute__((noreturn)); struct tiny { char c; ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D13351: [Power PC] add soft float support for ppc32
spetrovic set the repository for this revision to rL LLVM. spetrovic updated this revision to Diff 40143. spetrovic marked 2 inline comments as done. spetrovic added a comment. Comments addressed. Repository: rL LLVM http://reviews.llvm.org/D13351 Files: include/clang/Basic/DiagnosticDriverKinds.td lib/CodeGen/TargetInfo.cpp lib/Driver/Tools.cpp lib/Driver/Tools.h test/CodeGen/ppc-sfvarargs.c test/Driver/ppc-features.cpp Index: test/Driver/ppc-features.cpp === --- test/Driver/ppc-features.cpp +++ test/Driver/ppc-features.cpp @@ -12,6 +12,50 @@ // RUN: not %clang -target mips64-linux-gnu -faltivec -fsyntax-only %s 2>&1 | FileCheck %s // RUN: not %clang -target sparc-unknown-solaris -faltivec -fsyntax-only %s 2>&1 | FileCheck %s +// check -msoft-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT %s +// CHECK-SOFTFLOAT: "-target-feature" "+soft-float" + +// check -mfloat-abi=soft option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=soft -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT %s +// CHECK-FLOATABISOFT: "-target-feature" "+soft-float" + +// check -mhard-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mhard-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-HARDFLOAT %s +// CHECK-HARDFLOAT-NOT: "-target-feature" "+soft-float" + +// check -mfloat-abi=hard option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=hard -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABIHARD %s +// CHECK-FLOATABIHARD-NOT: "-target-feature" "+soft-float" + +// check combine -mhard-float -msoft-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mhard-float -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-HARDSOFT %s +// CHECK-HARDSOFT: "-target-feature" "+soft-float" + +// check combine -msoft-float -mhard-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -mhard-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTHARD %s +// CHECK-SOFTHARD-NOT: "-target-feature" "+soft-float" + +// check -mfloat-abi=x option +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=x -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-ERRMSG %s +// CHECK-ERRMSG: clang: error: invalid float ABI '-mfloat-abi=x' + +// check -msoft-float option for ppc64 +// RUN: %clang -target powerpc64-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT64 %s +// CHECK-SOFTFLOAT64: clang: error: soft float is not supported for ppc64 + +// check -mfloat-abi=soft option for ppc64 +// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mfloat-abi=soft -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT64 %s +// CHECK-FLOATABISOFT64: clang: error: soft float is not supported for ppc64 + +// check -msoft-float option for ppc64 +// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT64le %s +// CHECK-SOFTFLOAT64le: clang: error: soft float is not supported for ppc64 + +// check -mfloat-abi=soft option for ppc64 +// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -mfloat-abi=soft -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT64le %s +// CHECK-FLOATABISOFT64le: clang: error: soft float is not supported for ppc64 + // CHECK: invalid argument '-faltivec' only allowed with 'ppc/ppc64/ppc64le' // Check that -fno-altivec and -mno-altivec correctly disable the altivec Index: test/CodeGen/ppc-sfvarargs.c === --- test/CodeGen/ppc-sfvarargs.c +++ test/CodeGen/ppc-sfvarargs.c @@ -0,0 +1,17 @@ +// RUN: %clang -O0 --target=powerpc-unknown-linux-gnu -EB -msoft-float -S -emit-llvm %s -o - | FileCheck %s + +#include +void test(char *fmt, ...) { + va_list ap; + va_start(ap, fmt); + va_arg(ap, double); + va_end(ap); +} + +void foo() { + double a; + test("test",a); +} +// CHECK: %{{[0-9]+}} = add i8 %numUsedRegs, 1 +// CHECK: %{{[0-9]+}} = and i8 %{{[0-9]+}}, -2 +// CHECK: %{{[0-9]+}} = mul i8 %{{[0-9]+}}, 4 \ No newline at end of file Index: lib/Driver/Tools.h === --- lib/Driver/Tools.h +++ lib/Driver/Tools.h @@ -731,6 +731,16 @@ FloatABI getARMFloatABI(const ToolChain &TC, const llvm::opt::ArgList &Args); } + +namespace ppc { +enum class FloatABI { + Invalid, + Soft, + Hard, +}; + +FloatABI getPPCFloatABI(const Driver &D, const llvm::opt::ArgList &Args); +} namespace XCore { // For XCore, we do not need to instantiate tools for PreProcess, PreCompile and // Compile. Index: lib/Driver/Tools.cpp === --- lib/Driver/Tools.cpp +++ lib/Driver/Tools
Re: [PATCH] D13351: [Power PC] add soft float support for ppc32
spetrovic added a comment. ping http://reviews.llvm.org/D13351 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D14871: [Power PC] fix calculating address of arguments on stack for variadic functions
spetrovic created this revision. spetrovic added reviewers: petarj, hfinkel, rjmccall. spetrovic added a subscriber: cfe-commits. This patch fixes calculating address of double arguments on stack for variadic functions (rounding up address to alignment) on ppc32 architecture. http://reviews.llvm.org/D14871 Files: lib/CodeGen/TargetInfo.cpp test/CodeGen/ppc-varargs-struct.c Index: test/CodeGen/ppc-varargs-struct.c === --- test/CodeGen/ppc-varargs-struct.c +++ test/CodeGen/ppc-varargs-struct.c @@ -39,9 +39,13 @@ // CHECK-PPC:[[USING_OVERFLOW]] // CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 // CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 -// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to %struct.x** -// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* [[OVERFLOW_AREA]], i32 4 -// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA]], i8** [[OVERFLOW_AREA_P]] +// CHECK-PPC-NEXT: %{{[0-9]+}} = getelementptr i8, i8* %{{[0-9]+}}, i32 7 +// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %{{[0-9]+}} to i32 +// CHECK-PPC-NEXT: %{{[0-9]+}} = and i32 %{{[0-9]+}}, -8 +// CHECK-PPC-NEXT: %overflow_arg_area.align = inttoptr i32 %{{[0-9]+}} to i8* +// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* %overflow_arg_area.align to %struct.x** +// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* %overflow_arg_area.align, i32 4 +// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA:%[0-9]+]], i8** [[OVERFLOW_AREA_P]], align 4 // CHECK-PPC-NEXT: br label %[[CONT]] // // CHECK-PPC:[[CONT]] Index: lib/CodeGen/TargetInfo.cpp === --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -3543,9 +3543,23 @@ Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4)); Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr), OverflowAreaAlign); - -// The current address is the address of the varargs element. -// FIXME: do we not need to round up to alignment? +// Round up address of argument to alignment +llvm::Value *overflow_arg_area = OverflowArea.getPointer(); +uint32_t Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity(); +if (Align > 4) { + // overflow_arg_area = (overflow_arg_area + align - 1) & -align; + llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, Align - 1); + overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset); + llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(overflow_arg_area, + CGF.Int32Ty); + llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int32Ty, -(uint32_t)Align); + overflow_arg_area = +CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask), + overflow_arg_area->getType(), + "overflow_arg_area.align"); +} + +OverflowArea = Address(overflow_arg_area, CharUnits::fromQuantity(Align)); MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy); // Increase the overflow area. Index: test/CodeGen/ppc-varargs-struct.c === --- test/CodeGen/ppc-varargs-struct.c +++ test/CodeGen/ppc-varargs-struct.c @@ -39,9 +39,13 @@ // CHECK-PPC:[[USING_OVERFLOW]] // CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 // CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 -// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to %struct.x** -// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* [[OVERFLOW_AREA]], i32 4 -// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA]], i8** [[OVERFLOW_AREA_P]] +// CHECK-PPC-NEXT: %{{[0-9]+}} = getelementptr i8, i8* %{{[0-9]+}}, i32 7 +// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %{{[0-9]+}} to i32 +// CHECK-PPC-NEXT: %{{[0-9]+}} = and i32 %{{[0-9]+}}, -8 +// CHECK-PPC-NEXT: %overflow_arg_area.align = inttoptr i32 %{{[0-9]+}} to i8* +// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* %overflow_arg_area.align to %struct.x** +// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* %overflow_arg_area.align, i32 4 +// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA:%[0-9]+]], i8** [[OVERFLOW_AREA_P]], align 4 // CHECK-PPC-NEXT: br label %[[CONT]] // // CHECK-PPC:[[CONT]] Index: lib/CodeGen/TargetInfo.cpp === --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -3543,9 +3543,23 @@ Builder.CreateStructGEP(V
Re: [PATCH] D14871: [Power PC] fix calculating address of arguments on stack for variadic functions
spetrovic updated this revision to Diff 40915. spetrovic marked an inline comment as done. http://reviews.llvm.org/D14871 Files: lib/CodeGen/TargetInfo.cpp test/CodeGen/ppc-varargs-struct.c Index: test/CodeGen/ppc-varargs-struct.c === --- test/CodeGen/ppc-varargs-struct.c +++ test/CodeGen/ppc-varargs-struct.c @@ -39,9 +39,13 @@ // CHECK-PPC:[[USING_OVERFLOW]] // CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 // CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 -// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to %struct.x** -// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* [[OVERFLOW_AREA]], i32 4 -// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA]], i8** [[OVERFLOW_AREA_P]] +// CHECK-PPC-NEXT: %{{[0-9]+}} = getelementptr i8, i8* %{{[0-9]+}}, i32 7 +// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %{{[0-9]+}} to i32 +// CHECK-PPC-NEXT: %{{[0-9]+}} = and i32 %{{[0-9]+}}, -8 +// CHECK-PPC-NEXT: %overflow_arg_area.align = inttoptr i32 %{{[0-9]+}} to i8* +// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* %overflow_arg_area.align to %struct.x** +// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* %overflow_arg_area.align, i32 4 +// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA:%[0-9]+]], i8** [[OVERFLOW_AREA_P]], align 4 // CHECK-PPC-NEXT: br label %[[CONT]] // // CHECK-PPC:[[CONT]] Index: lib/CodeGen/TargetInfo.cpp === --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -3543,9 +3543,23 @@ Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4)); Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr), OverflowAreaAlign); - -// The current address is the address of the varargs element. -// FIXME: do we not need to round up to alignment? +// Round up address of argument to alignment +llvm::Value *OverflowArgArea = OverflowArea.getPointer(); +uint32_t Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity(); +if (Align > 4) { + // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align; + llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, Align - 1); + OverflowArgArea = CGF.Builder.CreateGEP(OverflowArgArea, Offset); + llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(OverflowArgArea, + CGF.Int32Ty); + llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int32Ty, -(uint32_t)Align); + OverflowArgArea = +CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask), + OverflowArgArea->getType(), + "overflow_arg_area.align"); +} + +OverflowArea = Address(OverflowArgArea, CharUnits::fromQuantity(Align)); MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy); // Increase the overflow area. Index: test/CodeGen/ppc-varargs-struct.c === --- test/CodeGen/ppc-varargs-struct.c +++ test/CodeGen/ppc-varargs-struct.c @@ -39,9 +39,13 @@ // CHECK-PPC:[[USING_OVERFLOW]] // CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 // CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 -// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to %struct.x** -// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* [[OVERFLOW_AREA]], i32 4 -// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA]], i8** [[OVERFLOW_AREA_P]] +// CHECK-PPC-NEXT: %{{[0-9]+}} = getelementptr i8, i8* %{{[0-9]+}}, i32 7 +// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %{{[0-9]+}} to i32 +// CHECK-PPC-NEXT: %{{[0-9]+}} = and i32 %{{[0-9]+}}, -8 +// CHECK-PPC-NEXT: %overflow_arg_area.align = inttoptr i32 %{{[0-9]+}} to i8* +// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* %overflow_arg_area.align to %struct.x** +// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* %overflow_arg_area.align, i32 4 +// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA:%[0-9]+]], i8** [[OVERFLOW_AREA_P]], align 4 // CHECK-PPC-NEXT: br label %[[CONT]] // // CHECK-PPC:[[CONT]] Index: lib/CodeGen/TargetInfo.cpp === --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -3543,9 +3543,23 @@ Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4)); Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr), OverflowAreaAlign); - -// The current address is the address of the varargs
Re: [PATCH] D14871: [Power PC] fix calculating address of arguments on stack for variadic functions
spetrovic updated the summary for this revision. spetrovic updated this revision to Diff 41142. spetrovic marked 4 inline comments as done. http://reviews.llvm.org/D14871 Files: lib/CodeGen/TargetInfo.cpp test/CodeGen/ppc-varargs-struct.c Index: test/CodeGen/ppc-varargs-struct.c === --- test/CodeGen/ppc-varargs-struct.c +++ test/CodeGen/ppc-varargs-struct.c @@ -39,9 +39,13 @@ // CHECK-PPC:[[USING_OVERFLOW]] // CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 // CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 -// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to %struct.x** -// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* [[OVERFLOW_AREA]], i32 4 -// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA]], i8** [[OVERFLOW_AREA_P]] +// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %{{[0-9]+}} to i32 +// CHECK-PPC-NEXT: %{{[0-9]+}} = add i32 %{{[0-9]+}}, 7 +// CHECK-PPC-NEXT: %{{[0-9]+}} = and i32 %{{[0-9]+}}, -8 +// CHECK-PPC-NEXT: %overflow_arg_area.align = inttoptr i32 %{{[0-9]+}} to i8* +// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* %overflow_arg_area.align to %struct.x** +// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* %overflow_arg_area.align, i32 4 +// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA:%[0-9]+]], i8** [[OVERFLOW_AREA_P]], align 4 // CHECK-PPC-NEXT: br label %[[CONT]] // // CHECK-PPC:[[CONT]] Index: lib/CodeGen/TargetInfo.cpp === --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -223,6 +223,23 @@ return Addr; } +static Address emitRoundPointerUpToAlignment(CodeGenFunction &CGF, + llvm::Value *OverflowArgArea, + CharUnits Align) { + llvm::Value *PtrAsInt = OverflowArgArea; + // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align; + PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy); + PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt, +llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1)); + llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int32Ty, + -Align.getQuantity()); + PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt, Mask); + PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt, +OverflowArgArea->getType(), +"overflow_arg_area.align"); + return Address(PtrAsInt, Align); +} + /// Emit va_arg for a platform using the common void* representation, /// where arguments are simply emitted in an array of slots on the stack. /// @@ -3543,9 +3560,14 @@ Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4)); Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr), OverflowAreaAlign); - -// The current address is the address of the varargs element. -// FIXME: do we not need to round up to alignment? +// Round up address of argument to alignment +llvm::Value *OverflowArgArea = OverflowArea.getPointer(); +CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty); +if (Align > OverflowAreaAlign) { + OverflowArea = emitRoundPointerUpToAlignment(CGF, OverflowArgArea, + Align); +} + MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy); // Increase the overflow area. Index: test/CodeGen/ppc-varargs-struct.c === --- test/CodeGen/ppc-varargs-struct.c +++ test/CodeGen/ppc-varargs-struct.c @@ -39,9 +39,13 @@ // CHECK-PPC:[[USING_OVERFLOW]] // CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 // CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 -// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to %struct.x** -// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* [[OVERFLOW_AREA]], i32 4 -// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA]], i8** [[OVERFLOW_AREA_P]] +// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %{{[0-9]+}} to i32 +// CHECK-PPC-NEXT: %{{[0-9]+}} = add i32 %{{[0-9]+}}, 7 +// CHECK-PPC-NEXT: %{{[0-9]+}} = and i32 %{{[0-9]+}}, -8 +// CHECK-PPC-NEXT: %overflow_arg_area.align = inttoptr i32 %{{[0-9]+}} to i8* +// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* %overflow_arg_area.align to %struct.x** +// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* %overflow_arg_area.align, i32 4 +// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA:%[0-9]+]], i8** [[OVERFLOW
Re: [PATCH] D14871: [Power PC] fix calculating address of arguments on stack for variadic functions
spetrovic updated this revision to Diff 41297. spetrovic marked 2 inline comments as done. http://reviews.llvm.org/D14871 Files: lib/CodeGen/TargetInfo.cpp test/CodeGen/ppc-varargs-struct.c test/CodeGen/x86_64-arguments.c Index: test/CodeGen/x86_64-arguments.c === --- test/CodeGen/x86_64-arguments.c +++ test/CodeGen/x86_64-arguments.c @@ -336,7 +336,8 @@ // CHECK-LABEL: define i32 @f44 // CHECK: ptrtoint -// CHECK-NEXT: and {{.*}}, -32 +// CHECK-NEXT: add i64 %{{[0-9]+}}, 31 +// CHECK-NEXT: and i64 %{{[0-9]+}}, -32 // CHECK-NEXT: inttoptr typedef int T44 __attribute((vector_size(32))); struct s44 { T44 x; int y; }; Index: test/CodeGen/ppc-varargs-struct.c === --- test/CodeGen/ppc-varargs-struct.c +++ test/CodeGen/ppc-varargs-struct.c @@ -39,9 +39,13 @@ // CHECK-PPC:[[USING_OVERFLOW]] // CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 // CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 -// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to %struct.x** -// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* [[OVERFLOW_AREA]], i32 4 -// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA]], i8** [[OVERFLOW_AREA_P]] +// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %argp.cur to i32 +// CHECK-PPC-NEXT: %{{[0-9]+}} = add i32 %{{[0-9]+}}, 7 +// CHECK-PPC-NEXT: %{{[0-9]+}} = and i32 %{{[0-9]+}}, -8 +// CHECK-PPC-NEXT: %argp.cur.aligned = inttoptr i32 %{{[0-9]+}} to i8* +// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* %argp.cur.aligned to %struct.x** +// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 4 +// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA:%[0-9]+]], i8** [[OVERFLOW_AREA_P]], align 4 // CHECK-PPC-NEXT: br label %[[CONT]] // // CHECK-PPC:[[CONT]] Index: lib/CodeGen/TargetInfo.cpp === --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -162,6 +162,23 @@ OS << ")\n"; } +// Dynamically round a pointer up to a multiple of the given alignment. +static llvm::Value* emitRoundPointerUpToAlignment(CodeGenFunction &CGF, + llvm::Value *Ptr, + CharUnits Align) { + llvm::Value *PtrAsInt = Ptr; + // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align; + PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy); + PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt, +llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1)); + PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt, + llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity())); + PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt, +Ptr->getType(), +Ptr->getName() + ".aligned"); + return PtrAsInt; +} + /// Emit va_arg for a platform using the common void* representation, /// where arguments are simply emitted in an array of slots on the stack. /// @@ -192,19 +209,11 @@ // If the CC aligns values higher than the slot size, do so if needed. Address Addr = Address::invalid(); - if (AllowHigherAlign && DirectAlign > SlotSize) { -llvm::Value *PtrAsInt = Ptr; -PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy); -PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt, - llvm::ConstantInt::get(CGF.IntPtrTy, DirectAlign.getQuantity() - 1)); -PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt, - llvm::ConstantInt::get(CGF.IntPtrTy, -DirectAlign.getQuantity())); -Addr = Address(CGF.Builder.CreateIntToPtr(PtrAsInt, Ptr->getType(), - "argp.cur.aligned"), - DirectAlign); - } else { -Addr = Address(Ptr, SlotSize); - } + if (AllowHigherAlign && DirectAlign > SlotSize) +Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign), + DirectAlign); + else +Addr = Address(Ptr, SlotSize); // Advance the pointer past the argument, then store that back. CharUnits FullDirectSize = DirectSize.RoundUpToAlignment(SlotSize); @@ -3072,20 +3081,10 @@ // byte boundary if alignment needed by type exceeds 8 byte boundary. // It isn't stated explicitly in the standard, but in practice we use // alignment greater than 16 where necessary. - uint64_t Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity(); - if (Align > 8) { -// overflow_arg_area = (overflow_arg_area + align - 1) & -align; -llvm::Value *Offset = - llvm::ConstantInt::get(CGF.Int64Ty, Align - 1); -overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset)
Re: [PATCH] D14871: [Power PC] fix calculating address of arguments on stack for variadic functions
spetrovic added a comment. Comments addressed. http://reviews.llvm.org/D14871 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D14871: [Power PC] fix calculating address of arguments on stack for variadic functions
spetrovic added a comment. Comments addressed. http://reviews.llvm.org/D14871 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D14871: [Power PC] fix calculating address of arguments on stack for variadic functions
spetrovic updated this revision to Diff 41498. spetrovic marked 3 inline comments as done. http://reviews.llvm.org/D14871 Files: lib/CodeGen/TargetInfo.cpp test/CodeGen/ppc-varargs-struct.c test/CodeGen/x86_64-arguments.c Index: test/CodeGen/x86_64-arguments.c === --- test/CodeGen/x86_64-arguments.c +++ test/CodeGen/x86_64-arguments.c @@ -336,7 +336,8 @@ // CHECK-LABEL: define i32 @f44 // CHECK: ptrtoint -// CHECK-NEXT: and {{.*}}, -32 +// CHECK-NEXT: add i64 %{{[0-9]+}}, 31 +// CHECK-NEXT: and i64 %{{[0-9]+}}, -32 // CHECK-NEXT: inttoptr typedef int T44 __attribute((vector_size(32))); struct s44 { T44 x; int y; }; Index: test/CodeGen/ppc-varargs-struct.c === --- test/CodeGen/ppc-varargs-struct.c +++ test/CodeGen/ppc-varargs-struct.c @@ -39,9 +39,13 @@ // CHECK-PPC:[[USING_OVERFLOW]] // CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 // CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 -// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to %struct.x** -// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* [[OVERFLOW_AREA]], i32 4 -// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA]], i8** [[OVERFLOW_AREA_P]] +// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %argp.cur to i32 +// CHECK-PPC-NEXT: %{{[0-9]+}} = add i32 %{{[0-9]+}}, 7 +// CHECK-PPC-NEXT: %{{[0-9]+}} = and i32 %{{[0-9]+}}, -8 +// CHECK-PPC-NEXT: %argp.cur.aligned = inttoptr i32 %{{[0-9]+}} to i8* +// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* %argp.cur.aligned to %struct.x** +// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 4 +// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA:%[0-9]+]], i8** [[OVERFLOW_AREA_P]], align 4 // CHECK-PPC-NEXT: br label %[[CONT]] // // CHECK-PPC:[[CONT]] Index: lib/CodeGen/TargetInfo.cpp === --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -162,6 +162,23 @@ OS << ")\n"; } +// Dynamically round a pointer up to a multiple of the given alignment. +static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF, + llvm::Value *Ptr, + CharUnits Align) { + llvm::Value *PtrAsInt = Ptr; + // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align; + PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy); + PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt, +llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1)); + PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt, + llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity())); + PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt, +Ptr->getType(), +Ptr->getName() + ".aligned"); + return PtrAsInt; +} + /// Emit va_arg for a platform using the common void* representation, /// where arguments are simply emitted in an array of slots on the stack. /// @@ -193,17 +210,11 @@ // If the CC aligns values higher than the slot size, do so if needed. Address Addr = Address::invalid(); if (AllowHigherAlign && DirectAlign > SlotSize) { -llvm::Value *PtrAsInt = Ptr; -PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy); -PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt, - llvm::ConstantInt::get(CGF.IntPtrTy, DirectAlign.getQuantity() - 1)); -PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt, - llvm::ConstantInt::get(CGF.IntPtrTy, -DirectAlign.getQuantity())); -Addr = Address(CGF.Builder.CreateIntToPtr(PtrAsInt, Ptr->getType(), - "argp.cur.aligned"), - DirectAlign); - } else { -Addr = Address(Ptr, SlotSize); +Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign), + DirectAlign); + } + else { +Addr = Address(Ptr, SlotSize); } // Advance the pointer past the argument, then store that back. @@ -3072,19 +3083,10 @@ // byte boundary if alignment needed by type exceeds 8 byte boundary. // It isn't stated explicitly in the standard, but in practice we use // alignment greater than 16 where necessary. - uint64_t Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity(); - if (Align > 8) { -// overflow_arg_area = (overflow_arg_area + align - 1) & -align; -llvm::Value *Offset = - llvm::ConstantInt::get(CGF.Int64Ty, Align - 1); -overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset); -llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(overflow_arg_area, -
Re: [PATCH] D14871: [Power PC] fix calculating address of arguments on stack for variadic functions
spetrovic updated this revision to Diff 41613. spetrovic marked an inline comment as done. http://reviews.llvm.org/D14871 Files: lib/CodeGen/TargetInfo.cpp test/CodeGen/ppc-varargs-struct.c test/CodeGen/x86_64-arguments.c Index: test/CodeGen/x86_64-arguments.c === --- test/CodeGen/x86_64-arguments.c +++ test/CodeGen/x86_64-arguments.c @@ -336,7 +336,8 @@ // CHECK-LABEL: define i32 @f44 // CHECK: ptrtoint -// CHECK-NEXT: and {{.*}}, -32 +// CHECK-NEXT: add i64 %{{[0-9]+}}, 31 +// CHECK-NEXT: and i64 %{{[0-9]+}}, -32 // CHECK-NEXT: inttoptr typedef int T44 __attribute((vector_size(32))); struct s44 { T44 x; int y; }; Index: test/CodeGen/ppc-varargs-struct.c === --- test/CodeGen/ppc-varargs-struct.c +++ test/CodeGen/ppc-varargs-struct.c @@ -39,9 +39,13 @@ // CHECK-PPC:[[USING_OVERFLOW]] // CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 // CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 -// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to %struct.x** -// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* [[OVERFLOW_AREA]], i32 4 -// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA]], i8** [[OVERFLOW_AREA_P]] +// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %argp.cur to i32 +// CHECK-PPC-NEXT: %{{[0-9]+}} = add i32 %{{[0-9]+}}, 7 +// CHECK-PPC-NEXT: %{{[0-9]+}} = and i32 %{{[0-9]+}}, -8 +// CHECK-PPC-NEXT: %argp.cur.aligned = inttoptr i32 %{{[0-9]+}} to i8* +// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* %argp.cur.aligned to %struct.x** +// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 4 +// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA:%[0-9]+]], i8** [[OVERFLOW_AREA_P]], align 4 // CHECK-PPC-NEXT: br label %[[CONT]] // // CHECK-PPC:[[CONT]] Index: lib/CodeGen/TargetInfo.cpp === --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -162,6 +162,23 @@ OS << ")\n"; } +// Dynamically round a pointer up to a multiple of the given alignment. +static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF, + llvm::Value *Ptr, + CharUnits Align) { + llvm::Value *PtrAsInt = Ptr; + // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align; + PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy); + PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt, +llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1)); + PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt, + llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity())); + PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt, +Ptr->getType(), +Ptr->getName() + ".aligned"); + return PtrAsInt; +} + /// Emit va_arg for a platform using the common void* representation, /// where arguments are simply emitted in an array of slots on the stack. /// @@ -193,17 +210,10 @@ // If the CC aligns values higher than the slot size, do so if needed. Address Addr = Address::invalid(); if (AllowHigherAlign && DirectAlign > SlotSize) { -llvm::Value *PtrAsInt = Ptr; -PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy); -PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt, - llvm::ConstantInt::get(CGF.IntPtrTy, DirectAlign.getQuantity() - 1)); -PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt, - llvm::ConstantInt::get(CGF.IntPtrTy, -DirectAlign.getQuantity())); -Addr = Address(CGF.Builder.CreateIntToPtr(PtrAsInt, Ptr->getType(), - "argp.cur.aligned"), - DirectAlign); +Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign), + DirectAlign); } else { -Addr = Address(Ptr, SlotSize); +Addr = Address(Ptr, SlotSize); } // Advance the pointer past the argument, then store that back. @@ -3072,19 +3082,10 @@ // byte boundary if alignment needed by type exceeds 8 byte boundary. // It isn't stated explicitly in the standard, but in practice we use // alignment greater than 16 where necessary. - uint64_t Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity(); - if (Align > 8) { -// overflow_arg_area = (overflow_arg_area + align - 1) & -align; -llvm::Value *Offset = - llvm::ConstantInt::get(CGF.Int64Ty, Align - 1); -overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset); -llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(overflow_arg_area, -CGF.I
Re: [PATCH] D13351: [Power PC] add soft float support for ppc32
spetrovic updated this revision to Diff 41736. spetrovic marked 3 inline comments as done. http://reviews.llvm.org/D13351 Files: lib/CodeGen/TargetInfo.cpp lib/Driver/Tools.cpp lib/Driver/Tools.h test/CodeGen/ppc-sfvarargs.c test/Driver/ppc-features.cpp Index: test/Driver/ppc-features.cpp === --- test/Driver/ppc-features.cpp +++ test/Driver/ppc-features.cpp @@ -12,6 +12,50 @@ // RUN: not %clang -target mips64-linux-gnu -faltivec -fsyntax-only %s 2>&1 | FileCheck %s // RUN: not %clang -target sparc-unknown-solaris -faltivec -fsyntax-only %s 2>&1 | FileCheck %s +// check -msoft-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT %s +// CHECK-SOFTFLOAT: "-target-feature" "+soft-float" + +// check -mfloat-abi=soft option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=soft -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT %s +// CHECK-FLOATABISOFT: "-target-feature" "+soft-float" + +// check -mhard-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mhard-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-HARDFLOAT %s +// CHECK-HARDFLOAT-NOT: "-target-feature" "+soft-float" + +// check -mfloat-abi=hard option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=hard -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABIHARD %s +// CHECK-FLOATABIHARD-NOT: "-target-feature" "+soft-float" + +// check combine -mhard-float -msoft-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mhard-float -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-HARDSOFT %s +// CHECK-HARDSOFT: "-target-feature" "+soft-float" + +// check combine -msoft-float -mhard-float option for ppc32 +// RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -mhard-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTHARD %s +// CHECK-SOFTHARD-NOT: "-target-feature" "+soft-float" + +// check -mfloat-abi=x option +// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=x -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-ERRMSG %s +// CHECK-ERRMSG: clang: error: invalid float ABI '-mfloat-abi=x' + +// check -msoft-float option for ppc64 +// RUN: %clang -target powerpc64-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT64 %s +// CHECK-SOFTFLOAT64: clang: error: invalid float ABI 'soft float is not supported for ppc64' + +// check -mfloat-abi=soft option for ppc64 +// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mfloat-abi=soft -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT64 %s +// CHECK-FLOATABISOFT64: clang: error: invalid float ABI 'soft float is not supported for ppc64' + +// check -msoft-float option for ppc64 +// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT64le %s +// CHECK-SOFTFLOAT64le: clang: error: invalid float ABI 'soft float is not supported for ppc64' + +// check -mfloat-abi=soft option for ppc64 +// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -mfloat-abi=soft -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT64le %s +// CHECK-FLOATABISOFT64le: clang: error: invalid float ABI 'soft float is not supported for ppc64' + // CHECK: invalid argument '-faltivec' only allowed with 'ppc/ppc64/ppc64le' // Check that -fno-altivec and -mno-altivec correctly disable the altivec Index: test/CodeGen/ppc-sfvarargs.c === --- test/CodeGen/ppc-sfvarargs.c +++ test/CodeGen/ppc-sfvarargs.c @@ -0,0 +1,17 @@ +// RUN: %clang -O0 --target=powerpc-unknown-linux-gnu -EB -msoft-float -S -emit-llvm %s -o - | FileCheck %s + +#include +void test(char *fmt, ...) { + va_list ap; + va_start(ap, fmt); + va_arg(ap, double); + va_end(ap); +} + +void foo() { + double a; + test("test",a); +} +// CHECK: %{{[0-9]+}} = add i8 %numUsedRegs, 1 +// CHECK: %{{[0-9]+}} = and i8 %{{[0-9]+}}, -2 +// CHECK: %{{[0-9]+}} = mul i8 %{{[0-9]+}}, 4 \ No newline at end of file Index: lib/Driver/Tools.h === --- lib/Driver/Tools.h +++ lib/Driver/Tools.h @@ -742,6 +742,16 @@ FloatABI getARMFloatABI(const ToolChain &TC, const llvm::opt::ArgList &Args); } // end namespace arm +namespace ppc { +enum class FloatABI { + Invalid, + Soft, + Hard, +}; + +FloatABI getPPCFloatABI(const Driver &D, const llvm::opt::ArgList &Args); +} // end namespace ppc + namespace XCore { // For XCore, we do not need to instantiate tools for PreProcess, PreCompile and // Compile. Index: lib/Driver/Tools.cpp === --- lib/Driver/Tools.cpp +++ lib/Driver/Tools.cpp @@ -1411,7 +1411,8 @@ return ""; } -static vo
Re: [PATCH] D13351: [Power PC] add soft float support for ppc32
spetrovic added inline comments. Comment at: lib/Driver/Tools.cpp:1439 @@ -1437,1 +1438,3 @@ + ppc::FloatABI FloatABI = ppc::getPPCFloatABI(D, Args); + if (FloatABI == ppc::FloatABI::Soft && I'm planning to support soft float for ppc64. At this moment I don't know name of ppc64 hardware without FP unit. I know that gcc supports soft float for ppc64. http://reviews.llvm.org/D13351 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D13351: [Power PC] add soft float support for ppc32
spetrovic added a comment. ping http://reviews.llvm.org/D13351 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits