[clang] [compiler-rt] [XRay] Add support for instrumentation of DSOs on x86_64 (PR #90959)

2024-05-26 Thread Tomer Shafir via cfe-commits 

tomershafir wrote:

@sebastiankreutzer hey, were you able to reach the maintainers of llvm-xray and 
probe them about its dev status? If yes, can you pls share how to reach them 
and what did they say?

https://github.com/llvm/llvm-project/pull/90959
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[clang] [lld] [llvm] [AArch64] Fix stale +zcm target feature to +zcm-gpr64 (PR #146260)

2025-06-29 Thread Tomer Shafir via cfe-commits 


@@ -170,7 +170,7 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, 
StringRef Mtune,
   // 'cyclone' and later have zero-cycle register moves and zeroing.
   if (MtuneLowerCase == "cyclone" ||
   StringRef(MtuneLowerCase).starts_with("apple")) {
-Features.push_back("+zcm");
+Features.push_back("+zcm-gpr64");

tomershafir wrote:

Yes, I plan to fix that in a future patch. This is just a quick fix.

https://github.com/llvm/llvm-project/pull/146260
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[clang] [lld] [llvm] [Clang][AArch64] Remove redundant tune args to the backend (PR #146896)

2025-07-04 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir updated 
https://github.com/llvm/llvm-project/pull/146896

>From 10e9d8f141c0a31ecc189b3365d5d18c65c7ae4b Mon Sep 17 00:00:00 2001
From: tomershafir 
Date: Thu, 3 Jul 2025 16:53:26 +0300
Subject: [PATCH 1/2] [Clang][AArch64] Remove redundant tune args to the
 backend

This change removes unnecessary tune args to the AArch64 backend. The AArch64 
backend automatically handles `tune-cpu` and adds the necessary features based 
on the models from TableGen.

It follows this fix: https://github.com/llvm/llvm-project/pull/146260 where 
updating a subtarget feature didn't fail the frontend test because both the 
toolchain and the test suffered from a coordinated error.
---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 11 ---
 .../test/Preprocessor/aarch64-target-features.c  | 16 
 lld/test/MachO/icf-safe-thunks-dwarf.ll  |  4 ++--
 lld/test/MachO/icf-safe-thunks.ll|  4 ++--
 .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir |  2 +-
 .../AArch64/GlobalISel/inline-memmove.mir|  2 +-
 .../CodeGen/AArch64/GlobalISel/inline-memset.mir |  2 +-
 .../AArch64/lr-reserved-for-ra-live-in.ll|  2 +-
 llvm/test/CodeGen/AArch64/memsize-remarks.ll |  4 ++--
 llvm/test/DebugInfo/debug_frame_symbol.ll|  2 +-
 .../AddressSanitizer/calls-only-smallfn.ll   |  2 +-
 .../AddressSanitizer/calls-only.ll   |  2 +-
 .../Util/trivial-auto-var-init-crash-20210521.ll |  2 +-
 .../llvm-dwarfdump/AArch64/template_ref_ptr.ll   |  2 +-
 .../macho-gsym-callsite-info-obj.test|  6 +++---
 15 files changed, 26 insertions(+), 37 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 343a18b9ca2ea..4f45c369c83db 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -163,17 +163,6 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, 
StringRef Mtune,
   if (!DecodeAArch64Mcpu(D, MtuneLowerCase, Tune, Extensions))
 return false;
 
-  // Handle CPU name is 'native'.
-  if (MtuneLowerCase == "native")
-MtuneLowerCase = std::string(llvm::sys::getHostCPUName());
-
-  // 'cyclone' and later have zero-cycle register moves and zeroing.
-  if (MtuneLowerCase == "cyclone" ||
-  StringRef(MtuneLowerCase).starts_with("apple")) {
-Features.push_back("+zcm-gpr64");
-Features.push_back("+zcz");
-  }
-
   return true;
 }
 
diff --git a/clang/test/Preprocessor/aarch64-target-features.c 
b/clang/test/Preprocessor/aarch64-target-features.c
index 6700153b79795..d7201207db572 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -316,7 +316,7 @@
 
 // == Check whether -mtune accepts mixed-case features.
 // RUN: %clang -target aarch64 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MTUNE-CYCLONE %s
-// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" "+v8a"
+// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a"
 
 // RUN: %clang -target aarch64 -mcpu=apple-a7 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
@@ -342,12 +342,12 @@
 // RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-THUNDERX2T99 %s
 // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-A64FX %s
 // RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-CARMEL %s
-// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" 
"+fp-armv8" "-target-feature" "+lor" "-target-feature" "+neon" 
"-target-feature" "+pan" "-target-feature" "+perfmon" "-target-feature" "+rdm" 
"-target-feature" "+sha2" "-target-feature" "+vh"
-// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" 
"aarch64{{.*}}"{{.*}}"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" 
"-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" 
"-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" 
"+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" 
"+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} 
"-target-feature" "+z

[clang] [lld] [llvm] [Clang][AArch64] Remove redundant tune args to the backend (PR #146896)

2025-07-03 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir updated 
https://github.com/llvm/llvm-project/pull/146896

>From 10e9d8f141c0a31ecc189b3365d5d18c65c7ae4b Mon Sep 17 00:00:00 2001
From: tomershafir 
Date: Thu, 3 Jul 2025 16:53:26 +0300
Subject: [PATCH] [Clang][AArch64] Remove redundant tune args to the backend

This change removes unnecessary tune args to the AArch64 backend. The AArch64 
backend automatically handles `tune-cpu` and adds the necessary features based 
on the models from TableGen.

It follows this fix: https://github.com/llvm/llvm-project/pull/146260 where 
updating a subtarget feature didn't fail the frontend test because both the 
toolchain and the test suffered from a coordinated error.
---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 11 ---
 .../test/Preprocessor/aarch64-target-features.c  | 16 
 lld/test/MachO/icf-safe-thunks-dwarf.ll  |  4 ++--
 lld/test/MachO/icf-safe-thunks.ll|  4 ++--
 .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir |  2 +-
 .../AArch64/GlobalISel/inline-memmove.mir|  2 +-
 .../CodeGen/AArch64/GlobalISel/inline-memset.mir |  2 +-
 .../AArch64/lr-reserved-for-ra-live-in.ll|  2 +-
 llvm/test/CodeGen/AArch64/memsize-remarks.ll |  4 ++--
 llvm/test/DebugInfo/debug_frame_symbol.ll|  2 +-
 .../AddressSanitizer/calls-only-smallfn.ll   |  2 +-
 .../AddressSanitizer/calls-only.ll   |  2 +-
 .../Util/trivial-auto-var-init-crash-20210521.ll |  2 +-
 .../llvm-dwarfdump/AArch64/template_ref_ptr.ll   |  2 +-
 .../macho-gsym-callsite-info-obj.test|  6 +++---
 15 files changed, 26 insertions(+), 37 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 343a18b9ca2ea..4f45c369c83db 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -163,17 +163,6 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, 
StringRef Mtune,
   if (!DecodeAArch64Mcpu(D, MtuneLowerCase, Tune, Extensions))
 return false;
 
-  // Handle CPU name is 'native'.
-  if (MtuneLowerCase == "native")
-MtuneLowerCase = std::string(llvm::sys::getHostCPUName());
-
-  // 'cyclone' and later have zero-cycle register moves and zeroing.
-  if (MtuneLowerCase == "cyclone" ||
-  StringRef(MtuneLowerCase).starts_with("apple")) {
-Features.push_back("+zcm-gpr64");
-Features.push_back("+zcz");
-  }
-
   return true;
 }
 
diff --git a/clang/test/Preprocessor/aarch64-target-features.c 
b/clang/test/Preprocessor/aarch64-target-features.c
index 6700153b79795..d7201207db572 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -316,7 +316,7 @@
 
 // == Check whether -mtune accepts mixed-case features.
 // RUN: %clang -target aarch64 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MTUNE-CYCLONE %s
-// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" "+v8a"
+// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a"
 
 // RUN: %clang -target aarch64 -mcpu=apple-a7 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
@@ -342,12 +342,12 @@
 // RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-THUNDERX2T99 %s
 // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-A64FX %s
 // RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-CARMEL %s
-// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" 
"+fp-armv8" "-target-feature" "+lor" "-target-feature" "+neon" 
"-target-feature" "+pan" "-target-feature" "+perfmon" "-target-feature" "+rdm" 
"-target-feature" "+sha2" "-target-feature" "+vh"
-// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" 
"aarch64{{.*}}"{{.*}}"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" 
"-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" 
"-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" 
"+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" 
"+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} 
"-target-feature" "+zcm-gp

[clang] [Clang][AArch64] Remove redundant tune args to the backend (PR #146896)

2025-07-03 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir updated 
https://github.com/llvm/llvm-project/pull/146896

>From 81792060d3229148df45ea70b23a24d5cbef4a36 Mon Sep 17 00:00:00 2001
From: tomershafir 
Date: Thu, 3 Jul 2025 16:53:26 +0300
Subject: [PATCH] [Clang][AArch64] Remove redundant tune args to the backend

This change removes unnecessary tune args to the AArch64 backend. The AArch64 
backend automatically handles `tune-cpu` and adds the necessary features based 
on the models from TableGen.

It follows this fix: https://github.com/llvm/llvm-project/pull/146260 where 
updating a subtarget feature didn't fail the frontend test because both the 
toolchain and the test suffered from a coordinated error.
---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 11 ---
 .../test/Preprocessor/aarch64-target-features.c  | 16 
 2 files changed, 8 insertions(+), 19 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 343a18b9ca2ea..4f45c369c83db 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -163,17 +163,6 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, 
StringRef Mtune,
   if (!DecodeAArch64Mcpu(D, MtuneLowerCase, Tune, Extensions))
 return false;
 
-  // Handle CPU name is 'native'.
-  if (MtuneLowerCase == "native")
-MtuneLowerCase = std::string(llvm::sys::getHostCPUName());
-
-  // 'cyclone' and later have zero-cycle register moves and zeroing.
-  if (MtuneLowerCase == "cyclone" ||
-  StringRef(MtuneLowerCase).starts_with("apple")) {
-Features.push_back("+zcm-gpr64");
-Features.push_back("+zcz");
-  }
-
   return true;
 }
 
diff --git a/clang/test/Preprocessor/aarch64-target-features.c 
b/clang/test/Preprocessor/aarch64-target-features.c
index 6700153b79795..d7201207db572 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -316,7 +316,7 @@
 
 // == Check whether -mtune accepts mixed-case features.
 // RUN: %clang -target aarch64 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MTUNE-CYCLONE %s
-// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" "+v8a"
+// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a"
 
 // RUN: %clang -target aarch64 -mcpu=apple-a7 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
@@ -342,12 +342,12 @@
 // RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-THUNDERX2T99 %s
 // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-A64FX %s
 // RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-CARMEL %s
-// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" 
"+fp-armv8" "-target-feature" "+lor" "-target-feature" "+neon" 
"-target-feature" "+pan" "-target-feature" "+perfmon" "-target-feature" "+rdm" 
"-target-feature" "+sha2" "-target-feature" "+vh"
-// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" 
"aarch64{{.*}}"{{.*}}"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" 
"-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" 
"-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" 
"+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" 
"+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8.3a" "-target-feature" "+aes" "-target-feature" "+complxnum" 
"-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" 
"+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" 
"-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" 
"+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" 
"+rdm" "-target-feature" "+sha2"
+// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" 
"-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
+// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a" "-targe

[clang] [Clang][AArch64] Remove redundant tune args to the backend (PR #146896)

2025-07-03 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir edited 
https://github.com/llvm/llvm-project/pull/146896
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[clang] [lld] [llvm] [Clang][AArch64] Remove redundant tune args to the backend (PR #146896)

2025-07-04 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir updated 
https://github.com/llvm/llvm-project/pull/146896

>From 10e9d8f141c0a31ecc189b3365d5d18c65c7ae4b Mon Sep 17 00:00:00 2001
From: tomershafir 
Date: Thu, 3 Jul 2025 16:53:26 +0300
Subject: [PATCH 1/2] [Clang][AArch64] Remove redundant tune args to the
 backend

This change removes unnecessary tune args to the AArch64 backend. The AArch64 
backend automatically handles `tune-cpu` and adds the necessary features based 
on the models from TableGen.

It follows this fix: https://github.com/llvm/llvm-project/pull/146260 where 
updating a subtarget feature didn't fail the frontend test because both the 
toolchain and the test suffered from a coordinated error.
---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 11 ---
 .../test/Preprocessor/aarch64-target-features.c  | 16 
 lld/test/MachO/icf-safe-thunks-dwarf.ll  |  4 ++--
 lld/test/MachO/icf-safe-thunks.ll|  4 ++--
 .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir |  2 +-
 .../AArch64/GlobalISel/inline-memmove.mir|  2 +-
 .../CodeGen/AArch64/GlobalISel/inline-memset.mir |  2 +-
 .../AArch64/lr-reserved-for-ra-live-in.ll|  2 +-
 llvm/test/CodeGen/AArch64/memsize-remarks.ll |  4 ++--
 llvm/test/DebugInfo/debug_frame_symbol.ll|  2 +-
 .../AddressSanitizer/calls-only-smallfn.ll   |  2 +-
 .../AddressSanitizer/calls-only.ll   |  2 +-
 .../Util/trivial-auto-var-init-crash-20210521.ll |  2 +-
 .../llvm-dwarfdump/AArch64/template_ref_ptr.ll   |  2 +-
 .../macho-gsym-callsite-info-obj.test|  6 +++---
 15 files changed, 26 insertions(+), 37 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 343a18b9ca2ea..4f45c369c83db 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -163,17 +163,6 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, 
StringRef Mtune,
   if (!DecodeAArch64Mcpu(D, MtuneLowerCase, Tune, Extensions))
 return false;
 
-  // Handle CPU name is 'native'.
-  if (MtuneLowerCase == "native")
-MtuneLowerCase = std::string(llvm::sys::getHostCPUName());
-
-  // 'cyclone' and later have zero-cycle register moves and zeroing.
-  if (MtuneLowerCase == "cyclone" ||
-  StringRef(MtuneLowerCase).starts_with("apple")) {
-Features.push_back("+zcm-gpr64");
-Features.push_back("+zcz");
-  }
-
   return true;
 }
 
diff --git a/clang/test/Preprocessor/aarch64-target-features.c 
b/clang/test/Preprocessor/aarch64-target-features.c
index 6700153b79795..d7201207db572 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -316,7 +316,7 @@
 
 // == Check whether -mtune accepts mixed-case features.
 // RUN: %clang -target aarch64 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MTUNE-CYCLONE %s
-// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" "+v8a"
+// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a"
 
 // RUN: %clang -target aarch64 -mcpu=apple-a7 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
@@ -342,12 +342,12 @@
 // RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-THUNDERX2T99 %s
 // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-A64FX %s
 // RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-CARMEL %s
-// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" 
"+fp-armv8" "-target-feature" "+lor" "-target-feature" "+neon" 
"-target-feature" "+pan" "-target-feature" "+perfmon" "-target-feature" "+rdm" 
"-target-feature" "+sha2" "-target-feature" "+vh"
-// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" 
"aarch64{{.*}}"{{.*}}"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" 
"-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" 
"-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" 
"+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" 
"+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} 
"-target-feature" "+z

[clang] [lld] [llvm] [Clang][AArch64] Remove redundant tune args to the backend (PR #146896)

2025-07-04 Thread Tomer Shafir via cfe-commits 


@@ -163,17 +163,6 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, 
StringRef Mtune,
   if (!DecodeAArch64Mcpu(D, MtuneLowerCase, Tune, Extensions))
 return false;
 

tomershafir wrote:

ok, I planned to simplify in a followup patch, but simplified this and a bit 
more in a new commit

https://github.com/llvm/llvm-project/pull/146896
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[clang] [lld] [llvm] [Clang][AArch64] Remove redundant tune args to the backend (PR #146896)

2025-07-04 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir updated 
https://github.com/llvm/llvm-project/pull/146896

>From 10e9d8f141c0a31ecc189b3365d5d18c65c7ae4b Mon Sep 17 00:00:00 2001
From: tomershafir 
Date: Thu, 3 Jul 2025 16:53:26 +0300
Subject: [PATCH 1/2] [Clang][AArch64] Remove redundant tune args to the
 backend

This change removes unnecessary tune args to the AArch64 backend. The AArch64 
backend automatically handles `tune-cpu` and adds the necessary features based 
on the models from TableGen.

It follows this fix: https://github.com/llvm/llvm-project/pull/146260 where 
updating a subtarget feature didn't fail the frontend test because both the 
toolchain and the test suffered from a coordinated error.
---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 11 ---
 .../test/Preprocessor/aarch64-target-features.c  | 16 
 lld/test/MachO/icf-safe-thunks-dwarf.ll  |  4 ++--
 lld/test/MachO/icf-safe-thunks.ll|  4 ++--
 .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir |  2 +-
 .../AArch64/GlobalISel/inline-memmove.mir|  2 +-
 .../CodeGen/AArch64/GlobalISel/inline-memset.mir |  2 +-
 .../AArch64/lr-reserved-for-ra-live-in.ll|  2 +-
 llvm/test/CodeGen/AArch64/memsize-remarks.ll |  4 ++--
 llvm/test/DebugInfo/debug_frame_symbol.ll|  2 +-
 .../AddressSanitizer/calls-only-smallfn.ll   |  2 +-
 .../AddressSanitizer/calls-only.ll   |  2 +-
 .../Util/trivial-auto-var-init-crash-20210521.ll |  2 +-
 .../llvm-dwarfdump/AArch64/template_ref_ptr.ll   |  2 +-
 .../macho-gsym-callsite-info-obj.test|  6 +++---
 15 files changed, 26 insertions(+), 37 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 343a18b9ca2ea..4f45c369c83db 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -163,17 +163,6 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, 
StringRef Mtune,
   if (!DecodeAArch64Mcpu(D, MtuneLowerCase, Tune, Extensions))
 return false;
 
-  // Handle CPU name is 'native'.
-  if (MtuneLowerCase == "native")
-MtuneLowerCase = std::string(llvm::sys::getHostCPUName());
-
-  // 'cyclone' and later have zero-cycle register moves and zeroing.
-  if (MtuneLowerCase == "cyclone" ||
-  StringRef(MtuneLowerCase).starts_with("apple")) {
-Features.push_back("+zcm-gpr64");
-Features.push_back("+zcz");
-  }
-
   return true;
 }
 
diff --git a/clang/test/Preprocessor/aarch64-target-features.c 
b/clang/test/Preprocessor/aarch64-target-features.c
index 6700153b79795..d7201207db572 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -316,7 +316,7 @@
 
 // == Check whether -mtune accepts mixed-case features.
 // RUN: %clang -target aarch64 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MTUNE-CYCLONE %s
-// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" "+v8a"
+// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a"
 
 // RUN: %clang -target aarch64 -mcpu=apple-a7 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
@@ -342,12 +342,12 @@
 // RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-THUNDERX2T99 %s
 // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-A64FX %s
 // RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-CARMEL %s
-// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" 
"+fp-armv8" "-target-feature" "+lor" "-target-feature" "+neon" 
"-target-feature" "+pan" "-target-feature" "+perfmon" "-target-feature" "+rdm" 
"-target-feature" "+sha2" "-target-feature" "+vh"
-// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" 
"aarch64{{.*}}"{{.*}}"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" 
"-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" 
"-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" 
"+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" 
"+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} 
"-target-feature" "+z

[clang] [lld] [llvm] [Clang][AArch64] Remove redundant tune args to the backend (PR #146896)

2025-07-04 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir updated 
https://github.com/llvm/llvm-project/pull/146896

>From 10e9d8f141c0a31ecc189b3365d5d18c65c7ae4b Mon Sep 17 00:00:00 2001
From: tomershafir 
Date: Thu, 3 Jul 2025 16:53:26 +0300
Subject: [PATCH 1/2] [Clang][AArch64] Remove redundant tune args to the
 backend

This change removes unnecessary tune args to the AArch64 backend. The AArch64 
backend automatically handles `tune-cpu` and adds the necessary features based 
on the models from TableGen.

It follows this fix: https://github.com/llvm/llvm-project/pull/146260 where 
updating a subtarget feature didn't fail the frontend test because both the 
toolchain and the test suffered from a coordinated error.
---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 11 ---
 .../test/Preprocessor/aarch64-target-features.c  | 16 
 lld/test/MachO/icf-safe-thunks-dwarf.ll  |  4 ++--
 lld/test/MachO/icf-safe-thunks.ll|  4 ++--
 .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir |  2 +-
 .../AArch64/GlobalISel/inline-memmove.mir|  2 +-
 .../CodeGen/AArch64/GlobalISel/inline-memset.mir |  2 +-
 .../AArch64/lr-reserved-for-ra-live-in.ll|  2 +-
 llvm/test/CodeGen/AArch64/memsize-remarks.ll |  4 ++--
 llvm/test/DebugInfo/debug_frame_symbol.ll|  2 +-
 .../AddressSanitizer/calls-only-smallfn.ll   |  2 +-
 .../AddressSanitizer/calls-only.ll   |  2 +-
 .../Util/trivial-auto-var-init-crash-20210521.ll |  2 +-
 .../llvm-dwarfdump/AArch64/template_ref_ptr.ll   |  2 +-
 .../macho-gsym-callsite-info-obj.test|  6 +++---
 15 files changed, 26 insertions(+), 37 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 343a18b9ca2ea..4f45c369c83db 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -163,17 +163,6 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, 
StringRef Mtune,
   if (!DecodeAArch64Mcpu(D, MtuneLowerCase, Tune, Extensions))
 return false;
 
-  // Handle CPU name is 'native'.
-  if (MtuneLowerCase == "native")
-MtuneLowerCase = std::string(llvm::sys::getHostCPUName());
-
-  // 'cyclone' and later have zero-cycle register moves and zeroing.
-  if (MtuneLowerCase == "cyclone" ||
-  StringRef(MtuneLowerCase).starts_with("apple")) {
-Features.push_back("+zcm-gpr64");
-Features.push_back("+zcz");
-  }
-
   return true;
 }
 
diff --git a/clang/test/Preprocessor/aarch64-target-features.c 
b/clang/test/Preprocessor/aarch64-target-features.c
index 6700153b79795..d7201207db572 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -316,7 +316,7 @@
 
 // == Check whether -mtune accepts mixed-case features.
 // RUN: %clang -target aarch64 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MTUNE-CYCLONE %s
-// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" "+v8a"
+// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a"
 
 // RUN: %clang -target aarch64 -mcpu=apple-a7 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
@@ -342,12 +342,12 @@
 // RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-THUNDERX2T99 %s
 // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-A64FX %s
 // RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-CARMEL %s
-// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" 
"+fp-armv8" "-target-feature" "+lor" "-target-feature" "+neon" 
"-target-feature" "+pan" "-target-feature" "+perfmon" "-target-feature" "+rdm" 
"-target-feature" "+sha2" "-target-feature" "+vh"
-// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" 
"aarch64{{.*}}"{{.*}}"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" 
"-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" 
"-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" 
"+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" 
"+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} 
"-target-feature" "+z

[clang] [Clang][AArch64] Remove redundant tune args to the backend (PR #146896)

2025-07-03 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir ready_for_review 
https://github.com/llvm/llvm-project/pull/146896
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[clang] [Clang][AArch64] Remove redundant tune args to the backend (PR #146896)

2025-07-03 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir created 
https://github.com/llvm/llvm-project/pull/146896

This change removes unnecessary tune args to the AArch64 backend. The AArch64 
backend automatically handles `tune-cpu` and adds the necessary features based 
on the models from TableGen.

>From 47da7044807f139512c04b3f3ad3ef6634d49a44 Mon Sep 17 00:00:00 2001
From: tomershafir 
Date: Thu, 3 Jul 2025 16:53:26 +0300
Subject: [PATCH] [Clang][AArch64] Remove redundant tune args to the backend

This change removes unnecessary tune args to the AArch64 backend. The AArch64 
backend automatically handles `tune-cpu` and adds the necessary features based 
on the models from TableGen.
---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 11 ---
 .../test/Preprocessor/aarch64-target-features.c  | 16 
 2 files changed, 8 insertions(+), 19 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 343a18b9ca2ea..4f45c369c83db 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -163,17 +163,6 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, 
StringRef Mtune,
   if (!DecodeAArch64Mcpu(D, MtuneLowerCase, Tune, Extensions))
 return false;
 
-  // Handle CPU name is 'native'.
-  if (MtuneLowerCase == "native")
-MtuneLowerCase = std::string(llvm::sys::getHostCPUName());
-
-  // 'cyclone' and later have zero-cycle register moves and zeroing.
-  if (MtuneLowerCase == "cyclone" ||
-  StringRef(MtuneLowerCase).starts_with("apple")) {
-Features.push_back("+zcm-gpr64");
-Features.push_back("+zcz");
-  }
-
   return true;
 }
 
diff --git a/clang/test/Preprocessor/aarch64-target-features.c 
b/clang/test/Preprocessor/aarch64-target-features.c
index 6700153b79795..f45f3e74d690f 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -316,7 +316,7 @@
 
 // == Check whether -mtune accepts mixed-case features.
 // RUN: %clang -target aarch64 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MTUNE-CYCLONE %s
-// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" "+v8a"
+// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a"
 
 // RUN: %clang -target aarch64 -mcpu=apple-a7 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
@@ -342,12 +342,12 @@
 // RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-THUNDERX2T99 %s
 // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-A64FX %s
 // RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-CARMEL %s
-// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" 
"+fp-armv8" "-target-feature" "+lor" "-target-feature" "+neon" 
"-target-feature" "+pan" "-target-feature" "+perfmon" "-target-feature" "+rdm" 
"-target-feature" "+sha2" "-target-feature" "+vh"
-// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" 
"aarch64{{.*}}"{{.*}}"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" 
"-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" 
"-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" 
"+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" 
"+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" 
"+v8.3a" "-target-feature" "+aes" "-target-feature" "+complxnum" 
"-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" 
"+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" 
"-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" 
"+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" 
"+rdm" "-target-feature" "+sha2"
+// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" 
"-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
+// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a" "-target-feature" "+aes" "-targ

[clang] [lld] [llvm] [Clang][AArch64] Remove redundant tune args to the backend (PR #146896)

2025-07-04 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir closed 
https://github.com/llvm/llvm-project/pull/146896
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[clang] [lld] [llvm] [AArch64] Fix stale +zcm target feature to +zcm-gpr64 (PR #146260)

2025-06-29 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir updated 
https://github.com/llvm/llvm-project/pull/146260

>From 91c9e0832a72f8ed9198b644b677f0e93a557d89 Mon Sep 17 00:00:00 2001
From: tomershafir 
Date: Sun, 29 Jun 2025 10:17:47 +0300
Subject: [PATCH] [AArch64] Fix stale +zcm target feature to +zcm-gpr64

Replaces all the uses of `+zcm` with `+zcm-gpr64`. A fix for: 
https://github.com/llvm/llvm-project/pull/146051
---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp |  2 +-
 .../test/Preprocessor/aarch64-target-features.c  | 16 
 lld/test/MachO/icf-safe-thunks-dwarf.ll  |  4 ++--
 lld/test/MachO/icf-safe-thunks.ll|  4 ++--
 .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir |  2 +-
 .../AArch64/GlobalISel/inline-memmove.mir|  2 +-
 .../CodeGen/AArch64/GlobalISel/inline-memset.mir |  2 +-
 .../AArch64/lr-reserved-for-ra-live-in.ll|  2 +-
 llvm/test/CodeGen/AArch64/memsize-remarks.ll |  4 ++--
 llvm/test/DebugInfo/debug_frame_symbol.ll|  2 +-
 .../AddressSanitizer/calls-only-smallfn.ll   |  2 +-
 .../AddressSanitizer/calls-only.ll   |  2 +-
 .../Util/trivial-auto-var-init-crash-20210521.ll |  2 +-
 .../llvm-dwarfdump/AArch64/template_ref_ptr.ll   |  2 +-
 .../macho-gsym-callsite-info-obj.test|  6 +++---
 15 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index ea906d2e2acfc..343a18b9ca2ea 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -170,7 +170,7 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, 
StringRef Mtune,
   // 'cyclone' and later have zero-cycle register moves and zeroing.
   if (MtuneLowerCase == "cyclone" ||
   StringRef(MtuneLowerCase).starts_with("apple")) {
-Features.push_back("+zcm");
+Features.push_back("+zcm-gpr64");
 Features.push_back("+zcz");
   }
 
diff --git a/clang/test/Preprocessor/aarch64-target-features.c 
b/clang/test/Preprocessor/aarch64-target-features.c
index fd83e4b689a2a..6700153b79795 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -316,7 +316,7 @@
 
 // == Check whether -mtune accepts mixed-case features.
 // RUN: %clang -target aarch64 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MTUNE-CYCLONE %s
-// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a"
+// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" "+v8a"
 
 // RUN: %clang -target aarch64 -mcpu=apple-a7 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
@@ -342,12 +342,12 @@
 // RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-THUNDERX2T99 %s
 // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-A64FX %s
 // RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-CARMEL %s
-// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" 
"-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" 
"-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" 
"-target-feature" "+lor" "-target-feature" "+neon" "-target-feature" "+pan" 
"-target-feature" "+perfmon" "-target-feature" "+rdm" "-target-feature" "+sha2" 
"-target-feature" "+vh"
-// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" 
"aarch64{{.*}}"{{.*}}"-target-feature" "+zcm" "-target-feature" "+zcz" 
"-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" 
"-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" 
"+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" 
"+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} 
"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" 
"-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" 
"+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" 
"-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" 
"-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" 
"+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" 
"+sha2"
+// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-tripl

[clang] [lld] [llvm] [AArch64] Fix stale +zcm target feature to +zcm-gpr64 (PR #146260)

2025-06-29 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir created 
https://github.com/llvm/llvm-project/pull/146260

Replaces all the uses of `+zcm` with `+zcm-gpr64`.

>From f7ba61ad76cf956d642aa36a98288ab0df3c56d8 Mon Sep 17 00:00:00 2001
From: tomershafir 
Date: Sun, 29 Jun 2025 10:17:47 +0300
Subject: [PATCH] [AArch64] Fix stale +zcm target feature to +zcm-gpr64

Replaces all the uses of `+zcm` with `+zcm-gpr64`.
---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp |  2 +-
 .../test/Preprocessor/aarch64-target-features.c  | 16 
 lld/test/MachO/icf-safe-thunks-dwarf.ll  |  4 ++--
 lld/test/MachO/icf-safe-thunks.ll|  4 ++--
 .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir |  2 +-
 .../AArch64/GlobalISel/inline-memmove.mir|  2 +-
 .../CodeGen/AArch64/GlobalISel/inline-memset.mir |  2 +-
 .../AArch64/lr-reserved-for-ra-live-in.ll|  2 +-
 llvm/test/CodeGen/AArch64/memsize-remarks.ll |  4 ++--
 llvm/test/DebugInfo/debug_frame_symbol.ll|  2 +-
 .../AddressSanitizer/calls-only-smallfn.ll   |  2 +-
 .../AddressSanitizer/calls-only.ll   |  2 +-
 .../Util/trivial-auto-var-init-crash-20210521.ll |  2 +-
 .../llvm-dwarfdump/AArch64/template_ref_ptr.ll   |  2 +-
 .../macho-gsym-callsite-info-obj.test|  6 +++---
 15 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index ea906d2e2acfc..343a18b9ca2ea 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -170,7 +170,7 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, 
StringRef Mtune,
   // 'cyclone' and later have zero-cycle register moves and zeroing.
   if (MtuneLowerCase == "cyclone" ||
   StringRef(MtuneLowerCase).starts_with("apple")) {
-Features.push_back("+zcm");
+Features.push_back("+zcm-gpr64");
 Features.push_back("+zcz");
   }
 
diff --git a/clang/test/Preprocessor/aarch64-target-features.c 
b/clang/test/Preprocessor/aarch64-target-features.c
index fd83e4b689a2a..6700153b79795 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -316,7 +316,7 @@
 
 // == Check whether -mtune accepts mixed-case features.
 // RUN: %clang -target aarch64 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MTUNE-CYCLONE %s
-// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a"
+// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm-gpr64" "-target-feature" "+zcz" "-target-feature" "+v8a"
 
 // RUN: %clang -target aarch64 -mcpu=apple-a7 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-APPLE-A7 %s
@@ -342,12 +342,12 @@
 // RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-THUNDERX2T99 %s
 // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-A64FX %s
 // RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MCPU-CARMEL %s
-// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" 
"-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" 
"-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" 
"-target-feature" "+lor" "-target-feature" "+neon" "-target-feature" "+pan" 
"-target-feature" "+perfmon" "-target-feature" "+rdm" "-target-feature" "+sha2" 
"-target-feature" "+vh"
-// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" 
"aarch64{{.*}}"{{.*}}"-target-feature" "+zcm" "-target-feature" "+zcz" 
"-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" 
"-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" 
"+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" 
"+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} 
"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" 
"-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" 
"+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" 
"-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" 
"-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" 
"+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" 
"+sha2"
+// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch

[clang] [lld] [llvm] [AArch64] Fix stale +zcm target feature to +zcm-gpr64 (PR #146260)

2025-06-29 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir ready_for_review 
https://github.com/llvm/llvm-project/pull/146260
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[clang] [lld] [llvm] [AArch64] Fix stale +zcm target feature to +zcm-gpr64 (PR #146260)

2025-06-29 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir edited 
https://github.com/llvm/llvm-project/pull/146260
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[clang] [lld] [llvm] [AArch64] Fix stale +zcm target feature to +zcm-gpr64 (PR #146260)

2025-06-29 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir closed 
https://github.com/llvm/llvm-project/pull/146260
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[clang] [Clang][Docs] Fix typo in clang.rst (PR #150907)

2025-07-28 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir created 
https://github.com/llvm/llvm-project/pull/150907

None

>From 4a749285d6c5315fc0f867bc36a7b362f9cc930e Mon Sep 17 00:00:00 2001
From: tomershafir 
Date: Mon, 28 Jul 2025 12:13:40 +0300
Subject: [PATCH] [Clang][Docs] Fix typo in clang.rst

---
 clang/docs/CommandGuide/clang.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/docs/CommandGuide/clang.rst 
b/clang/docs/CommandGuide/clang.rst
index 7d49f2cc28a10..4c1f8e47ce381 100644
--- a/clang/docs/CommandGuide/clang.rst
+++ b/clang/docs/CommandGuide/clang.rst
@@ -645,7 +645,7 @@ Driver Options
 
   Save internal code generation (LLVM) statistics to a file in the current
   directory (:option:`-save-stats`/"-save-stats=cwd") or the directory
-  of the output file ("-save-state=obj").
+  of the output file ("-save-stats=obj").
 
   You can also use environment variables to control the statistics reporting.
   Setting ``CC_PRINT_INTERNAL_STAT`` to ``1`` enables the feature, the report

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[clang] [Clang][Docs] Fix typo in clang.rst (PR #150907)

2025-07-28 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir ready_for_review 
https://github.com/llvm/llvm-project/pull/150907
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[clang] [Clang][Docs] Fix typo in clang.rst (PR #150907)

2025-07-28 Thread Tomer Shafir via cfe-commits 

https://github.com/tomershafir updated 
https://github.com/llvm/llvm-project/pull/150907

>From edcd628f469296fa1754f94767eacfe51c3131d9 Mon Sep 17 00:00:00 2001
From: tomershafir 
Date: Mon, 28 Jul 2025 12:13:40 +0300
Subject: [PATCH] [Clang][Docs] Fix typo in clang.rst

---
 clang/docs/CommandGuide/clang.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/docs/CommandGuide/clang.rst 
b/clang/docs/CommandGuide/clang.rst
index 7d49f2cc28a10..4c1f8e47ce381 100644
--- a/clang/docs/CommandGuide/clang.rst
+++ b/clang/docs/CommandGuide/clang.rst
@@ -645,7 +645,7 @@ Driver Options
 
   Save internal code generation (LLVM) statistics to a file in the current
   directory (:option:`-save-stats`/"-save-stats=cwd") or the directory
-  of the output file ("-save-state=obj").
+  of the output file ("-save-stats=obj").
 
   You can also use environment variables to control the statistics reporting.
   Setting ``CC_PRINT_INTERNAL_STAT`` to ``1`` enables the feature, the report

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