Role : ASIC Verification Engineer
Hi, Role : ASIC Verification Engineer Location: Cleveland, OH, USA Duration : 6+ Months Must: (ITA level or below only), - Min. 4 yrs, max 7 yrs experience with atleast 1 full chip formal verification projects on functional Logical Equivalance Checking at different levels of comparision. - Good experience in functional LEC design equivalence checking (RTL vs Pre-Routed Netlist, Pre-Routed Netlist vs Post Routed Netlist, Netlist Vs ECO-Netlist, with power aware and no power etc..) -Knowledge on physical design, Synthesis & Timing Closure - Excellent scripting skills (TCL,Perl,Shell,Bash,dofile, Makefile,run,etc...) - Good documentation, communcation skills Preferred: - Proficiency using Cadence Conformal LEC Analysis Tool (RTL to gates w/o power, RTL to gate w/ power, and gates to gates) - Development of Scripts for functional LEC flow and report analysis. - Should have good understanding of VHDL/Verilog/System Verilog code *Saurabh Sharma* SAP AND IT CONSULTING SERVICES 4606 FM 1960 Rd W, Suite 400 Houston, Texas-77069 T: 281 954 5503 | (855) 647-8754 EXT 702 Email: saur...@e-infionics.com <raj...@e-infionics.com> | saurabhsysmind...@gmail.com Web: www.e-infionics.com -- You received this message because you are subscribed to the Google Groups "Citrix and Sap problems" group. To unsubscribe from this group and stop receiving emails from it, send an email to citrix-and-sap-problems+unsubscr...@googlegroups.com. To post to this group, send email to citrix-and-sap-problems@googlegroups.com. Visit this group at https://groups.google.com/group/citrix-and-sap-problems. For more options, visit https://groups.google.com/d/optout.
Role : ASIC Verification Engineer
Hi, Role : ASIC Verification Engineer Location: Cleveland, OH, USA Duration : 6+ Months Must: (ITA level or below only), - Min. 4 yrs, max 7 yrs experience with atleast 1 full chip formal verification projects on functional Logical Equivalance Checking at different levels of comparision. - Good experience in functional LEC design equivalence checking (RTL vs Pre-Routed Netlist, Pre-Routed Netlist vs Post Routed Netlist, Netlist Vs ECO-Netlist, with power aware and no power etc..) -Knowledge on physical design, Synthesis & Timing Closure - Excellent scripting skills (TCL,Perl,Shell,Bash,dofile, Makefile,run,etc...) - Good documentation, communcation skills Preferred: - Proficiency using Cadence Conformal LEC Analysis Tool (RTL to gates w/o power, RTL to gate w/ power, and gates to gates) - Development of Scripts for functional LEC flow and report analysis. - Should have good understanding of VHDL/Verilog/System Verilog code *Saurabh Sharma* SAP AND IT CONSULTING SERVICES 4606 FM 1960 Rd W, Suite 400 Houston, Texas-77069 T: 281 954 5503 | (855) 647-8754 EXT 702 Email: saur...@e-infionics.com <raj...@e-infionics.com> | saurabhsysmind...@gmail.com Web: www.e-infionics.com -- You received this message because you are subscribed to the Google Groups "Citrix and Sap problems" group. To unsubscribe from this group and stop receiving emails from it, send an email to citrix-and-sap-problems+unsubscr...@googlegroups.com. To post to this group, send email to citrix-and-sap-problems@googlegroups.com. Visit this group at https://groups.google.com/group/citrix-and-sap-problems. For more options, visit https://groups.google.com/d/optout.
