Re: [coreboot] Ram Init: Intel i945: Timing parameters
Mohit Gupta wrote: > wondering how coreboot team was able to write i945 ram init? The code was written by individuals who had limited access to Intel documents and source code under NDA. Those individuals can not tutor you in the i945 MCH or in DDR2 technology. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram Init: Intel i945: Timing parameters
Thanks Vald … not possible to break intel safe .. wondering how coreboot team was able to write i945 ram init? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram Init: Intel i945: Timing parameters
Thanks Vald … not possible to break intel safe .. wondering how coreboot team was able to write i945 ram init? Regards Mohit Gupta On Friday, 14 February 2014 10:39 AM, Vladimir 'φ-coder/phcoder' Serbinenko wrote: On 14.02.2014 00:03, Mohit Gupta wrote: >> I am having trouble understanding i945 ram init code especially timing >> parameters. Can some explain me in layman language? When I go through >> DDR2 specification, timing related text is too complex and confusing. >> Interested in getting very simple explanation. >> >There isn't any. RAM init is difficult. >> Also, i945 ram init code is doing lot of settings in MCH. Is there any >> step by step documentation available? >> >Sure: >1) Locate intel offices >2) Locate their top-secret safes >3) Observe security >4) Buy military gear >5) Recruit and train a company (~200 people) for a year >6) Launch assault on the office >7) Break into the safe >8) Get out of Intel building >9) Read the documentation > > >> Regards >> Mohit Gupta >> >> > > > >-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram Init: Intel i945: Timing parameters
On Friday, February 14, 2014 12:38:58 AM Vladimir 'φ-coder/phcoder' Serbinenko wrote: > Sure: > 1) Locate intel offices > 2) Locate their top-secret safes > 3) Observe security > 4) Buy military gear > 5) Recruit and train a company (~200 people) for a year > 6) Launch assault on the office > 7) Break into the safe > 8) Get out of Intel building > 9) Read the documentation > Don't do that. As a member of the US Armed Forces, I will stop you. Instead, why not get enough cash, buy Intel, then you can make executive decisions. It's legal. Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram Init: Intel i945: Timing parameters
On 14.02.2014 00:03, Mohit Gupta wrote: > I am having trouble understanding i945 ram init code especially timing > parameters. Can some explain me in layman language? When I go through > DDR2 specification, timing related text is too complex and confusing. > Interested in getting very simple explanation. > There isn't any. RAM init is difficult. > Also, i945 ram init code is doing lot of settings in MCH. Is there any > step by step documentation available? > Sure: 1) Locate intel offices 2) Locate their top-secret safes 3) Observe security 4) Buy military gear 5) Recruit and train a company (~200 people) for a year 6) Launch assault on the office 7) Break into the safe 8) Get out of Intel building 9) Read the documentation > Regards > Mohit Gupta > > signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram-init: Intel
Thanks Peter for your support. I will have a look at provided links. Regards Mohit Gupta-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot port for macbook2,1
On 13.02.2014 23:47, Mono wrote: > Hallo > > finally I managed to enable SPI on the Beaglebone Black and use it as > external programmer with flashrom. > I read the macbook's flash chip twice, as suggested. Both rom files are > identical. But: a few days/week ago I read the flash chip with the macbook's > internal programmer. This file differs from what the external programmer got. > Some 9500 bytes (out of 2MiB) differ. apart from a few exeptions those bytes > are 0xff read with the internal programmer, but have random hex code when > read with the external programmer. Well, between the usage of internal and > external programmer the macbook was in normal use. I didnt expect the OS or > EC(?) or something to write to the flash chip while it is in normal use. what > do you think? what could cause this differnce? I can paste the rom contents > later somewhere if that would help any. > That is pretty normal. Some firmwares store debug log or parameters in flash. > best regards > Mono > > On Sat, Feb 08, 2014 at 03:37:40PM +0100, Vladimir 'φ-coder/phcoder' > Serbinenko wrote: >> On 08.02.2014 15:27, Mono wrote: >>> Hallo, >>> >>> On Mon, Feb 03, 2014 at 10:16:30PM +0100, Vladimir 'φ-coder/phcoder' >>> Serbinenko wrote: > CY8C24794-24LFXI My guess: it's part of keyboard + touchpad Do you already know which port is USBdebug one? >>> Yes, I found out with a USB stick, dmesg and lsusb -t. >>> Did you already test USB debug with dbgp? >>> Yes, I tested USB debug for the Thinkpad X60, I assume it would work the >>> same for Macbook. >>> >> I meant that you can use debug port as early printk device. It's >> recommended to check dongle this way if your dongle is the real dbgp dongle. > Um, there are much more 00's than for the Thinkpad X60. Not sure what this means Different firmware. Most likely less functions are on it (keyboard and touchpad are on USB and handled by another chip). You'll need to make directory ec/apple/h8 for it and no code from lenovo/h8 will be reusable. > What about those Block Protect things? Forget them for now, you'll be flashing externally until you have working version anyway >>> >>> I updated the webpage about what I did ( >>> http://macbook.donderklumpen.de/coreboot/ ). >>> At the moment I am looking at x60's romstage.c because I'd plan to copy as >>> much as possible from it. At the function static void ich7_enable_lpc(void) >>> I got stuck. I can make some guesses, but don't know where the details are >>> documented. If you could point me to any documentation, I'd love to read >>> it. I tried ich7 datasheet and LPC Interface Specification but did not spot >>> what the function ich7_enable_lpc does. >>> >>> By comparing the output of lspci -nnvvvxxx -s 00:1f.0 on the Thinkpad with >>> coreboot and the Macbook with factory bios I get the following: >>> >>> on the Thinkpad >>> $ lspci -nnvvvxxx -s 00:1f.0 >>> 00:1f.0 ISA bridge [0601]: Intel Corporation 82801GBM (ICH7-M) LPC >>> Interface Bridge [8086:27b9] (rev 02) >>> Subsystem: Lenovo ThinkPad T60/R60 series [17aa:2009] >>> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- >>> Stepping- SERR- FastB2B- DisINTx- >>> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- >>> SERR- >> Latency: 0 >>> Capabilities: [e0] Vendor Specific Information: Len=0c >>> Kernel driver in use: lpc_ich >>> Kernel modules: intel_rng, lpc_ich, leds_ss4200 >>> 00: 86 80 b9 27 07 00 10 02 02 00 01 06 00 00 80 00 >>> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> 20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 09 20 >>> 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 >>> 40: 01 05 00 00 80 00 00 00 81 04 00 00 10 00 00 00 >>> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> 60: 80 80 80 80 d0 00 00 00 80 80 80 80 00 00 00 00 >>> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> 80: 10 02 0d 1f 01 16 7c 00 e1 15 0c 00 81 16 1c 00 >>> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> a0: ac 06 00 00 30 00 00 00 13 1c 0a 00 00 03 00 00 >>> b0: 00 00 f0 00 00 00 00 00 00 00 02 0a 00 00 00 00 >>> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> d0: 33 22 11 00 67 45 00 00 cf ff 00 00 08 00 00 00 >>> e0: 09 00 0c 10 b4 02 24 17 00 00 00 00 00 00 00 00 >>> f0: 01 c0 d1 fe 00 00 00 00 86 0f 02 00 00 00 00 00 >>> >>> and on the Macbook >>> $ lspci -nnvvvxxx -s 00:1f.0 >>> 00:1f.0 ISA bridge [0601]: Intel Corporation 82801GBM (ICH7-M) LPC >>> Interface Bridge [8086:27b9] (rev 02) >>> Subsystem: Intel Corporation Device [8086:7270] >>> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- >>> Stepping- SERR- FastB2B- DisINTx- >>> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- >>> SERR- >> Latency: 0 >>> Capabilities: [e0] Vendor Specific Information: Len=0c >>> Kernel driver in use: lpc_ich >>> Kernel modules: intel_r
[coreboot] Ram Init: Intel i945: Timing parameters
I am having trouble understanding i945 ram init code especially timing parameters. Can some explain me in layman language? When I go through DDR2 specification, timing related text is too complex and confusing. Interested in getting very simple explanation. Also, i945 ram init code is doing lot of settings in MCH. Is there any step by step documentation available? Regards Mohit Gupta-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] How do I reply to a post?
Regards Mohit Gupta-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot port for macbook2,1
Hallo finally I managed to enable SPI on the Beaglebone Black and use it as external programmer with flashrom. I read the macbook's flash chip twice, as suggested. Both rom files are identical. But: a few days/week ago I read the flash chip with the macbook's internal programmer. This file differs from what the external programmer got. Some 9500 bytes (out of 2MiB) differ. apart from a few exeptions those bytes are 0xff read with the internal programmer, but have random hex code when read with the external programmer. Well, between the usage of internal and external programmer the macbook was in normal use. I didnt expect the OS or EC(?) or something to write to the flash chip while it is in normal use. what do you think? what could cause this differnce? I can paste the rom contents later somewhere if that would help any. best regards Mono On Sat, Feb 08, 2014 at 03:37:40PM +0100, Vladimir 'φ-coder/phcoder' Serbinenko wrote: > On 08.02.2014 15:27, Mono wrote: > > Hallo, > > > > On Mon, Feb 03, 2014 at 10:16:30PM +0100, Vladimir 'φ-coder/phcoder' > > Serbinenko wrote: > >>> CY8C24794-24LFXI > >> My guess: it's part of keyboard + touchpad > >> Do you already know which port is USBdebug one? > > Yes, I found out with a USB stick, dmesg and lsusb -t. > > > >> Did you already test USB debug with dbgp? > > Yes, I tested USB debug for the Thinkpad X60, I assume it would work the > > same for Macbook. > > > I meant that you can use debug port as early printk device. It's > recommended to check dongle this way if your dongle is the real dbgp dongle. > >> > >>> Um, there are much more 00's than for the Thinkpad X60. Not sure what > >> this means > >> Different firmware. Most likely less functions are on it (keyboard and > >> touchpad are on USB and handled by another chip). You'll need to make > >> directory ec/apple/h8 for it and no code from lenovo/h8 will be reusable. > >> > >>> What about those Block Protect things? > >> Forget them for now, you'll be flashing externally until you have > >> working version anyway > >> > > > > I updated the webpage about what I did ( > > http://macbook.donderklumpen.de/coreboot/ ). > > At the moment I am looking at x60's romstage.c because I'd plan to copy as > > much as possible from it. At the function static void ich7_enable_lpc(void) > > I got stuck. I can make some guesses, but don't know where the details are > > documented. If you could point me to any documentation, I'd love to read > > it. I tried ich7 datasheet and LPC Interface Specification but did not spot > > what the function ich7_enable_lpc does. > > > > By comparing the output of lspci -nnvvvxxx -s 00:1f.0 on the Thinkpad with > > coreboot and the Macbook with factory bios I get the following: > > > > on the Thinkpad > > $ lspci -nnvvvxxx -s 00:1f.0 > > 00:1f.0 ISA bridge [0601]: Intel Corporation 82801GBM (ICH7-M) LPC > > Interface Bridge [8086:27b9] (rev 02) > > Subsystem: Lenovo ThinkPad T60/R60 series [17aa:2009] > > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > > Stepping- SERR- FastB2B- DisINTx- > > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- > > SERR- > Latency: 0 > > Capabilities: [e0] Vendor Specific Information: Len=0c > > Kernel driver in use: lpc_ich > > Kernel modules: intel_rng, lpc_ich, leds_ss4200 > > 00: 86 80 b9 27 07 00 10 02 02 00 01 06 00 00 80 00 > > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 09 20 > > 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 > > 40: 01 05 00 00 80 00 00 00 81 04 00 00 10 00 00 00 > > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 60: 80 80 80 80 d0 00 00 00 80 80 80 80 00 00 00 00 > > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 80: 10 02 0d 1f 01 16 7c 00 e1 15 0c 00 81 16 1c 00 > > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > a0: ac 06 00 00 30 00 00 00 13 1c 0a 00 00 03 00 00 > > b0: 00 00 f0 00 00 00 00 00 00 00 02 0a 00 00 00 00 > > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > d0: 33 22 11 00 67 45 00 00 cf ff 00 00 08 00 00 00 > > e0: 09 00 0c 10 b4 02 24 17 00 00 00 00 00 00 00 00 > > f0: 01 c0 d1 fe 00 00 00 00 86 0f 02 00 00 00 00 00 > > > > and on the Macbook > > $ lspci -nnvvvxxx -s 00:1f.0 > > 00:1f.0 ISA bridge [0601]: Intel Corporation 82801GBM (ICH7-M) LPC > > Interface Bridge [8086:27b9] (rev 02) > > Subsystem: Intel Corporation Device [8086:7270] > > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > > Stepping- SERR- FastB2B- DisINTx- > > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- > > SERR- > Latency: 0 > > Capabilities: [e0] Vendor Specific Information: Len=0c > > Kernel driver in use: lpc_ich > > Kernel modules: intel_rng, lpc_ich, leds_ss4200 > > 00: 86 80 b9 27 07 00 10 02 02 00 01 06 00 00 80 00 > > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 20: 00
Re: [coreboot] Fwd: IMB-A180E H coreboot won't boot (new)
I thought the instructions from the coreboot HOWTO web page would give me the latest code. The git log command (below) did show recent changes, but when I "cd coreboot; git pull", none of them came down. What is the command to update src/mainboard/asrock/imb-a180? Thanks, Mark On 02/13/2014 10:51 AM, Kyösti Mälkki wrote: On 02/13/2014 07:58 PM, Mark C. Mason wrote: I'm new to coreboot, and I'm working to use it with an ASROCK IMB-A180, the H version with the LVDS port. Hey You seem to build with coreboot source from Aug 2013. There has been several changes affecting this board since then, some more critical than others so please update your tree. $ git log -- src/mainboard/asrock/imb-a180/ We generally do not trust the distributions' compiler toolchains, have you run: $ make crossgcc Regards, Kyösti -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Fwd: IMB-A180E H coreboot won't boot (new)
On 02/13/2014 07:58 PM, Mark C. Mason wrote: I'm new to coreboot, and I'm working to use it with an ASROCK IMB-A180, the H version with the LVDS port. Hey You seem to build with coreboot source from Aug 2013. There has been several changes affecting this board since then, some more critical than others so please update your tree. $ git log -- src/mainboard/asrock/imb-a180/ We generally do not trust the distributions' compiler toolchains, have you run: $ make crossgcc Regards, Kyösti -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] SeaVGABIOS with native vga init (Need testers)
On Thu, Feb 13, 2014 at 10:24:21AM +0100, Vladimir 'φ-coder/phcoder' Serbinenko wrote: > On 13.02.2014 01:23, Kevin O'Connor wrote: > >> Looking through the output of > >> > > >> > $ git grep k8t890 src/mainboard/ > >> > > >> > the boards Asus A8V-E Deluxe, Asus A8V-E SE, Asus K8V-X, Asus M2V-MX SE > >> > and Asus M2V should theoretically support that. > > Okay. The SeaVGABIOS implementation is expecting a coreboot table > > (LB_TAG_FRAMEBUFFER). So, as long as that is present it should work. > > > LB_TAG_FRAMEBUFFER is present only if display is placed in graphics > mode, otherwise EGA text mode is assumed. > EGA text mode is much easier to make use of (including for oprom) and > more compatible than graphics counterpart. > Lenovo X201 init makes use of EGA text mode as well. The SeaVGABIOS code I published is looking for a graphics framebuffer. -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Alias motherboard?
It's not supported until you can run the script on the node that shows it booted. We've gotten away from just saying "this is like that so it must work." Run the script. That's the requirement now. ron On Thu, Feb 13, 2014 at 5:23 AM, Oskar Enoksson wrote: > I noticed that "AMD Serenade" motherboard is not listed as supported. > However, supposedly that motherboard is identical to HP DL145 G1. So, > probably using the hp/dl145_g1 motherboard configuration will produce a > ROM that works with "AMD Serenade" aswell. > > Are such alias motherboards handled in any particular way? Should the info > at least go into the wiki-page of supported motherboards? > > > > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Alias motherboard?
I noticed that "AMD Serenade" motherboard is not listed as supported. However, supposedly that motherboard is identical to HP DL145 G1. So, probably using the hp/dl145_g1 motherboard configuration will produce a ROM that works with "AMD Serenade" aswell. Are such alias motherboards handled in any particular way? Should the info at least go into the wiki-page of supported motherboards? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram-init: Intel i945: sdram_detect_cas_latency_and_ram_speed
Mohit Gupta wrote: > I am trying to understand ram initialization process for intel i945 chipset. > Would some be able to guide me as what sdram_detect_cas_latency_and_ram_speed > is trying to do. I am a newbie, hence, entitled to ask stupid question :) Being a newbie is fine, asking too simple questions mhmh. https://en.wikipedia.org/wiki/DDR2_SDRAM http://www.jedec.org/standards-documents/docs/jesd-79-2e http://www.jedec.org/download/search/JESD208.pdf //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Trouble with coreboot for Roda RK9
Hello Dmitry, > Why can't I read the condition GP1 - GP4? > When I start the program superiotool with original bios, it shows regular > results, when I start the program superiotool with coreboot the program > shows 0 at GP1-GP4. It is in GP4 the DIP switcher locates to chose the > type of LCD. I'm sorry, but I can only confirm your problem. I tried reading those GPIOs with the coreboot version we had on our RK9 and everything worked out. After flashing the current upstream version, the VGA output was garbled. So this is a regression which needs further investigation. I can't currently work on this, but if you like to bisect the problem: I guess, commit 11a7db3 should be a working starting point. Kind regards, Nico -- M. Sc. Nico Huber Berater, SINA-Softwareentwicklung Public Sector secunet Security Networks AG Tel.: +49-201-5454-3635, Fax: +49-201-5454-1325 E-Mail: nico.hu...@secunet.com Mergenthalerallee 77, 65760 Eschborn, Deutschland www.secunet.com __ Sitz: Kronprinzenstraße 30, 45128 Essen, Deutschland Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Willem Bulthuis, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Peter Zattler __ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] SeaVGABIOS with native vga init (Need testers)
On 13.02.2014 01:23, Kevin O'Connor wrote: >> Looking through the output of >> > >> >$ git grep k8t890 src/mainboard/ >> > >> > the boards Asus A8V-E Deluxe, Asus A8V-E SE, Asus K8V-X, Asus M2V-MX SE >> > and Asus M2V should theoretically support that. > Okay. The SeaVGABIOS implementation is expecting a coreboot table > (LB_TAG_FRAMEBUFFER). So, as long as that is present it should work. > LB_TAG_FRAMEBUFFER is present only if display is placed in graphics mode, otherwise EGA text mode is assumed. EGA text mode is much easier to make use of (including for oprom) and more compatible than graphics counterpart. Lenovo X201 init makes use of EGA text mode as well. signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
