Re: [coreboot] `DEBUG_INTEL_ME` (incorrectly) only selected for Intel BD82x6x
On 26.02.2014 04:24, mrnuke wrote: On Wednesday, February 19, 2014 11:06:40 PM Paul Menzel wrote: looking through `src/console/Kconfig` I noticed You mean 'src/Kconfig' ? if SOUTHBRIDGE_INTEL_BD82X6X DEFAULT_CONSOLE_LOGLEVEL_8 This is a layering violation. We shouldn't have hardware-specific options in top-level Kconfig. This should be moved to southbridge Kconfig, and not depend on LOGLEVEL. Maybe we need to move ME handling to a common dir and handle the Kconfigs there. which seems odd as currently other chipsets needing the Intel Management Engine were submitted. $ git grep DEBUG_INTEL_ME [...] Smells like copypasta. Yet another reason to consider unifying ME handling across southbridges. Don't. This particular code is a good example why it shouldn't be done. On Ibexpeak this code (extended status print) would timeout. signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
David wrote: With just 1 stick in the A1 slot, please post a pastebin of the console output. Perfect! It is perfectly detailed, the cpu is not recognized: http://pastebin.com/2Lbew82b Thanks, best regards, -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
On Wed, Feb 26, 2014 at 12:54 PM, HacKurx hack...@gmail.com wrote: David wrote: With just 1 stick in the A1 slot, please post a pastebin of the console output. Perfect! It is perfectly detailed, the cpu is not recognized: http://pastebin.com/2Lbew82b Great, this is another big step in the right direction. It would still be helpful if you can post the details for this stick. You may also want to post the output of git diff for others who may want to try Richland on the F2A85-M. At this point, you'll need to study the code and find out exactly where it is dying. There may be someone who can spot it quickly, but I'm unsure of exactly what the issue is. I do think the line Initializing devices may mean that this is related to the devicetree code. It has successfully run the first part of AGESA, specifically initializing the memory controller, PCI-E, so you have a sort-of-working system. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
HacKurx [mailto:hack...@gmail.com] wrote:
] David wrote:
] With just 1 stick in the A1 slot, please post a pastebin of the console
] output.
]
]Perfect! It is perfectly detailed, the cpu is not recognized:
]http://pastebin.com/2Lbew82b
you could try adding your cupid to the list in
src/cpu/amd/agesa/family15tn/model_15_init.c:
static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */
{ X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 */
{ 0, 0 },
};
Thanks,
Scott
]Thanks, best regards,
--
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[coreboot] #202: Error building coreboot for Samsung Exynos5 Google Snow
#202: Error building coreboot for Samsung Exynos5 Google Snow +-- Reporter: bluestore.logmein@… | Owner: stepan@… Type: defect |Status: new Priority: major| Milestone: Component: coreboot | Keywords: Dependencies: | Patch Status: there is no patch +-- Hi, I am trying to compile a coreboot rom for the Samsung chromebook Series 3 - Exynos5, i followed the instructions at http://www.coreboot.org/Exynos5 to compile the armv7a-eabi toolchain and evertyhing went ok. At the menuconfig i selected Google MainBoard, model Snow, exit and save. It starts to compile until it returns this error: GENgenerated/romstage.ld LINK cbfs/fallback/romstage.debug build/ec/google/chromeec/ec.romstage.o: In function `google_chromeec_early_init': /home/suporte/coreboot/src/ec/google/chromeec/ec.c:117: undefined reference to `recovery_mode_enabled' collect2: error: ld returned 1 exit status make: *** [build/cbfs/fallback/romstage.debug] Error 1 Am i missing something? Also tried make clean and make crossgcc, and even the built went fine, when i run make always returns this error. Thank you, Pete -- Ticket URL: https://tracker.coreboot.org/trac/coreboot/ticket/202 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] #201: Error building coreboot for Samsung Exynos5 Google Snow
#201: Error building coreboot for Samsung Exynos5 Google Snow ---+--- Reporter: Pete bluestore.logmein@… | Owner: stepan@… Type: defect |Status: new Priority: major | Milestone: Component: coreboot| Keywords: Dependencies: | Patch Status: there is no | patch ---+--- Hi, I am trying to compile a coreboot rom for the Samsung chromebook Series 3 - Exynos5, i followed the instructions at http://www.coreboot.org/Exynos5 to compile the armv7a-eabi toolchain and evertyhing went ok. At the menuconfig i selected Google MainBoard, model Snow, exit and save. It starts to compile until it returns this error: GENgenerated/romstage.ld LINK cbfs/fallback/romstage.debug build/ec/google/chromeec/ec.romstage.o: In function `google_chromeec_early_init': /home/suporte/coreboot/src/ec/google/chromeec/ec.c:117: undefined reference to `recovery_mode_enabled' collect2: error: ld returned 1 exit status make: *** [build/cbfs/fallback/romstage.debug] Error 1 Am i missing something? Also tried make clean and make crossgcc, and even the built went fine, when i run make always returns this error. Thank you, Pete -- Ticket URL: https://tracker.coreboot.org/trac/coreboot/ticket/201 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
