Re: [coreboot] On Intel Boot Guard
Hi Iru, we aren't still sure which boards use Intel Boot Guard and which doesn't use it. But we expect most board use it, because it's recommended by intel - as we dont recommend it. Also there isn't yet a test script for Intel Boot Guard. Can you post a link to that forum post? I would like to look into a x240 flash image. If you have such board it would be nice if you can send me a copy of the flash image via private mail. Cheers, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgpFImtjh7IHP.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [Announcement] Please rebuild utility cbmem after new addition of time stamps
Dear coreboot folks, commit a7d92441 (timestamps: You can never have enough of them!) [1] added new time stamps. So please rebuild the utility `cbmem` so that the output does not contain any *unknown* strings [2]. Or on my ASRock E350M1 with 4.0-9470-g72645bb [3] With old cbmem: 12 entries total: 10:start of ramstage 5 30:device enumeration440 (435) 40:device configuration 94,705 (94,264) 50:device enable 98,542 (3,837) 60:device initialization 108,505 (9,963) 70:device setup done 236,433 (127,927) 75:cbmem post236,813 (379) 80:write tables 236,817 (4) 90:load payload 238,345 (1,528) 15:starting LZMA decompress (ignore for x86) 238,557 (211) 16:finished LZMA decompress (ignore for x86) 255,012 (16,454) 99:selfboot jump 255,033 (20) After rebuilding cbmem: 12 entries total: 10:start of ramstage 5 30:device enumeration440 (435) 40:device configuration 94,705 (94,264) 50:device enable 98,542 (3,837) 60:device initialization 108,505 (9,963) 70:device setup done 236,433 (127,927) 75:cbmem post236,813 (379) 80:write tables 236,817 (4) 90:load payload 238,345 (1,528) 15:unknown 238,557 (211) 16:unknown 255,012 (16,454) 99:selfboot jump 255,033 (20) Thanks, Paul [1] http://review.coreboot.org/9608 [2] http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asus/kfsn4-dre/4.0-9474-gbe34797/2015-04-23T14:35:51Z/coreboot_timestamps.txt;h=3ef32ac0b2caefb2031665b0c6101dc3079b59bb;hb=a405af9e188bd545be60f55042c402ee061393a2 signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [Announcement] Please rebuild utility cbmem after new addition of time stamps
* Paul Menzel paulepan...@users.sourceforge.net [150423 22:43]: With old cbmem: 15:starting LZMA decompress (ignore for x86) 238,557 (211) 16:finished LZMA decompress (ignore for x86) 255,012 (16,454) After rebuilding cbmem: 12 entries total: 15:unknown 238,557 (211) 16:unknown 255,012 (16,454) ... or possibly the other way around. :-) Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Smi handler issue
Dear all, While compiling coreboot, southbridge smm handler always compiles as empty function irrespective of the code present in it. As per declaration in smm.h, it is declared as attribute weak. Since it is defined in my southbridge smm handler, it should take the defined function which it is not happening (objdump shows that only the southbridge smm handler function has only ret instruction, rest all function have proper assembly code as per the required implementation .) I need smm handler for enabling acpi mode during os booting. Please help in solving this issue. Regards, N Solanki -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Asus M3A79-T Deluxe Support
Hello, are there any plans of supporting this motherboard? I am running an AMD Phenom 9950 Black Edition Processor with it. Northbridge: 790FX Southbridge: SB750 Vendor page: http://www.asus.com/Motherboards/M3A79T_Deluxe/overview/ lspci -tvnn: -[:00]-+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] RD790 Host Bridge [1002:5956] +-02.0-[01]--+-00.0 NVIDIA Corporation GF114 [GeForce GTX 560 Ti] [10de:1200] |\-00.1 NVIDIA Corporation GF114 HDMI Audio Controller [10de:0e0c] +-06.0-[02]00.0 Marvell Technology Group Ltd. 88E8056 PCI-E Gigabit Ethernet Controller [11ab:4364] +-07.0-[03]00.0 Marvell Technology Group Ltd. 88SE6121 SATA II / PATA Controller [11ab:6121] +-11.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode] [1002:4390] +-12.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] +-12.1 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0 USB OHCI1 Controller [1002:4398] +-12.2 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] +-13.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] +-13.1 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0 USB OHCI1 Controller [1002:4398] +-13.2 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] +-14.0 Advanced Micro Devices, Inc. [AMD/ATI] SBx00 SMBus Controller [1002:4385] +-14.1 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 IDE Controller [1002:439c] +-14.3 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d] +-14.4-[04]--+-06.0 C-Media Electronics Inc CMI8788 [Oxygen HD Audio] [13f6:8788] |\-08.0 LSI Corporation FW322/323 [TrueFire] 1394a Controller [11c1:5811] +-14.5 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI2 Controller [1002:4399] +-18.0 Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] +-18.1 Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map [1022:1201] +-18.2 Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller [1022:1202] +-18.3 Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control [1022:1203] \-18.4 Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control [1022:1204] superiotool -dV: superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0x, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0x, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8720F (id=0x8720, rev=0x2) at 0x2e Register dump: idx 20 21 22 23 24 2b val 87 20 02 10 00 00 def 87 20 05 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 02 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 val 01 03 f8 04 00 50 def 00 03 f8 04 00 50 LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 val 00 02 f8 03 00 50 def 00 02 f8 03 00 50 LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 00 03 78 07 78 07 04 0b def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 0e 80 0e 00 00 00 00 0c 00 00 00 bf def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 00 def 01 00 60 00 64 01 02 48 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 e5 e6 e7 e9 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff val 00 0c 00 00 01 00 83 00 00 0f 40 0a 30 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00 00 00 01 0c 00 40 01 01 00 00 40 00 00 00 00 00 00 00 00 00 27 00 00 00 00 00 00 00 00 00 00 00 00 2c
Re: [coreboot] Smi handler issue
On Tue, 2015-04-21 at 23:09 +0530, Naresh G. Solanki wrote: Dear all, While compiling coreboot, southbridge smm handler always compiles as empty function irrespective of the code present in it. As per declaration in smm.h, it is declared as attribute weak. Since it is defined in my southbridge smm handler, it should take the defined function which it is not happening (objdump shows that only the southbridge smm handler function has only ret instruction, rest all function have proper assembly code as per the required implementation .) I need smm handler for enabling acpi mode during os booting. Please help in solving this issue. Regards, N Solanki Which board and chipset is this? Please describe how to reproduce the error on current master from coreboot.org git using the reference xgcc toolchain? Kyösti -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] gerrit authentication
Hi, To provide more options to contributors, it's now possible to login to our code review system at http://review.coreboot.org using GitHub credentials. On the login screen, simply pick 'GitHub OAuth2'. If you already have an account, you can link your GitHub account to it by logging in on gerrit, clicking 'Link Another Identity' on http://review.coreboot.org/#/settings/web-identities, and selecting GitHub OAuth2 (and acknowleding on GitHub that you want to associate your account with coreboot code review). Of course, OpenID still works, as does logging in using Google Accounts through OAuth2. Regards, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham Law, Christine Elizabeth Flores -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] On Intel Boot Guard
Hi, I've just seen a forum thread about removing the white list of ThinkPad X240, so I think Boot Guard is not preventing modification of BIOS. Then I read some article, which says what Boot Guard locks is the boot block, so I think there's still some way to flash coreboot on a new Intel platform. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
