Re: [coreboot] How to build coreboot with alternate toolchain?
Dear David, Am Freitag, den 13.05.2016, 13:26 -0700 schrieb David Hendricks: > Do you have multiple versions of GCC installed? Yes, I do have several versions installed. The packages `gcc-4.9`, `gcc-5`, and `gcc-6`. > You might need to use "update-alternatives" to manage them. I haven't > done so with Debian, but this page seems to have a pretty good > explanation: > http://lektiondestages.blogspot.com/2013/05/installing-and-switching-gccg-versions.html Thank you for that suggestion, which Stefan Tauner also brought up in # coreb...@freenode.net. In Debian `cc` is not really managed by update- alternatives. ``` $ LANG=C sudo update-alternatives --config cc[sudo] password for paul: There is only one alternative in link group cc (providing /usr/bin/cc): /usr/bin/gcc Nothing to configure. $ LANG=C sudo update-alternatives --config gcc update-alternatives: error: no alternatives for gcc ``` As this is not required in other projects, like SeaBIOS, would it be useful to be able to pass variables in, so that the command below would work? ``` $ make HOSTCC=gcc-6 CC=gcc-6 ``` Thanks, Paul signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How to build coreboot with alternate toolchain?
Hi Paul, Do you have multiple versions of GCC installed? You might need to use "update-alternatives" to manage them. I haven't done so with Debian, but this page seems to have a pretty good explanation: http://lektiondestages.blogspot.com/2013/05/installing-and-switching-gccg-versions.html -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot with fsp hangs at post code 19 on Bayley Bay
Hello Kathappan, I need to look deeper into this area since I am not expert on FSP, but I have some ideas what could be wrong. Several questions for you: [1] Which BYT SoC you are using (example BYT-M N2807)? [2] How many DDR3 channels (1 or 2) are you using in your design, and what is the size of memory (most likely not a problem)? [3] PCH. Do you have PCIe channels initialized/set in default soft straps (you must have some, at least PCIe root port 0, and PCIe root port 1, as I recalled)? << IMPORTANT? Again, I need to think more about this, and I'll try to find some answers, later... Please, try to see/discover [3] using BCT tool! Zoran ___ On Fri, May 13, 2016 at 3:01 PM, Kathappan E < kathappa...@lnttechservices.com> wrote: > Hi all, > > > > When I try coreboot on Bayley Bay platform along with fsp > (BAYTRAIL_FSP_GOLD_004_22-MAY-2015), it is getting hang at post code 19. > > > > Also I tried with debug version fsp > (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG) , it still at that point and > below is the debug log. > > > > *Firmware Image*: Have used the 8 MB vendor bios and flashed the last 2 > MB region(60 to 7f) with coreboot image. > > > > *From the debug log*: coreboot gives the control to FSP binary routine( > *FspInitApi*) and it is getting hang when trying to do PCH initialize( > *PchMiscInit*) inside FSP part code. > > > > *POST 19 code info*: *EFI_COMPUTING_UNIT_CHIPSET* | > *EFI_CU_CLOCK_PEI_INIT_ENTRY* ==> Clock Init PEIM Entry > > > > I have not seen the clock related setting available when customizing fsp > binary using BCT. > > > > I tried to disable south cluster component such as EMMC,HSUART,SATA and > SIO using BCT , it didn't help me. > > > > Can anyone please help me provide some inputs such as related below to > proceed further debugging on it ? > > 1. Any other setting we can try out using BCT > > 2. About devices configuration to be initialized byPchMiscInit function. > > 3. Anything need to be cared/double checked from coreboot side in order to > giving control to FspInitApi function. > > 4. Does pch straps settings may cause this since I am using upper 6 MB > region flash data which is from vendor bios. > > 4. Please suggest anything on it. > > > > Thanks in advance, > > Kathappan > > > > Debug log Start > >>> > > > > coreboot-coreboot-unknown Thu May 12 08:04:42 UTC 2016 romstage starting... > > RTC Init > > POST: 0x44 > > POST: 0x47 > > POST: 0x48 > > Starting the Intel FSP (early_init) > > PM1_STS = 0x0 PM1_CNT = 0x0 GEN_PMCON1 = 0x44000 > > prev_sleep_state = S5 > > Configure Default UPD Data > > PcdMrcInitSPDAddr1: 0xa0 (default) > > PcdMrcInitSPDAddr2: 0xa2 (default) > > PcdSataMode:0x01 (set) > > PcdLpssSioEnablePciMode:0x01 (default) > > PcdMrcInitMmioSize: 0x800 (default) > > PcdIgdDvmt50PreAlloc: 0x02 (default) > > PcdApertureSize:0x02 (default) > > PcdGttSize: 0x02 (default) > > SerialDebugPortAddress: 0x3f8 (default) > > SerialDebugPortType:0x01 (default) > > PcdMrcDebugMsg: 0x01 (default) > > PcdSccEnablePciMode:0x01 (default) > > IgdRenderStandby: 0x00 (default) > > TxeUmaEnable: 0x00 (default) > > PcdOsSelection: 0x04 (default) > > PcdEMMC45DDR50Enabled: 0x01 (default) > > PcdEMMC45HS200Enabled: 0x00 (default) > > PcdEMMC45RetuneTimerValue: 0x08 (default) > > PcdEnableIgd: 0x01 (default) > > AutoSelfRefreshEnable: 0x00 (default) > > APTaskTimeoutCnt: 0x00 (default) > > GTT Size: 2 MB > > Tseg Size: 8 MB > > Aperture Size: 256 MB > > IGD Memory Size:64 MB > > MMIO Size: 2048 MB > > MIPI/ISP: Disabled > > Sdio: Enabled > > Sdcard: Enabled > > SATA: Enabled > > SIO Dma 0: Enabled > > SIO I2C0: Enabled > > SIO I2C1: Enabled > > SIO I2C2: Enabled > > SIO I2C3: Enabled > > SIO I2C4: Enabled > > SIO I2C5: Enabled > > SIO I2C6: Enabled > > Azalia: Enabled > > SIO Dma1: Enabled > > Pwm0: Enabled > > Pwm1: Enabled > > Hsuart0:Enabled > > Hsuart1:Enabled > > Spi:Enabled > > Lpe:Disabled > > eMMC Mode: eMMC 4.5 > > SATA Mode: AHCI > > Xhci: Enabled > > POST: 0x92 > > > > > > = PEIM FSP (VLYVIEW0 0x0304) = > > Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE > > Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 > > Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A > > The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle i
[coreboot] ASUS KFSN4-DRE (K8) Automated Test Failure [master]
The ASUS KFSN4-DRE (K8) fails verification for branch master as of commit 572f07497104e1f9c4e1ed0fd01850a9e2a4803f The following tests failed: BOOT_FAILURE Commits since last successful test: 572f074 inteltool: update documentation See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE (K8) test stand Want to test on your own equipment? Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering regarding any issues stemming from this notification 1463153506-2-automaster.log.bz2 Description: Binary data -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] coreboot with fsp hangs at post code 19 on Bayley Bay
Hi all, When I try coreboot on Bayley Bay platform along with fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015), it is getting hang at post code 19. Also I tried with debug version fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG) , it still at that point and below is the debug log. Firmware Image: Have used the 8 MB vendor bios and flashed the last 2 MB region(60 to 7f) with coreboot image. >From the debug log: coreboot gives the control to FSP binary >routine(FspInitApi) and it is getting hang when trying to do PCH >initialize(PchMiscInit) inside FSP part code. POST 19 code info: EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_ENTRY ==> Clock Init PEIM Entry I have not seen the clock related setting available when customizing fsp binary using BCT. I tried to disable south cluster component such as EMMC,HSUART,SATA and SIO using BCT , it didn't help me. Can anyone please help me provide some inputs such as related below to proceed further debugging on it ? 1. Any other setting we can try out using BCT 2. About devices configuration to be initialized byPchMiscInit function. 3. Anything need to be cared/double checked from coreboot side in order to giving control to FspInitApi function. 4. Does pch straps settings may cause this since I am using upper 6 MB region flash data which is from vendor bios. 4. Please suggest anything on it. Thanks in advance, Kathappan Debug log Start >>> coreboot-coreboot-unknown Thu May 12 08:04:42 UTC 2016 romstage starting... RTC Init POST: 0x44 POST: 0x47 POST: 0x48 Starting the Intel FSP (early_init) PM1_STS = 0x0 PM1_CNT = 0x0 GEN_PMCON1 = 0x44000 prev_sleep_state = S5 Configure Default UPD Data PcdMrcInitSPDAddr1: 0xa0 (default) PcdMrcInitSPDAddr2: 0xa2 (default) PcdSataMode:0x01 (set) PcdLpssSioEnablePciMode:0x01 (default) PcdMrcInitMmioSize: 0x800 (default) PcdIgdDvmt50PreAlloc: 0x02 (default) PcdApertureSize:0x02 (default) PcdGttSize: 0x02 (default) SerialDebugPortAddress: 0x3f8 (default) SerialDebugPortType:0x01 (default) PcdMrcDebugMsg: 0x01 (default) PcdSccEnablePciMode:0x01 (default) IgdRenderStandby: 0x00 (default) TxeUmaEnable: 0x00 (default) PcdOsSelection: 0x04 (default) PcdEMMC45DDR50Enabled: 0x01 (default) PcdEMMC45HS200Enabled: 0x00 (default) PcdEMMC45RetuneTimerValue: 0x08 (default) PcdEnableIgd: 0x01 (default) AutoSelfRefreshEnable: 0x00 (default) APTaskTimeoutCnt: 0x00 (default) GTT Size: 2 MB Tseg Size: 8 MB Aperture Size: 256 MB IGD Memory Size:64 MB MMIO Size: 2048 MB MIPI/ISP: Disabled Sdio: Enabled Sdcard: Enabled SATA: Enabled SIO Dma 0: Enabled SIO I2C0: Enabled SIO I2C1: Enabled SIO I2C2: Enabled SIO I2C3: Enabled SIO I2C4: Enabled SIO I2C5: Enabled SIO I2C6: Enabled Azalia: Enabled SIO Dma1: Enabled Pwm0: Enabled Pwm1: Enabled Hsuart0:Enabled Hsuart1:Enabled Spi:Enabled Lpe:Disabled eMMC Mode: eMMC 4.5 SATA Mode: AHCI Xhci: Enabled POST: 0x92 = PEIM FSP (VLYVIEW0 0x0304) = Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FD4 The 1th FV start address is 0x000FFFB, size is 0x0002F400, handle is 0xFFFB Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926 PcdMrcInitTsegSize = 8 PcdMrcInitMmioSize = 800 PcdMrcInitSPDAddr1 = A0 PcdMrcInitSPDAddr2 = A2 Setting BootMode to 0 Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE About to call MrcInit(); BayleyBay Platform Type RID = 0x11. Reg_EFF_DualCH_EN = 0x40030040. CurrentMrcData.BootMode = 4 C1.D0: SPD not present. Configuring Memory Start... START_RMT: RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight CmdLeft CmdRight -
