[coreboot] New on blogs.coreboot.org: [GSoC] Better RISC-V support, week #1

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A new post titled "[GSoC] Better RISC-V support, week #1" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/06/01/gsoc-better-risc-v-support-week-1/

Hi, I’m Jonathan Neuschäfer (jn__ on IRC) and my GSoC project for this year is to improve coreboot’s support for RISC-V platforms. RISC-V is a new instruction set architecture (ISA) that can be implemented without paying license fees and is relatively simple.
Coreboot has already been ported to RISC-V in 2014, and has since received a bunch of patches, but since the RISC-V Privileged ISA Specification (which defines things like interrupt handling and virtual memory) is still in flux, it has become unbootable again.
My first first goal last week was to run coreboot in SPIKE, the official RISC-V emulator, and get some console output. I checked out commit 419f1b5f3 (current master) of the riscv-tools repository and built SPIKE from there.
After I patched a few outdated instructions and worked around the fact that the RISC-V binutils port currently included in coreboot targets a newer version of the RISC-V Privileged Spec by hardcoding some Control and Status Register numbers, I finally got coreboot booting until the point where it would jump into a payload, had I specified one.
All patches can be found under the riscv topic on gerrit.
Plans for this week
This week I will update my SPIKE to a version that supports the upcoming Privileged Spec 1.9, which will be released in the next couple weeks. This has the advantage that I don’t need to patch instructions because GCC encodes them differently than SPIKE decodes them. Additionally, I’ll try to get Linux to boot in SPIKE, under coreboot.


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Re: [coreboot] What purpose the "mrc.cache"?

[김유석 책임연구원]

Dear Martin.


Thank you, your prompt reply. It is very useful to me.


I'll study the document of FSP. and tools.


Thank you.


2016-06-02 오전 5:23에 Martin Roth 이(가) 쓴 글:

1) The MRC cache is a location for saving the state of the memory
registers. These values are typically used to restore the memory
controller state on resume from S3 suspend, or to help the system boot
faster.  On systems using the Rangeley FSP it is not optional as it is
on some other platforms.

2) The file you see in cbfs is actually just a placeholder.  If you
look in that area of the rom, you'll see that it's empty.  It's just
there to reserve the space for coreboot to write the memory register
information into, and to prevent anything else from being put into
that location.

3) The memory code for Rangeley is part of the FSP.  This is currently
only available for the Rangeley chip as a binary blob.  You can
download it, along with the FSP documentation and the Binary
Configuration Tool, from Intel's website:  http://intel.com/fsp

Martin

On Tue, May 31, 2016 at 10:38 PM, 김유석 책임연구원  wrote:

Dear Sir.


My ENV.

   Platform : intel atom rangeley mohon peak CRB(C2358)


This time, I'm try to study for MRC(Memory Reference Code).


But, I'm can not found a some example code on coreboot source tree.(rangely)


Anyway, I'm get a some hint on last image.


Performing operation on 'COREBOOT' region...
Name   Offset Type Size
cbfs master header 0x0cbfs header  32
fallback/romstage  0x80   stage24356
config 0x6040 raw  440
revision   0x6240 raw  567
cmos_layout.bin0x64c0 cmos_layout  1316
fallback/dsdt.aml  0x6a40 raw  8074
payload_config 0x8a40 raw  1574
payload_revision   0x90c0 raw  244
(empty)0x9200 null 27800
mrc.cache  0xfec0mrc_cache  65536
cpu_microcode_blob.bin 0x1ff00microcode167936
fallback/ramstage  0x48f80stage48170
fallback/payload   0x54c00payload  61309
(empty)0x63bc0null 1163992
fsp.bin0x17fec0   fsp  389120
(empty)0x1def00   null 133528
bootblock  0x1ff8c0   bootblock1528


Question.

  1. What purpose the "mrc.cache"?

  2. Where to location the source code for "mrc.cache" ?

  3. How modify the MRC ? for the sdram.


Thank you.





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