Re: [coreboot] [coreboot-announce] SHORT NOTICE: coreboot.berlin next weekend, Oct. 7-9
See you there! I just registered and am really looking forward to seeing everyone! Thanks Peter! ron On Fri, Sep 30, 2016 at 9:41 AM Peter Stuge wrote: > Hello all, > > I'm happy to *finally* have the information and registration page online: > > https://coreboot.berlin/ > > > Yes, it's very late, but I hope that we will still be a good number > of people meeting up next weekend. > > Quick feedback helps me make sure that everyone will get food. > > If you are interested in attending, but unable to register at the > Community Registration Fee cost then please get in touch with me, > so that we can try to work something out. > > > Thank you very much, and hope to see you in Berlin on the 7:th! > > //Peter > > ___ > coreboot-announce mailing list > coreboot-annou...@coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot-announce > -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] SHORT NOTICE: coreboot.berlin next weekend, Oct. 7-9
Hello all, I'm happy to *finally* have the information and registration page online: https://coreboot.berlin/ Yes, it's very late, but I hope that we will still be a good number of people meeting up next weekend. Quick feedback helps me make sure that everyone will get food. If you are interested in attending, but unable to register at the Community Registration Fee cost then please get in touch with me, so that we can try to work something out. Thank you very much, and hope to see you in Berlin on the 7:th! //Peter -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] LPC and m.2 connector
Hi everyone I have a question. Sometime ago i bought a Mini Pcie post card to do some tests, and it works really well, on a really old notebook. Now I'm doing some research on a newer notebook, that doesn't have a Mini Pcie connector. The only available connector is a m.2 Key A. So my question is. What are the chances os my PCie post card work on the m.2 connector after having an adapter like these: [image: pasted1] [image: pasted2] Does any one know if the m.2 connector has any direct connection to the LPC lines, on the same way as the PCIe slots have ? Thanks and Regards Rafael R. Machado -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New Defects reported by Coverity Scan for coreboot
Hi,
Please find the latest report on new defect(s) introduced to coreboot found
with Coverity Scan.
1 new defect(s) introduced to coreboot found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 1363355:(SIZEOF_MISMATCH)
/src/drivers/intel/fsp2_0/upd_display.c: 37 in fspm_display_arch_params()
/src/drivers/intel/fsp2_0/upd_display.c: 40 in fspm_display_arch_params()
*** CID 1363355:(SIZEOF_MISMATCH)
/src/drivers/intel/fsp2_0/upd_display.c: 37 in fspm_display_arch_params()
31 {
32 /* Display the architectural parameters for MemoryInit */
33 printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n",
34 new);
35 fsp_display_upd_value("Revision", sizeof(old->Revision),
36 old->Revision, new->Revision);
>>> CID 1363355:(SIZEOF_MISMATCH)
>>> Passing argument "old->NvsBufferPtr" of type "void * const" and
>>> argument "4UL /* sizeof (old->NvsBufferPtr) */" to function
>>> "fsp_display_upd_value" is suspicious.
37 fsp_display_upd_value("NvsBufferPtr", sizeof(old->NvsBufferPtr),
38 (uintptr_t)old->NvsBufferPtr,
39 (uintptr_t)new->NvsBufferPtr);
40 fsp_display_upd_value("StackBase", sizeof(old->StackBase),
41 (uintptr_t)old->StackBase,
42 (uintptr_t)new->StackBase);
/src/drivers/intel/fsp2_0/upd_display.c: 40 in fspm_display_arch_params()
34 new);
35 fsp_display_upd_value("Revision", sizeof(old->Revision),
36 old->Revision, new->Revision);
37 fsp_display_upd_value("NvsBufferPtr", sizeof(old->NvsBufferPtr),
38 (uintptr_t)old->NvsBufferPtr,
39 (uintptr_t)new->NvsBufferPtr);
>>> CID 1363355:(SIZEOF_MISMATCH)
>>> Passing argument "old->StackBase" of type "void * const" and argument
>>> "4UL /* sizeof (old->StackBase) */" to function "fsp_display_upd_value" is
>>> suspicious.
40 fsp_display_upd_value("StackBase", sizeof(old->StackBase),
41 (uintptr_t)old->StackBase,
42 (uintptr_t)new->StackBase);
43 fsp_display_upd_value("StackSize", sizeof(old->StackSize),
44 old->StackSize, new->StackSize);
45 fsp_display_upd_value("BootLoaderTolumSize",
To view the defects in Coverity Scan visit,
https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V05UPxvVjWch-2Bd2MGckcRbLuoVetFLSjdonCi1EjfHRqWGQvojmmkYaBE-2BPJiTQvQ-3D-3D_q4bX76XMySz3BXBlWr5fXXJ4cvAsgEXEqC7dBPM7O5bttigs8QtwnKKnhkTIL7bVQSAel3CxsulsREKzUQLrTjrXrFHRfVjxo0x5rk0cIQLSOm6x0PWeFb8SRxBlfYPSFVUI7-2BO2gSCZ0LnNi9KbBggTRTtnyZrD-2B9K03yUrSIQMHHDX0KFKS7oJTYZ03ayIjosRWlCy-2Bk6KGQ7zMu0LBg-3D-3D
To manage Coverity Scan email notifications for "coreboot@coreboot.org", click
https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V05UPxvVjWch-2Bd2MGckcRbVDbis712qZDP-2FA8y06Nq4e-2BpBzwOa5gzBZa9dWpDbzfofODnVj1enK2UkK0-2BgCCqyeem8IVKvTxSaOFkteZFcnohwvb2rnYNjswGryEWCURnUk6WHU42sbOmtOjD-2Bx5c-3D_q4bX76XMySz3BXBlWr5fXXJ4cvAsgEXEqC7dBPM7O5bttigs8QtwnKKnhkTIL7bVhKGrtNAuqb3rQKT6xl5AX4sbp4A-2FlPxkxGSPDx-2B14y53aHTJF0bVHS0S1KrBDdJSaL-2BePvKJzOKrHzQ9CEmXJ4bgny9PB84-2Bd3wz38OwbAth0cZHM-2Bi-2B8s18lR88t0c6fsrUDIcrlH5gBBc367YOEw-3D-3D
--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] where to put info about linux payload and kgpe-d16
Am 30.09.2016 9:09 vorm. schrieb "Paul Menzel via coreboot" < coreboot@coreboot.org>: > If not, that means, if it’s also related to for example QEMU, I’d > create a page *Linux Payload* or so. Generic information about Linux payloads could also be put in documentation/ in the source tree as markdown text. Patrick -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] where to put info about linux payload and kgpe-d16
Dear Ron, Am Donnerstag, den 29.09.2016, 20:09 + schrieb ron minnich: > I'd lke to track some things I'm learning about linux paylaod on kgpe-d16 > > I'm thinking of keep track of > working linux ref and a working .config > working coreboot ref and a working .config > > I'm not quite sure where in the wiki this belongs; ideas anyone? If it’s really ASUS KGPE-D16 related, that as a subpage of the board page. If not, that means, if it’s also related to for example QEMU, I’d create a page *Linux Payload* or so. > reon Did you change your name? :P Thanks, Paul signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
