[coreboot] TALOS project short of funding goals - where to now?
I am incredibly sad that TALOS has not gotten the required cash flow, short of a miracle in the next few days. The coreboot project is pretty much dead in the water without it, the only real choices for further development are either super low power crappy ARM devices or always going to be expensive IBM/TYAN POWER servers, so what do we do? I am wondering, how come they didn't bark up some government or corporate trees for TALOS funding? AFIAK there are various government agencies interested in secure hardware and assured computing; I have always wondered what the NSA uses for their own computing needs, maybe they paid intel for firmware source code and a system that doesn't need ME to run. The way things are going: +10 years - Microsoft and Intel have announced the "PrivaSec" initiative, aimed at producing a secure vertically intergrated computing platform where firmware agents prohibit the execution of unapproved programs - protecting your data from unauthorized access. +20 years - We're sorry, but the GlobeX Trade Agreement and the Secure Communities act of 2035 prohibit the viewing, copying or transmission of this file - Further violations may result in fine, arrest and or the revocation of your work permit and internet operators license. Thoughts: It seems that so many linux people just don't really care about libre anything, considering that the average linux sysadmin makes over $100K per year the community could have easily funded the project. These days there are a lot more people with skills, but without the computer enthusiast/hacker culture of the 90's, the kind of hypocritical people who use a macbook, facebook, etc but who chide me for saying that working for the government is not at all immoral. If I wasn't unemployed I would happily pay $5K for a high performance libre computer, but not everyone is me. People went nuts for the faux libre purism laptop but talos gets hardly any comparative publicity/hype - why? - "We'll get intel to open up ME one day, we promise!" -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] CPU Turbo [KGPE-D16]
On 12/09/2016 09:51 AM, Timothy Pearson wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 12/08/2016 11:20 PM,taii...@gmx.com wrote: I am wondering as to: * Why 6274 cpu refuses to turbo to the second turbo state with half of the cores in use (it stops around 100mhz before the first turbo state) The CPU will not turbo to the highest frequency unless half the cores are in the CC6 power state. Have you verified that the CC6 power saving mode is enabled via nvramtool? * Is it possible to force enable second turbo state for all cpu cores, assuming adequate cooling? Or is it controlled on the CPU itself? This is controlled by a black box on the CPU die itself. There is no way to override the settings of this black box unless you have an engineering sample (obtaining one at this point is illegal in at least the United States). We do have some experience overclocking the Opteron systems through other methods, but won't discuss further outside of a development contract. Off topic but would rather not make another thread: * Does NUMA ram alignment matter performance wise with only one physical CPU? (RAM being split half and half per core set at the moment) Yes! The G34 CPUs are actually two dies in one package, with 4 sticks of RAM attached to each node (making 8 sticks per package for the KGPE-D16). * Does anyone know where I could get a reasonably priced 6287SE or 6284SE? or (even better) an engineering model of 62xx? Those are rare chips and very expensive. See above for engineering samples; they're not legal here so I would have no idea. I hope this helps! - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -BEGIN PGP SIGNATURE- Version: GnuPG v1 Comment: Using GnuPG with Mozilla -http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJYSsThAAoJEK+E3vEXDOFbSdkH/RJ5dJrN4a3dGopOqYWt3FSr OeIk/SYh6JtiuyUeLV4XMwSbXOTgAEsRGKj2Dt/o0LZZnjkVOm1OaXKfn5K9+0iZ Ec4ae142KjIolNbgl1re3BY7MqW2QCiSqBCsOBmqzYXu1Ypi9IevzfpXDnilToJW sBzwA33kp3Xk7ldtMAIYjtp9ys9z6KSwAJwPJHd6f9aIGmpzh1Gdw2AQeF9wbplf DJLY9xup4SRCns922r/Z93eat34QGb7PZy+1oz8nWAojk+y5JFbRNMTCtjdzAbM5 tPVQykNTfBGQoeV+hL0NmukAJmJDWaCnkOsJTD01WpCKDLIIKf8N6ShxS6Qi1Ds= =DUK+ -END PGP SIGNATURE- Thanks! helpful as always >:D Yes c states and cc6 states are enabled, 1 or 2 cores can get up to around 100mhz or so less than turbo 2 however I cannot get the whole advertised 8 or even 4 (i get max around 2.5ghz as reported by "cpupower monitor" ), my temp is 35C with full load cpu usage and my fans nearly off (tower cooler) so I don't think that could be the issue. - Do mismatched cpus work at their native clock speeds? What would happen if I inserted for instance a 6220 in to the second cpu socket. -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dealing with PCI reset
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 12/11/2016 03:48 PM, Paul Menzel via coreboot wrote: > Dear coreboot folks, > > > Several devices using the Intel 945 chipset copied code for PCI reset, > costing 200 ms of boot time. > > ``` > /* Force PCIRST# */ > pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); > udelay(200 * 1000); > pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); > ``` > > The change-set Ia37d9f0ecf5655531616edb20b53757d5d47b42f [1] removes > that code from the Lenovo X60. > > That code was added for some crypto card on a Roda device. > > My question is, if removing that code is fine, or if it should be left > in and be made configurable (Kconfig/NVRAM)? > > Are there often cases where there are extensions card with problems, > that need such a PCI reset? We have run into this issue on the KGPE-D16 and LSI SAS controllers. However, in this case it's not so much the reset itself as it is the time it takes for the card to start up and become ready for PCI scan. We handled this with a devicetree.cb option to set a delay between reset and PCI scan. Perhaps something similar could be used in this instance? - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -BEGIN PGP SIGNATURE- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJYTcspAAoJEK+E3vEXDOFbbzQH/34G9MP0fpe5a83ifoXu20Dq 12GLduOIsknFdYoe45yBHwKCsejJPrc4cMYjv7cYMHVP1Ujlu9UoKVyMN4IiAGTK i5fIvjyMsDh8XB4zngBoffhZUckvIwxiCvIojMhkUebRB04j+nYluZgpFNNHPo1B vOZtAXP1Vst6qc82fid9U2b5gWOyTNgaTxCdf9FeKFGdIKoW14Gn3c1o3TJN88hf CTsDAamKGs2ZPINbfX5VIrlQL+ft87I+Az5IpwJKY4Vy8JA4L5AgNHnaMrTYKyu2 GbGtNTORjGij5XSTrDWTZxBa0oLzpLkNzvCWZBqohSwIv1L5p2NOUtgTvRc7AS0= =uoXv -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Dealing with PCI reset
Dear coreboot folks, Several devices using the Intel 945 chipset copied code for PCI reset, costing 200 ms of boot time. ``` /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); udelay(200 * 1000); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); ``` The change-set Ia37d9f0ecf5655531616edb20b53757d5d47b42f [1] removes that code from the Lenovo X60. That code was added for some crypto card on a Roda device. My question is, if removing that code is fine, or if it should be left in and be made configurable (Kconfig/NVRAM)? Are there often cases where there are extensions card with problems, that need such a PCI reset? Thanks, Paul [1] https://review.coreboot.org/17703 signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
