Re: [coreboot] Coreboot at Apollo Lake Oxbohill CRB
On 02/25/2017 11:52 AM, Gailu Singh wrote: Thank you once again for your help and support. Managed to build the coreboot 16MB image with FSP, ifwi and descriptor.bin and flashed it on the board. When power-on board, I see Red LED (DS3B1) is ON that seems to be some error. User guide only provide description of 4 LEDs (DS6B1, DS2C1, DS6B2, D5L1) so I assume red led is indicating some error condition. Currently: DS6B1 : Green ON DS6B2 : Green ON DS2C1 : OFF DS3B1 : RED ON No Output on serial console or HDMI. Red light is never a good sign. Do you have a way to know if PLTRST# has been de-asserted? Another thing is that when you stitch with FIT you need to turn off boot guard completely. I suspect you have it on and that makes CSE to check signatures. Please check that in Platform protection -> Bootguard configuration it is set to "bootguard profile 0 - legacy". Then try restitching fit image and rebuilding coreboot again. - Andrey -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot at Apollo Lake Oxbohill CRB
Thank you once again for your help and support. Managed to build the coreboot 16MB image with FSP, ifwi and descriptor.bin and flashed it on the board. When power-on board, I see Red LED (DS3B1) is ON that seems to be some error. User guide only provide description of 4 LEDs (DS6B1, DS2C1, DS6B2, D5L1) so I assume red led is indicating some error condition. Currently: DS6B1 : Green ON DS6B2 : Green ON DS2C1 : OFF DS3B1 : RED ON No Output on serial console or HDMI. On Sun, Feb 26, 2017 at 12:42 AM, Andrey Petrov wrote: > On 02/25/2017 11:05 AM, Gailu Singh wrote: > > Thanks Andrey, > > Manage to extract required blob with SplitFspBin.py.' I have prebuilt > IFWI binary. only missing part is to find/generate correct descriptor.bin. > > just dd if=fitimage.bin bs=4096 count=1 of=descriptor.bin > where fitimage.bin is output from FIT tool. > > -Andrey > -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot at Apollo Lake Oxbohill CRB
On 02/25/2017 11:05 AM, Gailu Singh wrote: Thanks Andrey, Manage to extract required blob with SplitFspBin.py.' I have prebuilt IFWI binary. only missing part is to find/generate correct descriptor.bin. just dd if=fitimage.bin bs=4096 count=1 of=descriptor.bin where fitimage.bin is output from FIT tool. -Andrey -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot at Apollo Lake Oxbohill CRB
Thanks Andrey, Manage to extract required blob with SplitFspBin.py.' I have prebuilt IFWI binary. only missing part is to find/generate correct descriptor.bin. On Sun, Feb 26, 2017 at 12:20 AM, Andrey Petrov wrote: > > On 02/25/2017 02:48 AM, Gailu Singh wrote: > > >>you need a bunch of blobs (of course), most importantly fitimage.bin and > >>fsp. > > >>Please use https://review.coreboot.org/#/c/18479/3 as starting point. > >>That is for Leafhill. But once you apply that patch, select mainboard > >>intel/leafhill in 'make nconfig', put the sacred blobs in the designated > >>location and 'make' should give you flashable coreboot.rom. > > I pulled the leafhill patches and yes I get options to specify FSP when > selected leafhill. However not clear about the difference between FSP-M.fv > and FSP-S.fv. I have FSP.bsf and FSP.fd files for FSP. Can you please let me > know how to create required FSP blob from FSP.bsf and FSP.fd files? > > You need to use script to break the big blob into smaller blobs: > https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/ > Tools/SplitFspBin.py > > $ SplitFspBin.py split FSP.fd > > Here is some video on FSP2.0 and what blobs does what: > > https://www.youtube.com/watch?v=uzfiTiP9dEM&feature=youtu.be > > Here is formal FSP2.0 spec: > > http://www.intel.com/content/www/us/en/embedded/software/ > fsp/fsp-architecture-spec-v2.html > > Best, > Andrey > -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot at Apollo Lake Oxbohill CRB
On 02/25/2017 02:48 AM, Gailu Singh wrote: >>you need a bunch of blobs (of course), most importantly fitimage.bin and fsp. >>Please usehttps://review.coreboot.org/#/c/18479/3 as starting point. >>That is for Leafhill. But once you apply that patch, select mainboard >>intel/leafhill in 'make nconfig', put the sacred blobs in the designated >>location and 'make' should give you flashable coreboot.rom. I pulled the leafhill patches and yes I get options to specify FSP when selected leafhill. However not clear about the difference between FSP-M.fv and FSP-S.fv. I have FSP.bsf and FSP.fd files for FSP. Can you please let me know how to create required FSP blob from FSP.bsf and FSP.fd files? You need to use script to break the big blob into smaller blobs: https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/Tools/SplitFspBin.py $ SplitFspBin.py split FSP.fd Here is some video on FSP2.0 and what blobs does what: https://www.youtube.com/watch?v=uzfiTiP9dEM&feature=youtu.be Here is formal FSP2.0 spec: http://www.intel.com/content/www/us/en/embedded/software/fsp/fsp-architecture-spec-v2.html Best, Andrey -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot at Apollo Lake Oxbohill CRB
> I pulled the leafhill patches and yes I get options to specify FSP when > selected leafhill. However not clear about > the difference between FSP-M.fv and FSP-S.fv. I have FSP.bsf and FSP.fd files > for FSP. Can you please let me know > how to create required FSP blob from FSP.bsf and FSP.fd files? FSP-M: MRC code FSP-S: Silicon init code > I have built coreboot image for Apollo Lake and trying to boot Oxbohill CRB > but no console or display at HDMI port. Good Luck with your build! ;-) Zoran PS. Tiho, Andrei. Potihon6ky, ponjatno. Esli M(R)C zametit6 tebja, koecto mozet slucitsja, esli on tebja (prezde vsego) NE pozvolil hozjataistvovat6 zdes6. ;-) Elki Palki (Kopalki)! Udaci! Zoran On Sat, Feb 25, 2017 at 11:48 AM, Gailu Singh wrote: > >>you need a bunch of blobs (of course), most importantly fitimage.bin and > >>fsp. > > >>Please use https://review.coreboot.org/#/c/18479/3 as starting point. > >>That is for Leafhill. But once you apply that patch, select mainboard > >>intel/leafhill in 'make nconfig', put the sacred blobs in the designated > >>location and 'make' should give you flashable coreboot.rom. > > > I pulled the leafhill patches and yes I get options to specify FSP when > selected leafhill. However not clear about the difference between FSP-M.fv > and FSP-S.fv. I have FSP.bsf and FSP.fd files for FSP. Can you please let me > know how to create required FSP blob from FSP.bsf and FSP.fd files? > > > > On Sat, Feb 25, 2017 at 10:49 AM, Gailu Singh wrote: > >> Hi Experts, >> >> I have built coreboot image for Apollo Lake and trying to boot Oxbohill >> CRB but no console or display at HDMI port. >> >> My coreboot.rom details >> >> Name Offset Type Size >> cbfs master header 0x0cbfs header 32 >> fallback/romstage 0x80 stage28268 >> cpu_microcode_blob.bin 0x6f40 microcode0 >> fallback/ramstage 0x6fc0 stage65343 >> config 0x16f40raw 291 >> revision 0x170c0raw 569 >> fallback/postcar 0x17340stage16916 >> fallback/dsdt.aml 0x1b5c0raw 99 >> fallback/payload 0x1b680payload 361265 >> (empty)0x73a00null 443544 >> mrc.cache 0xdfec0mrc_cache65536 >> (empty)0xeff00null 32664 >> bootblock 0xf7ec0bootblock32768 >> >> This is an 8 MB image, I flashed it to SPI flash at address 0. When I >> boot the board no output is observed either on USB serial console or on >> HDMI display. >> >> Do I need to add something more to see at least coreboot log. I am tryng >> to use GRUB2 as payload to coreboot. >> >> Thanks >> >> > > -- > coreboot mailing list: coreboot@coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot at Apollo Lake Oxbohill CRB
>>you need a bunch of blobs (of course), most importantly fitimage.bin and fsp. >>Please use https://review.coreboot.org/#/c/18479/3 as starting point. >>That is for Leafhill. But once you apply that patch, select mainboard >>intel/leafhill in 'make nconfig', put the sacred blobs in the designated >>location and 'make' should give you flashable coreboot.rom. I pulled the leafhill patches and yes I get options to specify FSP when selected leafhill. However not clear about the difference between FSP-M.fv and FSP-S.fv. I have FSP.bsf and FSP.fd files for FSP. Can you please let me know how to create required FSP blob from FSP.bsf and FSP.fd files? On Sat, Feb 25, 2017 at 10:49 AM, Gailu Singh wrote: > Hi Experts, > > I have built coreboot image for Apollo Lake and trying to boot Oxbohill > CRB but no console or display at HDMI port. > > My coreboot.rom details > > Name Offset Type Size > cbfs master header 0x0cbfs header 32 > fallback/romstage 0x80 stage28268 > cpu_microcode_blob.bin 0x6f40 microcode0 > fallback/ramstage 0x6fc0 stage65343 > config 0x16f40raw 291 > revision 0x170c0raw 569 > fallback/postcar 0x17340stage16916 > fallback/dsdt.aml 0x1b5c0raw 99 > fallback/payload 0x1b680payload 361265 > (empty)0x73a00null 443544 > mrc.cache 0xdfec0mrc_cache65536 > (empty)0xeff00null 32664 > bootblock 0xf7ec0bootblock32768 > > This is an 8 MB image, I flashed it to SPI flash at address 0. When I boot > the board no output is observed either on USB serial console or on HDMI > display. > > Do I need to add something more to see at least coreboot log. I am tryng > to use GRUB2 as payload to coreboot. > > Thanks > > -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [RFC] Always include coreboot banner in console independent of log level
Dear Martin, dear Julius, Am Freitag, den 24.02.2017, 16:41 -0700 schrieb Martin Roth: > My argument is that if nothing at all is shown, its difficult to know if > that's because nothing needs to be shown, or because the console is busted. That was my original motivation too. The image for QEMU with log level WARNING, didn’t print anything to the console, so I didn’t know if QEMU was called incorrectly, or if there was another problem with the build. > Maybe we break up the banner, and don't print both romstage and > ramstage banners, but just the romstage banner. I'd say that just printing > the coreboot version should be sufficient, especially since the build date > is based on the commit id: > > So at loglevel 0, we get: > coreboot-4.5-1079-g613350897d But can’t the version for romstage and ramstage differ? (Though very unlikely.) > At loglevel 5 (or whatever) we get the additional text: With the current definitions, it should be log level 6 (INFO). 5 (NOTICE) is “Normal but significant conditions.”, while 6 (INFO) is “Informational messages.”. (No idea how “significant” condition is defined.) >coreboot-4.5-1079-g613350897d Fri Feb 24 14:59:42 UTC 2017 romstage > starting... Julius, do you have any measurements, how much time printing 100 characters over the serial console would take? Also, does that really matter for production systems? What log level are they normally shipped with? Thanks, Paul signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] x220 tablet flash chip
-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 hi, can someone with an X220 Tablet tell me whether it's wson or soic8? - -- Leah Rowe Libreboot developer Use free software. Free as in freedom. https://en.wikipedia.org/wiki/Free_software Use a free operating system, GNU+Linux. https://libreboot.org/docs/distros/ Or BSD: https://libreboot.org/docs/bsd/ Use a free BIOS. https://libreboot.org/ Support computer user freedom. https://peers.community/ Minifree Ltd, trading as Ministry of Freedom | Registered in England, No. 9361826 | VAT No. GB202190462 Registered Office: 19 Hilton Road, Canvey Island, Essex SS8 9QA, UK | Web: https://minifree.org/ -BEGIN PGP SIGNATURE- iQEzBAEBCAAdFiEE+JRrnG26iGmvPhSA/0W3TPnRz5QFAlixSTwACgkQ/0W3TPnR z5Q23Qf9HVtILM/6shbAQGNdhIFQV7eTSPp25JVBAx2yY8PTlaedmipT0zaESalE v7UM7eV3egYsFYZHSPylx/v+WlWEDPb4bHkAYeAwiv3RCFx7phwk3MX2kr8Zq6UJ LifULv9LLyA1SZPZqB8v5+BfuCfJS22u1k4VVqSc/PyZENxtEU5KBObo6v4YRvW9 GhrQhslfUtkFrl6XyBjnrxqaKlSYoMy80LUWm5WThNgDOuOZSVwM36cuNdlsc2VI xj/t9ccHX0qftUVVx4rvAKPYGvtPCT/J9Dalo4qxsOxOt8AJ6eb7T+70rS5X39wY 812nI8G3cqWiwCaZqm22g2zZxQmEgQ== =j43+ -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
