[coreboot] Intel NIC security
Is it worth figuring out how to externally re-flash grey market "intel" nics - or is the onboard NVM flash unable to do anything too terrible? In the newer (the 3 digit i/x series like i350, x540 etc) nics intel has added a "security" flash write protect feature so I imagine their flash stuff isn't as potentially innocent as in the older chips. If so does anyone how to do this? How is this dealt with from a coreboot onboard NIC perspective? Obvious stuff applies, such as a general NIC exploit leading to a WAN>LAN pivot bypassing IOMMU if both WAN and LAN are processed on the same chip but that isn't what I am referring to. You may find this interesting: https://www.servethehome.com/investigating-fake-intel-i350-network-adapters/ When this news first came out there was a conspiracy theory started on the pfsense forums and a lot of smart people bought in to the idea that they were some kind of foreign intelligence agency scheme to spy on american companies (I myself know a few important corps that use DIY routers, so it could be true) -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dell Precision M4600 support
On 06/09/2017 05:20 PM, Zoran Stojsavljevic wrote: What was your question here, or I missed something??? ;-) Zoran I believe he read the part on the wiki about asking if a pc is supported, it requests one posts that info. OP - it is not supported but you could port it although IMO it wouldn't be worth the effort as you'd have to write code for a new Super I/O as well. I would simply replace it with a comparable ThinkPad W530, and put in the better "thinkpad classic" non-chiclet W520 keyboard/palmrest. It is just as nice and it has better linux support as everyone has one. -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot + Seabios Asus F2A85-M LE card
It takes some skill to extract a vgabios from official BIOS image, in some cases (for some types of the official BIOS) it is hardly doable. I recommend that you follow this path - https://www.coreboot.org/VGA_support#Retrieval_via_Linux_kernel Install the official BIOS image again, then boot Linux and extract vgabios using these steps mentioned at the link above. Good luck 2017-06-09 16:41 GMT+03:00 Gabriel Bosque : > Okay. I tried a path, which I thought was the most practical, but I have a > problem: > _I downloaded the .cap file from the card in Asus site > _Using the UEFITool draw for asus.rom > _By using ./bios_extract asus.rom, it gives msg: > Error: Unable to detect BIOS Image type. > Any tips? > > 2017-06-08 12:19 GMT-03:00 Piotr Kubaj : >> >> https://www.coreboot.org/VGA_support >> >> On 17-06-08 11:01:55, Gabriel Bosque wrote: >> > Internal. Where do I find firmware for it? >> > >> > Tanks in advance >> > >> > 2017-06-08 10:45 GMT-03:00 Piotr Kubaj : >> > >> > > Do you use the internal GPU or external? If you use internal, you >> > > probably >> > > need firmware from AMD (SeaVGABIOS won't work). If you have external >> > > GPU, >> > > you don't need VGA option ROM at all. >> > > >> > > Anyway, you don't need SeaVGABIOS. >> > > >> > > You also put CONFIG_QEMU_HARDWARE=y, which is unnecessary. >> > > >> > >> > -- >> > This message has been scanned for viruses and >> > dangerous content by MailScanner, and is >> > believed to be clean. >> > >> >> -- >> >> / No matter where I go, the place is \ >> \ always called "here". / >> >> \ ^__^ >> \ (oo)\___ >> (__)\ )\/\ >> ||w | >> || || > > > > -- > coreboot mailing list: coreboot@coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dell Precision M4600 support
What was your question here, or I missed something??? ;-) Zoran On Fri, Jun 9, 2017 at 5:22 PM, Valentine Levshuk wrote: > > >1. Dell Precision M4600 laptop: > > -- CPU: Intel Core i7-2860QM > > -- SouthBridge: Intel Cougar Point QM67 > > -- NorthBridge: Intel Sandy Bridge-MB IMC > > -- MXM 3.0a graphics slot, 2x Mini Pci-e, 1x Mini Pci-e combined with > mSATA, 1x Expresscard slot. > > > >1. “lspci -tvnn” output: > > > > -[:00]-+-00.0 Intel Corporation 2nd Generation Core Processor Family > DRAM Controller [8086:0104] > >+-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] > Venus XTX [Radeon HD 8890M / R9 M275X/M375X] [1002:6820] > >|\-00.1 Advanced Micro Devices, Inc. [AMD/ATI] > Cape Verde/Pitcairn HDMI Audio [Radeon HD 7700/7800 Series] [1002:aab0] > >+-16.0 Intel Corporation 6 Series/C200 Series Chipset Family > MEI Controller #1 [8086:1c3a] > >+-16.3 Intel Corporation 6 Series/C200 Series Chipset Family > KT Controller [8086:1c3d] > >+-19.0 Intel Corporation 82579LM Gigabit Network Connection > [8086:1502] > >+-1a.0 Intel Corporation 6 Series/C200 Series Chipset Family > USB Enhanced Host Controller #2 [8086:1c2d] > >+-1b.0 Intel Corporation 6 Series/C200 Series Chipset Family > High Definition Audio Controller [8086:1c20] > >+-1c.0-[02]-- > >+-1c.2-[03-08]-- > >+-1c.3-[09]00.0 NEC Corporation uPD720200 USB 3.0 Host > Controller [1033:0194] > >+-1c.4-[0a]00.0 Broadcom Limited BCM4360 802.11ac Wireless > Network Adapter [14e4:43a0] > >+-1c.7-[0b-12]--+-00.0 O2 Micro, Inc. OZ600 1394a-2000 > Controller [1217:11f7] > >| +-00.1 O2 Micro, Inc. OZ600RJ1/OZ900RJ1 SD/MMC > Card Reader Controller [1217:8320] > >| \-00.2 O2 Micro, Inc. OZ600 MS/xD Controller > [1217:8330] > >+-1d.0 Intel Corporation 6 Series/C200 Series Chipset Family > USB Enhanced Host Controller #1 [8086:1c26] > >+-1f.0 Intel Corporation QM67 Express Chipset Family LPC > Controller [8086:1c4f] > >+-1f.2 Intel Corporation 82801 Mobile SATA Controller [RAID > mode] [8086:282a] > >\-1f.3 Intel Corporation 6 Series/C200 Series Chipset Family > SMBus Controller [8086:1c22] > > > >1. Superiotools found SMSC FDC37C93xFR >2. Winbond SOIC8 soldered two flash chips: 1x 8Mb and 1x2Mb – 10240 Kb >in total >3. Motherboard schematics: https://1drv.ms/b/s! >AooKL5SiajFyioJPEP1Jla85VqPy3w > > > > -- > coreboot mailing list: coreboot@coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot > -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Where to buy the KCMA-D8? *brand new*
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/22/2017 04:40 PM, taii...@gmx.com wrote: > Does anyone know? I have checked everywhere > I can't find the accessories for the board family either (TPM etc) > > I would just get another KGPE-D16 but I want to make a router with one > of the 35W C32 "EE" opterons and the retail price is a little cheaper. > > > And does anyone know how much longer they are making the KGPE-D16? I > wanna buy more before they stop (I could get arm or power, but I still > need x86 to play video games) I suppose it is possible to port to > another better available similar board like something from supermicro > (H8DGI-way, way better specs, first released 2014) but I have no idea > how complex that is. Complexity isn't the main issue; the fact that the H8DGi appears to have a proprietary, non-removable BMC is a far larger issue for truly blob-free operation. We could port coreboot to something like the H8DGi for a fairly reasonable cost, but again the result likely won't be truly blob-free (or may be missing significant functionality) so the utility of anyine funding such a port is still in question. We're still heavily invested in POWER and will likely have some very good news for advocates of owner-controlled systems in the coming months, so I'd really encourage people to evaluate whether they really *need* x86 or whether they might consider a cheap x86 gaming-only machine plus an OpenPOWER machine for "real work". - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -BEGIN PGP SIGNATURE- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJZOwwhAAoJEK+E3vEXDOFbNnAH/AwBDLwOCxzYGM9jpS4Xf41z 3QxDVdIh/8mqMEUFb51Cen/8Mk1a5pxWnVhHVyb1034wPVJ1PXU9bqDpmpvoZFCn fRfmO5usUhE2+eSPycPNnIvg2GOcmdNMYiA20Ki4Ysr9iodgHLwnEiQruqpllPNp 0kEk92CDP4k9OUioKjg2aoFLyTd09S5Ue009nj+dcU+uApTubejQKf+pbBioCYRg jIHmLQ045ZVlG1rB99OGnj4k2iGt7eQ96HTHpkiKqJz7XbVx+D1cOjQlMtL9w9ty GJoFHdgElgccQTDSaE1lzVSDlc4jW/z1VUXI1VSpi2pyFYLFGhwS3Ki+vRuarcg= =g3iv -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ASUS KFSN4-DRE Automated Test Failure [master]
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 06/09/2017 02:06 PM, Nico Huber wrote: > On 09.06.2017 17:27, Raptor Engineering Automated Coreboot Test Stand wrote: >> The ASUS KFSN4-DRE fails verification for branch master as of commit >> 43dcbfd85581de4f173953282a4917c1ee9a5922 >> >> The following tests failed: >> VIDEO_FAILURE > > May be fixed with https://review.coreboot.org/#/c/20131/. REACTS didn't > tell me (yet). Behaviour is still different from before the Kconfig > changes: SeaVGABIOS (cbvga) is now always included, also when running > in text mode (it seems there wasn't any VGA BIOS run before on REACTS, > don't know if SeaBIOS displayed anything at all in this config?). > > Nico It looks like the recent Gerrit updates broke the REACTS Gerrit integration. We're working on a fix and should have the main system back up and running, along with patches for those with existing support contracts, by early next week. Sorry for the temporary breakage, and thanks for working on a fix for the video failure! - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -BEGIN PGP SIGNATURE- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJZOwyVAAoJEK+E3vEXDOFbWv4IAJtcWvxZSvp6fG+BJRx6EY3Q z2tXGmXa7IPGTle8hp4teoxyXLjKi29o4fsQzSqbabWWUivyNBLJpylD91rHG6/9 QLYHFQQ4XZQJoHIq+BDcAHOSGO8rJpN37bnOvrmefTcFmFYxu1GSlm+lrozvqgL9 1kbdfdfQL7hDcfHWN3APXc+A31S0asyqa3b0J0K1kDkcXxhYEzcgcv2rgx4VBm3D uzNDv0nmxabkxTovPSAYBCB/3pqX7xpuFlRWvbqUIlt5FPkGtTbGKNJDpo9XgJp/ HGQ1nbyhqFwSpbnYPYSgfcxfu25uYlCAfsAMiPbPCtHfqF3yT9UWh7q0OrIXKKk= =31p+ -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ASUS KFSN4-DRE Automated Test Failure [master]
On 09.06.2017 17:27, Raptor Engineering Automated Coreboot Test Stand wrote: > The ASUS KFSN4-DRE fails verification for branch master as of commit > 43dcbfd85581de4f173953282a4917c1ee9a5922 > > The following tests failed: > VIDEO_FAILURE May be fixed with https://review.coreboot.org/#/c/20131/. REACTS didn't tell me (yet). Behaviour is still different from before the Kconfig changes: SeaVGABIOS (cbvga) is now always included, also when running in text mode (it seems there wasn't any VGA BIOS run before on REACTS, don't know if SeaBIOS displayed anything at all in this config?). Nico > > Commits since last successful test: > 43dcbfd soc/braswell: fix ACPI table by recollecting TOLM > debb785 purism/librem13v2: Update PCI config > 0ff3b73 purism/librem13v2: Don't disable PM timer > 9d8cd50 purism/librem13v2: Enable SATA, disable eMMC support > 6b8570d purism/librem13v2: Add microcode values in Kconfig > > <24 commits skipped> > > 2e7f6cc fsp/gop: Add running the GOP to the choice of gfx init > d4ebeaf device/Kconfig: Put gfx init methods into a `choice` > 26ce9af device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INIT > eb881d4 3rdparty/libgfxinit: Update submodule pointer > 7b79a33 3rdparty/libhwbase: Update submodule pointer > > See attached log for details > > This message was automatically generated from Raptor Engineering's ASUS > KFSN4-DRE test stand > Want to test on your own equipment? Check out > https://www.raptorengineering.com/content/REACTS/intro.html > > Raptor Engineering also offers coreboot consulting services! Please visit > https://www.raptorengineering.com for more information > > Please contact Timothy Pearson at Raptor Engineering > regarding any issues stemming from this > notification > > > -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] riscv: How to debug (王翔)
On Fri, Jun 09, 2017 at 12:47:59PM +0800, 王翔 wrote: > On Friday,June 9, 2017 at 12:34 PM,王翔 wrote: [...] > >I get source frome https://github.com/riscv/riscv-tools.git. > >Compare the difference with https://github.com/riscv/riscv-isa-sim/pull/53 > >and fix the code. > >The difference of Our patch is **UART_BASE**. You use 0x0210, me use > >0x40001000. > >In my test 0x40001000 can be work with **coreboot**, but 0x0210 can not. > >My patch is in the attachment of the message. > > > I'm sorry. I not change **uintptr_t uart_platform_base(int idx)** I've updated https://github.com/riscv/riscv-isa-sim/pull/53 and uploaded a coreboot patch to use the new UART address¹: https://review.coreboot.org/#/c/20126/ > >>What did you test? How did it fail? > > > >I test by **spike**. I have report the patch. > >https://review.coreboot.org/#/c/20043/ > >https://review.coreboot.org/#/c/20105/ > > > But these bugs still exist. Thank you for these patches. Regards, Jonathan Neuschäfer ¹) It wasn't strictly necessary to change the UART address, but I think 0x0210 fits better into the current address map. The old patch is available at https://github.com/neuschaefer/riscv-isa-sim/commits/uart-old-v1. signature.asc Description: PGP signature -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] ASUS KFSN4-DRE Automated Test Failure [master]
The ASUS KFSN4-DRE fails verification for branch master as of commit 43dcbfd85581de4f173953282a4917c1ee9a5922 The following tests failed: VIDEO_FAILURE Commits since last successful test: 43dcbfd soc/braswell: fix ACPI table by recollecting TOLM debb785 purism/librem13v2: Update PCI config 0ff3b73 purism/librem13v2: Don't disable PM timer 9d8cd50 purism/librem13v2: Enable SATA, disable eMMC support 6b8570d purism/librem13v2: Add microcode values in Kconfig <24 commits skipped> 2e7f6cc fsp/gop: Add running the GOP to the choice of gfx init d4ebeaf device/Kconfig: Put gfx init methods into a `choice` 26ce9af device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INIT eb881d4 3rdparty/libgfxinit: Update submodule pointer 7b79a33 3rdparty/libhwbase: Update submodule pointer See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering regarding any issues stemming from this notification 1497021898-0-automaster.log.bz2 Description: application/bzip2 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] Dell Precision M4600 support
1. Dell Precision M4600 laptop: -- CPU: Intel Core i7-2860QM -- SouthBridge: Intel Cougar Point QM67 -- NorthBridge: Intel Sandy Bridge-MB IMC -- MXM 3.0a graphics slot, 2x Mini Pci-e, 1x Mini Pci-e combined with mSATA, 1x Expresscard slot. 1. “lspci -tvnn” output: -[:00]-+-00.0 Intel Corporation 2nd Generation Core Processor Family DRAM Controller [8086:0104] +-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] Venus XTX [Radeon HD 8890M / R9 M275X/M375X] [1002:6820] |\-00.1 Advanced Micro Devices, Inc. [AMD/ATI] Cape Verde/Pitcairn HDMI Audio [Radeon HD 7700/7800 Series] [1002:aab0] +-16.0 Intel Corporation 6 Series/C200 Series Chipset Family MEI Controller #1 [8086:1c3a] +-16.3 Intel Corporation 6 Series/C200 Series Chipset Family KT Controller [8086:1c3d] +-19.0 Intel Corporation 82579LM Gigabit Network Connection [8086:1502] +-1a.0 Intel Corporation 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #2 [8086:1c2d] +-1b.0 Intel Corporation 6 Series/C200 Series Chipset Family High Definition Audio Controller [8086:1c20] +-1c.0-[02]-- +-1c.2-[03-08]-- +-1c.3-[09]00.0 NEC Corporation uPD720200 USB 3.0 Host Controller [1033:0194] +-1c.4-[0a]00.0 Broadcom Limited BCM4360 802.11ac Wireless Network Adapter [14e4:43a0] +-1c.7-[0b-12]--+-00.0 O2 Micro, Inc. OZ600 1394a-2000 Controller [1217:11f7] | +-00.1 O2 Micro, Inc. OZ600RJ1/OZ900RJ1 SD/MMC Card Reader Controller [1217:8320] | \-00.2 O2 Micro, Inc. OZ600 MS/xD Controller [1217:8330] +-1d.0 Intel Corporation 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #1 [8086:1c26] +-1f.0 Intel Corporation QM67 Express Chipset Family LPC Controller [8086:1c4f] +-1f.2 Intel Corporation 82801 Mobile SATA Controller [RAID mode] [8086:282a] \-1f.3 Intel Corporation 6 Series/C200 Series Chipset Family SMBus Controller [8086:1c22] 1. Superiotools found SMSC FDC37C93xFR 2. Winbond SOIC8 soldered two flash chips: 1x 8Mb and 1x2Mb – 10240 Kb in total 3. Motherboard schematics: https://1drv.ms/b/s!AooKL5SiajFyioJPEP1Jla85VqPy3w -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot + Seabios Asus F2A85-M LE card
Okay. I tried a path, which I thought was the most practical, but I have a problem: _I downloaded the .cap file from the card in Asus site _Using the UEFITool draw for asus.rom _By using ./bios_extract asus.rom, it gives msg: Error: Unable to detect BIOS Image type. Any tips? 2017-06-08 12:19 GMT-03:00 Piotr Kubaj : > https://www.coreboot.org/VGA_support > > On 17-06-08 11:01:55, Gabriel Bosque wrote: > > Internal. Where do I find firmware for it? > > > > Tanks in advance > > > > 2017-06-08 10:45 GMT-03:00 Piotr Kubaj : > > > > > Do you use the internal GPU or external? If you use internal, you > probably > > > need firmware from AMD (SeaVGABIOS won't work). If you have external > GPU, > > > you don't need VGA option ROM at all. > > > > > > Anyway, you don't need SeaVGABIOS. > > > > > > You also put CONFIG_QEMU_HARDWARE=y, which is unnecessary. > > > > > > > -- > > This message has been scanned for viruses and > > dangerous content by MailScanner, and is > > believed to be clean. > > > > -- > > / No matter where I go, the place is \ > \ always called "here". / > > \ ^__^ > \ (oo)\___ > (__)\ )\/\ > ||w | > || || > -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] New Defects reported by Coverity Scan for coreboot
Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1375986:(NEGATIVE_RETURNS) /src/mainboard/google/link/i915.c: 281 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 287 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 291 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 297 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 304 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 310 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 315 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 318 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 324 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 329 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 332 in i915lightup_sandy() *** CID 1375986:(NEGATIVE_RETURNS) /src/mainboard/google/link/i915.c: 281 in i915lightup_sandy() 275 vsync = (mode->va + mode->vso - 1) | 276 ((mode->va + mode->vso + mode->vspw - 1) << 16); 277 printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync); 278 279 printk(BIOS_SPEW, "Table has %d elements\n", niodefs); 280 >>> CID 1375986:(NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 281 index = run(0); 282 printk(BIOS_SPEW, "Run returns %d\n", index); 283 auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_DPCD_REV << 8|0xe; 284 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14); 285 auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; 286 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); /src/mainboard/google/link/i915.c: 287 in i915lightup_sandy() 281 index = run(0); 282 printk(BIOS_SPEW, "Run returns %d\n", index); 283 auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_DPCD_REV << 8|0xe; 284 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14); 285 auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; 286 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); >>> CID 1375986:(NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 287 index = run(index); 288 printk(BIOS_SPEW, "Run returns %d\n", index); 289 auxout[0] = 0 << 31 /* i2c */|0 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; 290 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); 291 index = run(index); 292 printk(BIOS_SPEW, "Run returns %d\n", index); /src/mainboard/google/link/i915.c: 291 in i915lightup_sandy() 285 auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; 286 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); 287 index = run(index); 288 printk(BIOS_SPEW, "Run returns %d\n", index); 289 auxout[0] = 0 << 31 /* i2c */|0 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; 290 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); >>> CID 1375986:(NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 291 index = run(index); 292 printk(BIOS_SPEW, "Run returns %d\n", index); 293 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_SET_POWER << 8|0x0; 294 auxout[1] = 0x0100; 295 /* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */ 296 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); /src/mainboard/google/link/i915.c: 297 in i915lightup_sandy() 291 index = run(index); 292 printk(BIOS_SPEW, "Run returns %d\n", index); 293 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_SET_POWER << 8|0x0; 294 auxout[1] = 0x0100; 295 /* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */ 296 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); >>> CID 1375986:(NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 297 index = run(index); 298 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8; 299 auxout[1] = 0x0a84; 300 /*( DP_LINK_BW_2_7 &0xa)|0x840a*/ 301 auxout[2] = 0x; 302 auxout[3] = 0x0100; /src/mainboard/google/link/i915.c: 304 in i915lightup_sandy() 298 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8; 299 auxout[1] = 0x0a84; 300 /*( DP_LINK_BW_2_7 &0xa)|0x840a*
