Re: [coreboot] Intel G41 - Asrock G41M-GS: no coreboot screen output from Intel GPU on VGA
On 16.08.2018 12:27, h...@memeware.net wrote: > On 2018-08-15 21:22, Nico Huber wrote: >> Hi, >> >> On 14.08.2018 13:41, h...@memeware.net wrote: >>> So it seems to have detected that my screen is 1920*1080. GPU + screen >>> detection seems to be working. But i dont get any coreboot output on the >>> screen. >> >> you can set CONFIG_DEBUG_ADA_CODE to enable verbose messages in >> libgfxinit. At least this would show if the GFX hardware is indeed >> enabled or if it bails out for some reason. >> >> When you set drm.debug=6 in your kernel command line, there'll also >> be a lot of information in the log about what configuration Linux >> finds before (re)initializing graphics. >> >> Hope that helps, >> Nico > > The new additional output: > > [...] > Looks all good to me. If you'd provide a full log (including SeaBIOS) with loglevel `Debug`, that might help to trace it down. Please also attach your .config (just to be sure, I know you used the defaults but those can change between code revisions). Nico -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Building an image a second/third/... time fails
On 16.08.2018 12:47, h...@memeware.net wrote: > I have not changed anything. I was able to reproduce that every single > time i tried. Ah, sorry I wasn't referring to the error but to your mail's subject. The "second/third/... time fails" (as opposed to the first time) because you changed parameters (maybe outside of coreboot or in the config). That's what I was trying to tell you. If you wanted help with the error, you should have told so. It's a known incompatibility of older SeaBIOS versions with current IASL. I guess, SeaBIOS master should build fine. Nico -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] Updated invitation with note: community meeting @ Every 4 weeks from 10:00 to 11:00 on Thursday from Thu Aug 17, 2017 to Wed Aug 15 (PDT) (coreboot@coreboot.org)
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Re: [coreboot] Building an image a second/third/... time fails
I have not changed anything. I was able to reproduce that every single
time i tried.
rm -r coreboot
git clone coreboot
build buildchain
build corebot image for g41m-gs (ONLY open make menuconfig, choose
model, press esc and save)
rm .coreboot*
try to build image for gigabyte g41 board (ONLY open make menuconfig,
choose model, press esc and save)
It fails with the written error every single time.
On 2018-08-15 21:26, Nico Huber wrote:
On 14.08.2018 12:49, h...@memeware.net wrote:
I had build once a coreboot image for a Intel G41 board. Then i liked
to
build for an other Intel G41 board.
It looks like you either used an older IASL for this initial build or
chose a different SeaBIOS version.
Nico
I first removed the config: rm .config*
then i ran again 'make menuconfig'
chose the other Intel G41 board and ran 'make'.
I got this error:
.
Compile checking out/src/fw/smm.o
Compile checking out/src/fw/smp.o
Compile checking out/src/fw/mtrr.o
Compile checking out/src/fw/xen.o
Compiling IASL src/fw/ssdt-misc.hex
out/src/fw/ssdt-misc.dsl.i 4: DefinitionBlock ("ssdt-misc.aml",
"SSDT", 0x01, "BXPC", "BXSSDTSUSP", 0x1)
Error 6155
-
Invalid OEM Table ID ^ (Length cannot exceed 8 characters)
ASL Input: out/src/fw/ssdt-misc.dsl.i - 102 lines, 2567 bytes, 35
keywords
Listing File: out/src/fw/ssdt-misc.lst - 8393 bytes
Hex Dump: out/src/fw/ssdt-misc.hex - 4096 bytes
Compilation complete. 1 Errors, 0 Warnings, 0 Remarks, 2 Optimizations
Makefile:254: recipe for target 'src/fw/ssdt-misc.hex' failed
make[2]: *** [src/fw/ssdt-misc.hex] Error 255
Makefile:80: recipe for target 'build' failed
make[1]: *** [build] Error 2
payloads/external/Makefile.inc:85: recipe for target 'seabios' failed
make: *** [seabios] Error 2>
I then removed the config with rm .config* ran again 'make
menuconfig'
and chose again the board that i was able to build an image before
some
minutes with a warning (
https://mail.coreboot.org/pipermail/coreboot/2018-August/087162.html
).
Then i ran 'make'.
Now i also get for that board the issue i have copied above. This
Compiling IASL src/fw/ssdt-misc.hex failed again. But it was probably
working before because i had got an image.
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Re: [coreboot] Intel G41 - Asrock G41M-GS: no coreboot screen output from Intel GPU on VGA
On 2018-08-15 21:22, Nico Huber wrote: Hi, On 14.08.2018 13:41, h...@memeware.net wrote: So it seems to have detected that my screen is 1920*1080. GPU + screen detection seems to be working. But i dont get any coreboot output on the screen. you can set CONFIG_DEBUG_ADA_CODE to enable verbose messages in libgfxinit. At least this would show if the GFX hardware is indeed enabled or if it bails out for some reason. When you set drm.debug=6 in your kernel command line, there'll also be a lot of information in the log about what configuration Linux finds before (re)initializing graphics. Hope that helps, Nico The new additional output: coreboot: [23.031272] Trying to enable port Analog [23.035086] HW.GFX.GMA.Registers.Is_Set_Mask: GMCH_PFIT_CONTROL [23.040719] HW.GFX.GMA.Registers.Read: 0x2000 <- 0x00061230:GMCH_PFIT_CONTROL [23.047998] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting [23.053371] HW.GFX.GMA.PLLs.Alloc [23.056404] HW.GFX.GMA.PLLs.On [23.059324] Valid clock found. [23.062019] Best/Target/Delta: 14880/14850/30. [23.067219] HW.GFX.GMA.PLLs.Program_DPLL [23.070859] HW.GFX.GMA.Registers.Write: 0x00021507 -> 0x6040:GMCH_FPA0 [23.077445] HW.GFX.GMA.Registers.Write: 0x00021507 -> 0x6044:GMCH_FPA1 [23.084031] HW.GFX.GMA.Registers.Write: 0x14020c00 -> 0x6014:GMCH_DPLL_A [23.090791] HW.GFX.GMA.Registers.Set_Mask: 0x8000 .S GMCH_DPLL_A [23.096858] HW.GFX.GMA.Registers.Read: 0x14020c00 <- 0x6014:GMCH_DPLL_A [23.103618] HW.GFX.GMA.Registers.Write: 0x94020c00 -> 0x6014:GMCH_DPLL_A [23.110378] HW.GFX.GMA.Registers.Read: 0x94020c00 <- 0x6014:GMCH_DPLL_A [23.117289] HW.GFX.GMA.Registers.Read: 0x <- 0x00061114:PORT_HOTPLUG_STAT [23.124485] HW.GFX.GMA.Connectors.Pre_On [23.128126] HW.GFX.GMA.Pipe_Setup.On [23.131419] HW.GFX.GMA.Transcoder.Setup [23.134972] HW.GFX.GMA.Registers.Write: 0x0897077f -> 0x0006:HTOTAL_A [23.141471] HW.GFX.GMA.Registers.Write: 0x0897077f -> 0x00060004:HBLANK_A [23.147971] HW.GFX.GMA.Registers.Write: 0x080307d7 -> 0x00060008:HSYNC_A [23.154385] HW.GFX.GMA.Registers.Write: 0x04640437 -> 0x0006000c:VTOTAL_A [23.160884] HW.GFX.GMA.Registers.Write: 0x04640437 -> 0x00060010:VBLANK_A [23.167383] HW.GFX.GMA.Registers.Write: 0x0440043b -> 0x00060014:VSYNC_A [23.173796] HW.GFX.GMA.Pipe_Setup.Setup_FB [23.177609] HW.GFX.GMA.Registers.Write: 0x -> 0x00070080:CUR_CTL_A [23.184196] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A [23.190783] HW.GFX.GMA.Registers.Write: 0x -> 0x00070084:CUR_BASE_A [23.197456] HW.GFX.GMA.Pipe_Setup.Setup_Display [23.201701] HW.GFX.GMA.Registers.Unset_And_Set_Mask: GMCH_VGACNTRL [23.207595] HW.GFX.GMA.Registers.Read: 0x8000 <- 0x00071400:GMCH_VGACNTRL [23.214528] HW.GFX.GMA.Registers.Write: 0x008e -> 0x00071400:GMCH_VGACNTRL [23.221462] HW.GFX.GMA.Registers.Write: 0x027f018f -> 0x0006001c:PIPEASRC [23.227960] HW.GFX.GMA.Registers.Is_Set_Mask: GMCH_PFIT_CONTROL [23.233594] HW.GFX.GMA.Registers.Read: 0x2000 <- 0x00061230:GMCH_PFIT_CONTROL [23.240873] HW.GFX.GMA.Registers.Write: 0x8800 -> 0x00061230:GMCH_PFIT_CONTROL [23.248154] HW.GFX.GMA.Registers.Write: 0x -> 0x00070080:CUR_CTL_A [23.254740] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A [23.261327] HW.GFX.GMA.Registers.Write: 0x -> 0x00070084:CUR_BASE_A [23.267999] HW.GFX.GMA.Registers.Write: 0x8000 -> 0x00070008:PIPEACONF [23.274586] HW.GFX.GMA.Registers.Read: 0xc000 <- 0x00070008:PIPEACONF [23.281172] HW.GFX.GMA.Connectors.Post_On [23.284899] HW.GFX.GMA.GMCH.VGA.On [23.288019] HW.GFX.GMA.Registers.Unset_And_Set_Mask: FDI_TX_CTL_B [23.293824] HW.GFX.GMA.Registers.Read: 0x <- 0x00061100:FDI_TX_CTL_B [23.300671] HW.GFX.GMA.Registers.Write: 0x8018 -> 0x00061100:FDI_TX_CTL_B [23.307518] Enabled port Analog PCI: 00:02.0 init finished in 1614701 usecs PCI: 00:02.1 init ... PCI: 00:02.1 init finished in 2010 usecs Linux Kernel 4.18.1 (updated for this test to use latest kernel): [3.435445] [drm:i915_driver_load [i915]] No PCH found. [3.435488] [drm:intel_wopcm_init_early [i915]] WOPCM size: 1024KiB [3.435530] [drm:intel_uc_init_early [i915]] enable_guc=0 (submission:no huc:no) [3.435571] [drm:intel_uc_init_early [i915]] guc_log_level=0 (enabled:no, verbose:no, verbosity:0) [3.435609] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00 [3.436282] [drm:i915_driver_load [i915]] ppgtt mode: 0 [3.478646] [drm:i915_ggtt_probe_hw [i915]] GGTT size = 2048M [3.478685] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M [3.478723] [drm:i915_ggtt_probe_hw [i915]] DSM size = 64M [3.478803] fb: switching to inteldrmfb from EFI VGA [3.485009] [drm] Replacing VGA console driver [3.485250] [drm:i915_gem_init_stolen [i915]] ELK_STOLEN_RESERVED = [3.485290] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 65536K [
Re: [coreboot] Build fails on Thinkpad W520
Same problem with T420 and i5-3380 CPU.Сommenting lines 210 and 215:printram("OTHP Workaround [%x] = %x\n", addr, reg);and printram("OTHP [%x] = %x\n", addr, reg);in src/northbridge/intel/sandybridge/raminit_common.c (function static void dram_odt_stretch)will resolve the error. 16.08.2018, 09:27, "Andreas Restle" :Building coreboot for Thinkpad W520 currently fails with the following error: CC romstage/northbridge/intel/sandybridge/raminit_common.oIn file included from src/northbridge/intel/sandybridge/raminit_common.c:18:src/northbridge/intel/sandybridge/raminit_common.c: In function 'dram_odt_stretch':src/northbridge/intel/sandybridge/raminit_common.c:211:49: error: 'reg' undeclared (first use in this function); did you mean 'prog'? printram("OTHP Workaround [%x] = %x\n", addr, reg); ^~~src/include/console/console.h:65:31: note: in definition of macro 'printk' do { do_printk(LEVEL, fmt, ##args); } while (0) ^~~~src/northbridge/intel/sandybridge/raminit_common.c:211:3: note: in expansion of macro 'printram' printram("OTHP Workaround [%x] = %x\n", addr, reg); ^~~~src/northbridge/intel/sandybridge/raminit_common.c:211:49: note: each undeclared identifier is reported only once for each function it appears in printram("OTHP Workaround [%x] = %x\n", addr, reg); ^~~src/include/console/console.h:65:31: note: in definition of macro 'printk' do { do_printk(LEVEL, fmt, ##args); } while (0) ^~~~src/northbridge/intel/sandybridge/raminit_common.c:211:3: note: in expansion of macro 'printram' printram("OTHP Workaround [%x] = %x\n", addr, reg); ^~~~make: *** [Makefile:339: build/romstage/northbridge/intel/sandybridge/raminit_common.o] Fehler 1 I've been using coreboot on the W520 for some time now, thanks to Charlotteplusplus and Nico Rikken (thank you both!). This is the first time I encountered this error. Branch master, freshly pulled of git. Thinkpad W520, 32GB Ram, i7-3940XM (Ivybridge). Any help is much appreciated. --<°)))>
Re: [coreboot] Build fails on Thinkpad W520
commit 9fe248fb removes the use of addr and reg variable in this function,
that's why this code doesn't compile with CONFIG_DEBUG_RAM_SETUP.
I've submitted a fix for this:
https://review.coreboot.org/#/c/coreboot/+/28117/
or remove the printram statement?
On Thu, Aug 16, 2018 at 4:27 PM, Andreas Restle
wrote:
> Hi Nico,
>
> thanks for the quick reply. If it’s on, it must have been by accident.
> I’ll check later today and report back.
>
> Building with the same .config worked fine two weeks ago though. But your
> last sentence probably is an explanation for that.
>
> Viele Grüße
>
> Andreas Restle
>
>
> --
> <°)))><
> Andreas Restle
> andreas.res...@gmail.com
>
> On 16. Aug 2018, at 10:10, Nico Huber wrote:
>
> Hi Andreas,
>
> On 16.08.2018 08:25, Andreas Restle wrote:
>
> Building coreboot for Thinkpad W520 currently fails with the following
>
> error:
>
>
>CC romstage/northbridge/intel/sandybridge/raminit_common.o
>
> In file included from src/northbridge/intel/sandybridge/raminit_common.c:
> 18:
>
> src/northbridge/intel/sandybridge/raminit_common.c: In function
>
> 'dram_odt_stretch':
>
> src/northbridge/intel/sandybridge/raminit_common.c:211:49: error: 'reg'
>
> undeclared (first use in this function); did you mean 'prog'?
>
> printram("OTHP Workaround [%x] = %x\n", addr, reg);
>
>
> it seems you have CONFIG_DEBUG_RAM_SETUP enabled. This is really only
> for debugging and nothing for end users / production builds. Debugging
> code is often broken (even when it does compile).
>
> Nico
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
>
--
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Re: [coreboot] Build fails on Thinkpad W520
Hi Nico,
thanks for the quick reply. If it’s on, it must have been by accident. I’ll
check later today and report back.
Building with the same .config worked fine two weeks ago though. But your last
sentence probably is an explanation for that.
Viele Grüße
Andreas Restle
--
<°)))><
Andreas Restle
andreas.res...@gmail.com
> On 16. Aug 2018, at 10:10, Nico Huber wrote:
>
> Hi Andreas,
>
>> On 16.08.2018 08:25, Andreas Restle wrote:
>> Building coreboot for Thinkpad W520 currently fails with the following
>> error:
>>
>>CC romstage/northbridge/intel/sandybridge/raminit_common.o
>> In file included from src/northbridge/intel/sandybridge/raminit_common.c:18:
>> src/northbridge/intel/sandybridge/raminit_common.c: In function
>> 'dram_odt_stretch':
>> src/northbridge/intel/sandybridge/raminit_common.c:211:49: error: 'reg'
>> undeclared (first use in this function); did you mean 'prog'?
>> printram("OTHP Workaround [%x] = %x\n", addr, reg);
>
> it seems you have CONFIG_DEBUG_RAM_SETUP enabled. This is really only
> for debugging and nothing for end users / production builds. Debugging
> code is often broken (even when it does compile).
>
> Nico
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Re: [coreboot] Build fails on Thinkpad W520
Hi Andreas,
On 16.08.2018 08:25, Andreas Restle wrote:
> Building coreboot for Thinkpad W520 currently fails with the following
> error:
>
> CC romstage/northbridge/intel/sandybridge/raminit_common.o
> In file included from src/northbridge/intel/sandybridge/raminit_common.c:18:
> src/northbridge/intel/sandybridge/raminit_common.c: In function
> 'dram_odt_stretch':
> src/northbridge/intel/sandybridge/raminit_common.c:211:49: error: 'reg'
> undeclared (first use in this function); did you mean 'prog'?
>printram("OTHP Workaround [%x] = %x\n", addr, reg);
it seems you have CONFIG_DEBUG_RAM_SETUP enabled. This is really only
for debugging and nothing for end users / production builds. Debugging
code is often broken (even when it does compile).
Nico
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Re: [coreboot] L1TF
Hi, On 15.8.2018 15:58, Shawn wrote: According to the vulnerability analysis, the SMM is affected by L1TF. Since SMM code base in coreboot is much smaller than OEM's firmware, IMOHO L1TF is not practical on coreboot. Any idea about is coreboot vulnerable to L1TF? You need an updated microcode, so the RSM will flush L1 cache (if L1D flush is advertised) else perhaps you will need as a workaround read at least 64KB of memory (L1 is 32KB but replacement policy is "not exactly LRU") also, you need to make sure that that all SMM cores will enter SMM same time. I don't remember how coreboot does that on Intel chips. Perhaps it is so. Remember that with L1TF you can only read any secrets which could be stored in L1. If coreboot has no secrets there, you don't need to do anything. Modification of data is not possible with this attack. Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] Build fails on Thinkpad W520
Building coreboot for Thinkpad W520 currently fails with the following
error:
CC romstage/northbridge/intel/sandybridge/raminit_common.o
In file included from src/northbridge/intel/sandybridge/raminit_common.c:18:
src/northbridge/intel/sandybridge/raminit_common.c: In function
'dram_odt_stretch':
src/northbridge/intel/sandybridge/raminit_common.c:211:49: error: 'reg'
undeclared (first use in this function); did you mean 'prog'?
printram("OTHP Workaround [%x] = %x\n", addr, reg);
^~~
src/include/console/console.h:65:31: note: in definition of macro 'printk'
do { do_printk(LEVEL, fmt, ##args); } while (0)
^~~~
src/northbridge/intel/sandybridge/raminit_common.c:211:3: note: in
expansion of macro 'printram'
printram("OTHP Workaround [%x] = %x\n", addr, reg);
^~~~
src/northbridge/intel/sandybridge/raminit_common.c:211:49: note: each
undeclared identifier is reported only once for each function it appears in
printram("OTHP Workaround [%x] = %x\n", addr, reg);
^~~
src/include/console/console.h:65:31: note: in definition of macro 'printk'
do { do_printk(LEVEL, fmt, ##args); } while (0)
^~~~
src/northbridge/intel/sandybridge/raminit_common.c:211:3: note: in
expansion of macro 'printram'
printram("OTHP Workaround [%x] = %x\n", addr, reg);
^~~~
make: *** [Makefile:339:
build/romstage/northbridge/intel/sandybridge/raminit_common.o] Fehler 1
I've been using coreboot on the W520 for some time now, thanks to
Charlotteplusplus and Nico Rikken (thank you both!). This is the first
time I encountered this error.
Branch master, freshly pulled of git. Thinkpad W520, 32GB Ram, i7-3940XM
(Ivybridge).
Any help is much appreciated.
--
<°)))><
Andreas Restle
andreas.res...@gmail.com
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