[coreboot] Re: GSoC 23 - Contributor Introduction
Dear all, I have drafted my GSoC proposal and uploaded it to Google Docs. You can leave suggestions as comments in the document. https://docs.google.com/document/d/1SktYJUou7MtPIhnATjVoM63HDKIkZcBRRKtcO0pVpCs/edit?usp=sharing I'm a bit unclear about how to break down the edk2 porting into discrete tasks, so your suggestion on that would help me a lot. Please have a look at it and let me know what you think. I apologize for not giving you much time for this review. Regards, Utkarsh On Sat, Apr 1, 2023 at 8:02 PM Utkarsh Verma via coreboot wrote: > > Dear all, > > With some time and consideration, I have decided that I would like to > take up the project "Port edk2 or U-Boot payloads to ARM or AArch64". > I would prefer to develop something for AArch64 since I have a > Raspberry Pi 4 Model B with me. However, before that, I need clarity > on the time commitment of the project. I would love to take up the > task of porting any payload which I could finish within 175 hours. > Also, what does "the UI part" correspond to U-Boot porting to > coreboot? Would that involve working on the TUI? In case both of these > would require more than 175 hours, I would like to take up porting > EDK2 to AArch64. > > Therefore, I look forward to hearing from potential mentors regarding the > same. > > Best regards, > Utkarsh Verma > > > On Sun, Mar 19, 2023 at 5:41 PM Utkarsh Verma via coreboot > wrote: > > > > Dear all, > > > > My name is Utkarsh Verma and I am a final-year undergraduate student. > > I want to participate in this year's GSoC and contribute to coreboot. > > This is not the first time I've found out about the coreboot project. > > I stumbled upon it last year when I wished to change the BIOS on my > > laptop as the vendor BIOS is a bit buggy. Since coreboot didn't > > directly support my laptop, I wanted to work towards adding support > > for it. However, time and skill constraints forced me to leave it for > > later. Now, with GSoC around the corner, I believe is the perfect time > > for me to work towards this goal. > > > > I had a look at the list of projects, and found the following to be > > interesting, mentioned in decreasing order of preference: > > > > - Support Power9/Power8 in coreboot > > - Port edk2 or U-Boot payloads to ARM, AArch64 or RISC-V > > - Fix POST code handling > > > > I am completely new to coreboot, however, I do have experience with > > the Linux kernel compilation and patching process on Gentoo. I have > > familiarity with the Assembly language and have done various embedded > > projects for AVR microcontrollers. I would love to make contributions > > to the firmware side of coreboot, and on a personal level, it would be > > really fulfilling to use coreboot on my own machine once I become > > capable of adding support for it through this GSoC internship. > > > > I have mentioned my motivation and interests above, so please let me > > know if I might have misjudged a project or if some other project > > would be more fitting for me. Also, it would be really helpful if you > > could suggest some starter issues for which I could submit some > > patches. > > > > I have attached the serial output of the tutorial below as a plain > > text file, which you may check in any terminal using cat. > > > > Thank you for your time. > > Regards, > > Utkarsh Verma > > ___ > > coreboot mailing list -- coreboot@coreboot.org > > To unsubscribe send an email to coreboot-le...@coreboot.org > ___ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: How can I set up a userspace test for coreboot code in 2023?
Hi Keith, On 02.04.23 15:33, Keith Hui wrote: > Here is the command line I figured would work, gathered with "make -n": > > gcc -Isrc -Isrc/include -Isrc/commonlib/include > -Isrc/commonlib/bsd/include -Ibuild -I3rdparty/vboot/firmware/include > -include src/include/kconfig.h -include src/include/rules.h -include > src/commonlib/bsd/include/commonlib/bsd/compiler.h -I3rdparty > -D__BUILD_DIR__=\"build\" -Isrc/arch/x86/include -D__ARCH_x86_32__ > -Isrc/device/oprom/include -nostdinc -pipe -g -std=gnu11 -nostdlib > -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings > -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wshadow > -Wdate-time -Wtype-limits -Wvla -Wold-style-definition -Wdangling-else > -Wmissing-include-dirs -fno-common -ffreestanding -fno-builtin > -fomit-frame-pointer -fstrict-aliasing -ffunction-sections > -fdata-sections -fno-pie -Wno-packed-not-aligned -fconserve-stack > -Wnull-dereference -Wreturn-type -Wlogical-op -Wduplicated-cond > -Wno-unused-but-set-variable -Werror -Os -Wno-address-of-packed-member > -m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none > -fno-delete-null-pointer-checks -Wlogical-op -march=i686 -mno-mmx > --param asan-globals=0 -D__RAMSTAGE__ -include build/config.h > src/northbridge/intel/i440bx/raminit.c > src/northbridge/intel/i440bx/raminittest.c -o raminittest2023 > > The C test code is attached. I'm seeing two errors, smbus_read_byte() not being declared and missing. For the former, you should build with -D__ROMSTAGE__ (not R*A*MSTAGE). For the latter, I guess it might be better to compile `raminit.c` with the coreboot include paths and your `raminittest.c` with your host headers, i.e. *without* `-nostdinc` and coreboot paths. If that actually works depends a lot on details; it would be best to compile everything with the host's standard headers and only use those coreboot headers that are coreboot specific. However, both kinds of headers are mixed in coreboot's directory structure and some headers in coreboot that have standard names are actually not standard :-/ With separate compilation, I get to fatal error: standalonetest.h: No such file or directory ;) Cheers, Nico ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] How can I set up a userspace test for coreboot code in 2023?
Years ago when I first wrote the 440BX ram init code, I also wrote a
test program that would read some SPD dump files and set up a
simulated environment to run my ram init code in, without actually
flashing a chip. I now have to do it again and I can't seem to get it
to work again. Maybe the build system has changed since then.
I am looking to just compile this program and
nb/intel/i440bx/raminit.c (unmodified beyond patches I'm testing) and
link them together for an executable to run from the command line.
Here is the command line I figured would work, gathered with "make -n":
gcc -Isrc -Isrc/include -Isrc/commonlib/include
-Isrc/commonlib/bsd/include -Ibuild -I3rdparty/vboot/firmware/include
-include src/include/kconfig.h -include src/include/rules.h -include
src/commonlib/bsd/include/commonlib/bsd/compiler.h -I3rdparty
-D__BUILD_DIR__=\"build\" -Isrc/arch/x86/include -D__ARCH_x86_32__
-Isrc/device/oprom/include -nostdinc -pipe -g -std=gnu11 -nostdlib
-Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings
-Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wshadow
-Wdate-time -Wtype-limits -Wvla -Wold-style-definition -Wdangling-else
-Wmissing-include-dirs -fno-common -ffreestanding -fno-builtin
-fomit-frame-pointer -fstrict-aliasing -ffunction-sections
-fdata-sections -fno-pie -Wno-packed-not-aligned -fconserve-stack
-Wnull-dereference -Wreturn-type -Wlogical-op -Wduplicated-cond
-Wno-unused-but-set-variable -Werror -Os -Wno-address-of-packed-member
-m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none
-fno-delete-null-pointer-checks -Wlogical-op -march=i686 -mno-mmx
--param asan-globals=0 -D__RAMSTAGE__ -include build/config.h
src/northbridge/intel/i440bx/raminit.c
src/northbridge/intel/i440bx/raminittest.c -o raminittest2023
The C test code is attached.
Any suggestions is appreciated.
Thanks
Keith
#include
#include
#include
#include
#include
#include
#include
#include
#include "standalonetest.h"
enum timestamp_id {
TS_START_ROMSTAGE = 1,
TS_BEFORE_INITRAM = 2,
TS_AFTER_INITRAM = 3,
};
void timestamp_add_now(enum timestamp_id id);
#include
#include "i440bx.h"
#include "raminit.h"
#include
int smbus_read_byte(u8 device, u8 address);
void udelay(unsigned int usecs) {}
int do_printk(int msg_level, const char *fmt, ...)
__attribute__((format(printf, 2, 3)));
// #define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args)
#define printk(level, fmt, args...) printf(fmt, ##args)
void die(const char *fmt, ...);
void * pcicfgspace;
u8 pci_read_config8(u32 dev, u16 where)
{
u8 * p = (u8 *)pcicfgspace+where;
return *p;
}
u16 pci_read_config16(u32 dev, u16 where)
{
u16 * p = (u16 *)pcicfgspace+where;
return *p;
}
void pci_write_config8(u32 dev, u16 where, u8 value)
{
u8 * p = (u8 *)(pcicfgspace+where);
*p=value;
}
void pci_write_config16(u32 dev, u16 where, u16 value)
{
u16 * p = (u16 *)(pcicfgspace+where);
*p=value;
}
/* void dump_spd_registers(void)
{
int i;
printf("\n");
for (i = 0; i < DIMM_SOCKETS; i++) {
unsigned int device;
device = DIMM0 + i;
if (device) {
int j = 0;
printf("DIMM %d: %02x", i, device);
int c = smbus_read_byte(device, 0);
printf("\n%02x:", 0);
if (c < 0) {
printf("bad device\n");
break;
}
printf(" %02x", c);
for (j = 1; j < c; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
printf("\n%02x:", j);
}
status = smbus_read_byte(device, j);
byte = status & 0xff;
printf(" %02x", byte);
}
printf("\n");
}
}
} */
void dump_pci_device(unsigned dev)
{
int i;
for (i = 0; i <= 255; i++) {
unsigned char val;
val = pci_read_config8(dev, i);
if ((i & 0x0f) == 0)
printf("%02x:", i);
printf(" %02x", val);
if ((i & 0x0f) == 0x0f)
printf("\n");
}
}
u8 * spd_50;
u8 * spd_51;
u8 * spd_52;
u8 * spd_53;
int smbus_read_byte(u8 device, u8 address) {
u8 * spd;
int r = -1;
switch (device) {
case 0x50:
spd = spd_50;
break;
case 0x51:
spd = spd_51;
break;
case 0x52:
spd = spd_52;
break;
case 0x53:
spd = spd_53;
break;
default:
spd = 0;
}
if (spd)
r = spd[address];
return r;
}
unsigned char cmos_read(unsigned char addr) {
return 0;
}
void cmos_write_inner(unsigned char val, unsigned char addr) {}
void timestamp_add_now(enum timestamp_id id) {}
static void bx_powerup(void) {
// u32 * p32;
pcicfgspace = calloc(1,256);
/*
p32 = (u32 *)pcicfgspace + 0;
*p32 = 0x71908086;
p32+=4;
*p32 = 0x216;
p32+=4;
*p32 = 0x602;
p32 = (u32 *)pcicfgspace + 0x10;
*p32 = 0x8;
*(pcicfgspace+0x34) = 0xa0;
*(pcicfgspace+0x58) = 0x3;
*(pcicfgspace+0x72) = 0x2;
*(pcicfgspace+0x73) = 0x38;
*(pcicfgspace+0x7b) = 0x38;
*(pcicfgspace+0x90) = 0x80;
p32 = (u32 *)pcicfgspace + 0xa0;
*p32 = 0x12;
p32 += 4;
*p32 = 0x1f000203;
*/
}
static void freeall(void) {
free(pcicfgspace);
if (spd_50) free(spd_50);
if (spd_51) free(spd_51);
if (spd_52) free(spd_52);
if (spd_53) free(spd_53);
}
/*
int
