[coreboot] GSoC-2014 Coreboot project
Hi, everyone, I've sent a preliminary proposal about Tianocore as coreboot payload. https://www.google-melange.com/gsoc/proposal/review/student/google/gsoc2014/jinyiyan/5629499534213120 I'd like to get more feedback about the goal and the test environment. Thanks! Regards! Jinyi Yan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] GSoC-2014 Coreboot project
Hi, David, When at AsusTek Suzhou, my work is mainly responsible for bios porting and fixing bug. There were four mainboards P5KPL-S, P5QL-E, P5QL-SE, P5QL. All based on Intel platform and AMI Legacy BIOS Core In the second half year of 2008, I worked on pre-development of EFI-BIOS for ASUS mainboard. I wrote a Dual bootblock module and added NTFS support(read only) for AutoRecovery module using AMI Apito platform (based on EFI). Interesting experience, but memories will fade! Details can't be remembered clearly. As Vladimir said, if the chipset is unsupported then writing MRC for it will be a very long and difficult process. If the chipset is supported then adding mainboard support may be a relatively simple task that not sufficient for GSoC. Do we need to write MRC by ourselves in coreboot? Isn't MRC code supported by Intel? If you have experience with UEFI, perhaps you can implement features that are missing in our Tianocore support: http://www.coreboot.org/TianoCore . Implementing UEFI CBFS driver and GOP driver are very clear goal. questions: I don't know whether coreboot or some payload implement common flash interface for flash programming software. If not, why? https://trello.com/b/pEdlwYTb/tiano-payload It seems that Tiano payload is a very activity project. I think I can try my best to implement one feature or twp for the project! Like use a seperate Fv in CBFS as Fault Tolerant Variable Storage Look forward to your kind advice! On 3/20/14, David Hendricks dhend...@google.com wrote: Hi Jinyi, Can you provide more details about your work as a BIOS engineer? As Vladimir said, if the chipset is unsupported then writing MRC for it will be a very long and difficult process. If the chipset is supported then adding mainboard support may be a relatively simple task that not sufficient for GSoC. If you have experience with UEFI, perhaps you can implement features that are missing in our Tianocore support: http://www.coreboot.org/TianoCore . On Wed, Mar 19, 2014 at 6:06 AM, Allen Yan lex...@gmail.com wrote: Hi, I am Jinyi Yan , a second year PhD candidate from Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences. I used to be a mainboard BIOS engineer in ASUS Technology Suzhou Co., Ltd for about two years (2007.7~2009.2). My major now is optoelectronics. But I have a lot of fun while programming, in my heart the working experience of being a BIOS engineer is still very exciting. I think GsoC is a nice platform for me to participate the open source community. When I search the GsoC projects and organizations, the coreboot and flashrom projects are definitely the right choices for me. I have a spare ASUS P5KPL PC at my hand, but the chipset is not in the support list of coreboot project. As Stefan Tauner's suggestion, maybe porting coreboot to new mainboard or implementing advanced coreboot features on exsiting mainboards are nice too. Now I'm not very familiar with the program structure of coreboot, so I expect your guidence and hope to contribute for coreboot and flashrom even if my application is not accpeted. Thanks! Look forward to your kind advice! Regards, Jinyi Yan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] GSoC 2014
Hi, coreboot+seabios running in QEMU output: coreboot-4.0-5656-gb34739b Thu Mar 13 10:37:43 CST 2014 starting... CBMEM region 3fee-3fff (cbmem_check_toc) CBMEM region 3fee-3fff (cbmem_initialize_empty) Adding CBMEM entry as no. 1 Adding CBMEM entry as no. 2 Trying CBFS ramstage loader. CBFS: loading stage fallback/coreboot_ram @ 0x10 (180280 bytes), entry @ 0x10 QEMU debugcon not found [port 0x402] coreboot-4.0-5656-gb34739b Thu Mar 13 10:37:43 CST 2014 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: : enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:01.3: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: : enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:01.3: enabled 1 scan_static_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: enabled CPU_CLUSTER: 0 scanning... QEMU: firmware config interface detected QEMU: max_cpus is 1 CPU: APIC: 00 enabled DOMAIN: scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] ops PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] bus ops PCI: 00:01.0 [8086/7000] enabled PCI: 00:01.1 [8086/7010] ops PCI: 00:01.1 [8086/7010] enabled PCI: 00:01.3 [8086/7113] bus ops Wakeup from ACPI sleep type S5 (PMCNTRL=) PCI: 00:01.3 [8086/7113] enabled PCI: 00:02.0 [1013/00b8] ops PCI: 00:02.0 [1013/00b8] enabled PCI: 00:03.0 [8086/100e] enabled scan_static_bus for PCI: 00:01.0 scan_static_bus for PCI: 00:01.0 done scan_static_bus for PCI: 00:01.3 scan_static_bus for PCI: 00:01.3 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done QEMU: 5 files in fw_cfg QEMU: etc/boot-fail-wait [size=4] QEMU: genroms/kvmvapic.bin [size=9216] QEMU: etc/system-states [size=6] QEMU: etc/pvpanic-port [size=2] QEMU: bootorder [size=0] QEMU: cmos: 1024 MiB RAM below 4G. QEMU: cmos: 0 MiB RAM above 4G. QEMU: reserve ioports 0x0510-0x0511 [firmware-config] QEMU: reserve ioports 0x5658-0x5658 [vmware-port] QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug] QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug] QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0] CBMEM region 3fee-3fff (cbmem_late_set_table) DOMAIN: read_resources bus 0 link: 0 DOMAIN: read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: child on link 0 PCI: 00:00.0 DOMAIN: resource base 0 size 0 align 0 gran 0 limit flags 40040100 index 1000 DOMAIN: resource base 0 size 0 align 0 gran 0 limit flags 40040200 index 1100 DOMAIN: resource base 0 size a align 0 gran 0 limit 0 flags e0004200 index a DOMAIN: resource base c size 3ff4 align 0 gran 0 limit 0 flags e0004200 index b DOMAIN: resource base 510 size 2 align 0 gran 0 limit flags e100 index c DOMAIN: resource base 5658 size 1 align 0 gran 0 limit flags e100 index d DOMAIN: resource base ae00 size 10 align 0 gran 0 limit flags e100 index e DOMAIN: resource base af00 size 20 align 0 gran 0 limit flags e100 index f DOMAIN: resource base afe0 size 4 align 0 gran 0 limit flags e100 index 10 DOMAIN: resource base fec0 size 10 align 0 gran 0 limit flags e200 index 2 DOMAIN: resource base fee0 size 1 align 0 gran 0 limit flags e200 index 3 PCI: 00:00.0 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit flags c100 index 1 PCI: 00:01.0 resource base ff80 size 80 align 0 gran 0 limit 0 flags d200 index 2 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit flags 100 index 20 PCI: 00:01.3 PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit flags d100 index 1 PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit flags d100 index 2 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 200 align 25 gran 25 limit flags 1200 index 10 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit flags 200 index 14 PCI: 00:02.0 resource base 0 size 1 align 16 gran 16 limit flags 2200 index 30
[coreboot] GSoC-2014 Coreboot project
Hi, I am Jinyi Yan , a second year PhD candidate from Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences. I used to be a mainboard BIOS engineer in ASUS Technology Suzhou Co., Ltd for about two years (2007.7~2009.2). My major now is optoelectronics. But I have a lot of fun while programming, in my heart the working experience of being a BIOS engineer is still very exciting. I think GsoC is a nice platform for me to participate the open source community. When I search the GsoC projects and organizations, the coreboot and flashrom projects are definitely the right choices for me. I have a spare ASUS P5KPL PC at my hand, but the chipset is not in the support list of coreboot project. As Stefan Tauner's suggestion, maybe porting coreboot to new mainboard or implementing advanced coreboot features on exsiting mainboards are nice too. Now I'm not very familiar with the program structure of coreboot, so I expect your guidence and hope to contribute for coreboot and flashrom even if my application is not accpeted. Thanks! Look forward to your kind advice! Regards, Jinyi Yan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
