Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
Hello Nico, > you might have to accept that adding VGA compatibility for Windows may > break compatibility with the secondary payloads. That"s not generally > the case but about the last thing that gets tested. From what I have learned so far it seems that the usecase Coreboot + Windows is that common which I can understand as it may sound strange to reduce the possible attacks via BIOS/AMT but then use an OS like Windows. > If you don"t get this setup with SeaBIOS running, there are alterna- > tives. One that comes to mind: Do native GFX init in coreboot, add the > VGA blob (so far your config below) but use GRUB as primary payload and > run SeaBIOS as secondary. You"d have to hand-craft your grub.cfg, some- > thing like four choices: 1. Run your favorite open source OS 2. SeaBIOS > for legacy compatibility 3. coreinfo 4. nvramcui using grub as primary payload (instead of SeaBIOS) means that I have small linux running from my BIOS? honestly this sounds like this is something that can be done by Coreboot Pro's to which I wouldn't count myself yet. As my current Coreboot installation (SeaBIOS + VGA.rom) has not only break secondary payloads but also standby/resume, I want to rebuild my BIOS from scratch - unfortunately I need to wait until I have a new Clip for flashing as my old broke. >> I"ve seen the following option in make nconfig for coreboot under >> "General Setup": │ [*] Include the coreboot .config file into the ROM >> image │ >> QUESTION: How can I extract this .config file? > You can do that with cbfstool, e.g. > $ build/cbfstool build/coreboot.rom extract -n config -f config.txt > where your replace `build/coreboot.rom` with the path of your image and > `config.txt` with the path to the output file. I've done this but the resulting config is very short and doesn't include all settings which have been made in the first place. A good approach might be: 1) Use a recommended config for X230 which will run Linux as OS and 2ndary payloads and Standby/Resume running 2) Change the config slightly to get windows boot running (adding a vga.rom) Then do troubleshooting in case that the boot of secondary payloads and/or Standby/Resume is broken (with an included VGA.rom). This is the config for Coreboot on a X230 which is in the coreboot wiki. Is this the "best practise" configuration or just "a" configuration which has been stored there? https://review.coreboot.org/cgit/board-status.git/tree/lenovo/x230/4.6-938-gb08d73b845/2017-08-01T23_05_52Z/config.txt I tried to build a rom with this config but run into errors when building the ROM. > Another question about your setup, do you configure anything in SeaBIOS > that is not visible from your coreboot .config? Anything GFX related? > splashscreen? VESA mode? I haven't configured SeaBIOS I've just git'ed coreboot, run make nconfig and added SeaBIOS as Payload there. Haven't tweaked any SeaBIOS configs. I have seen that I can also get Seabios via GIT and then use nconfig to adapt that configuration, but this wasn't covered in the wiki for the x230 and as such I have only used the coreboot configuration screen. Any guidance how to build a specific SeaBIOS and how to include this in coreboot? >> [Devices] >> │ Graphics initialization (Use native graphics init) > With this option you let coreboot initialize GFX. But you also let Sea- > BIOS run the VGA BIOS. The former will be completely overrun. I doubt > that it causes your secondary payload trouble, though. Ok, as soon as I have a new flash clip, I will try to investigate this. Which settings to you suggest in "Devices > Graphics initialization"? >> | --> Framebuffer mode (Legacy VGA text mode) >> │ Display >> │ -*- Enable PCIe Common Clock │ >> │ -*- Enable PCIe ASPM >> [*] Add a VGA BIOS image >> │ (./3rdparty/blobs/mainboard/lenovo/x230/pci8086,0166.rom) VGA BIOS >> │ (8086,0166) VGA device PCI IDs >> >> [Generic Drivers] >> │ [*] Serial port on SuperIO > WTF? What is the problem here? Is this a bad choice? I took this from existing documentation without knowing what the last option is. All other optiions >> │ [*] Support Intel PCI-e WiFi adapters >> │ [*] PS/2 keyboard init > Is this required? It"s odd to set it when using SeaBIOS. The PS/2 Keyboard init was suggested in one of the howtos. regarding Intel PCI-e Wifi, I am not sure - I can make a test without this option and look if this has impact to my wifi card. >> │ [*] Enable TPM support >> >> [Console] >> │ [*] Squelch AP CPUs from early console. >> │ [*] Send console output to a CBMEM buffer >> │ (0x2) Room allocated for console output in CBMEM >> │ [*] Send POST codes to an external device >> │ Device to send POST codes to (None) >> │ [*] Send POST codes to an IO port >> │ (0x80) IO port for POST codes >> >> [System tables] >> │ [*] Generate SMBIOS tables >> >> [Payload] >> │ Add a payload (SeaBIOS) ---> │ >> │ SeaBIOS version (1.10.2) ---> │ >> │ (0) PS/2 keyboard controller initialization timeout
Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
Hello Nico, > I suspect some misconfiguration or that something confuses the libpay- > load VGA driver (which these two secondary payload rely on). This might be true, but I don't understand why I can see the SeaBios Menu (Press ESC) and can also use graphical boot (Windows and Qubes OS) but the secondary payloads don't work. Can you check my .config especially the setting for the VGA device? >> If you thing I"ve missed out important steps, I am happy to hear your >> comments. > Don"t think you missed anything [...] But you might do too much already. > Especially flashing anything but the BIOS region when you want to track > down coreboot issues makes things harder to reason about. I had the seconday payloads booting when lynxis did the coreboot flashing. But we flashed without adding a vga-rom so that I couldn't boot into windows. I've extracted the vga rom and then tried to rebuild coreboot, but I seem to miss some configuration to get graphical boot (vga rom) and secondary payload boot running. I've seen the following option in make nconfig for coreboot under "General Setup": │[*] Include the coreboot .config file into the ROM image│ QUESTION: How can I extract this .config file? I could then extract this from my first flashing together with lynxis to see which settings have been applied there. > Please attach your .config file. Nobody can say anything for sure > with-out knowing what you chose. I've attached the config file and will also list the activated options here: (only enabled options are shown): [General Setup] │[*] Use CMOS for configuration values │[*] Compress ramstage with LZMA │[*] Include the coreboot .config file into the ROM image │[*] Create a table of timestamps collected during boot │-*- Build the ramstage to be relocatable in 32-bit address space [Mainboard] │Mainboard vendor (Lenovo) │ Mainboard model (ThinkPad X230) │ ROM chip size (12288 KB (12 MB)) │ (0x40) Size of CBFS filesystem in ROM [Chipset] │ *** CPU *** │ [*] Enable VMX for virtualization │ [*] Set lock bit after configuring VMX │ Include CPU microcode in CBFS (Generate from tree) │ *** Northbridge *** │ -*- Use native raminit │ *** Southbridge *** │ Flash locking during chipset lockdown (Don't lock flash sections) │ [*] Lock down chipset in coreboot │ *** Embedded Controllers *** │ [*] Beep on fatal error │ [*] Flash LEDs on fatal error │*** Intel Firmware *** │ [*] Add Intel descriptor.bin file │ (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin) │ [*] Add Intel ME/TXE firmware │ (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin) │ [*] Verify the integrity of the supplied ME/TXE firmware │ [*] Add gigabit ethernet firmware │ (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin) │ [*] Lock ME/TXE section │ Verified Boot (vboot) │ Bootblock behaviour (Always load fallback) [Devices] │ Graphics initialization (Use native graphics init) | --> Framebuffer mode (Legacy VGA text mode) │ Display │ -*- Enable PCIe Common Clock │ │ -*- Enable PCIe ASPM [*] Add a VGA BIOS image │ (./3rdparty/blobs/mainboard/lenovo/x230/pci8086,0166.rom) VGA BIOS │ (8086,0166) VGA device PCI IDs [Generic Drivers] │ [*] Serial port on SuperIO │ [*] Support Intel PCI-e WiFi adapters │ [*] PS/2 keyboard init │ [*] Enable TPM support [Console] │ [*] Squelch AP CPUs from early console. │ [*] Send console output to a CBMEM buffer │ (0x2) Room allocated for console output in CBMEM │ [*] Send POST codes to an external device │ Device to send POST codes to (None) │ [*] Send POST codes to an IO port │ (0x80) IO port for POST codes [System tables] │ [*] Generate SMBIOS tables [Payload] │ Add a payload (SeaBIOS) ---> │ │ SeaBIOS version (1.10.2) ---> │ │ (0) PS/2 keyboard controller initialization timeout (milliseconds) │ │ [*] Hardware init during option ROM execution │ │ () SeaBIOS config file│ │ () SeaBIOS bootorder file │ │ (-1) SeaBIOS debug level (verbosity) │ │ *** Using default SeaBIOS log level *** │ │ [*] Use LZMA compression for payloads │ │ Secondary Payloads ---> │ [*] Load coreinfo as a secondary payload │ [*] Load nvramcui as a secondary payload [Debugging] all deactivated kind regards [788]# # Automatically generated file; DO NOT EDIT. # coreboot configuration # # # General setup # CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION=""
Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
Hello, after reading the dd howtos it seems that the 12 MB coreboot.rom file can be split like this: # Split first 8MB of coreboot.rom (bottom-chip) dd if=coreboot.rom of=x230-coreboot-8mb.rom bs=1024 count=$[1024*8] skip=0 # Split last 4MB of coreboot.rom (top-chip) dd if=coreboot.rom of=x230-coreboot-4mb.rom bs=1024 count=$[1024*4] skip=$[1024*8] at least this is what I did - while it was good enough that my X230 is booting up I still can't boot the secondary payloads (I have choosen nvramcui and coreinfo). As mentioned I am writing a howto whch is target at a newbie user, who has basic linux skills and has just about coreboot and wants to try it out. I've run the following steps (I've already written the howto which covers more information about each step, but unfortunately I can't access the wiki as an editor, asked for it already). If you thing I've missed out important steps, I am happy to hear your comments. --- on your raspberry pi --- 0) Put External Flash Clip, female jumper cables and Raspberry pi together (kind of a lego thing) 1) Install Raspberian on Pi using Noobs 2) Update Pi and install additional packages including 'flashrom' 3) take keyboard and palmrest of your "coreboot target laptop" (target) off to access the BIOS Chip(s) 4) Connect the BIOS-Clip to BIOS-chips and read the content from your pi (x230-default-part2-4mb.rom / x230-default-part2-8mb.rom) 5) merge the two files into one 12 MB ROM file (x230-default-12mb.rom) --- on your build laptop --- 6) Copy all three files to your "build laptop" (laptop) Build Laptop must run Linux, this howto assumes you are using Ubuntu 16.04.3 LTS (could also be installed on an USB thumbdrive or external harddrive) 7) Download Coreboot from GIT 7) Install UEFITool on laptop 8) Extract VGA BLOB from the x230-default-12mb.rom file save the file in the coreboot/blobs directory (./coreboot/3rdparty/blobs/mainboard/lenovo/x230/pci8086,0166.rom) 9) Build Coreboot Toolchain 10) Compile ifdtool located in the coreboot/utils directory 11) Extract BLOBS from x230-default-12mb.rom using ifdtool save the files in the coreboot/blobs directory (./coreboot/3rdparty/blobs/mainboard/lenovo/x230/descriptor.bin) (./coreboot/3rdparty/blobs/mainboard/lenovo/x230/me.bin) (./coreboot/3rdparty/blobs/mainboard/lenovo/x230/gbe.bin) 11b) [Optionally] Use ME_Cleaner on me.bin file ) (also it seems that ME_Cleaner is included in Coreboot: Coreboot nconfig: Chipset > Add Intel descriptor.bin file > Add Intel ME/TXE firmware --> Strip down the Intel ME/TXE firmware ) I've choosen to leave the me.bin as is until everything is working. 12) Configure Coreboot (make nconfig) choose parameters/features and add the 4 binary blobs (step 8 and 11) 13) build coreboot image (./coreboot/build/coreboot.rom) 14) Split coreboot.rom into two separate files to flash them to your 2 chips (x230-coreboot-8mb.rom and x230-coreboot-4mb.rom) 15) copy both files to your Raspberry Pi --- on your Raspberry pi --- 16) flash both files using flashrom again 17) Reboot target laptop 18) should boot up with coreboot. [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot+SeaBios Boot speed: ~12sec till Grub Boot Screen
Hello Martin, >> You don"t have serial console enabled, so that"s not the issue. >> I would recommend going into the console menu and enabling "Send >> console output to a CBMEM buffer". >> Once you boot to an OS, you"ll be able to see that with cbmem, which >> needs to be run as root. Ok thank you for the idea, as I am running Qubes OS on my X230, I must install coreboot in dom0 (the core vm, where no other software should be running/installed). I think I'll try to use cbmem from an ubuntu which runs on a USB-drive, so that I don't have to touch my Qubes Installation. >> Everything looks ok in the config to me, so I"m not positive what >> the issue is. We"d need to get a bit deeper into things to figure it out. As mentioned my current configuration is far from beeing perfect, as my secondary payloads are shown in the coreboot (escape-key) menu but if I select them, they don't seem to work (blank screen). I think that I've made something wrong splitting the compiled Coreboot.rom on my two Chips (4MB + 12MB) or that I am missing some other configuration steps after I've changed my CBFS from 0x1 to 0x4. If you/someone can provide any guidance here, this would be great. Before I try to reduce the bootup time I'd like to get a fully working coreboot including secondary payloads (mainly to use the "View Timestamps" feature). kind regards [799] On Mon, Sep 25, 2017 at 6:30 PM, One7two99 via coreboot <coreboot@coreboot.org> wrote: > Hello Martin, > > > Original Message > Subject: Re: [coreboot] Coreboot+SeaBios Boot speed: ~12sec till Grub Boot > Screen > Local Time: 25 September 2017 3:53 AM > From: gauml...@gmail.com > > Is serial console enabled? If so, disabling that will speed things up > immensely. > > > To which position in the menuconfig tree are you referencing? > Have disabled all entries under "Console" in menuconfig but still get the > boot delay. > I"ve thecoreboot .config in case that this is helpfull, see attached file. > > > Can you post a miniconfig? Run "make savedefconfig" and post the file > "defconfig"? > > > Sure, at your service: > > $ make savedefconfig && cat defconfig > CONFIG_USE_OPTION_TABLE=y > CONFIG_COLLECT_TIMESTAMPS=y > CONFIG_VENDOR_LENOVO=y > CONFIG_CBFS_SIZE=0x40 > CONFIG_VGA_BIOS=y > CONFIG_VGA_BIOS_FILE="~/my-coreboot/MyROMs/original/vga.rom" > # CONFIG_POST_IO is not set > # CONFIG_POST_DEVICE is not set > CONFIG_BOARD_LENOVO_X230=y > CONFIG_DRIVERS_PS2_KEYBOARD=y > # CONFIG_CONSOLE_CBMEM is not set > CONFIG_CPU_MICROCODE_CBFS_NONE=y > CONFIG_SEABIOS_PS2_TIMEOUT=10 > # CONFIG_DRIVERS_INTEL_WIFI is not set > CONFIG_LPC_TPM=y > # CONFIG_SQUELCH_EARLY_SMP is not set > CONFIG_SEABIOS_MASTER=y > CONFIG_SEABIOS_THREAD_OPTIONROMS=y > CONFIG_COREINFO_SECONDARY_PAYLOAD=y > > Can you post timestamp information so we can see what"s using all the time? > > > Unfortunately not as I haven"t been able to create a 2nd payload in order to > read the timstamps from coreinfo. > Coreinfo is shown in the boot menu when hitting ESC, but after launching, > the screen goes blank and nothing happens. > Maybe this is related to the fact, that I flashed only 4 MB of the Chip(s) > and as such some part of the code is missing (whoch would be in the 8 MB > part of the rom-file)? > > [799] > > -- > coreboot mailing list: coreboot@coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
Hello, as I can always reflash with the stock ROM I've decided to give it a try and splitted the generated 12 MB coreboot.rom as mentioned in my last email: > to flash the upper 4 MB part of the BIOS: > dd of=x230-4mb.rom bs=1M if=build/coreboot.rom skip=8 > to flash the 8 mb chip I'll try: > dd of=x230-8mb.rom bs=1M if=build/coreboot.rom count=8 After flashing those files to both chips the Laptop boots up fine and I can boot Qubes and also Windows including graphics. Unfortunately the two added Payloads are not working: I get only a black backlight illuminated blank screen when hitting ESC and choosing one of the secondary Payloads. My guess is, that something with the CBFS filesize is not correct, I've set it to 0x40. Any idea how to investigate this problem further? [799] Question: Is the above approach correct? I tried so already once but it didn't work (short flashing of Power-On-button -> nothing more) [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
> Original Message > Subject: Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work > Local Time: 26 September 2017 12:49 PM > UTC Time: 26 September 2017 10:49 > From: one7tw...@protonmail.com > > Next step is to clean the flashregion_2_intel_me.bin (me.bin) with me_cleaner > which is describe well. It seems that ME_cleaner is now included in Coreboot looking at the options in menuconfig. As such I asssume I don't need to manually clean flashregion_2_intel_me.bin (me.bin) The extracted Blobs are located at ./3rdparty/blobs/mainboard/lenovo/x230 and have been proper renamed and I have enabled the options under "Chipset": *** Intel Firmware *** [*] Add Intel descriptor.bin file (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin) [ ] Configure IFD for EM100 usage [*] Add Intel ME/TXE firmware (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin) [*] Verify the integrity of the supplied ME/TXE firmware │ [*] Strip down the Intel ME/TXE firmware [*] Add gigabit ethernet firmware (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin) I have enlarged the CBFS under coreboot nconfig in "Mainboard" ROM chip size (12288 KB (12 MB)) (0x10) Size of CBFS filesystem in ROM 0x10 wasn't enough, so I tried 0x20 which was enough to add corinfo as secondary payload. Adding also nvramcui would need a bigger CBFS. The later works if I increase the size of CBFS to 0x40, as such I've proceed with this CBFS size. I've read https://www.coreboot.org/CBFS but honestly, this information is currently more than I can understand (not a hardware hacker :-). When I look at the picture from me_cleaner... https://camo.githubusercontent.com/3ea0ff670edb94372124ad0c36bd5e2b3c522f7e/687474703a2f2f6f6936352e74696e797069632e636f6d2f3130726e3132642e6a7067 ... the pictures explains to me that the Chips consists of several "areas": Descriptor / GbE Blob / ME Firmware Blob / BIOS Is the CBFS something like a "container" within the BIOS, which would mean that if I want to increase the size of the CBFS over a ceratin point I need to shrink ME Firmware (which is covered by the documentation from me_cleaner). What would be the maximum CBFS size I can use without further modifications to the ME Firmware or will Coreboot reduce the size of the ME Firmware area to gain additional space automatically? Now the obvious last step is to split the 12 MB coreboot.rom into two parts to flash the upper 4 MB chip and the 8 MB chip (which should include the "cleaned" version of Intel ME, as I have enabled "Strip down the Intel ME/TXE firmware" in the coreboot config). Getting the last 4 MB of the coreboot.rom is covered by the coreboot wiki: # to flash the upper 4 MB part of the BIOS: dd of=x230-4mb.rom bs=1M if=build/coreboot.rom skip=8 to flash the 8 mb chip I'll try: dd of=x230-8mb.tom bs=1M if=build/coreboot.rom count=8 Question: Is the above approach correct? I tried so already once but it didn't work (short flashing of Power-On-button -> nothing more) [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
Hello Peter, Original Message Subject: Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work Local Time: 26 September 2017 11:05 AM From: pe...@stuge.se >> 1) How to get Coreboot running (general part) > The 1) is quite a large topic. Strangely that part seems to much easier as there is already excellent documentation available how to install all dependencies, build the toolchain. I've verified this several times by installing coreboot on a freshly installed Ubuntu 16.04.3 LTS. >> I"ve followed the howto in the coreboot wiki: > Sure, but what do the steps in the howto actually mean? > Why are you sure that they are correct? I am not sure that is why I am asking :-) And I got already different answers. >> honestly I was also wondering why this is working and even more, >> why I am skipping the first 8MB of the file. > Perfect! Please also *answer* those questions; they are important. I good a better understanding after looking at the picture one the me_cleaner site here: https://github.com/corna/me_cleaner/wiki/External-flashing This picture shows the content of the Chip: https://camo.githubusercontent.com/3ea0ff670edb94372124ad0c36bd5e2b3c522f7e/687474703a2f2f6f6936352e74696e797069632e636f6d2f3130726e3132642e6a7067 I got confused in the beginning as the X230 contains two chips which are see as one 12 MB chip. As I have saved the original content of both of my chips (x230-4mb.rom and x230-8m.rom) I have already looked at the content of the 8 MB chip: cd ~/coreboot/MyFactoryROM ifdtool -x x230_8mb.rom will extract 4 files: flashregion_0_flashdescriptor.bin (4K) --> renamed to: descriptor.bin flashregion_1_bios.bin (4,8M) flashregion_2_intel_me.bin (5,0M)--> renamed to: me.bin flashregion_3_gbe.bin (8,0K)-- > renamed to: gbe.bin I have verified the ME image as described here https://github.com/corna/me_cleaner/wiki/External-flashing cd ~/coreboot/MyFactoryROM ~/me_cleaner/me_cleaner.py -c x230_8mb.rom Full image detected The ME/TXE region goes from 0x3000 to 0x50 Found FPT header at 0x3010 Found 23 partition(s) Found FTPR header: FTPR partition spans from 0x183000 to 0x24d000 ME/TXE firmware version 8.1.71.3608 Checking the FTPR RSA signature... VALID Strangely the 8MB chips seems to also contains the "flashregion_1_bios.bin". I tought that the BIOS part is located on the top 4 MB Chip. I'd like to both files (4MB + 8MB) into one and use that with idftool. I tried to run idftool with --chip 1 on the extracted x230-4mb.rom but this didn't succeed. Next step is to clean the flashregion_2_intel_me.bin (me.bin) with me_cleaner which is describe well. QUESTION: what I am really struggling with is, is the size of the CBFS filesystem in ROM (can be set under Mainboard in coreboot make nconfig). I need a bigger CBFS to be able to run payloads but then I can't just flash the upper 4 MB chip. As such the question is: what do I need to do with the coreboot.bin after compiling to be able to flash the whole 12 MB (4 mb chip + 12 mb chip). Any help would be great here, as I am currently mainly struggling with this. [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot+SeaBios Boot speed: ~12sec till Grub Boot Screen
Hello Paul, Original Message Subject: Re: [coreboot] Coreboot+SeaBios Boot speed: ~12sec till Grub Boot Screen Local Time: 25 September 2017 9:17 AM From: paulepan...@users.sourceforge.net >> First, please just sent plain text messages to mailing lists. ok, I'll try >> 1. Your coreboot configuration (`.config`). See attached. >> 2. The output of `build/cbfstool build/coreboot.rom print`. ./coreboot/build/cbfstool ./coreboot/build/coreboot.rom print Name Offset Type Size cbfs master header 0x0cbfs header 32 fallback/romstage 0x80 stage81604 config 0x13fc0raw 641 revision 0x14280raw 570 cmos.default 0x14500cmos_default 256 cmos_layout.bin0x14640cmos_layout 1804 fallback/dsdt.aml 0x14dc0raw 13643 payload_config 0x18380raw 1611 payload_revision 0x18a40raw 237 etc/ps2-keyboard-spinup0x18b80raw 8 (empty)0x18bc0null 29400 mrc.cache 0x1fec0mrc_cache65536 fallback/ramstage 0x2ff00stage79642 pci8086,0166.rom 0x43680optionrom65536 img/coreinfo 0x53700payload 1150904 fallback/payload 0x16c700 payload 67051 (empty)0x17cd40 null 2631064 bootblock 0x3ff300 bootblock3000 >> 3. Build the utility cbmem with `make -C util/cbmem`. ok, done. >> 4. The output of `./util/cbmem/cbmem -c`. >> 5. The output of `./util/cbmem/cbmem -t`. both commands fail with "Failed to gain memory access: Permission denied" But I think before I'll try to improbe booting time, I need to make sure that: - the 2nd part of the BIOS (the 8MB chip) is flashed - additional payloads are working - write proper documentation about everything to save others asking the same (maybe annoying) questions... [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot+SeaBios Boot speed: ~12sec till Grub Boot Screen
Hello Martin, > Original Message > Subject: Re: [coreboot] Coreboot+SeaBios Boot speed: ~12sec till Grub Boot > Screen > Local Time: 25 September 2017 3:53 AM > From: gauml...@gmail.com > > Is serial console enabled? If so, disabling that will speed things up > immensely. To which position in the menuconfig tree are you referencing? Have disabled all entries under "Console" in menuconfig but still get the boot delay. I've thecoreboot .config in case that this is helpfull, see attached file. > Can you post a miniconfig? Run "make savedefconfig" and post the file > "defconfig"? Sure, at your service: $ make savedefconfig && cat defconfig CONFIG_USE_OPTION_TABLE=y CONFIG_COLLECT_TIMESTAMPS=y CONFIG_VENDOR_LENOVO=y CONFIG_CBFS_SIZE=0x40 CONFIG_VGA_BIOS=y CONFIG_VGA_BIOS_FILE="~/my-coreboot/MyROMs/original/vga.rom" # CONFIG_POST_IO is not set # CONFIG_POST_DEVICE is not set CONFIG_BOARD_LENOVO_X230=y CONFIG_DRIVERS_PS2_KEYBOARD=y # CONFIG_CONSOLE_CBMEM is not set CONFIG_CPU_MICROCODE_CBFS_NONE=y CONFIG_SEABIOS_PS2_TIMEOUT=10 # CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_LPC_TPM=y # CONFIG_SQUELCH_EARLY_SMP is not set CONFIG_SEABIOS_MASTER=y CONFIG_SEABIOS_THREAD_OPTIONROMS=y CONFIG_COREINFO_SECONDARY_PAYLOAD=y > Can you post timestamp information so we can see what"s using all the time? Unfortunately not as I haven't been able to create a 2nd payload in order to read the timstamps from coreinfo. Coreinfo is shown in the boot menu when hitting ESC, but after launching, the screen goes blank and nothing happens. Maybe this is related to the fact, that I flashed only 4 MB of the Chip(s) and as such some part of the code is missing (whoch would be in the 8 MB part of the rom-file)? [799] coreboot-config Description: Binary data -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
Hello, I tried to flash the 8 MB Chip on my X230, but it didn't worked out. > Me: what do I need to do to flash the 2nd (8MB) chip. > If the 1st chip contains the last 4MB of the file, I assume the correct > command could be: > dd of=chip8mb.rom bs=1M if=build/coreboot.rom count=8 > > Is this correct? If this is right I'll add this to the wiki as soon as I have > write permissions. I've dd'ed the first 8MB of the coreboot.rom file with the above command and flashed it on the 8MB chip, but when booting my machine only illuminated the on-off-button for a second before it dies. When reflashing the 8MB chip with the stock image which I grabbed before will bring my laptop back to life. As such it seems that there must be another was two flash both chips and to strip the coreboot.rom image. Any ideas what went wrong? As all howto's I've found so far, which cover the flashing of only the upper 4 MB Chip, the question is also, if someone has already flashed both chips and what (s)he did to make it work. [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
Hello Peter, > Original Message > Subject: Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work > Local Time: September 25, 2017 1:25 AM > From: pe...@stuge.se > > As you document your experience, please investigate what is specific > for the X230, and what is not - and be clear in what you write. > (Most things are in no way X230-specific.) yes, you are right most stuff is not X230-specific, but while I am currently learning how to flash my X230 I am collecting information from various sites. From a newbie perspective I'd like to get this information from one or two locations: 1) How to get Coreboot running (general part) 2) How to flash the X230 >> Most howtos include that it is sufficient to flash only the upper >> 4MB BIOS Chip and leave the 2nd 8 MB BIOS Chip untouched. > > I would consider that bad advice, if coreboot.rom is 12 MB. > There are not "two BIOSes" just because there are two memory chips. > The two memory chips are mapped after each other and function as one > unit. The CPU sees them as one, and so should you. Thanks, I know, what I've meant: there are two physical chips which are seen as one by the mainboard. >> After creating my 12 MB Coreboot.rom I split it and use only 4MB >> for flashing. > > So you flash only the last third of the CBFS, and ignore the beginning. > I think it is just luck that your system boots at all. If you used a > larger payload such as a kernel then your method will likely cut the > payload in half and end up writing incomplete junk to your flash. I've followed the howto in the coreboot wiki: https://www.coreboot.org/Board:lenovo/x230#Hardware_Flashring "(...) Write the flash. Since you have to write only top 4M, first split out those 4M: dd of=top.rom bs=1M if=build/coreboot.rom skip=8 (...)" This is exactly what I have done, honestly I was also wondering why this is working and even more, why I am skipping the first 8MB of the file. Can someone provide guidance how to split the generated 12 MB coreboot.rom file into two to flash them to the 1st (4MB) and 2nd (8MB) to flash the 4MB chip (from the coreboot wiki): dd of=chip4mb.rom bs=1M if=build/coreboot.rom skip=8 QUESTION: what do I need to do to flash the 2nd (8MB) chip. If the 1st chip contains the last 4MB of the file, I assume the correct command could be: dd of=chip8mb.rom bs=1M if=build/coreboot.rom count=8 Is this correct? If this is right I'll add this to the wiki as soon as I have write permissions. >> Or is the 2nd BIOS not used at all after flashing Coreboot to the >> top 4MB chip? > > Please study the hardware you are working with. What software you put > in either memory is not relevant for how the hardware works, for how > the two memories are mapped to physical CPU addresses. Honestly I am trying to understand as much as I can, but understanding more about coreboot need some knowledge I am just started to learn, while I knew what AMT is, I have never heard of EHCI. The good thing is, that a good howto is often written or improved by an interested user, not the tech-power. As such I am happy to contribute to the documentation to make it easier for the next newbie who might not be interested in how his CPU works, but wants to reduce possible entry points which might break his privacy :-) [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] Coreboot+SeaBios Boot speed: ~12sec till Grub Boot Screen
Hello, Booting to my Grub Selection screen takes ~12sec on my X230, loosing lots of second from pressing the Power Button to the "Hit Escape Key" message from SeaBios. Are there any options to accelerate this and what are you Booting times to the Grub OS selection screen? [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
Hello Matt, > Original Message > Subject: Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work > Local Time: September 23, 2017 10:59 PM > From: matt.devill...@gmail.com > coreboot + Tianocore/CorebootPayloadPkg works perfectly well to run Windows > on everything from SandyBridge to Skylake I'll stick to coreboot + SeaBios as I can boot linux/windows which perfectly fine and the installation seems to be easier and I can't see any reason why switching from (Sea)BIOS to UEFI. One additional general question regarding the flashing on X230s. Most howtos include that it is sufficient to flash only the upper 4MB BIOS Chip and leave the 2nd 8 MB BIOS Chip untouched. After creating my 12 MB Coreboot.rom I split it and use only 4MB for flashing. See also the Coreboot Wiki at https://www.coreboot.org/Board:lenovo/x230#Hardware_Flashring "(...) Write the flash. Since you have to write only top 4M, first split out those 4M: dd of=top.rom bs=1M if=build/coreboot.rom skip=8 Use flashrom to flash top.rom (...)" As far as I understand the 2nd Chip include the Intel Mangement Engine (ME), shouldn't this chip also touched and (at least party) ME'cleaned? Or is the 2nd BIOS not used at all after flashing Coreboot to the top 4MB chip? [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot on X230 and Dualboot: works = Qubes 3.2 + Win 10 Enterprise
Hello Peter, Original Message > Subject: Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work > Local Time: September 23, 2017 10:01 PM > >>> VGA init can be proper without Windows being able to boot. I know, this was the setup I had before, but having a PC which is unable to run windows is sometimes a no-go :-) > Windows will require SeaBIOS. (In theory perhaps TianoCore+CorebootPkg > works too, but I wouldn"t bet on that.) > Windows will also require the VGA BIOS. I am currently only using SeaBIOS and the vga.rom and SUCCESS, I am able to boot into my Qubes 3.2 installation AND (!) my Windows 10 Enteprise, whis is great as this was broken after switching to Coreboot. > If you have SeaBIOS then I recommend letting SeaBIOS run the VGA BIOS. I don't really understand what this means, when I document my setup/coreboot configuration, I am happy for any suggestion how to improve it. >> 1) Devices > Add a Video Bios Table (VBT) binary to CBFS (yes or no?) > No - the VGA BIOS creates a VBT. Is that not documented sufficiently? Maybe I don't get it, but in menuconfig I have disabled this option. >> 2) Devices > Graphic initialization (currently: use native graphics init) >> (should I switch this to: Run VGA Option Roms?) > No - disable graphics init in coreboot and let SeaBIOS run your VGA BIOS. Ok, I'll try that and will disable graphic initalization in coreboot. As mentioned with the current setting I can boot into Linux and Windows 10. Is there any benefit disabling native graphics init in coreboot? > As you can find in SeaBIOS docs, that requires the VGA BIOS to be > stored with the correct name in CBFS, which coreboot may or may not > do automatically. (It should, but bugs.) > If you store the VGA BIOS with a name in CBFS containing a special > subdirectory (I think vgaroms/) then the rest of the filename doesn"t > matter. I think some documentation here would be great, as I am currently a bit lost. What I got from your reply, it is possible that coreboot will use the vga.rom but it can also be handled by SeaBIOS, do I need to modify any additional things there (in SeaBIOS)? > You can of course always add the VGA BIOS file to CBFS manually, if you > want it to have a particular name in CBFS. It is not neccessary that the > coreboot build system adds it. I need to do some more reading about CBFS ... currently I am just happy that I got coreboot working for dualbooting Qubes and Win 10. I'll do some more testing to see if everything works (external display / standby/resume / LTE/etc) What has been improved already: Booting up Qubes OS doesn't can also be done with graphical but, before including vga.rom into coreboot I had to edit grub. In order to enter my passphrase to unlock my LUKS encrypted drive in Qubes I had to change grub to boot in "console mode" instead of relying on graphics: sudo nano /etc/default/grub GRUB_TERMINAL_OUTPUT="vga_text" Remove rhgb quiet from GRUB_CMDLINE_LINUX I've rolled back these changes and now I get the graphical splash screen during boot. Nice:-) [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
Hello Matt, > Original Message > From: matt.devill...@gmail.com > ME >> Question: Can I use this file for my X230? > > absolutely not. You need to use one which is for your GPU/platform, and > configured to match the outputs on your x230. Which is why it's best to > extract from the vendor firmware using UEFITool Thank your, I (think at least) I have succesfully extracted the information from my BIOS Rom File. This is was I did (running Ubuntu 16.04.3 LTS from USB): - Install QMAKE as this is needed to build UEFIToool sudo apt-get install qt5-default qt5-make - Get UEFITool from GIT git clone http://github.com/LongSoft/UEFITool.git - Compile UEFITool cd UEFITool/ && qmake && make - Start: ./UEFITool - File > Open BIOS Image File Open the ROM-file from the 4MB BIOS-Chip will generate the following (error?) messages - which I ignored: "parseVolume: unknown file system FFF12B8D-7696-4C8B-A985-2747075B4F50 parseBios: volume size stored in header 61000h (397312) differs from calculated using block map 4h (262144) parseVolume: unknown file system 00504624-8A59-4EEB-BD0F-6B36E96128E0 parseBios: volume size stored in header 2F000h (192512) differs from calculated using block map 3h (196608) parseFile: invalid data checksum" - Hit CTRL+F (Search...), 3rd Tab (Text) - Search for: VGA Compatible BIOS (Uncheck Unicode) - Will show the following message: ASCII text "VGA Compatible BIOS" found in Raw section at offset 22h - Double click on the line in the message windows which bring you to the raw section - Right Click on "Raw section" and choose "Extract Body" - Save file as vga.rom If the above procedere is correct I would like to add it to the Coreboot Wiki as currently the documentation is present on other pages, but as newbie (like me) has to look at various pages - also how and what packages I need to install to compile UEFITool etc. I guess the next step is to link to this vga BLOB when running make menuconfig in coreboot under DEVICES > ADD A VGA BIOS IMAGE. QUESTION: add which location should I place my extracted vga blob, so that it can be found during the Coreboot Build process, I am currently referencing the whole path, I tried to place into 3rdparty/blobs/mainboard/lenovo/x230 where I have also placed the other extracted blobs from my 8MB BIOS Chip (descriptor.bin gbe.bin me.bin) but it didn't work. What other settings are suggested to get proper vga initialization to be able to boot windows: 1) Devices > Add a Video Bios Table (VBT) binary to CBFS (yes or no?) 2) Devices > Graphic initialization (currently: use native graphics init) (should I switch this to: Run VGA Option Roms?) [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
Original-Nachricht an 23. Sep. 2017, 16:56, Klemens Nanni schrieb: >> These are 4/8 *mebi*byte in size. Yes of course ;-) just a typo as I am more used working with GB than MB these days... >> Web search shows X230 uses UEFI >> so you'll need UEFITool instead. Thanks, I'll give this a try. The Coreboot Wiki states that it is also possible to get the VGA blob from Intel itself: "(...) For Intel onboard graphics you can download the vbios (vga bios) from Intel's download section. The vbios is included with some versions of the graphics driver. The summary will say something like "NOTE:These materials are intended for use by developers.Includes VBIOS". The actual vbios file is the *.dat file included with the graphics driver. (...)" Unfortunately a Link to the correct download page at Intels Website to get the VGA BIOS is the only missing information. I've searched for Intel VBIOS and found the following page: https://downloadcenter.intel.com/download/26069/Intel-Embedded-Media-and-Graphics-Driver-for-VBIOS-build-3967-v36-2-11-32-bit-Install-Package "(...) This install package downloads the Intel® Embedded Media and Graphics Driver for VBIOS (build #3967), 32-bit. This is the graphics driver installation package for the Intel® Atom™ Processor E3800 product family and the Intel® Celeron® Processor N2920/J1900, bundled with user guide and release notes text files. The 32-bit VBIOS supports legacy boot and could be used at both 32-bit or 64-bit operating system booting. (...)" As it only mentions the Intel Atom and Celeron CPUs I am unsure if I should try to use the VBIOS for my X230 which has a Core i5 CPU. Within the Zip-file you can find a file named "Vga.dat" (64k Size) in the folder IEMGD_HEAD_VBIOS\Release which is the VBIOS file according to the Coreboot wiki. Question: Can I use this file for my X230? [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] Coreboot on X230 and Dualboot / How to make it work
Hello, After some initial help from Lynxis/AFRA Berlin I got my X230 initial flashed with coreboot. After getting the proper equipment I have now also reflashed several time both Chips to understand how the build and flashing process works. Booting Linux/Qubes is working great with Coreboot. Also no impact on Peripherals like LTE card, battery runtime. I would like to rebuild my Coreboot now so that it supports dualbooting (Linux / Windows). Most howtos for the X230 only cover the flashing without supporting graphical boot. The wiki page http://www.coreboot.org/VGA_support seem to cover some part, but is not specific to the X230. Has someone build coreboot including the support for graphics from startup to be able to boot into windows? I'm interested in what to choose in "make menuconfig" and where to get the vga bios rom for the x230, I would then condense the information in a X230 How-to for Dualboot-Setup. [799]-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ECC’17: Fund developer travel costs
Hello, On 22.09.2017 08:44, Paul Menzel wrote: Dear coreboot folks, The European coreboot conference 2017 is around the corner and starts on October 26th. Are there developers who need funding of their travel costs? Are there any plans to raise funds for travel costs? I have seen companies giving more money for much less usefull events ;-) Is there something like a fundraising group within the Coreboot community? -=/799/=- -- Send via wireless magic technology using ProtonMail mobile Original-Nachricht An 22. Sep. 2017, 11:05, Zaolin schrieb: > We can also help out to finding cheap hotels if needed. > In order to do so, please contact Justine Spalik: > > [justine.spa...@9elements.com](mailto:justine.spa...@9elements.com?subject=Contact%20from%20Website%3A%20ECC%2717) > > On 22.09.2017 08:44, Paul Menzel wrote: > >> Dear coreboot folks, >> >> The European coreboot conference 2017 is around the corner and starts >> on October 26th [1]. >> >> Are there developers who need funding of their travel costs? Kyösti, >> Arthur, Patrick, …? Please tell the community and note the amount. >> >> Until we know for sure, it’d be great if the coreboot community members >> would be willing to fund some of these costs. >> >> Thanks, >> >> Paul >> >> [1] >> https://ecc2017.coreboot.org/-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Berlin Meeting 21. Sep Thursday @afra_berlin
Hello Alexander, Original-Nachricht An 17. Sep. 2017, 02:39, Alexander Couzens schrieb: > Next meeting is coming. > 21.09.2017 18:30 (open end) AfRA > (different location!) Thank you for the reply. Great news - I'm happy to join as a Coreboot-newbie. >> PS: If you want to flash your laptop, send me a notice in advance. If possible I'd like to, but in a less agressive way (afraid to remove the Bios-Chip physically). I also would like to setup Coreboot with vga-blob/SeaBios which seems to be a bit more complicated. If needed I can figure out the Type of BiosChip in advance. Kind regards - O7-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] Intro and Support for flashing Coreboot to X230 (Qubes OS)
Hello, my first posting to this group after reading for a while using the mailman-archives. I was interested in Coreboot for a while but my laptops were not on the HCL. After using Qubes OS on my corporate laptop on a 2nd SSD for a while I made the decision to use a better supported laptop for Qubes OS which should also be coreboot'ed. As such I'm writing this from a Lenovo X230 and after reading several howto's I think I'm ready to coreboot, but even more interested to know someone who did so in Berlin and could support me with either coreboot'ing as I would need to buy all the equipment to do so. I'm happy to buy to be fair. Question: When is the next Coreboot-meeting taking place? Kind regards from Berlin. 17299. Sent with [ProtonMail](https://protonmail.com) Secure Email.-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
