Re: [coreboot] Coreboot + Seabios Asus F2A85-M LE card

[qma ster]

It takes some skill to extract a vgabios from official BIOS image, in
some cases (for some types of the official BIOS) it is hardly doable.
I recommend that you follow this path -
https://www.coreboot.org/VGA_support#Retrieval_via_Linux_kernel
Install the official BIOS image again, then boot Linux and extract
vgabios using these steps mentioned at the link above. Good luck

2017-06-09 16:41 GMT+03:00 Gabriel Bosque :
> Okay. I tried a path, which I thought was the most practical, but I have a
> problem:
> _I downloaded the .cap file from the card in Asus site
> _Using the UEFITool draw for asus.rom
> _By using ./bios_extract asus.rom, it gives msg:
>   Error: Unable to detect BIOS Image type.
> Any tips?
>
> 2017-06-08 12:19 GMT-03:00 Piotr Kubaj :
>>
>> https://www.coreboot.org/VGA_support
>>
>> On 17-06-08 11:01:55, Gabriel Bosque wrote:
>> > Internal. Where do I find firmware for it?
>> >
>> > Tanks in advance
>> >
>> > 2017-06-08 10:45 GMT-03:00 Piotr Kubaj :
>> >
>> > > Do you use the internal GPU or external? If you use internal, you
>> > > probably
>> > > need firmware from AMD (SeaVGABIOS won't work). If you have external
>> > > GPU,
>> > > you don't need VGA option ROM at all.
>> > >
>> > > Anyway, you don't need SeaVGABIOS.
>> > >
>> > > You also put CONFIG_QEMU_HARDWARE=y, which is unnecessary.
>> > >
>> >
>> > --
>> > This message has been scanned for viruses and
>> > dangerous content by MailScanner, and is
>> > believed to be clean.
>> >
>>
>> --
>>  
>> / No matter where I go, the place is \
>> \ always called "here".  /
>>  
>> \   ^__^
>>  \  (oo)\___
>> (__)\   )\/\
>> ||w |
>> || ||
>
>
>
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> https://mail.coreboot.org/mailman/listinfo/coreboot

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[coreboot] make crossgcc-i386 : ubsan.c error (with fix!) for GCC

[qma ster]

Good day! While building the coreboot's toolchain by using GCC 7.1.1
version, I am getting the following error:

ubsan.c:1474:23: error: ISO C++ forbids comparison between pointer and
integer [-fpermissive]
   || xloc.file == '\0' || xloc.file[0] == '\xff'

The fix is very simple - just open
./util/crossgcc/gcc-6.3.0/gcc/ubsan.c and change

   || xloc.file == '\0' || xloc.file[0] == '\xff'

to

   || xloc.file[0] == '\0' || xloc.file[0] == '\xff'

Found this solution here -
https://patchwork.openembedded.org/patch/138884/ . Would be great if
you could somehow import it to your code

Best regards,
qmastery

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[coreboot] Easier accessibility for coreboot/flashrom wikipedias? What do you think?

[qma ster]

Dear coreboot/flashrom mailing list members,

As you may have noticed it is not that easy or straightforward to gain the
edit rights for coreboot/flashrom wikipedias so the people are mass
migrating to the unofficial wikis. For example: recently Zoran Stojsavljevic
had to bring his Coreboot/VBT article to Jimmy Wales wikipedia instead of
coreboot wikipedia, Mike Banon had to put his EC KB9012 chip flashing
article to DangerousPrototypes wikipedia instead of flashrom wikipedia, and
I could provide many other similar examples if needed

Currently, to get the edit rights for coreboot/flashrom wikipedias you have
to personally contact the wikipedias administration, who are the highly
active open source developers with a lot of things to do and may simply
forget to review your request - and you have to provide a good enough
detailed explanation of what exactly you are going to write or edit,
despite that your plans might change and suddenly you would like to improve
another article, write your own, or maybe even want to improve the many
other random articles: doing small changes like fixing the typos /
replacing the broken links / updating the clearly outdated information /
other fixes that are minor by nature but still are majorly improving the
wikipedias quality

I believe that the current administrative barriers are too high: to gain
the edit rights you should not be required to go through what seems to be
like a job interview, especially because this is not like a job offer and
your work at these wikipedias will be unpaid

My proposal is to give the edit rights to all the subscribers of the
coreboot/flashrom mailing lists, or at least to all those who have been the
subscribers for at least a day / a week / or a month. Could see only the
positive outcome from this action, because I strongly believe that all the
members of coreboot/flashrom mailing lists are responsible smart
individuals and their wiki contributions will be of high quality.
Alternatively, the registration could be made completely open, but with a
strong registration/login captcha or maybe even per-edit captcha to prevent
the automatic bots/spammers from ruining the wiki pages

Please share your opinions about this proposal. It is interesting to hear
your thoughts, and maybe they could influence the coreboot/flashrom
projects future

Best regards,
qmastery
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Re: [coreboot] Overheating on f2a85-m

[qma ster]

Before investigating the software methods, in this situation I would have
tried to: using some great thermal paste, cleaning the dust, and - most
likely - switching to a manual fan control: there are the hardware fan
control adapters, and if you don't have those - temporarily you could just
wire your fan so that it will always work on the max speed instead of
taking the fan control commands from the motherboard

2017-03-26 22:35 GMT+03:00 Rudolf Marek :

> Hi again,
>
> Sorry, I pasted wrong dump. Before I installed right /etc/sensors3.conf
>
> radeon-pci-0008
> Adapter: PCI adapter
> temp1:+35.0°C  (crit = +120.0°C, hyst = +90.0°C)
>
> it8603-isa-0290
> Adapter: ISA adapter
> Vcore:+1.27 V  (min =  +1.12 V, max =  +2.96 V)  ALARM
> in1:  +1.66 V  (min =  +2.69 V, max =  +0.08 V)  ALARM
> +12V:+12.38 V  (min = +14.98 V, max =  +0.00 V)  ALARM
> +5V:  +5.07 V  (min =  +3.96 V, max =  +0.12 V)  ALARM
> in4:  +1.20 V  (min =  +1.92 V, max =  +0.12 V)  ALARM
> 3VSB: +3.31 V  (min =  +0.79 V, max =  +2.88 V)  ALARM
> Vbat: +3.14 V
> +3.3V:+3.36 V
> CPU Fan: 2824 RPM  (min =  200 RPM)
> CHA Fan:0 RPM  (min =  600 RPM)  ALARM
> CPU Temp: +64.0°C  (low  = +50.0°C, high = -126.0°C)  ALARM  sensor =
> thermistor
> M/B Temp: +38.0°C  (low  = +100.0°C, high = +122.0°C)  sensor =
> thermistor
> temp3:   -128.0°C  (low  = -24.0°C, high =  +0.0°C)  sensor =
> thermistor
> intrusion0:  OK
>
> k10temp-pci-00c3
> Adapter: PCI adapter
> temp1:+48.9°C  (high = +70.0°C)
>(crit = +70.0°C, hyst = +69.0°C)
>
> Thanks
> Rudolf
>
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Re: [coreboot] RYZen single APU design

[qma ster]

As far as I know, AMD does not have any "evil brother" of Intel ME. It only
has AMD PSP (Platform Secure Processor) that is built-in to CPU. So, I
don't think that cutting a PCH from AMD CPU has any practical value: even
if the platform will boot after such a radical change to computer's
hardware, you'll lose a lot of essential stuff like USB ports

2017-03-16 8:03 GMT+03:00 Zoran Stojsavljevic :

> Hello Coreboot folks,
>
> I have couple of interesting questions here.
>
> Recently, I have started learning about AMD (RYZen did not live me
> unemotional), so after reading several articles (especially one with AMD
> architecture):
> http://www.anandtech.com/show/11182/how-to-get-ryzen-working
> -on-windows-7-x64
>
> I found/got from this article very interesting thought: AMD's APU, as
> shown on this picture, could be left alone, even not connecting
> Chipset/PCH!?
>
> I know that for INTEL this is impossible to do. With early INTEL ME
> involvement to HW bring up (wrt PMIC and EC), I am wondering if this is
> very similar architecture with AMD?
>
> [image: Inline image 1]
>
> [1] Did anybody try some proprietary embedded design, with AMD's APU all
> alone (is it at all possible)?
> [2] if [1] true, does anybody have some HW schema showing in details how
> this is done/designed?
> [3] if [1] is true. does Coreboot support such AMD designs (sans
> chipsets/PCHs)?
>
> Thank you,
> Zoran
>
>
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Re: [coreboot] Where to get ME image/flash descriptors for the x220?

[qma ster]

Hi Taiidan, try following these instructions:
1) download the latest official BIOS update .exe file from your laptop
manufacturer's website (Lenovo in this case)
2) open this .exe file with 7zip utility and extract all its' contents to a
separate folder
3) most likely is that amoung these extracted files you will see a several
megabytes binary file, which contains not just a BIOS image but also EC
firmware image and some other images. Then you open this binary file in a
hex editor like Okteta and search for some ASCII string symbols like for
example _EC_IMG to e.g. locate the beginning of EC firmware block, and
knowing what size in bytes the EC firmware should be - you cut the same
amount of bytes after _EC_IMG text - and save into a new binary file
Something like that, will probably work for you. Good luck in your research
;)

2017-03-07 5:23 GMT+00:00 taii...@gmx.com :

> Uhh thanks but that's kinda missing the point of this - that I don't want
> binaries from random people on the internet.
>
> I need to know how to extract it from the bios update files, not the bios
> already on the EEPROM.
>
>
> On 03/06/2017 11:35 PM, Matt DeVillier wrote:
>
> I have the IFD and ME from an x220 that I recently flashed with coreboot
> for a customer, extracted from their stock firmware, and verified working
> with the coreboot ROM I subsequently flashed.  Can zip and send via email,
> or whatever you prefer
>
> On Mon, Mar 6, 2017 at 10:23 PM, taii...@gmx.com  
>  wrote:
>
>
> On 03/05/2017 05:20 AM, Arthur Heymans wrote:
> "taii...@gmx.com"    
> writes:
>
> Well I managed to download the latest BIOS from the lenovo site, which
>
> includes an ME update now the issue is that I can't seem to figure out
> how to extract it from the .FL1 and .FL2 files.
>
> Those might have a length too long to fit a flash so you need to trim
>
> those down before using ifdtool on those (If they contain and ifd of
> course)
> so depending on size of rom
> dd if=FL1(or 2)file of=vendor_bios.rom bs=1 count=xM
>
> and then ifdtool -x vendor_bios.rom
>
>
> It didn't work :( after that still "no flash descriptor found in this
> image"
>
> These are the files and the flash chip on the board is 8M
> 8523776 '$01CB000.FL1'
> 8523776 '$01CB000.FL2'
> 8523776 '$01CB100.FL2'
> All of them have different hashes, but I do not know what makes them
> different (maybe it is for various board revisions?)
>
>
>
> I would also like to know as to how I can re-flash the EC firmware if
>
> that could potentially cause problems, I of course do not know if it
> has DMA.
>
> Only existing tool to flash EC is using vendor tool.
>
> EC are only accessed trough port mapped IO (or on newer ones also via
> memory mapped IO). EC itself does not have DMA afaik.
>
>
>
> --
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> coreboot@coreboot.orghttps://www.coreboot.org/mailman/listinfo/coreboot
>
>
>
>
>
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Re: [coreboot] Where to get ME image/flash descriptors for the x220?

[qma ster]

It should be possible to reflash EC internal firmware through a keyboard
port, - or maybe through some other debug port that may or may not be
soldered by default... For example, here is a guide that describes how to
reflash EC KB9012 internal firmware on Lenovo G505S - "AMD based laptop
that is supported by coreboot project" ,
http://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate .
Thanks to this method it is possible to flash a completely clean EC KB9012
firmware image, which: 1) does not contain any "secret configs" (could be
stored in the free place after the firmware) 2) does not contain any serial
numbers or other specific laptop information ... For any EC it is
guaranteed that it IS possible to reflash a firmware through In-System
Programming (direct flashing) - otherwise, 1) how the manufacturers flash
EC for the first time? ;) 2) if some laptop's EC is burned, how do repair
shops flash a firmware to a new replacement EC?
Sadly, for this direct flashing method you may need to buy a proprietary
programmer (closed source hardware/software) , because a flashrom does not
support every EC in existence

2017-03-05 13:20 GMT+03:00 Arthur Heymans :

> "taii...@gmx.com"  writes:
>
> > Well I managed to download the latest BIOS from the lenovo site, which
> > includes an ME update now the issue is that I can't seem to figure out
> > how to extract it from the .FL1 and .FL2 files.
> >
> Those might have a length too long to fit a flash so you need to trim
> those down before using ifdtool on those (If they contain and ifd of
> course)
> so depending on size of rom
> dd if=FL1(or 2)file of=vendor_bios.rom bs=1 count=xM
>
> and then ifdtool -x vendor_bios.rom
>
> > I would also like to know as to how I can re-flash the EC firmware if
> > that could potentially cause problems, I of course do not know if it
> > has DMA.
> >
>
> Only existing tool to flash EC is using vendor tool.
> EC are only accessed trough port mapped IO (or on newer ones also via
> memory mapped IO). EC itself does not have DMA afaik.
>
> --
> Arthur Heymans
>
> --
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Re: [coreboot] No external PCIe GPU possible/working on Gigabyte g41m-es2l

[qma ster]

Maybe to fix this PCIe GPU issue he just needs to edit a
*./coreboot/src/device/Kconfig
*file?


*./coreboot/src/device/Kconfig*
change

config MULTIPLE_VGA_ADAPTERS
   bool
   default n

to

config MULTIPLE_VGA_ADAPTERS
   bool
   default y

and completely rebuild the coreboot

I enabled these options for my G505S laptop with both integrated/discrete
graphic, however I am not a gamer so can't notice if there is any positive
effect from this option. But maybe this option will significantly improve
the thread starter's eGPU experience? What do you think ?

2017-02-28 0:57 GMT+03:00 Arthur Heymans :

> Stefan Reinauer  writes:
>
> > * i1w5d7gf38...@tutanota.com  [170226
> 21:59]:
> >> Hardware: Gigabyte g41m-es2l, latest coreboot git, latest seabios git,
> two
> >> nvidia gpu cards tested
> >>
> >> I tried to use some external GPU on a g41m-es2l to get some digial
> screen
> >> output. It does not seem to work. When having build coreboot with native
> >> vga-init for the internal intel gpu, i never get a output from the
> nvidia card.
> >> When i connect the analog VGA cable to the internal intel gpu and boot
> up i can
> >> see many nouveau (memory-space?) errors. Both GPUs (nvidia and intel)
> are then
> >> enabled at once. Kernel 4.10 cant boot.
> >>
> >> I tried removing the native vga-init. The only change is then that the
> Intel
> >> GPU works only when the kernel have load. Nvidia card deliver still same
> >> errors.
> >>
> >> With OEM-bios the intel card gets disabled and a PCIe GPU works fine.
> >
> > Please provide coreboot boot logs.
> >
> > Stefan
>
> Actually https://review.coreboot.org/#/c/18504/
> https://review.coreboot.org/#/c/18511/ (not sure if needed) and
> https://review.coreboot.org/#/c/18513/ (works but might be improved)
> fix this issue.
>
> --
> Arthur Heymans
>
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Re: [coreboot] payload coreinfo - no button press works

[qma ster]

Inside the " payloads/coreinfo/coreinfo.c " file, at lines 290 - 296 there
is a code:

int main(void) {
int i, j;
#if IS_ENABLED(CONFIG_LP_USB)
usb_initialize();
#endif

It could be that your board has CONFIG_LP_USB option disabled at libpayload
config. If you are unsure about how to check it, you could just remove #if
IS_ENABLED(CONFIG_LP_USB) and #endif to just leave usb_initialize(); , to
make sure that the code of usb_initialize(); function will be run at every
coreinfo launch ! Then completely rebuild a coreboot with its' payloads to
make sure that this changed source code gets into your final BIOS image,
before flashing it. Good luck!

2017-02-27 10:57 GMT+03:00 Paul Menzel via coreboot :

> Dear i1w5d7gf38keg,
>
>
> Am Sonntag, den 26.02.2017, 21:23 +0100 schrieb i1w5d7gf38...@tutanota.com
> :
> > Hardware: g41m-es2l, latest coreboot git, latest seabios git, native
> > vga, ps2 keyboard + usb keyboard
>
> Please always add the commit hashes to your reports, as reading the
> mailing list archive [1] in the future, “latest” is harder to map to a
> specific commit.
>
> > I liked to try out coreinfo. It show the CPU Information page at
> > start. When i then press any button (f1,f2,a,b,c,d) nothing happens.
> > I also cant reboot by pressing ctrl+alt+del. Have to press the ATX-
> > power-on/off-button.
> >
> > I then shut down and connected a USB-Keyboard. I pressed in Seabios
> > esc (usb keyboard is working) and then inside coreinfo i was again
> > unable to get any functionality by pressing some button.
>
> The payload *coreinfo* works with QEMU for me, so I guess it’s an issue
> with the board. Please verify, if there are any differences if you use
> the payload *coreinfo* directly. (The problem will probably be the
> same.)
>
> Then please try the same payload files/setup (SeaBIOS, coreinfo) with a
> coreboot image built for QEMU.
>
> If it works for you there, the reason is probably incomplete support
> for your device. Please provide debug logs. Remember, that this is one
> of the main advantages of coreboot, that you get elaborate messages.
>
> Though, I have no idea, if somebody will have time and motivation to
> fix this. So you might have to fix this yourself.
>
> To not forget about this, and document this issue, it’d be great if you
> created an issue in the coreboot bug tracker [2], and attach your
> config files and captured log messages there.
>
>
> Thanks,
>
> Paul
>
>
> PS: It’d be great, if you just send plain text messages with no HTML
> parts to mailing lists.
>
>
> [1] https://www.coreboot.org/pipermail/coreboot/2017-February/083418.html
> [2] https://ticket.coreboot.org/
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Re: [coreboot] Lenovo T420 Question

[qma ster]

Hi, i took my results from this page (could use google translate) -
https://www.overclockers.ru/lab/79286_4/testirovanie-termointerfejsov-v-poiskah-idealnoj-termopasty-ili-novinki-protiv-vcherashnih-chempionov.html
>From your 1st test, Grizzly is better by 0.33 C , and from your 2nd test -
by 0.31 C. Even if your tests are more correct, 10g of GC-Extreme at my
local market cost the same as 5,55g of Grizzly -- that means, Grizzly is
almost twice more expensive per 1g ; that is too big price difference for
just 0.3 C . BTW it took me just 1 year to spend the first 10g, so had to
buy another 10g

2017-02-24 13:53 GMT+03:00 :

> This test here show the opposite:
> http://extreme.pcgameshardware.de/attachments/831791d1434218266-
> review-thermal-grizzly-kryonaut-hydronaut-auswertung.jpg
>
> The Gelid GC-Extreme is not as good as Thermal Grizzly Kryonaut also
> listed by this test here:
> http://overclocking.guide/wp-content/uploads/2015/06/Tim_test_update1.png
>
> and also some other tests i had read.
>
> I dont know where you got this test you paste the results. I have never
> seen a test result where the GC-extreme was better then the Thermal Grizzly
> Kryonaut before.
>
> 5,55gramm of the Thermal Grizzly Kryonaut cost about 15€. I dont think
> that you should go there for the best price. You apply it once and 5,55g is
> really much for a normal user. You would probably have enough for years.
>
> 23. Feb 2017 16:36 by qmaster...@gmail.com:
>
> Actually there is an even better non-conductive thermal paste (not liquid
> metal) than "Grizzly" --- it is called " Gelid GC-Extreme ". Here is a
> comparison from one review website that I screenshotted -
> https://s4.postimg.org/qvp326pjx/Thermal_Grease.png  . The difference
> between them is not big, but I think in your case every degree counts.
> Also, there is a packaging of Gelid GC-Extreme that is 10g -
> http://gelidsolutions.com/thermal-solutions/thermal-
> compound-gc-extreme-10g/ , this larger packaging gives a very affordable
> price per 1g and will last for a long time ;)
>
> 2017-02-23 4:49 GMT+03:00 :
>
>> Could you try out "Thermal Grizzly Kryonaut" or even liquid metal based
>> products and report about the temperatures? It would be great if you could
>> try out first the Thermal Grizzly Kryonaut and later then for example the
>> Thermal Grizzly Conductonaut and report here.
>> http://www.overclock.net/t/1588116/thermal-grizzly-conductonaut-73-w-mk
>>
>> Please clean up the surface before applying when possible with
>> https://en.wikipedia.org/wiki/Isopropyl_alcohol (its cheap and easy to
>> get).
>>
>> 23. Feb 2017 01:28 by coreb...@semioptimal.net:
>>
>>
>> Hi
>>
>>
>> Untested/unknown: If a ivy bridge CPU would work. The OEM bios didn't had
>> support for those.
>>
>>
>> Ivy Bridge works, have a 3740QM in mine. However, (quoting myself here):
>>
>>
>> I'm running one albeit with an i7-3740qm - which is too much thermal
>> load, runs up to 2.9 GHz for me reaching 93°C (70K to ambient) with fan set
>> to disengaged, normal auto fan control works and allows up to 2.5 GHz.
>>
>> with that CPU RAPL does not work, thermald does but out-of-the-box
>> settings gives me less performance than with fix limits, and I'm sure as
>> hell not going to configure something with an xml config file.
>>
>> used to have a 2720m which worked without any issues AFAIR, but the
>> 3740qm effectively gives me double the cores that are a little faster.
>>
>>
>> Regards, Arian
>>
>>
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>> https://www.coreboot.org/mailman/listinfo/coreboot
>>
>
>
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Re: [coreboot] Lenovo T420 Question

[qma ster]

Actually there is an even better non-conductive thermal paste (not liquid
metal) than "Grizzly" --- it is called " Gelid GC-Extreme ". Here is a
comparison from one review website that I screenshotted -
https://s4.postimg.org/qvp326pjx/Thermal_Grease.png  . The difference
between them is not big, but I think in your case every degree counts.
Also, there is a packaging of Gelid GC-Extreme that is 10g -
http://gelidsolutions.com/thermal-solutions/thermal-compound-gc-extreme-10g/
, this larger packaging gives a very affordable price per 1g and will last
for a long time ;)

2017-02-23 4:49 GMT+03:00 :

> Could you try out "Thermal Grizzly Kryonaut" or even liquid metal based
> products and report about the temperatures? It would be great if you could
> try out first the Thermal Grizzly Kryonaut and later then for example the
> Thermal Grizzly Conductonaut and report here.
> http://www.overclock.net/t/1588116/thermal-grizzly-conductonaut-73-w-mk
>
> Please clean up the surface before applying when possible with
> https://en.wikipedia.org/wiki/Isopropyl_alcohol (its cheap and easy to
> get).
>
> 23. Feb 2017 01:28 by coreb...@semioptimal.net:
>
>
> Hi
>
>
> Untested/unknown: If a ivy bridge CPU would work. The OEM bios didn't had
> support for those.
>
>
> Ivy Bridge works, have a 3740QM in mine. However, (quoting myself here):
>
>
> I'm running one albeit with an i7-3740qm - which is too much thermal load,
> runs up to 2.9 GHz for me reaching 93°C (70K to ambient) with fan set to
> disengaged, normal auto fan control works and allows up to 2.5 GHz.
>
> with that CPU RAPL does not work, thermald does but out-of-the-box
> settings gives me less performance than with fix limits, and I'm sure as
> hell not going to configure something with an xml config file.
>
> used to have a 2720m which worked without any issues AFAIR, but the 3740qm
> effectively gives me double the cores that are a little faster.
>
>
> Regards, Arian
>
>
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> coreboot mailing list: coreboot@coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>
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Re: [coreboot] install help

[qma ster]

Hi Chris, you could read this article, it describes the laptop BIOS
flashing procedure in a great detail:
http://dangerousprototypes.com/docs/Flashing_a_BIOS_chip_with_Bus_Pirate
Although it is written with Bus Pirate programmer in mind, other
programmers like cheap CH341A have almost the same flashing instructions,
just a flashrom command is slightly different!

It would be much better if you learn how to do it by yourself, instead of
relying on others to reflash your BIOS each time you need to install/update
it. "give a man a fish and you feed him for a day; teach a man to fish and
you feed him for a lifetime"

2017-02-20 14:23 GMT+03:00 njolk via coreboot :

> Dear coreboot community,
>
> I need help installing libreboot on my laptop, as I'm inexperienced with
> the practices involved, and wish to avoid borking my device. might anyone
> in Berlin be available to walk me through it?
>
> thank you so much in advance,
> regards,
> Chris Penn
>
>
>
> Sent with ProtonMail  Secure Email.
>
>
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[coreboot] FILO 0.6.0 payload bootloader - Questions?

[qma ster]

I have successfully built and added FILO bootloader to my Lenovo G505S
coreboot image! First of all, I had to use Xubuntu 16.04.1 *i386* because
FILO fails to compile on x86_64 bit system. Also: from
*./coreboot/payloads/libpayload/drivers/storage/ahci.c * removed two " #if
IS_ENABLED(CONFIG_LP_STORAGE_AHCI_ONLY_TESTED) ... #endif " parts, ---
because there are only three tested controllers in a list and FILO doesnt
even try to initialize the not listed controllers - despite that they could
work! By default, FILO just outputs "ahci: Not using untested SATA
controller" message, without any option for a user to try forcing its usage
to test it and made it a tested controller...

now FILO outputs the following log:

Booting from CBFS...
coreboot: ... version (its from the beginning of December 2016) ...
FILO version 0.6.0 (user@pc) date-of-the-build
ahci: Found SATA controller 00:11.00 (1022:7801) <--- this is AMD SATA AHCI
controller, built-in inside Bolton A76M FCH Southbridge of Lenovo G505S
ahci: ATA drive on port #1.
ata: Identified [my 1TB HDD drive model here]
ahci: ATAPI drive on port #2.
atapi: Identified [my DVD drive model here]
ERROR: No such CMOS option (boot_devices)

Then, it shows me FILO screen with " root_dev = unset " message on top, and
FILO command line

Questions:

could you give some good examples about how to use FILO ? Do I have to set
boot_devices in CMOS through nvramcui payload, or it is possible to choose
that root_dev in FILO - if yes, how?

I tried some random commands like
filo> kernel hda:/vmlinuz
but it tells:
Disk read error dev=1 drive=0 sector=0
Disk read error dev=1 drive=0 sector=2
Disk read error dev=1 drive=0 sector=2
Disk read error dev=1 drive=0 sector=128
Disk read error dev=1 drive=0 sector=16
Disk read error dev=1 drive=0 sector=64
Disk read error dev=1 drive=0 sector=0
Disk read error dev=1 drive=0 sector=64
Disk read error dev=1 drive=0 sector=0
Disk read error dev=1 drive=0 sector=0
Unknown filesystem type.

Error 15: Filo not found.

EDIT: found https://www.coreboot.org/FILO but its too basic - for example,
it does not tell how I could see the list of available devices. When I run
"probe" command it only tells 6 messages "IDE channel X not found"  (with X
changing 0,0,1,1,2,2,3,3) - does not show SATA drive, despite I know that
it successfully initialized, because it output its model and brand

Please give any real world FILO usage examples with a modern Linux, it will
help a lot!

Best regards,
qmastery
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