Re: [coreboot] Acer Chromebook 15 debug

2015-09-03 Thread John Lewis 

I'm still no further along. On the very first boot after flash I get:

coreboot-5cbe3a8-dirty romstage Thu Sep  3 10:28:23 BST 2015 starting...

PM1_STS:   0010
PM1_EN:
PM1_CNT:   
TCO_STS:    
GPE0_STS:  1ef86df0 187d4fdf 0005f240 0001
GPE0_EN:      
GEN_PMCON: 0200 20a0 1a09
Previous Sleep State: S0
CPU: Intel(R) Core(TM) i3-5005U CPU @ 2.00GHz
CPU: ID 306d4, Broadwell E0 or F0, ucode: 001d
CPU: AES supported, TXT NOT supported, VT supported
MCH: device id 1604 (rev 09) is Broadwell F0
PCH: device id 9cc5 (rev 03) is Broadwell U Base
IGD: device id 1616 (rev 09) is Broadwell U GT2
CPU: frequency set to 2000 MHz
POST: 0x32
SPD: index 1 (GPIO47=0 GPIO9=0 GPIO13=1)
SPD: module type is DDR3
SPD: module part is HMT425S6AFR6A-PB
SPD: banks 8, ranks 1, rows 15, columns 10, density 4096 Mb
SPD: device width 16 bits, bus width 64 bits
SPD: module size is 2048 MB (per channel)
POST: 0x32
ME: FW Partition Table  : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode  : NO
ME: Boot Options Present: NO
ME: Update In Progress  : NO
ME: Current Working State   : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode  : Normal
ME: Error Code  : No Error
ME: Progress Phase  : BUP Phase
ME: Power Management Event  : Pseudo-global reset
ME: Progress Phase State: Waiting for DID BIOS message
ME: HSIO Version: 8705 (CRC 0xfbc2)
No MRC cache found.
Rebooting with EC in RO mode:
POST: 0x00

Reverting to the previous log on subsequent boots. Note I have also 
built the ROM inside the CrOS SDK.


What should I do now?

See attached changes + config.

-John.diff --git a/Makefile.inc b/Makefile.inc
index 2b4d33e..47b1556 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -464,11 +464,11 @@ $(obj)/coreboot.pre1: $(CBFSTOOL)
 	mv $(obj)/coreboot.rom $@
 endif
 
-ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y)
-REFCODE_BLOB=$(obj)/refcode.rmod
-$(REFCODE_BLOB): $(RMODTOOL)
-	$(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@
-endif
+# ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y)
+# REFCODE_BLOB=$(obj)/refcode.rmod
+# $(REFCODE_BLOB): $(RMODTOOL)
+# 	$(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@
+# endif
 
 $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB) $(REFCODE_BLOB)
 	@printf "CBFS   $(subst $(obj)/,,$(@))\n"
@@ -504,7 +504,7 @@ ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y)
 	$(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG)
 endif
 ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y)
-	$(CBFSTOOL) $@.tmp add-stage -f $(REFCODE_BLOB) -n $(CONFIG_CBFS_PREFIX)/refcode -c $(CBFS_COMPRESS_FLAG)
+	$(CBFSTOOL) $@.tmp add -f $(CONFIG_REFCODE_BLOB_FILE) -n $(CONFIG_CBFS_PREFIX)/refcode -t raw
 endif
 ifeq ($(CONFIG_PXE_ROM),y)
 	$(CBFSTOOL) $@.tmp add -f $(CONFIG_PXE_ROM_FILE) -n pci$(CONFIG_PXE_ROM_ID).rom -t raw
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 0ef12fb..1e058a7 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -161,6 +161,7 @@ void google_chromeec_check_ec_image(int expected_type)
 	}
 }
 
+#if CONFIG_CHROMEOS
 /* Check for recovery mode and ensure EC is in RO */
 void google_chromeec_early_init(void)
 {
@@ -169,6 +170,7 @@ void google_chromeec_early_init(void)
 		google_chromeec_check_ec_image(EC_IMAGE_RO);
 	}
 }
+#endif
 
 void google_chromeec_check_pd_image(int expected_type)
 {
@@ -200,6 +202,7 @@ void google_chromeec_check_pd_image(int expected_type)
 	}
 }
 
+#if CONFIG_CHROMEOS
 /* Check for recovery mode and ensure PD is in RO */
 void google_chromeec_early_pd_init(void)
 {
@@ -210,6 +213,8 @@ void google_chromeec_early_pd_init(void)
 }
 #endif
 
+#endif
+
 u16 google_chromeec_get_board_version(void)
 {
 	struct chromeec_command cmd;
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 89c057f..8518ccf 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -130,7 +130,7 @@ $(obj)/lib/uart8250.smm.o : $(OPTION_TABLE_H)
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
 # Include rmodule.c in romstage if vboot verification is selected.
-romstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += rmodule.c
+romstage-y += rmodule.c
 
 RMODULE_LDSCRIPT := $(src)/lib/rmodule.ld
 
diff --git a/src/mainboard/google/auron_yuna/Kconfig b/src/mainboard/google/auron_yuna/Kconfig
index 2db9689..1e56e0f 100644
--- a/src/mainboard/google/auron_yuna/Kconfig
+++ b/src/mainboard/google/auron_yuna/Kconfig
@@ -12,8 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_ACPI_RESUME
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
-	select CHROMEOS
-	select CHROMEOS_VBNV_CMOS
 	select EXTERNAL_MRC_BLOB
 	select CACHE_ROM
 	select MARK_GRAPHICS_MEM_WRCOMB
diff --git a/src/mainboard/google/auron_yuna/romstage.c b/src/mainboard/google/auron_yuna/romstage.c

Re: [coreboot] Acer Chromebook 15 debug

2015-09-02 Thread John Lewis 

Coolstar Organisation wants to do his Windows thang with one of the
Broadwell Chromebooks, so I'm trying to build a working ROM with
chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-yuna-6301.59.B
to give him a hand. Luckily USB debug works with this, so here is
what I'm getting. What could I do next?


Do you happen to know if the hang happens at the same spot when using
serial?


I don't. What do you mean by "using serial"? Serial console? I can tell
you that if USB debug isn't enabled, it will hang/lock almost
immediately after pressing the power button, and require a long-press to
switch off. If using USB debug, it switches itself off and terminates
the console at the end of the log. The only other thing I notice is that
on a "normal" boot using the backup, the next bit of log is vboot
related which I am not using i.e.

Verified boot TPM initialization.
TPM: Init
Found TPM SLB9635 TT 1.2 by Infineon
TPM: Open
TPM: Resume
TPM: command 0x99 returned 0x0
TPM: OK.
Loading image.
Loading ramstage from 7d30.
Jumping to image.
coreboot-3cbf0db Mon Jan 12 11:23:56 PST 2015 booting...



Incidentally, if I flash back my backup, it goes into recovery mode
now every time I boot (flags are 0x489), I've tried pulling the
battery to no avail. If anyone has a trick to get around that, I'd
appreciate it, as the Acer is my main machine.


What is the recovery reason? ( at the recovery screen)



I managed to get around that one by flashing a shellball ROM and then
flashing back the backup internally. Next time I do it I'll press the
TAB key.



coreboot-⁠5cbe3a8-⁠dirty romstage Sun Aug 23 12:18:55 BST 2015
starting...
PM1_STS:   8910
PM1_EN:
PM1_CNT:   
TCO_STS:    
GPE0_STS:  1ef82df0 187d4fdf 0005f240 
GPE0_EN:      
GEN_PMCON: 0200 2024 520b
Previous Sleep State: S5
CPU: Intel(R) Core(TM) i3-⁠5005U CPU @ 2.00GHz
CPU: ID 306d4, Broadwell E0 or F0, ucode: 001d
CPU: AES supported, TXT NOT supported, VT supported
MCH: device id 1604 (rev 09) is Broadwell F0
PCH: device id 9cc5 (rev 03) is Broadwell U Base
IGD: device id 1616 (rev 09) is Broadwell U GT2
CPU: frequency set to 2000 MHz
SPD: index 1 (GPIO47=0 GPIO9=0 GGPIO13=1)
SPD: module type is DDR3
SPD: module part is HMT425S6AFR6A-⁠PB
SPD: banks 8, ranks 1, rows 15, columns 10, density 4096 Mb
SPD: device width 16 bits, bus width 64 bits
SPD: module size is 2048 MB (per channel)
Boot Count incremented to 8
ME: FW Partition Table  : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode  : NO
ME: Boot Options Present: NO
ME: Update In Progress  : NO
ME: Current Working State   : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode  : Normal
ME: Error Code  : No Error
ME: Progress Phase  : BUP Phase
ME: Power Management Event  : Pseudo-⁠global reset
ME: Progress Phase State: Waiting for DID BIOS message
ME: HSIO Version: 8705 (CRC 0xfbc2)
No FMAP found at ffe1.
FMAP: area RW_MRC_CACHE not found
No MRC cache found.
Starting Memory Reference Code
Initializing Policy
Installing common PPI
MRC: Starting...
Initializing Memory
MRC: Done.
MRC Version 2.6.0 Build 0
memcfg DDR3 clock 1600 MHz
memcfg channel assignment: A: 0, B  1, C  2
memcfg channel[0] config (00780008):
   enhanced interleave mode on
   rank interleave on
   DIMMA 2048 MB width x16 single rank, selected
   DIMMB 0 MB width x16 single rank
memcfg channel[1] config (00780008):
   enhanced interleave mode on
   rank interleave on
   DIMMA 2048 MB width x16 single rank, selected
   DIMMB 0 MB width x16 single rank
CBMEM: root @ 7cfff000 254 entries.
MRC data at ff7d0d9c 6246 bytes
Relocate MRC DATA from ff7d0d9c to 7cfeb000 (6246 bytes)
create cbmem for dimm information



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Re: [coreboot] Acer Chromebook 15 debug

2015-09-02 Thread John Lewis 

Coolstar Organisation wants to do his Windows thang with one of the
Broadwell Chromebooks, so I'm trying to build a working ROM with 
chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-yuna-6301.59.B

to give him a hand. Luckily USB debug works with this, so here is
what I'm getting. What could I do next?


Do you happen to know if the hang happens at the same spot when using
serial?


I don't. What do you mean by "using serial"? Serial console? I can tell 
you that if USB debug isn't enabled, it will hang/lock almost 
immediately after pressing the power button, and require a long-press to 
switch off. If using USB debug, it switches itself off and terminates 
the console at the end of the log. The only other thing I notice is that 
on a "normal" boot using the backup, the next bit of log is vboot 
related which I am not using i.e.


Verified boot TPM initialization.
TPM: Init
Found TPM SLB9635 TT 1.2 by Infineon
TPM: Open
TPM: Resume
TPM: command 0x99 returned 0x0
TPM: OK.
Loading image.
Loading ramstage from 7d30.
Jumping to image.
coreboot-3cbf0db Mon Jan 12 11:23:56 PST 2015 booting...



Incidentally, if I flash back my backup, it goes into recovery mode
now every time I boot (flags are 0x489), I've tried pulling the
battery to no avail. If anyone has a trick to get around that, I'd
appreciate it, as the Acer is my main machine.


What is the recovery reason? ( at the recovery screen)



I managed to get around that one by flashing a shellball ROM and then 
flashing back the backup internally. Next time I do it I'll press the 
TAB key.




coreboot-⁠5cbe3a8-⁠dirty romstage Sun Aug 23 12:18:55 BST 2015
starting...
PM1_STS:   8910
PM1_EN:
PM1_CNT:   
TCO_STS:    
GPE0_STS:  1ef82df0 187d4fdf 0005f240 
GPE0_EN:      
GEN_PMCON: 0200 2024 520b
Previous Sleep State: S5
CPU: Intel(R) Core(TM) i3-⁠5005U CPU @ 2.00GHz
CPU: ID 306d4, Broadwell E0 or F0, ucode: 001d
CPU: AES supported, TXT NOT supported, VT supported
MCH: device id 1604 (rev 09) is Broadwell F0
PCH: device id 9cc5 (rev 03) is Broadwell U Base
IGD: device id 1616 (rev 09) is Broadwell U GT2
CPU: frequency set to 2000 MHz
SPD: index 1 (GPIO47=0 GPIO9=0 GPIO13=1)
SPD: module type is DDR3
SPD: module part is HMT425S6AFR6A-⁠PB
SPD: banks 8, ranks 1, rows 15, columns 10, density 4096 Mb
SPD: device width 16 bits, bus width 64 bits
SPD: module size is 2048 MB (per channel)
Boot Count incremented to 8
ME: FW Partition Table  : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode  : NO
ME: Boot Options Present: NO
ME: Update In Progress  : NO
ME: Current Working State   : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode  : Normal
ME: Error Code  : No Error
ME: Progress Phase  : BUP Phase
ME: Power Management Event  : Pseudo-⁠global reset
ME: Progress Phase State: Waiting for DID BIOS message
ME: HSIO Version: 8705 (CRC 0xfbc2)
No FMAP found at ffe1.
FMAP: area RW_MRC_CACHE not found
No MRC cache found.
Starting Memory Reference Code
Initializing Policy
Installing common PPI
MRC: Starting...
Initializing Memory
MRC: Done.
MRC Version 2.6.0 Build 0
memcfg DDR3 clock 1600 MHz
memcfg channel assignment: A: 0, B  1, C  2
memcfg channel[0] config (00780008):
   enhanced interleave mode on
   rank interleave on
   DIMMA 2048 MB width x16 single rank, selected
   DIMMB 0 MB width x16 single rank
memcfg channel[1] config (00780008):
   enhanced interleave mode on
   rank interleave on
   DIMMA 2048 MB width x16 single rank, selected
   DIMMB 0 MB width x16 single rank
CBMEM: root @ 7cfff000 254 entries.
MRC data at ff7d0d9c 6246 bytes
Relocate MRC DATA from ff7d0d9c to 7cfeb000 (6246 bytes)
create cbmem for dimm information



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Re: [coreboot] Acer Chromebook 15 debug

2015-09-02 Thread John Lewis 

On 2015-09-02 01:26, Stefan Reinauer wrote:

* John Lewis  [150830 18:43]:

Hi Guys,

Coolstar Organisation wants to do his Windows thang with one of the
Broadwell Chromebooks, so I'm trying to build a working ROM with 
chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-yuna-6301.59.B

to give him a hand. Luckily USB debug works with this, so here is
what I'm getting. What could I do next?


Do you happen to know if the hang happens at the same spot when using
serial?



Incidentally, if I flash back my backup, it goes into recovery mode
now every time I boot (flags are 0x489), I've tried pulling the
battery to no avail. If anyone has a trick to get around that, I'd
appreciate it, as the Acer is my main machine.


What is the recovery reason? ( at the recovery screen)



0x54 TPM read error in rewritable firmware

I've done a bit more work and got that coreboot branch building in what 
I think is a relatively sane manner, although it doesn't get us any 
further in the bootstrap process. I'm going to continue with that, as at 
the moment the external refcode binary is being left out. If I get 
stuck, or I make progress, I'll post the diff and log output. Thanks for 
your input so far.


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Re: [coreboot] Acer Chromebook 15 debug

2015-09-02 Thread John Lewis 
I think I'm going to come at this from a different angle. I'm trying to 
do a fresh build and here is what I have so far. What's the best way of 
getting around these errors?:


build/lib/cbfs.romstage.o: In function `load_stage_from_cbfs':
/home/dad/coreboot/firmware-yuna-6301.59.B/src/lib/cbfs.c:132: undefined 
reference to `rmodule_stage_load_from_cbfs'
build/soc/intel/broadwell/romstage/romstage.romstage.o: In function 
`romstage_main':
/home/dad/coreboot/firmware-yuna-6301.59.B/src/soc/intel/broadwell/romstage/romstage.c:75: 
undefined reference to `mainboard_pre_console_init'

collect2: error: ld returned 1 exit status
src/arch/x86/Makefile.inc:213: recipe for target 
'build/cbfs/fallback/romstage_null.debug' failed

make: *** [build/cbfs/fallback/romstage_null.debug] Error 1

These are the changes I've made so far:

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 0ef12fb..1e058a7 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -161,6 +161,7 @@ void google_chromeec_check_ec_image(int 
expected_type)

}
 }

+#if CONFIG_CHROMEOS
 /* Check for recovery mode and ensure EC is in RO */
 void google_chromeec_early_init(void)
 {
@@ -169,6 +170,7 @@ void google_chromeec_early_init(void)
google_chromeec_check_ec_image(EC_IMAGE_RO);
}
 }
+#endif

 void google_chromeec_check_pd_image(int expected_type)
 {
@@ -200,6 +202,7 @@ void google_chromeec_check_pd_image(int 
expected_type)

}
 }

+#if CONFIG_CHROMEOS
 /* Check for recovery mode and ensure PD is in RO */
 void google_chromeec_early_pd_init(void)
 {
@@ -210,6 +213,8 @@ void google_chromeec_early_pd_init(void)
 }
 #endif

+#endif
+
 u16 google_chromeec_get_board_version(void)
 {
struct chromeec_command cmd;
diff --git a/src/mainboard/google/auron_yuna/Kconfig 
b/src/mainboard/google/auron_yuna/Kconfig

index 2db9689..1e56e0f 100644
--- a/src/mainboard/google/auron_yuna/Kconfig
+++ b/src/mainboard/google/auron_yuna/Kconfig
@@ -12,8 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_RESUME
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
-   select CHROMEOS
-   select CHROMEOS_VBNV_CMOS
select EXTERNAL_MRC_BLOB
select CACHE_ROM
select MARK_GRAPHICS_MEM_WRCOMB
diff --git a/src/mainboard/google/auron_yuna/romstage.c 
b/src/mainboard/google/auron_yuna/romstage.c

index 705b0af..c1a3916 100644
--- a/src/mainboard/google/auron_yuna/romstage.c
+++ b/src/mainboard/google/auron_yuna/romstage.c
@@ -35,8 +35,10 @@ void mainboard_romstage_entry(struct romstage_params 
*rp)


post_code(0x32);

+   #if CONFIG_CHROMEOS
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
+   #endif

/* Initialize GPIOs */
init_gpios(mainboard_gpio_config);

And this is my current .config (minus things which aren't set):

CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_ALT_CBFS_LOAD_PAYLOAD=y
CONFIG_COMPILER_GCC=y
CONFIG_COMPRESS_RAMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_DYNAMIC_CBMEM=y
CONFIG_COLLECT_TIMESTAMPS=y

CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="google/auron_yuna"
CONFIG_MAINBOARD_PART_NUMBER="Auron_Yuna"
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_MAINBOARD_VENDOR="GOOGLE"
CONFIG_MAX_CPUS=8
CONFIG_RAMTOP=0x20
CONFIG_HEAP_SIZE=0x4000
CONFIG_RAMBASE=0x10
CONFIG_VGA_BIOS_ID="8086,1616"
CONFIG_STACK_SIZE=0x1000
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_VGA_BIOS=y
CONFIG_CONSOLE_POST=y
CONFIG_DCACHE_RAM_BASE=0xff7c
CONFIG_DCACHE_RAM_SIZE=0x1
CONFIG_SERIAL_CPU_INIT=y
CONFIG_ACPI_SSDTX_NUM=0
CONFIG_VGA_BIOS_FILE="pci8086,0406.rom"
CONFIG_MMCONF_BASE_ADDRESS=0xf000
CONFIG_XIP_ROM_SIZE=0x1
CONFIG_VENDOR_SPECIFIC_OPTIONS=y
CONFIG_BOARD_GOOGLE_AURON_YUNA=y
CONFIG_VBOOT_RAMSTAGE_INDEX=0x2
CONFIG_VBOOT_REFCODE_INDEX=0x3
CONFIG_MAINBOARD_FAMILY="Google_Auron"
CONFIG_BOOT_MEDIA_SPI_BUS=0
CONFIG_MMCONF_SUPPORT_DEFAULT=y
CONFIG_LOGICAL_CPUS=y
CONFIG_IOAPIC=y
CONFIG_SMP=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
CONFIG_USBDEBUG=y
CONFIG_CPU_ADDR_BITS=36
CONFIG_BOARD_ROMSIZE_KB_8192=y
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
CONFIG_COREBOOT_ROMSIZE_KB=8192
CONFIG_ROM_SIZE=0x80
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_ENCLOSURE_TYPE=0x3
CONFIG_ARCH_X86=y

CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_MARK_GRAPHICS_MEM_WRCOMB=y
CONFIG_X86_BOOTBLOCK_SIMPLE=y
CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
CONFIG_PC80_SYSTEM=y
CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="soc/intel/broadwell/bootblock/systemagent.c"
CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="soc/intel/broadwell/bootblock/pch.c"
CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
CONFIG_HPET_ADDRESS=0xfed0
CONFIG_ID_SECTION_OFFSET=0x80

CONFIG_ARM_BOOTBLOCK_SIMPLE=y



CONFIG_BOOTBLOCK_CPU_INIT="soc/intel/broadwell/bootblock/cpu.c"

Re: [coreboot] Acer Chromebook 15 debug

2015-09-01 Thread Stefan Reinauer 
* John Lewis  [150830 18:43]:
> Hi Guys,
> 
> Coolstar Organisation wants to do his Windows thang with one of the
> Broadwell Chromebooks, so I'm trying to build a working ROM with 
> chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-yuna-6301.59.B
> to give him a hand. Luckily USB debug works with this, so here is
> what I'm getting. What could I do next?
 
Do you happen to know if the hang happens at the same spot when using
serial?


> Incidentally, if I flash back my backup, it goes into recovery mode
> now every time I boot (flags are 0x489), I've tried pulling the
> battery to no avail. If anyone has a trick to get around that, I'd
> appreciate it, as the Acer is my main machine.
 
What is the recovery reason? ( at the recovery screen)


> -⁠John.
> 
> coreboot-⁠5cbe3a8-⁠dirty romstage Sun Aug 23 12:18:55 BST 2015
> starting...
> 
> PM1_STS:   8910
> 
> PM1_EN:
> 
> PM1_CNT:   
> 
> TCO_STS:    
> 
> GPE0_STS:  1ef82df0 187d4fdf 0005f240 
> 
> GPE0_EN:      
> 
> GEN_PMCON: 0200 2024 520b
> 
> Previous Sleep State: S5
> 
> CPU: Intel(R) Core(TM) i3-⁠5005U CPU @ 2.00GHz
> 
> CPU: ID 306d4, Broadwell E0 or F0, ucode: 001d
> 
> CPU: AES supported, TXT NOT supported, VT supported
> 
> MCH: device id 1604 (rev 09) is Broadwell F0
> 
> PCH: device id 9cc5 (rev 03) is Broadwell U Base
> 
> IGD: device id 1616 (rev 09) is Broadwell U GT2
> 
> CPU: frequency set to 2000 MHz
> 
> SPD: index 1 (GPIO47=0 GPIO9=0 GPIO13=1)
> 
> SPD: module type is DDR3
> 
> SPD: module part is HMT425S6AFR6A-⁠PB
> 
> SPD: banks 8, ranks 1, rows 15, columns 10, density 4096 Mb
> 
> SPD: device width 16 bits, bus width 64 bits
> 
> SPD: module size is 2048 MB (per channel)
> 
> Boot Count incremented to 8
> 
> ME: FW Partition Table  : OK
> 
> ME: Bringup Loader Failure  : NO
> 
> ME: Firmware Init Complete  : NO
> 
> ME: Manufacturing Mode  : NO
> 
> ME: Boot Options Present: NO
> 
> ME: Update In Progress  : NO
> 
> ME: Current Working State   : Normal
> 
> ME: Current Operation State : Bring up
> 
> ME: Current Operation Mode  : Normal
> 
> ME: Error Code  : No Error
> 
> ME: Progress Phase  : BUP Phase
> 
> ME: Power Management Event  : Pseudo-⁠global reset
> 
> ME: Progress Phase State: Waiting for DID BIOS message
> 
> ME: HSIO Version: 8705 (CRC 0xfbc2)
> 
> No FMAP found at ffe1.
> 
> FMAP: area RW_MRC_CACHE not found
> 
> No MRC cache found.
> 
> Starting Memory Reference Code
> 
> Initializing Policy
> 
> Installing common PPI
> 
> MRC: Starting...
> 
> Initializing Memory
> 
> MRC: Done.
> 
> MRC Version 2.6.0 Build 0
> 
> memcfg DDR3 clock 1600 MHz
> 
> memcfg channel assignment: A: 0, B  1, C  2
> 
> memcfg channel[0] config (00780008):
> 
>enhanced interleave mode on
> 
>rank interleave on
> 
>DIMMA 2048 MB width x16 single rank, selected
> 
>DIMMB 0 MB width x16 single rank
> 
> memcfg channel[1] config (00780008):
> 
>enhanced interleave mode on
> 
>rank interleave on
> 
>DIMMA 2048 MB width x16 single rank, selected
> 
>DIMMB 0 MB width x16 single rank
> 
> CBMEM: root @ 7cfff000 254 entries.
> 
> MRC data at ff7d0d9c 6246 bytes
> 
> Relocate MRC DATA from ff7d0d9c to 7cfeb000 (6246 bytes)
> 
> create cbmem for dimm information
> 
> -- 
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

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[coreboot] Acer Chromebook 15 debug

2015-08-30 Thread John Lewis 

Hi Guys,

Coolstar Organisation wants to do his Windows thang with one of the 
Broadwell Chromebooks, so I'm trying to build a working ROM with 
chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-yuna-6301.59.B 
to give him a hand. Luckily USB debug works with this, so here is what 
I'm getting. What could I do next?


Incidentally, if I flash back my backup, it goes into recovery mode now 
every time I boot (flags are 0x489), I've tried pulling the battery to 
no avail. If anyone has a trick to get around that, I'd appreciate it, 
as the Acer is my main machine.


-⁠John.

coreboot-⁠5cbe3a8-⁠dirty romstage Sun Aug 23 12:18:55 BST 2015 
starting...


PM1_STS:   8910

PM1_EN:

PM1_CNT:   

TCO_STS:    

GPE0_STS:  1ef82df0 187d4fdf 0005f240 

GPE0_EN:      

GEN_PMCON: 0200 2024 520b

Previous Sleep State: S5

CPU: Intel(R) Core(TM) i3-⁠5005U CPU @ 2.00GHz

CPU: ID 306d4, Broadwell E0 or F0, ucode: 001d

CPU: AES supported, TXT NOT supported, VT supported

MCH: device id 1604 (rev 09) is Broadwell F0

PCH: device id 9cc5 (rev 03) is Broadwell U Base

IGD: device id 1616 (rev 09) is Broadwell U GT2

CPU: frequency set to 2000 MHz

SPD: index 1 (GPIO47=0 GPIO9=0 GPIO13=1)

SPD: module type is DDR3

SPD: module part is HMT425S6AFR6A-⁠PB

SPD: banks 8, ranks 1, rows 15, columns 10, density 4096 Mb

SPD: device width 16 bits, bus width 64 bits

SPD: module size is 2048 MB (per channel)

Boot Count incremented to 8

ME: FW Partition Table  : OK

ME: Bringup Loader Failure  : NO

ME: Firmware Init Complete  : NO

ME: Manufacturing Mode  : NO

ME: Boot Options Present: NO

ME: Update In Progress  : NO

ME: Current Working State   : Normal

ME: Current Operation State : Bring up

ME: Current Operation Mode  : Normal

ME: Error Code  : No Error

ME: Progress Phase  : BUP Phase

ME: Power Management Event  : Pseudo-⁠global reset

ME: Progress Phase State: Waiting for DID BIOS message

ME: HSIO Version: 8705 (CRC 0xfbc2)

No FMAP found at ffe1.

FMAP: area RW_MRC_CACHE not found

No MRC cache found.

Starting Memory Reference Code

Initializing Policy

Installing common PPI

MRC: Starting...

Initializing Memory

MRC: Done.

MRC Version 2.6.0 Build 0

memcfg DDR3 clock 1600 MHz

memcfg channel assignment: A: 0, B  1, C  2

memcfg channel[0] config (00780008):

   enhanced interleave mode on

   rank interleave on

   DIMMA 2048 MB width x16 single rank, selected

   DIMMB 0 MB width x16 single rank

memcfg channel[1] config (00780008):

   enhanced interleave mode on

   rank interleave on

   DIMMA 2048 MB width x16 single rank, selected

   DIMMB 0 MB width x16 single rank

CBMEM: root @ 7cfff000 254 entries.

MRC data at ff7d0d9c 6246 bytes

Relocate MRC DATA from ff7d0d9c to 7cfeb000 (6246 bytes)

create cbmem for dimm information

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[coreboot] Acer Chromebook 15 debug

2015-08-29 Thread John Lewis 

Hi Guys,

Coolstar Organisation wants to do his Windows thang with one of the 
Broadwell Chromebooks, so I'm trying to build a working ROM with 
https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-yuna-6301.59.B 
to give him a hand. Luckily USB debug works with this, so here is what 
I'm getting. What could I do next?


-John.

coreboot-5cbe3a8-dirty romstage Sun Aug 23 12:18:55 BST 2015 starting...

PM1_STS:   8910

PM1_EN:

PM1_CNT:   

TCO_STS:    

GPE0_STS:  1ef82df0 187d4fdf 0005f240 

GPE0_EN:      

GEN_PMCON: 0200 2024 520b

Previous Sleep State: S5

CPU: Intel(R) Core(TM) i3-5005U CPU @ 2.00GHz

CPU: ID 306d4, Broadwell E0 or F0, ucode: 001d

CPU: AES supported, TXT NOT supported, VT supported

MCH: device id 1604 (rev 09) is Broadwell F0

PCH: device id 9cc5 (rev 03) is Broadwell U Base

IGD: device id 1616 (rev 09) is Broadwell U GT2

CPU: frequency set to 2000 MHz

SPD: index 1 (GPIO47=0 GPIO9=0 GPIO13=1)

SPD: module type is DDR3

SPD: module part is HMT425S6AFR6A-PB

SPD: banks 8, ranks 1, rows 15, columns 10, density 4096 Mb

SPD: device width 16 bits, bus width 64 bits

SPD: module size is 2048 MB (per channel)

Boot Count incremented to 8

ME: FW Partition Table  : OK

ME: Bringup Loader Failure  : NO

ME: Firmware Init Complete  : NO

ME: Manufacturing Mode  : NO

ME: Boot Options Present: NO

ME: Update In Progress  : NO

ME: Current Working State   : Normal

ME: Current Operation State : Bring up

ME: Current Operation Mode  : Normal

ME: Error Code  : No Error

ME: Progress Phase  : BUP Phase

ME: Power Management Event  : Pseudo-global reset

ME: Progress Phase State: Waiting for DID BIOS message

ME: HSIO Version: 8705 (CRC 0xfbc2)

No FMAP found at ffe1.

FMAP: area RW_MRC_CACHE not found

No MRC cache found.

Starting Memory Reference Code

Initializing Policy

Installing common PPI

MRC: Starting...

Initializing Memory

MRC: Done.

MRC Version 2.6.0 Build 0

memcfg DDR3 clock 1600 MHz

memcfg channel assignment: A: 0, B  1, C  2

memcfg channel[0] config (00780008):

   enhanced interleave mode on

   rank interleave on

   DIMMA 2048 MB width x16 single rank, selected

   DIMMB 0 MB width x16 single rank

memcfg channel[1] config (00780008):

   enhanced interleave mode on

   rank interleave on

   DIMMA 2048 MB width x16 single rank, selected

   DIMMB 0 MB width x16 single rank

CBMEM: root @ 7cfff000 254 entries.

MRC data at ff7d0d9c 6246 bytes

Relocate MRC DATA from ff7d0d9c to 7cfeb000 (6246 bytes)

create cbmem for dimm information



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