Re: [coreboot] Asus M2N-E no boot, post codes A5 80 73

[Balázs Vinarz]

Hi,
the first postlog is the same, so A5-80 in an endless loop, there was one
time when its end with 79 then shuts down itself, thistime the memory is in
the B1 slot.
I was made a video at 60fps, and its more accurate, so the sequence is
FF-88-80-88-78-72-28-29-24-29-25-55-89-73 than a shutdown, this time the
memory is in the A1 slot.
Im using a single-core Athlon64 3000+. I will have a try with the 2012
source, if i found one. Sadly im working on ramdisk, and the toolchain
compile takes a while even if 4 cores :) Im also considering to build a
parmanents toolchain, but thats my own problem at the moment.

Best regards.
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Re: [coreboot] Asus M2N-E no boot, post codes A5 80 73

[Balázs Vinarz]

Hi,
the first postlog is the same, so A5-80 in an endless loop, there was one
time when its end with 79 then shuts down itself, thistime the memory is in
the B1 slot.
I was made a video at 60fps, and its more accurate, so the sequence is
FF-88-80-88-78-72-28-29-24-29-25-55-89-73 than a shutdown, this time the
memory is in the A1 slot.
Im using a single-core Athlon64 3000+. I will have a try with the 2012
source, if i found one. Sadly im working on ramdisk, and the toolchain
compile takes a while even if 4 cores :)

Best regards.

2015-11-05 9:06 GMT+01:00 Kyösti Mälkki :

> Please reply to list.
>
> Yes, you need better development setup than ramdisk.
>
> Kyösti
>
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Re: [coreboot] Asus M2N-E no boot, post codes A5 80 73

[Kyösti Mälkki]

On Thu, Oct 22, 2015 at 5:59 PM, Balázs Vinarz  wrote:

> Hi.
> I compiled from the source about 6 months and now. The mobo is still
> unable to boot.
> Serial debugs are attached, i tried with many memory-modules in all
> sockets.
> There are two options, when the postcard jumps between codes A5 and 80:
>
>



>
>
PCI: 00:18.0 assign_resources, bus 0 link: 0
> PCI: 00:18.3 94 <- [0x00f800 - 0x00fbff] size 0x0400 g#�
>
> #END
>
>
Not sure if this is related, but it stops when writing AGP aperture
resource.

Can you add some more POST codes or debugging in
northbridge/amd/amdk8/misc_control.c: set_agp_aperture() ?

You could try "iommu=0" on line 52 to disable this resource, to see if you
get any further.

As for the board, it may have not been tested for several years now. Try to
go further back in history, like build from 2012. Wiki notes tell
multi-processor was never tested.

Regards,
Kyösti
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[coreboot] Asus M2N-E no boot, post codes A5 80 73

[Balázs Vinarz]

Hi.
I compiled from the source about 6 months and now. The mobo is still unable
to boot.
Serial debugs are attached, i tried with many memory-modules in all sockets.
There are two options, when the postcard jumps between codes A5 and 80:

#START
coreboot-4.1-781-g744729a Tue Oct 20 14:50:25 UTC 2015 romstage starting...

*sysinfo range: [000c8020,000c8750]

bsp_apicid=0x00

Enabling routing table for node 0 done.

Enabling UP settings

Disabling read/write/fill probes for UP... done.

coherent_ht_finalize

done

core0 started:

started ap apicid:

SBLink=00

NC node|link=00

entering optimize_link_incoherent_ht

sysinfo->link_pair_num=0x1

entering ht_optimize_link

pos=0x8a, unfiltered freq_cap=0x8075

pos=0x8a, filtered freq_cap=0x75

pos=0x52, unfiltered freq_cap=0x7f

pos=0x52, filtered freq_cap=0x7f

freq_cap1=0x75, freq_cap2=0x7f

dev1 old_freq=0x6, freq=0x6, needs_reset=0x0

dev2 old_freq=0x6, freq=0x6, needs_reset=0x0

width_cap1=0x11, width_cap2=0x11

dev1 input ln_width1=0x4, ln_width2=0x4

dev1 input width=0x1

dev1 output ln_width1=0x4, ln_width2=0x4

dev1 input|output width=0x11

old dev1 input|output width=0x11

dev2 input|output width=0x11

old dev2 input|output width=0x11

after ht_optimize_link for link pair 0, reset_needed=0x0

after optimize_link_read_pointers_chain, reset_needed=0x0

mcp55_num: 01

Ram1.00

setting up CPU 00 northbridge registers

done.

Ram2.00

sdram_set_spd_registers: paramx :000cff38

Unbuffered

333MHz

333MHz

Interleaving disabled

RAM end at 0x0010 kB

Ram3

Initializing memory:  done

Setting variable MTRR 2, base:0MB, range: 1024MB, type WB

set DQS timing:RcvrEn:Pass1: 00

 CTLRMaxDelay=ae

Total DQS Training : tsc [00]=12a29d35

Total DQS Training : tsc [01]=4d330002

Total DQS Training : tsc [02]=7a48

Total DQS Training : tsc [03]=fff85d4d0064

Ram4

Prepare CAR migration and stack regions... Fill [001ff400-001f] ...
Done
Copying data from cache to RAM...  Copy [000c8000-000c877f] to [001ff880 -
001fe
Switching to use RAM as stack...





INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00} ---



Issuing SOFT_RESET...

coreboot-4.1-781-g744729a Tue Oct 20 14:50:25 UTC 2015 romstage starting...

*sysinfo range: [000c8020,000c8750]

bsp_apicid=0x00

Enabling routing table for node 0 done.

Enabling UP settings

Disabling read/write/fill probes for UP... done.

coherent_ht_finalize

done

core0 started:

started ap apicid:

SBLink=00

NC node|link=00

entering optimize_link_incoherent_ht

sysinfo->link_pair_num=0x1

entering ht_optimize_link

pos=0x8a, unfiltered freq_cap=0x8075

pos=0x8a, filtered freq_cap=0x75

pos=0x52, unfiltered freq_cap=0x7f

pos=0x52, filtered freq_cap=0x7f

freq_cap1=0x75, freq_cap2=0x7f

dev1 old_freq=0x6, freq=0x6, needs_reset=0x0

dev2 old_freq=0x6, freq=0x6, needs_reset=0x0

width_cap1=0x11, width_cap2=0x11

dev1 input ln_width1=0x4, ln_width2=0x4

dev1 input width=0x1

dev1 output ln_width1=0x4, ln_width2=0x4

dev1 input|output width=0x11

old dev1 input|output width=0x11

dev2 input|output width=0x11

old dev2 input|output width=0x11

after ht_optimize_link for link pair 0, reset_needed=0x0

after optimize_link_read_pointers_chain, reset_needed=0x0

mcp55_num: 01

Ram1.00

setting up CPU 00 northbridge registers

done.

Ram2.00

sdram_set_spd_registers: paramx :000cff38

Unbuffered

333MHz

333MHz

Interleaving disabled

RAM end at 0x0010 kB

Ram3

Initializing memory:  done

Setting variable MTRR 2, base:0MB, range: 1024MB, type WB

set DQS timing:RcvrEn:Pass1: 00

 CTLRMaxDelay=ae

Total DQS Training : tsc [00]=12a29d35

Total DQS Training : tsc [01]=4d330002

Total DQS Training : tsc [02]=7a48

Total DQS Training : tsc [03]=fff85d4d0064

Ram4

Prepare CAR migration and stack regions... Fill [001ff400-001f] ...
Done
Copying data from cache to RAM...  Copy [000c8000-000c877f] to [001ff880 -
001fe
Switching to use RAM as stack...





INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00} ---



Issuing SOFT_RESET...

#END

And when it turn off and ends with postcode 73:

#START

ENDS WITH post 73

coreboot-4.1-781-g744729a Tue Oct 20 14:50:25 UTC 2015 romstage starting...
*sysinfo range: [000c8020,000c8750]
bsp_apicid=0x00
Enabling routing table for node 0 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
core0 started:
started ap apicid:
SBLink=00
NC node|link=00
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x807f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11