Re: [coreboot] Coreboot table
On 03/06/2016 07:50 AM, daoud yessine wrote: Hi I need your help please :) About coreboot table , where is its location in memory ? Its size ? Its contents ? Is it saved in buffer ? The coreboot table typically lives at the end of physical memory in the 4G space (e.g. in "cbmem space"). There is a forwarder entry pointing to it, living in the lower 4k of memory (typically at 0x500) The coreboot table contains various information coreboot collects about the system, such as - memory map - coreboot version - cmos options - framebuffer configuration You can use the nvramtool utility to dump the coreboot table and look at it. Stefan -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Coreboot table
Hi I need your help please :) About coreboot table , where is its location in memory ? Its size ? Its contents ? Is it saved in buffer ? Thanks ᐧ -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot table and i82801xx GPIO conflicts
> -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] > On Behalf Of Rudolf Marek > Sent: Wednesday, June 18, 2008 6:42 PM > To: Coreboot > Subject: Re: [coreboot] coreboot table and i82801xx GPIO conflicts > > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > Peter Stuge wrote: > > On Wed, Jun 18, 2008 at 12:33:32PM -0400, Joseph Smith wrote: > >> Ah, duh, your right. But what could be causing this then? > >> > >> Kernel: > >> PCI quirk: region 0400-047f claimed by ICH4 ACPI/GPIO/TCO > >> PCI quirk: region 0500-053f claimed by ICH4 GPIO > > > > Can't say without more kernel message context. > > Well that the PNP subsytem needs to be aware on non-std bars which claim > this > IO. Imagine if PCI IO allocator in linux will for some non-assigned > resource > assign same region as above. Well this wont happen because PCI io usually > starts > at 1000 but in general it might be above 1000 too. I think this was the > reason > for this quirk. - The ACPI pnp might claim this region too and in fact > ACPI > should do that. Even more specially this quirk is here mostly when ACPI > fails to > do so and the IO is above 1000 ;) > > You may ignore this as "mostly harmless". No really it is harmless for > you. > Thanks Rudolf that makes sense. That would explain it because I also get this message from coreboot " Disabling local apic...done." (Although I have no idea why coreboot disables it?). And this from the kernel: Local APIC disabled by BIOS -- you can enable it with "lapic" You can check out the boot log here to see what I mean: http://www.coreboot.org/pipermail/coreboot/2008-March/032221.html Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot table and i82801xx GPIO conflicts
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Peter Stuge wrote: > On Wed, Jun 18, 2008 at 12:33:32PM -0400, Joseph Smith wrote: >> Ah, duh, your right. But what could be causing this then? >> >> Kernel: >> PCI quirk: region 0400-047f claimed by ICH4 ACPI/GPIO/TCO >> PCI quirk: region 0500-053f claimed by ICH4 GPIO > > Can't say without more kernel message context. Well that the PNP subsytem needs to be aware on non-std bars which claim this IO. Imagine if PCI IO allocator in linux will for some non-assigned resource assign same region as above. Well this wont happen because PCI io usually starts at 1000 but in general it might be above 1000 too. I think this was the reason for this quirk. - The ACPI pnp might claim this region too and in fact ACPI should do that. Even more specially this quirk is here mostly when ACPI fails to do so and the IO is above 1000 ;) You may ignore this as "mostly harmless". No really it is harmless for you. Thanks, Rudolf -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFIWY9O3J9wPJqZRNURAqiZAJ9FHan7sztUCbnH0HPBabm8DF86IgCfYpzf qXGUZBwRg9gV/x+1raU0GgU= =VpT6 -END PGP SIGNATURE- -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot table and i82801xx GPIO conflicts
On Wed, Jun 18, 2008 at 12:33:32PM -0400, Joseph Smith wrote: > Ah, duh, your right. But what could be causing this then? > > Kernel: > PCI quirk: region 0400-047f claimed by ICH4 ACPI/GPIO/TCO > PCI quirk: region 0500-053f claimed by ICH4 GPIO Can't say without more kernel message context. //Peter -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot table and i82801xx GPIO conflicts
On Wed, 18 Jun 2008 18:12:48 +0200, Rudolf Marek <[EMAIL PROTECTED]> wrote: > Hi, > > You are mixing up memory and IO ports memory. IO ports have their own > address > space accessible with inb/outb. > Ah, duh, your right. But what could be causing this then? Kernel: PCI quirk: region 0400-047f claimed by ICH4 ACPI/GPIO/TCO PCI quirk: region 0500-053f claimed by ICH4 GPIO -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot table and i82801xx GPIO conflicts
Hi, You are mixing up memory and IO ports memory. IO ports have their own address space accessible with inb/outb. Rudolf -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] coreboot table and i82801xx GPIO conflicts
Hello, I was just reading Stefan's API wiki page and something dawned on me. For the i82801xx, the LPC GPIO Base address is set to 0x500. According to Stefan's API wiki page the coreboot table is also at 0x500. The output from the kernel indicates a conflict at 0x500? Could this be causing a conflict??? Kernel: PCI quirk: region 0400-047f claimed by ICH4 ACPI/GPIO/TCO PCI quirk: region 0500-053f claimed by ICH4 GPIO -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
