[coreboot] New on blogs.coreboot.org: coreboot changelog March 2 - March 15
A new post titled "coreboot changelog March 2 - March 15" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/03/22/coreboot-changelog-march-2-march-15/ This changelog covers 187 commits in the two week period between March 2, 2016 and March 15, 2016. (c77e0419 – 80547369) Once again this time, we had many changes in the payloads area. We added a memtest86+ git repository, and set it up as a secondary payload within the coreboot build process. SeaBIOS updated the stable version from 1.9.0 to 1.9.1 and has a new option to build from any specified commit instead of just master or stable branches. Google’s depthcharge payload was added for ChromeOS builds, and the coreinfo payload started getting some updates – removing obsolete pieces, fixing the makefile, and correcting issues with cbfs. The MediaTek MT8173 ARM based SOC and the Google OAK board using it received a significant number of patches, adding trusted firmware support, and initialization routines for memory, USB, audio, TPM, GPIOs, I2c and RTC. Several other groups of patches were to perform cleanup for various chipsets. One series unified and fixed up the UDELAY settings, many of which were incorrectly specifying TSC delays which weren’t supported by those platforms. Other sets removed code #includes of C files, merged the MRC cache implementations into a single common version, and combined Sandybridge & Ivybridge LVDS implementations. The FSP version of Intel’s Bay Trail was updated to mirror the non-FSP implementation, enabling LPE and LPSS in ACPI mode. The plan with Bay Trail is to make the two versions as similar as possible, then work to combine the directories and use common code for both. Intel has started adding support for their Xeon D (Broadwell DE) processor. So far only the vendorcode has been merged. The coreboot code is another 4700 lines of chipset code and 800 lines of mainboard code, so that’s taking some time to get reviewed. The patches bringing up the Quark and Apollo Lake Intel chips continued, with Quark getting minor updates and Apollo Lake continuing to add core functionality like memory init and the various calls into the FSP. Additional work was done on Skylake as well, updating the FSP parameter table, adding a Voltage Regulator mailbox command, and adding clock gating for the 8254 timer. Utilities only got a few changes this time. The cbmem utility got a fix a regression and correctly scale the timestamp values and an option to change the SPI ROM chip sizes was added to ifdtool. Cbfstool got a couple of fixes as well, making sure the structure sizes are the same whether compiled for 32-bit or 64 bit platforms, and zeroing out unused Linux parameters. AMD’s native memory initialization got some more cleanup and several fixes, restoring DQS delay values on a failed loop, and making sure that both read and write training pass before proceeding to the next training phase instead of continuing when either one passed. SMBIOS changes included a patch to add SMBIOS type 17 (Memory) fields to the Sandy Bridge / Ivy Bridge platforms, and another patch to fix the length calculated for those fields for every platform. A third patch added the names of several different DIMM vendors. The X86 bootblock renamed several symbols for clarification, removed some unused code, and marked the reset vector as executable so it would show up in objdump. We had a slew of patches from new authors merged in the past two weeks. Welcome to all new authors and thank you to everyone. Antonello Dettori had 3 patches merged, allowing SeaBIOS to be build from any revision, and cleaning up early serial on the roda rk9 and amd thatcher platforms. Bayi Cheng wrote a patch adding NOR flash DMA read routines for the Mediatek MT8173. Georg Wicherski updated and added Google’s auron paine board. Huki Huang modified the ChromeOS wifi regulatory domain to use the region key from VPD. Jan Tatje updated the Intel Firmware Descriptor tool (iftdool) to allow the SPI rom sizes to be updated. Jitao Shi added the parade ps8640 MIPI-to-eDP video format converter driver. Jonathan Neuschäfer had an astounding 7 patches merged in his first couple of weeks submitting to coreboot. He fixed a syntax error in buildgcc, and updating several areas in coreinfo. Jun Gao did I2C work on Mediatek MT8173 and on Google’s Oak board, Lance Zhao had a pair of patches for Intel’s Apollo Lake reference board, setting up the devicetree, and adding memory training configuration. Medha Garima added runtime SD card detection to Intel’s Kunimitsu board. Milton Chiang had a patch updating the infracfg register map for the Mediatek MT8173. Peter Kao wrote a pair of patches adding DRAM initialization to the Mediatek MT8173 and Google’s Oak board. PH Hsu set up 4GB mode on Mediatek MT8173 and Google’s Oak board. coreboot statistics - Total commits: 187 - Total authors: 44 - New authors: 13 - Total lines added: 15724 - Total lines removed: -1750 -
[coreboot] New on blogs.coreboot.org: coreboot changelog Feb 17 - March 1
A new post titled "coreboot changelog Feb 17 - March 1" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/03/06/coreboot-changelog-feb-17-march-1/ This changelog covers 105 commits in the two week period between February 17, 2016 and March 1, 2016. (6a622311 – 163506a8) We’ve entered a lower volume period for patches being submitted, so for a while, blog posts will be every two weeks instead of every week. Once we get above 100 patches a week, blog posts will be weekly again. Payloads got some attention during this period, adding a way to include additional modules into the GRUB2 build. An option was added to build and include coreinfo as a ‘secondary’ payload, allowing it to be run from another payload. We also added U-Boot as a coreboot payload. This is currently still just in development, and needs additional work before it will act as a generic payload for all platforms. We added LZ4 compression to the build with runtime decompression for cbfs. LZ4’s speed should be roughly the same as LZMA, trading a smaller compressed size for slightly slower decompressoin. LZ4’s main advantage is that it requires much less memory to do the decompression, allowing for compression of stages that couldn’t previously be compressed. The suite of board-status scripts got several updates, fixing timestamp handling for the sanitized path names, handling when the script is run as super-user in a better way, and adding a script that will set up a Ubuntu Live-image to allow users to more easily run the board-status script. In the build tools and utilities, we had some fixes for the toolchain builder, updating the GDB builds for x86_64 and MIPS. A couple of scripts were also added. One utility downloads and extracts binary blobs from Chrome OS recovery images, and the other new script allow easier testing of POST cards. Intel based boards and chipsets received a large percentage of the patches for the past two weeks: The Galileo board and Quark chip had several pieces new added, along with additional documentation for those changes. Major pieces done were to set up the basic registers, in the ACPI FADT, setting up the memory map, and enabling the UART. We received the final set of patches to finish out the changes combining many of the the Intel GPIO initialization routines into a single common set of functions. The autoport script was updated to use the common GPIO functions. Sandy Bridge / Ivy Bridge memory initialization also continued to receive updates, adding support for XMP profiles in the SPD, updating logging, and fixing some bugs. Intel’s Skylake chipset and boards were updated to enable Hardware P-state control (HWP) based on Intel’s Speed Shift Technology (SST). Another change to Skylake platforms increased stolen memory for graphics to 64MB. Intel Bay Trail got a couple of updates, adding a fix for issues with displayport on the FSP version, and adding IOSF access support to the reg_script module. Intel Apollo Lake had several more foundational pieces added to the codebase. Many more patches for Apollo Lake are expected in the next couple of weeks. On the non-X86 side, the instructions for running the Arm7 Qemu board were updated, and the memory map was corrected. RISC-V got a couple of patches, adding additional debugging, and fixing some inline asm code. The coreboot project would like to recognize another pair of developers who have hit major milestones in the past two weeks: Lee Leahy just reached his 100th commit merged into coreboot.org. Lee is a developer with Intel who has been working on coreboot for about a year and a half. He has worked on many of the recent intel chipsets, and is currently adding support and documentation for the Intel Galileo board and Quark chips in a way that each step of the process can be tested and verified. While this takes significantly more effort than the typical method of porting, it should result in a better platform. Tobias Diedrich has just had his 50th patch merged. Tobias has been contributing patches to coreboot for over five years, and his patches have spanned a number of boards and chipsets. Finally, please welcome our newest authors: – Andrew Waterman contributed the pair of RISC-V patches. – Joe Pillow added the Chrome OS recovery image script. coreboot statistics - Total commits: 105 - Total authors: 25 - Total lines added: 13396 - Total lines removed: -3127 - Total difference: 10269 Added 1 mainboard: emulation/qemu-power8 Added 1 processor: qemu-power8 Submodule updates: - 3rdparty/arm-trusted-firmware (329 commits) - 3rdparty/vboot (2 commits) === Top Authors - Number of commits === Leroy P Leahy20 (19.048%) Aaron Durbin 11 (10.476%) Patrick Rudolph 8 (7.619%) Patrick Georgi8 (7.619%) Martin Roth 8 (7.619%) Stefan Reinauer 5 (4.762%) Vladimir Serbinenko 5 (4.762%) Denis 'GNUtoo' Carikli4 (3.810%)
[coreboot] New on blogs.coreboot.org: coreboot changelog Feb 10 - Feb 16
A new post titled "coreboot changelog Feb 10 - Feb 16" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/02/18/coreboot-changelog-feb-10-feb-16/ This changelog covers 77 commits in the week between February 10, 2016 and February 16, 2016. (318ef96a – 0188b139) Many of the big changes this week surrounded native initialization of the Sandybridge/Ivybridge platforms. We got patches to change platforms which had been previously based on Intel’s MRC blob to build with either the MRC or coreboot’s native memory initialization. We also got patches combining the Intel GPIO initialization for various chipsets into a single common set of functions. Continuing the series from the past several weeks, we merged patches for the Intel Apollo Lake, Skylake, and Quark platforms. Apollo Lake got a skeleton for its initial mainboard, and added code to support GPIO init. Quark added FSP initialization and MTRR support. The more mature Skylake SoC received some minor fixes for graphics and to finalize SMM inside coreboot. Another of the Intel FSP platforms, the FSP version of the Intel Bay Trail codebase was updated to support version 5 of the Bay Trail FSP, which should be released to the Intel website shortly. On the ARM side, we got several small fixes, and a patch to verify consistency of the page table descriptors. This sounds like it will help prevent ‘interesting’ debug sessions due to conflicting memory types for the same memory area. The build system and toolchain received fixes for issues downloading git submodules, for the gitconfig make target, and for building under paths that have an ‘@’ character in their name. A couple of changes were added to make Kconfig’s strict mode slightly less strict and more user friendly. Two new lint tools were added this week, one to make sure that the site-local directory doesn’t get pushed and committed, and another that checks over the Kconfig files for various issues. Other changes this week included a change to allow bootblock code to use CAR_GLOBAL variables, and continued work updating and adding license headers throughout the coreboot codebase. Finally, I’d like to recognize two contributors this week: Damien Zammit (damo22) reached his 50th commit merged into coreboot last week. His contributions have included the addition of two complete platforms, the Intel D510MO board with the Intel Pineview Atom processor, and the Gigabyte GA-G41M-ES2L board with the Intel x4x northbridge and Intel i82801gx southbridge. Damien joined coreboot in July of 2013, but has recently become very active. Vladimir Serbinenko (phcoder) just broke 550 patches merged with his work moving Sandybridge/Ivybridge MRC platforms to native init mentioned earlier. Vladimir joined coreboot just under 3 years ago, and has been a fantastic contributor to the community. Thanks to both of you, and to all the rest of the coreboot contributors. coreboot statistics - Total commits: 77 - Total authors: 16 - Total Commits: 77 - Total lines added: 6494 - Total lines removed: -1569 - Total difference: 4925 Added 1 mainboard: intel/apollolake_rvp === Top Authors - Number of commits === Patrick Georgi 12 (15.584%) Vladimir Serbinenko 12 (15.584%) Aaron Durbin 9 (11.688%) Julius Werner 7 (9.091%) Andrey Petrov 6 (7.792%) Duncan Laurie 5 (6.494%) Martin Roth 5 (6.494%) Leroy P Leahy 4 (5.195%) Alexandru Gagniuc 3 (3.896%) Patrick Rudolph 3 (3.896%) Yves Roth 3 (3.896%) Stefan Reinauer 3 (3.896%) === Top Authors - Lines added === Ruilin Hao 2528 (38.928%) Andrey Petrov 817 (12.581%) Vladimir Serbinenko 681 (10.487%) Yves Roth 678 (10.440%) Leroy P Leahy 451 (6.945%) Patrick Rudolph 355 (5.467%) Alexandru Gagniuc 242 (3.727%) Aaron Durbin213 (3.280%) Patrick Georgi 194 (2.987%) Julius Werner 131 (2.017%) === Top Authors - Lines removed === Vladimir Serbinenko 892 (56.851%) Aaron Durbin247 (15.743%) Julius Werner 244 (15.551%) Patrick Georgi 68 (4.334%) Yves Roth64 (4.079%) Martin Roth 13 (0.829%) Duncan Laurie12 (0.765%) Patrick Rudolph 11 (0.701%) Andrey Petrov 7 (0.446%) Ruilin Hao4 (0.255%) === Top Reviewers - Number of patches reviewed === Martin Roth 31 (40.260%) Aaron Durbin 16 (20.779%) Patrick Georgi 13 (16.883%) Paul Menzel 13 (16.883%) Alexandru Gagniuc12 (15.584%) Stefan Reinauer 11 (14.286%) FEI WANG 3 (3.896%) York Yang 2 (2.597%) Andrey Petrov 2
[coreboot] New on blogs.coreboot.org: coreboot changelog Feb 3 - Feb 9
A new post titled "coreboot changelog Feb 3 - Feb 9" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/02/11/coreboot-changelog-feb-3-feb-9/ This changelog covers 107 commits in the week between February 3, 2016 and February 9, 2016. (2cc2ff6f – c285b30b) This week, it looks like the biggest set of changes were the changes directly supporting chrome verified boot, adding options for the GBB flags and supporting VBNV (vboot non-volatile storage) in cmos, flash, and the EC. The verified boot (vboot) submodule included by coreboot was also updated, bringing in another 26 patches. These changes included a variety of work committed to the chromium vboot repo over the past several months. Another submodule was added this week to bring the Chrome EC codebase into the coreboot tree. There were several additional commits to update the build to use the new submodule. The Intel Skylake and associated boards continued to get updates including more GPIO fixes, disabling the PM timer in ACPI, and unconditionally setting up the BAR for the SPI controller. Intel continued adding documentation in the Documentation/Intel directory. This is mostly targeting the newly added Galileo mainboard, the newly added Quark X1000 Soc, and version 1.1 of the Intel FSP. The AMD Family 10h / Family 15h directory and mainboard got some more patches, updating the RDIMM memory training code to work around some failures. The other main feature added was a CMOS option to enable/disable core boost. There were a number of ACPI ASL changes this week. Several were bugfixes, some were to get rid of unused variables causing warning, and others worked around different warnings generated by new versions of the IASL ACPI compiler. These will help the effort to upgrade the IASL ACPI compiler to the latest version. The native memory initialization code for the Intel Sandybridge/Ivybridge platforms had a fix for using two DIMMs per channel, and there were a few changes working towards switching the MRC based Sandybridge/Ivybridge implementations over to using native graphics and memory initialization. The goal is that the boards that currently use the Intel MRC should be able to build with either path. More of these changes will be merged in the coming weeks. The toolchain builder, buildgcc, had several changes to clean up and reorganize the makefiles, and to add a toolchain build for the nds32le architecture in support of the chrome EC builds. coreboot’s site-local directory was extended to use a Kconfig file and adds a make target which gets run at the end of the rest of the build. Documentation on how to use this should be completed and released next week. Miscellaneous other fixes include a new lint test ensuring assembly is in AT syntax, an update to the QT version for the ‘xconfig’ Kconfig front end, adding PS/2 Aux presence detect to the nuvoton nct5572d SuperIO, and adding a new ARM SoC, Marvell’s Armada 38x. Thank you to everyone who contributes to the coreboot community. New issues that we saw this week – The toolchain build seems to be broken for some people as of commit 8e68aff51 – “buildgcc: enable multilib for gcc” – There were issues with make gitconfig on a newly cloned repo caused by commit ec0b586 – “3rdparty/chromeec: Add Chrome EC firmware sources”. – Commit ec0b586 – “3rdparty/chromeec: Add Chrome EC firmware sources” also causes issues pulling down the blobs submodule. New bugs filed this week – board-status allows invalid uploads – Windows doesn’t like ToString() calls in ACPI – [Haswell/Broadwell] LPC power optimizer RCBA instructions break eDP display with Intel VBIOS – cbmem utility fails on newer linux kernels “Failed to mmap /dev/mem: Resource temporarily unavailable” – Provide and use enums for SerialIoI2cVoltage coreboot statistics for the past week - Total commits: 107 - New authors: 3 - Total authors: 24 - Reviewers on submitted patches: 11 - Total lines added: 13759 - Total lines removed: -1974 - Total difference: 11785 Added 2 mainboards: asus/kcma-d8 & intel/galileo Added 1 mainboard variant: lenovo/X220i Added 2 SoCs: intel/quark & marvell/armada38x === Top Authors - Number of commits === Leroy P Leahy15 (14.019%) Patrick Georgi 15 (14.019%) Aaron Durbin 14 (13.084%) Vladimir Serbinenko 10 (9.346%) Timothy Pearson 8 (7.477%) Duncan Laurie 7 (6.542%) Martin Roth 6 (5.607%) Stefan Reinauer 6 (5.607%) Ruilin Hao5 (4.673%) Total Authors: 25 === Top Authors - Lines added === Timothy Pearson3956 (28.752%) Ruilin Hao 2964 (21.542%) Leroy P Leahy 2780 (20.205%) Duncan Laurie 1091 (7.929%) Zheng Bao 463 (3.365%) Dhaval Sharma 450 (3.271%) Patrick Georgi 397 (2.885%) Aaron Durbin397 (2.885%) Lee Leahy 346
[coreboot] New on blogs.coreboot.org: coreboot changelog Jan 27 – Feb 2
A new post titled "coreboot changelog Jan 27 – Feb 2" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/02/03/coreboot-changelog-jan-27-feb-2/ This changelog covers 131 commits in the week between January 27, 2016 and February 2, 2016. (dd4b66e2 – 95909924) The biggest news of the past week was getting the 4.3 release done. The 4.4 release should come towards the end of April. Of particular note to anyone submitting patches, we added 2 new code checkers this week, one to verify that the executable bit isn’t set on source files, and one to verify that the standard coreboot license header is used on files using the GPL 2 or 2+ licenses. These checks will be run automatically when you commit code if you have the git commit hook in place, and will also be run on the build server. coreboot again had numerous patches surrounding the build system, tools, and utilities. The flood of cbfstool related patches finally slowed a bit, but we still had some cleanup, both in the tool and in the cbfs sections of the Makefiles. In the toolchain area, we updated LLVM to version 3.7.1, and added GNU Make to the toolchain. The addition of make was to address some upcoming patches that needed the newer version, as well as to support platforms that don’t install GNU make by default. The kconfig_lint tool had various updates to get rid of warnings that we don’t care about, to add documentation, and to add a couple of additional checks. Next week will see a few more fixes, and it will be put in place as a stable lint tool. We had significant updates to a number of mainboards and the related chipsets in the past week as well. Intel had a large number of changes for their Braswell SoC and its reference board, Strago, merged this week. These included fixes for GPIOs, clocks, SD cards, and thermal support, as well as FSP integration updates. The Asus kgpe-d16 mainboard, along with the AMD Fam10h-Fam15h processor directory and the SB700 soutbridge had numerous patches to improve stability, fix IRQ routing and APIC identification, and improve ACPI. The winbond w83667hg-a was added to the coreboot codebase for the board as well. The Intel d510mo board had some improvements related to native graphics initialization, GPIOs and ACPI. The gigabyte ga-g41m-es2l and the Intel x4x northbridge code had some general cleanup and improvements to cbmem and memory initialization. We also saw the introduction of the initial framework for the new Intel Apollo Lake SoC. We’ll be seeing many more patches related to Apollo Lake in the coming weeks. Other changes of note included code to initialize the PS/2 aux port, a way to access memory address 0 without GCC “optimizing” it into a crash, and the addition of some documentation from Intel about developing new FSP based boards and chipsets. Finally, the Intel sklrvp Skylake reference board was dropped in favor of using the kunimitsu board. coreboot statistics for the past week - Total commits: 131 - New authors: 8 - Total authors: 30 - Total lines added: 3833 - Total lines removed: -3652 - Delta: 181 === Top Authors - Number of commits === Timothy Pearson 22 (16.794%) Martin Roth 21 (16.031%) Patrick Georgi 15 (11.450%) Damien Zammit13 (9.924%) Hannah Williams 12 (9.160%) Leroy P Leahy 5 (3.817%) Stefan Reinauer 5 (3.817%) Divagar Mohandass 4 (3.053%) Vladimir Serbinenko 3 (2.290%) Alexandru Gagniuc 3 (2.290%) Total Authors: 31 === Top Authors - Lines added === Damien Zammit 725 (18.915%) Timothy Pearson 701 (18.289%) Leroy P Leahy 646 (16.854%) Subrata Banik 427 (11.140%) Martin Roth 262 (6.835%) Aaron Durbin204 (5.322%) Patrick Georgi 179 (4.670%) Alexandru Gagniuc 140 (3.652%) shkim 107 (2.792%) Nico Huber 91 (2.374%) === Top Authors - Lines removed === Martin Roth1688 (46.221%) Hannah Williams 661 (18.100%) Divagar Mohandass 315 (8.625%) Damien Zammit 307 (8.406%) Timothy Pearson 212 (5.805%) Patrick Georgi 104 (2.848%) Nico Huber 102 (2.793%) Leroy P Leahy95 (2.601%) Stefan Reinauer 43 (1.177%) Lee Leahy23 (0.630%) === Top Reviewers - Number of patches reviewed === Martin Roth 71 (54.198%) Stefan Reinauer 20 (15.267%) Patrick Georgi 18 (13.740%) Paul Menzel 16 (12.214%) Alexandru Gagniuc14 (10.687%) Aaron Durbin 10 (7.634%) Felix Held8 (6.107%) Timothy Pearson 7 (5.344%) Nico Huber4 (3.053%) Alexander Couzens 3 (2.290%) Total Reviewers: 15 === Top Submitters - Number of
[coreboot] New on blogs.coreboot.org: coreboot changelog Jan 5 - Jan 24
A new post titled "coreboot changelog Jan 5 - Jan 24" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/01/20/coreboot-changelog-jan-5-jan-24/ This changelog covers the 180 commits between January 5, 2016 and January 19, 2016. (af91b8b0 – 967881d0) We’re preparing for the coreboot 4.3 release, expected to happen sometime in the next week, so there has been a lot of activity surrounding Intel’s Skylake chips, both in the mainboards and SOC directories. The Skylake and braswell platforms are finally being build-tested by jenkins, which will help keep the platforms working. The changes in cbfstool are continuing to roll in, although this should be wrapping up before long as the merger of cbfs with FMAP is completed. The effort to standardize coreboot’s license headers across all files is just starting, and will be going on for a few weeks as we verify that all source files have the correct headers. We’ve added and improved the lint checkers for these so expect failures from jenkins if files with non-compliant headers are pushed. A fair amount of work was done in the build system in the past couple of weeks. This removed the warnings about cross compilers not existing unless that architecture is currently being built, fixed some dependency issues, and fixed several other minor issues. A make target to check that the coreboot toolchain was also added. We had a slight toolchain change, going to MPFR version 3.1.3 to fix some issues seen on the upcoming Power8 processor. Additional changes added NetBSD support for various utilities, and update the intel/gm45 and intel/pineview northbridges. Added 1 mainboard: ——- – google/guado coreboot statistics ——- – Total commits: 180 – New authors: 13 – Total authors: 45 – Total reviwewrs: 19 – Total lines added: 9168 – Total lines removed: -2130 – Total difference: 7038 === Authors – Number of commits === Martin Roth 56 (31.111%) David Wu 15 (8.333%) Aaron Durbin 12 (6.667%) Duncan Laurie 9 (5.000%) Subrata Banik 8 (4.444%) Rizwan Qureshi 7 (3.889%) Nico Huber 6 (3.333%) Patrick Georgi 6 (3.333%) Timothy Pearson 5 (2.778%) Barnali Sarkar 5 (2.778%) Total Authors: 45 === Authors – Lines added === Martin Roth 2359 (25.731%) Matt DeVillier 2243 (24.466%) Aaron Durbin 1988 (21.684%) Rizwan Qureshi 606 (6.610%) Subrata Banik 292 (3.185%) Barnali Sarkar 178 (1.942%) robbie zhang 158 (1.723%) Nico Huber 144 (1.571%) Andrey Korolyov 133 (1.451%) David Wu 128 (1.396%) === Authors – Lines removed === Martin Roth 1038 (48.732%) Barnali Sarkar 173 (8.122%) Aaron Durbin 144 (6.761%) Nico Huber 108 (5.070%) Patrick Georgi 98 (4.601%) Shaunak Saha 81 (3.803%) Paul Menzel 69 (3.239%) Patrick Rudolph 68 (3.192%) Subrata Banik 64 (3.005%) Duncan Laurie 61 (2.864%) === Reviewers – Number of patches reviewed === Martin Roth 91 (50.556%) Stefan Reinauer 43 (23.889%) Patrick Georgi 43 (23.889%) Paul Menzel 23 (12.778%) Alexandru Gagniuc 13 (7.222%) Nico Huber 7 (3.889%) York Yang 3 (1.667%) Werner Zeh 3 (1.667%) Aaron Durbin 3 (1.667%) Total Reviewers: 19 === Submitters – Number of patches submitted === Martin Roth 89 (49.444%) Patrick Georgi 73 (40.556%) Aaron Durbin 9 (5.000%) Stefan Reinauer 4 (2.222%) Vladimir Serbinenko 3 (1.667%) Werner Zeh 1 (0.556%) Nico Huber 1 (0.556%) Total Submitters: 7 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New on blogs.coreboot.org: coreboot changelog
A new post titled "coreboot changelog" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2015/11/23/coreboot-changelog-6/ The week leading up to November 15th has seen 132 commits (8bd1c36..3ca4116). The leading themes were the removal of support for old mainboards, and the integration of more non-AGESA AMD support code for Family 10h to 15h that spans everything from fixes to memory configuration to workarounds to problems in the SATA controller, to new feature development, enabling CC6 power-state support and everything in-between. Other chipset level contributions provided bug fixes to the drivers supporting Intel’s Skylake and AMD’s newer chipsets and mainboards (Kabini, Merlin Falcon, Mullins). Rockchip RK3288 now properly configures displays whether they’re connected through HDMI or DVI. ARM/ARM64 saw some cleanup in its transition between stages to accommodate more processor configurations on ARM64 SoCs (that sometimes come with smaller 32bit cores for supporting purposes). Also new is the Intel i8900 southbridge support that can be used with Sandy Bridge and Ivy Bridge, with an Intel reference board, the stargo2, and the SUNW Ultra40m2 board support. The USB device mode driver for DesignWare’s USB2 controller (DWC2) in libpayload became more robust. The other notable field of work in libpayload is work with PDcurses’ upstream to synchronize their development and our copy. In terms of the ongoing efforts to clean up old cruft across the entire tree, references to the getpir utility were dropped, after the tool was removed nearly two years ago. We also removed empty mainboard driver files that used to be required by the build system, even if the mainboard needed no special handling in its ramstage. To help keep the quality bar high, automated testing now also covers intelvbttool. Another forward-looking addition is a clang-format specification of our coding style. It isn’t complete yet, but the hope is that we can eventually use it to simplify adhering to a consistent style and then enforce it. The script to help organizing the commit log for release notes was pushed into util/release. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New on blogs.coreboot.org: coreboot changelog
A new post titled "coreboot changelog" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2015/11/10/coreboot-changelog-5/ This changelog covers the week up to November 8th, spanning 63 commits (f6dc544..8bd1c36). Last week’s code submissions gave us a lot of improvements pretty much everywhere, but the most user-visible change is probably the addition of ACPI S3 support to asrock/e350m1. Speaking of ACPI, support for the DMAR tables used to report Intel IOMMU (VT-d) information to the operating system was significantly improved and is enabled on Sandy Bridge and Ivy Bridge. Another user visible change is the rework of the fallback mechanism in our bootblock, making its CMOS-backed state handling more robust. cbmem also saw some changes in that all its entries are now listed separately in cbtables (and util/cbmem uses that new structure) to cut down on what coreboot exposes as interface. On the architectures side, ARM64 dropped its sec(urity) mon(itor) code in favor of using ARM Ltd’s Open Source arm-trusted-firmware, which we already import in 3rdparty. The integration of commits to support AMD Fam15h CPUs with a non-AGESA implementation that integrates better with coreboot saw some progress. The AMD Binary PI side saw a number of bug fixes, too. Boards based on Intel’s Skylake architecture also saw more development. In addition to these targetted developments, there was also the usual set of bug fixes across the entire tree, providing some cleanups to the code and configuration system, some portability fixes for Windows and Mac OS X, deduplication of ACPI table generation on i945, and the removal of a Super IO that wasn’t used by any board (and thus isn’t even build tested). The USB device mode driver in libpayload for the DesignWare USB2 controller works better under debugging, while the XHCI USB3 host controller driver gained a workaround for Intel XHCI controllers. Finally, the board-status scripts that parse boot success reports into the list of supported motherboards on the wiki were modified to point out more clearly that the list on the wiki describes the current status. This became necessary because some users assumed that it’s outdated. Since the i440bx mainboards that were at the top of the list may have contributed to that impression, desktop boards were moved down in favor of notebooks and server boards where most of the current development happens. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New on blogs.coreboot.org: coreboot changelog
A new post titled "coreboot changelog" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2015/11/05/coreboot-changelog-4/ This changelog covers 2 weeks up to November 1st, during which coreboot-4.2 was released. In that timeframe, the repository saw 214 commits spanning d98471c..f6dc544. Before we get to the stuff that the tech media gets excited about, the first thing to report about is a bunch of efforts to improve the reliability of our tree and the automated testing we conduct. abuild, the utility for automatically building the default configuration of every board in the tree, learned to deal with mainboard directories that cover multiple variants of a board. This brings back build test coverage for google/veyron. Various programs in the util/ hierarchy of the tree are now automatically tested by our build test infrastructure, and the related code saw some refactoring to make testing more tools really simple. During that development, some Makefiles below util/ were also cleaned up. Another area of clean ups was the conversion of `#ifdef` statements to using the `IS_ENABLED` macro. This ensures that even unused code paths are syntactically validated before the optimizer drops them, leading to the same binary output with better build test coverage. In preparation of future improvements, we gained a lint tool for Kconfig files. It will be hooked up to the build system once the tree is clean, until then it provides a way to see what’s still missing. Check out `util/lint/kconfig_lint` if you’re curious. As a proof of concept, util/fuzz-tests now provides an environment to test the jpeg decoder we ship for splash screens using [afl-fuzz](http://lcamtuf.coredump.cx/afl/). The same approach can be applied to other coreboot components to find potential crash bugs (or worse). Finally, several chip drivers were removed because they had no user in the tree anymore and thus saw no testing at all. Some of them will likely come back together with new mainboards that use them. In addition to the code development to improve code quality, `util/scripts/maintainers.go` provides a way to query the MAINTAINERS database that we’re building, as one piece of a larger effort to improve code quality through formal submodule maintainership. Another formal clean-up was the tree-wide removal of the last paragraph of the GPL license header in files, the one denoting where to obtain the license text. First, we ship it in the tree, second, it’s probably easier to get with a quick search engine request than by writing a letter to a US post address that may or may not be current. Rockchip’s RK3288 gained support for additional power/clock states and a more robust EDID handling. The ongoing effort to support booting in long mode (64 bit) on AMD64 progressed by the integration of changes to make SMM handling and AMD chipset drivers 64bit clean. Some ACPI for older Intel chipsets was consolidated and is now used for multiple chipset generations. The Intel GMA driver has also seen improvements, allowing brightness levels for laptop panels to be configured per board, and to disable the graphics chip entirely. In terms of drivers, the aspeed driver provides native VGA text, and there were improvements to superio and i2c chip drivers, supporting more of their features. Sandybridge now initializes CPUs serially for robustness reasons, and Intel FSP supports loading microcode from coreboot. cbfstool now extracts stages and rmodules as ELF files, including relocation information for the former, so that roundtrips of add-stage/extract/add-stage become possible. It now also compiles more reliably on Cygwin. libpayload saw the additional of a graphics library to layout images on a framebuffer using framebuffer independent coordinates, and some bug fixes to its USB drivers. In addition to all those cleanups and little new features, coreboot also provides support for a couple new boards, in particular two Intel Skylake based boards by Google (google/chell and google/lars) as well as Asus KFSN4-DRE with K8 CPUs and Asus KGPE-D16 with more recent AMD CPUs (Fam10h and Fam15h). All related chipsets also saw significant improvements, of which the still ongoing effort to provide non-AGESA implementations for the Fam15h CPU, as well as a ton (metric, in case you’re curious) of bugfixes and feature developments (for example Suspend to RAM) for all AMD CPUs starting with K8 is particularly notable. Besides those changes, and minor (but valuable) contributions to improve the code style, there’s a bucket list of improvements across the entire tree: more robust SMM entry on i945, fixes to our SMBIOS table generation, changes to the resource allocator to become more robust and IOMMU friendly and to measure the time it takes, and improvements to the robustness of our build process. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New on blogs.coreboot.org: coreboot changelog
A new post titled "coreboot changelog" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2015/10/22/coreboot-changelog-3/ This report covers commits b66d673..d98471c, the week up to Sunday, 2015-10-18 This week has an interesting distribution in its commits: A few very large and impactful commits (and commit sets), but otherwise lots of tiny little things. The last months typically saw more cohesive changes each week, affecting a small number of subsystems or drivers – but not this week. The biggest item in terms of code size was the reintroduction of Intel’s Rangeley SoC and related mainboard, which were found to still be requested by users after all. The biggest item in terms of impact was probably the improvement of our automated build testing by adding our lint tests and build tests for various utilities to our build infrastructure, reporting any errors (and preventing them from creeping into the master branch). We don’t test all tools yet, but adding the others should be painless now. libpayload also gained a new test configuration so both libcurses implementations are now covered. The vboot verstage concept was ported to x86 and added to FSP 1.1, allowing a separate verification stage to check romstage before executing it (from a potentially unsafe location). AMD microcode can now be loaded from CBFS, and using their standard format instead of a custom layout that was used by coreboot until now. Apart from these, changes happened all across the tree: SMBIOS tables report memory vendors; ACPI was cleaned up to work better with new ACPI compiler versions; there’s better reporting for MTRR configurations, and related macros have more sensible names; the ARMv7 code avoids miscompilation with gcc-5.2, which is significant because that’s our standard compiler version; Intel GMA ACPI saw improvements; there were tons of style fixes in preparation to deal with the addition of lint tests to the automated tests; cbfstool can now add files after files of the same name were removed from an image; the coreinfo payload has the sense to reboot after it’s done; the cbmem utility is more robust, and several more cleanups and bugfixes. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New on blogs.coreboot.org: coreboot changelog – Weeks of 2015-08-10 and 2015-08-17
A new post titled "coreboot changelog – Weeks of 2015-08-10 and 2015-08-17" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2015/08/29/coreboot-changelog-weeks-of-2015-08-10-and-2015-08-17/ this report covers commits 1cbef1c to 410f9ad The vast majority of changes in these two weeks were upstreamed from Chrome OS and cover work on the Intel Skylake chipset and two mainboards based on it. QEmu and Getac P470 saw a couple of improvements. On AMD, there were some bugfixes to Fam10h concerning VGA memory and SMM initialization. The latter was in response to the Memory Sinkhole vulnerability, although it is as yet unclear if it even affects AMD. Finally, an important memory structure used on pre-AGESA AMD code is now also usable outside Cache-as-RAM. There was more progress on fixing 64bit issues across the codebase. Our reference compiler was updated to gcc 5.2. This became necessary to support an update to the RISC-V specification. Our other tools also saw a couple of improvements: ifdtool now works for descriptors on Skylake and newer platforms. cbfstool saw some refactorings that allow us to extend the format. cbmem now emits the accumulated boot time. In our configuration system, the Kconfig definitions were cleaned up, so that boards dont define symbols that their code never uses, that Chrome OS capable boards define MAINBOARD_HAS_CHROMEOS (which defines the capability) instead of CHROMEOS (which defines that this mode should be used) and that dependencies between Kconfig options become more consistent. There is a pending commit on gerrit to enforce clean dependencies by making errors out of kconfigs warnings, that the latter changes prepare for. On the build system side, it is now possible to build SeaBIOS as part of our build system even with an enabled ccache. The payload config and revision can also be stored in CBFS for better reproducibility. Finally, its possible to override the location from where the vboot source code for Chrome OS-style verified boot is taken from. In libpayload, the non-accelerated memmove implementation now also works with size == 0 (instead of trying to move 4GB), and there were a couple of bug fixes to the DWC2 (some ARM) and XHCI (USB3) controller drivers, including support for the newer XHCI 1.1 specification. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New on blogs.coreboot.org: coreboot changelog - Weeks of 2015-07-27 and 2015-08-03
A new post titled "coreboot changelog - Weeks of 2015-07-27 and 2015-08-03" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2015/08/12/coreboot-changelog-weeks-of-2015-07-27-and-2015-08-03/ This covers commits ef0158ec up to commit 1cbef1c Development is typically slower during the summer and 2015 is no exception, so the report switches to a biweekly installment for a while. The last two weeks have seen improvements in our development tools: coreboot upstream can now build Chrome OS boards with Chrome OS features (verified boot, interaction with Chrome EC, flash based error logging) enabled, and the projects builders at http://qa.coreboot.org/ are now routinely building these configurations alongside the regular default configs for all boards. The builders now run ‘make what-jenkins does’ (see coreboot/Makefile.inc) instead of a hard-coded set of commands, which provides the community the capability to adapt the test build without admin intervention. When adding the .config used for building an image into said image, it’s now minimized which gives visibility to the relevant changes to the config compared to the board’s defaults. Kconfig features a strict mode, which acts as a ‘warnings-as-errors’ equivalent and fails the build if kconfig would emit any warning. Since we still have a couple of those in the tree, it’s not enabled yet. For users of cscope or ctags, we now have new make targets to create tree-wide indexes (make ctags-project cscope-project). Reproducible builds got a boost by fixes to the build.h generator script, which can finally emit stable timestamps based on the git revision, instead of the local time. External payload integration was coalesced within payloads/external, with more work in progress. The integrated SeaBIOS build can now also be used when building with ccache. libpayload gained robustness in different developer environments, being smarter about looking for compilers, configs and include files in all the right places. On the Free Software side, more microcode blobs were moved to the 3rdparty/blobs repository and one false positive that libreboot’s blob detector tripped over was eliminated, and with a little more progress, it should soon be possible to build from a fully blob-free coreboot tree. Before you get your hopes up, please note that the result may not be very useful on a lot of boards, so more care must be taken. The effort to make coreboot capable of booting in 64bit mode on x86-64 is still ongoing and saw the integration of more commits. coreboot should have an easier time again when building on Cygwin and BSD systems. Skylake was the chipset with the largest amount of work in the 2 weeks, but there was also the addition of a coreboot port for RISC-V’s Spike ISA Simulator, contributions to the AMD Bettong mainboard and its chipset drivers, as well as fixes and cleanups to AMD K8 and Intel i945. In terms of style, a bunch of extraneous whitespaces, indenting errors and FSF addresses were also dealt with. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New on blogs.coreboot.org: coreboot changelog - Week of 2015-07-20
A new post titled "coreboot changelog - Week of 2015-07-20" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2015/07/29/coreboot-changelog-week-of-2015-07-20/ This covers commits 406effd5 up to commit ef0158ec Apart from adding the google/glados board, this week’s activity concentrated on bug fixes in chipsets and mainboards, spanning AMD K8 and Hudson, Intel Sandy Bridge, Braswell and Skylake, Nvidia Tegra, Rockchip RK3288 and RISC-V. Most of the changes are too small individually and too spread out across the code base for a shout-out (or this report becomes just a fancy kind of “git log”), but two changes stand out: Native RAM init on Sandybridge gained support for multiple DIMMs on the same channel, further improving the reverse engineered code base for that chipset. To improve Skylake support, our 8250mem serial port driver now also supports Skylakes 32bit UART access mode. This may also be useful when reducing code duplication in our serial console drivers (such as on ARM SoCs). -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New on blogs.coreboot.org: coreboot changelog - Week of 2015-07-13
A new post titled "coreboot changelog - Week of 2015-07-13" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2015/07/22/coreboot-changelog-week-of-2015-07-13/ This covers commits 6cb3a59 (which is the 4.1 tag) up to commit 406effd5 This week brought the addition of one new chipset and four new mainboards: Welcome the Intel Skylake SoC, and the new mainboards google/cyan, intel/kunimitsu, intel/sklrvp, and intel/strago, which are Braswell or Skylake based. As for tools, the script that generated the 4.1 release was added to the tree. To aid with debugging build issues, buildgcc shows the URLs it uses to download the sources to the toolchain. The standard git hook now uses a customized version of Linux’s checkpatch.pl utility for better coding style compliance tests. The cbmem utility gained OpenBSD compatibility when reading timestamps. The USB host drivers in libpayload saw improvements both for USB3, supporting SuperSpeed hubs and showing more robustness in the presence of strangely behaving USB devices, and for DWC2 controllers, which now support LowSpeed devices behind HighSpeed hubs. coreboot also passes more information to libpayload on where to find the flash part as well as the parameters of the CBFS that was used during boot. The CBFS format is seeing new development: The default alignment for files is now hardcoded to 64 bytes, which was already the default. There are no known instances where this value was changed, and it simplifies development going forward. The change is forward compatible in that old users can still read new CBFS images. New users run into problems if they work on a CBFS image with a different alignment configuration. Furthermore there were discussions on how to extend the CBFS format compatibility. So far this led to numerous refactorings in cbfstool to simplify further development. Finally, there were a whole lot of bug fixes: ARM64, the code for Nvidia’s Tegra210 chipset and the google/foster and google/smaug boards saw lots of development, from making them boot again to various hardware enablement. AMD’s RS780 chipset was effectively disabled due to a typo in the build system. There’s an ongoing effort to bring AMD K8/Fam10h into shape again, which also positively affected HD Audio configuration. CBMEM timestamps are more complete than ever. There was also the usual bunch of cleanups that get rid of unused Kconfig symbols and configuration options, deal with wrong indentation, and replace magic numbers with meaningful names. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
