Re: [coreboot] Ram Init: Intel i945: Timing parameters
Mohit Gupta wrote: Don't understand why Intel has made DRAM controller setup/Ram-init documentation NDA, Many people wonder about the same thing. It's not clear. and have made chipset documentation public The chipset docs aren't really published. Only some parts of them. ** Important Note This email (including any attachments) contains information which is confidential Why are you sending confidential information in plain text to a public mailing list which is archived all on the web? That seems silly. Please make sure not to include any such nonsense disclaimers in your emails at the very least when you participate in open source projects. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram Init: Intel i945: Timing parameters
Thanks Vald ... not possible to break intel safe :).. wondering how coreboot team was able to write i945 ram init? ** Important Note This email (including any attachments) contains information which is confidential and may be subject to legal privilege. If you are not the intended recipient you must not use, distribute or copy this email. If you have received this email in error please notify the sender immediately and delete this email. Any views expressed in this email are not necessarily the views of IRESS Limited. It is the duty of the recipient to virus scan and otherwise test the information provided before loading onto any computer system. IRESS Limited does not warrant that the information is free of a virus or any other defect or error. ** -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram Init: Intel i945: Timing parameters
Thanks Peter once again for helpful information. I was reading code line by line and going through i945 Express chipset document, tried to understand register settings and values. Seems to be tough job writing RAM init, and wouldn't have been possible without any documentation. Don't understand why Intel has made DRAM controller setup/Ram-init documentation NDA, and have made chipset documentation public ** Important Note This email (including any attachments) contains information which is confidential and may be subject to legal privilege. If you are not the intended recipient you must not use, distribute or copy this email. If you have received this email in error please notify the sender immediately and delete this email. Any views expressed in this email are not necessarily the views of IRESS Limited. It is the duty of the recipient to virus scan and otherwise test the information provided before loading onto any computer system. IRESS Limited does not warrant that the information is free of a virus or any other defect or error. ** -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Ram Init: Intel i945: Timing parameters
I am having trouble understanding i945 ram init code especially timing parameters. Can some explain me in layman language? When I go through DDR2 specification, timing related text is too complex and confusing. Interested in getting very simple explanation. Also, i945 ram init code is doing lot of settings in MCH. Is there any step by step documentation available? Regards Mohit Gupta-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram Init: Intel i945: Timing parameters
On 14.02.2014 00:03, Mohit Gupta wrote: I am having trouble understanding i945 ram init code especially timing parameters. Can some explain me in layman language? When I go through DDR2 specification, timing related text is too complex and confusing. Interested in getting very simple explanation. There isn't any. RAM init is difficult. Also, i945 ram init code is doing lot of settings in MCH. Is there any step by step documentation available? Sure: 1) Locate intel offices 2) Locate their top-secret safes 3) Observe security 4) Buy military gear 5) Recruit and train a company (~200 people) for a year 6) Launch assault on the office 7) Break into the safe 8) Get out of Intel building 9) Read the documentation Regards Mohit Gupta signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram Init: Intel i945: Timing parameters
On Friday, February 14, 2014 12:38:58 AM Vladimir 'φ-coder/phcoder' Serbinenko wrote: Sure: 1) Locate intel offices 2) Locate their top-secret safes 3) Observe security 4) Buy military gear 5) Recruit and train a company (~200 people) for a year 6) Launch assault on the office 7) Break into the safe 8) Get out of Intel building 9) Read the documentation Don't do that. As a member of the US Armed Forces, I will stop you. Instead, why not get enough cash, buy Intel, then you can make executive decisions. It's legal. Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram Init: Intel i945: Timing parameters
Thanks Vald … not possible to break intel safe .. wondering how coreboot team was able to write i945 ram init? Regards Mohit Gupta On Friday, 14 February 2014 10:39 AM, Vladimir 'φ-coder/phcoder' Serbinenko phco...@gmail.com wrote: On 14.02.2014 00:03, Mohit Gupta wrote: I am having trouble understanding i945 ram init code especially timing parameters. Can some explain me in layman language? When I go through DDR2 specification, timing related text is too complex and confusing. Interested in getting very simple explanation. There isn't any. RAM init is difficult. Also, i945 ram init code is doing lot of settings in MCH. Is there any step by step documentation available? Sure: 1) Locate intel offices 2) Locate their top-secret safes 3) Observe security 4) Buy military gear 5) Recruit and train a company (~200 people) for a year 6) Launch assault on the office 7) Break into the safe 8) Get out of Intel building 9) Read the documentation Regards Mohit Gupta -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram Init: Intel i945: Timing parameters
Thanks Vald … not possible to break intel safe .. wondering how coreboot team was able to write i945 ram init? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ram Init: Intel i945: Timing parameters
Mohit Gupta wrote: wondering how coreboot team was able to write i945 ram init? The code was written by individuals who had limited access to Intel documents and source code under NDA. Those individuals can not tutor you in the i945 MCH or in DDR2 technology. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
