[dpdk-dev] [PATCH] crypto/qat: fix compile of qat on freebsd
Using sys/types.h instead of linux/types.h
so as to compile QAT_PMD on freebsd.
Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")
Signed-off-by: Deepak Kumar Jain
---
drivers/crypto/qat/qat_adf/icp_qat_fw.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/qat/qat_adf/icp_qat_fw.h
b/drivers/crypto/qat/qat_adf/icp_qat_fw.h
index 498ee83..5de34d5 100644
--- a/drivers/crypto/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/crypto/qat/qat_adf/icp_qat_fw.h
@@ -46,7 +46,7 @@
*/
#ifndef _ICP_QAT_FW_H_
#define _ICP_QAT_FW_H_
-#include
+#include
#include "icp_qat_hw.h"
#define QAT_FIELD_SET(flags, val, bitpos, mask) \
--
2.5.5
[dpdk-dev] [PATCH v3] crypto/qat: add Intel(R) QuickAssist C3xxx device
From: Deepak Kumar JAIN Signed-off-by: Deepak Kumar Jain Acked-by: Fiona Trahe --- Changes in v3: Updated qat.rst by removing the limitation. Changes in v2: Added new feature information in release_16_11.rst file. doc/guides/cryptodevs/qat.rst | 76 ++ doc/guides/rel_notes/release_16_11.rst | 3 ++ drivers/crypto/qat/rte_qat_cryptodev.c | 3 ++ 3 files changed, 75 insertions(+), 7 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 50bfc95..61bbdef 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -31,8 +31,8 @@ Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver == The QAT PMD provides poll mode crypto driver support for **Intel QuickAssist -Technology DH895xxC** and **Intel QuickAssist Technology C62x** -hardware accelerator. +Technology DH895xxC** , **Intel QuickAssist Technology C62x** and +**Intel QuickAssist Technology C3xxx** hardware accelerator. Features @@ -77,7 +77,6 @@ Limitations * Snow3g(UIA2) supported only if hash length, hash offset fields are byte-aligned. * No BSD support as BSD QAT kernel driver not available. - Installation @@ -99,14 +98,16 @@ If you are running on kernel 4.4 or greater, see instructions for `Installation using kernel.org driver`_ below. If you are on a kernel earlier than 4.4, see `Installation using 01.org QAT driver`_. -For **Intel QuickAssist Technology C62x** device, kernel 4.5 or greater is -needed. See instructions for `Installation using kernel.org driver`_ below. +For **Intel QuickAssist Technology C62x** and **Intel QuickAssist Technology C3xxx** +device, kernel 4.5 or greater is needed. +See instructions for `Installation using kernel.org driver`_ below. Installation using 01.org QAT driver -NOTE: There is no driver available for **Intel QuickAssist Technology C62x** on 01.org. +NOTE: There is no driver available for **Intel QuickAssist Technology C62x** and +**Intel QuickAssist Technology C3xxx** devices on 01.org. Download the latest QuickAssist Technology Driver from `01.org <https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_ @@ -185,6 +186,7 @@ Installation using kernel.org driver For **Intel QuickAssist Technology DH895xxC**: + Assuming you are running on at least a 4.4 kernel, you can use the stock kernel.org QAT driver to start the QAT hardware. @@ -243,7 +245,6 @@ cd to your linux source root directory and start the qat kernel modules: **Note**:The following warning in /var/log/messages can be ignored: ``IOMMU should be enabled for SR-IOV to work correctly`` - For **Intel QuickAssist Technology C62x**: Assuming you are running on at least a 4.5 kernel, you can use the stock kernel.org QAT driver to start the QAT hardware. @@ -288,6 +289,47 @@ the bdf of the 48 VF devices are available per ``C62x`` device. To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_. +For **Intel QuickAssist Technology C3xxx**: +Assuming you are running on at least a 4.5 kernel, you can use the stock kernel.org QAT +driver to start the QAT hardware. + +The steps below assume you are: + +* Running DPDK on a platform with one ``C3xxx`` device. +* On a kernel at least version 4.5. + +In BIOS ensure that SRIOV is enabled and VT-d is disabled. + +Ensure the QAT driver is loaded on your system, by executing:: + +lsmod | grep qat + +You should see the following output:: + +qat_c3xxx 16384 0 +intel_qat 122880 1 qat_c3xxx + +Next, you need to expose the Virtual Functions (VFs) using the sysfs file system. + +First find the bdf of the physical function (PF) of the C3xxx device + +lspci -d:19e2 + +You should see output similar to:: + +01:00.0 Co-processor: Intel Corporation Device 19e2 + +For c3xxx device there is 1 PFs. +Using the sysfs, enable the 16 VFs:: + +echo 16 > /sys/bus/pci/drivers/c3xxx/\:01\:00.0/sriov_numvfs + +If you get an error, it's likely you're using a QAT kernel driver earlier than kernel 4.5. + +To verify that the VFs are available for use - use ``lspci -d:19e3`` to confirm +the bdf of the 16 VF devices are available per ``C3xxx`` device. +To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_. + Binding the available VFs to the DPDK UIO driver @@ -333,3 +375,23 @@ if yours are different adjust the unbind command below:: echo "8086 37c9" > /sys/bus/pci/drivers/igb_uio/new_id You can use ``lspci -vvd:37c9`` to confirm that all devices are now in use by igb_uio kernel driver. + +For **Intel(R) QuickAssist Technology C3xxx** device: +The unbind command below assumes ``bdfs
[dpdk-dev] [PATCH v2] doc/guides: fix name of algorithm
From: Deepak Kumar JAIN
Update documentation with correct names of algorithm supported.
Fixes: 1703e94ac5cee ("qat: add driver for QuickAssist devices")
Signed-off-by: Deepak Kumar Jain
Acked-by: Fiona Trahe
---
Changes in v2:
* Extended fixes in AESNI, KASUMI and SNOW3G PMD.
doc/guides/cryptodevs/aesni_mb.rst | 18 +-
doc/guides/cryptodevs/kasumi.rst | 4 ++--
doc/guides/cryptodevs/qat.rst | 14 +++---
doc/guides/cryptodevs/snow3g.rst | 4 ++--
4 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/doc/guides/cryptodevs/aesni_mb.rst
b/doc/guides/cryptodevs/aesni_mb.rst
index 60a8914..655515a 100644
--- a/doc/guides/cryptodevs/aesni_mb.rst
+++ b/doc/guides/cryptodevs/aesni_mb.rst
@@ -45,18 +45,18 @@ AESNI MB PMD has support for:
Cipher algorithms:
-* RTE_CRYPTO_SYM_CIPHER_AES128_CBC
-* RTE_CRYPTO_SYM_CIPHER_AES192_CBC
-* RTE_CRYPTO_SYM_CIPHER_AES256_CBC
-* RTE_CRYPTO_SYM_CIPHER_AES128_CTR
-* RTE_CRYPTO_SYM_CIPHER_AES192_CTR
-* RTE_CRYPTO_SYM_CIPHER_AES256_CTR
+* RTE_CRYPTO_CIPHER_AES128_CBC
+* RTE_CRYPTO_CIPHER_AES192_CBC
+* RTE_CRYPTO_CIPHER_AES256_CBC
+* RTE_CRYPTO_CIPHER_AES128_CTR
+* RTE_CRYPTO_CIPHER_AES192_CTR
+* RTE_CRYPTO_CIPHER_AES256_CTR
Hash algorithms:
-* RTE_CRYPTO_SYM_HASH_SHA1_HMAC
-* RTE_CRYPTO_SYM_HASH_SHA256_HMAC
-* RTE_CRYPTO_SYM_HASH_SHA512_HMAC
+* RTE_CRYPTO_HASH_SHA1_HMAC
+* RTE_CRYPTO_HASH_SHA256_HMAC
+* RTE_CRYPTO_HASH_SHA512_HMAC
Limitations
---
diff --git a/doc/guides/cryptodevs/kasumi.rst b/doc/guides/cryptodevs/kasumi.rst
index 7346b21..8b5f172 100644
--- a/doc/guides/cryptodevs/kasumi.rst
+++ b/doc/guides/cryptodevs/kasumi.rst
@@ -41,11 +41,11 @@ KASUMI PMD has support for:
Cipher algorithm:
-* RTE_CRYPTO_SYM_CIPHER_KASUMI_F8
+* RTE_CRYPTO_CIPHER_KASUMI_F8
Authentication algorithm:
-* RTE_CRYPTO_SYM_AUTH_KASUMI_F9
+* RTE_CRYPTO_AUTH_KASUMI_F9
Limitations
---
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 326b228..c86058a 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -41,13 +41,13 @@ The QAT PMD has support for:
Cipher algorithms:
-* ``RTE_CRYPTO_SYM_CIPHER_AES128_CBC``
-* ``RTE_CRYPTO_SYM_CIPHER_AES192_CBC``
-* ``RTE_CRYPTO_SYM_CIPHER_AES256_CBC``
-* ``RTE_CRYPTO_SYM_CIPHER_AES128_CTR``
-* ``RTE_CRYPTO_SYM_CIPHER_AES192_CTR``
-* ``RTE_CRYPTO_SYM_CIPHER_AES256_CTR``
-* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2``
+* ``RTE_CRYPTO_CIPHER_AES128_CBC``
+* ``RTE_CRYPTO_CIPHER_AES192_CBC``
+* ``RTE_CRYPTO_CIPHER_AES256_CBC``
+* ``RTE_CRYPTO_CIPHER_AES128_CTR``
+* ``RTE_CRYPTO_CIPHER_AES192_CTR``
+* ``RTE_CRYPTO_CIPHER_AES256_CTR``
+* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
* ``RTE_CRYPTO_CIPHER_AES_GCM``
* ``RTE_CRYPTO_CIPHER_NULL``
diff --git a/doc/guides/cryptodevs/snow3g.rst b/doc/guides/cryptodevs/snow3g.rst
index 670a62a..11d181b 100644
--- a/doc/guides/cryptodevs/snow3g.rst
+++ b/doc/guides/cryptodevs/snow3g.rst
@@ -41,11 +41,11 @@ SNOW 3G PMD has support for:
Cipher algorithm:
-* RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2
+* RTE_CRYPTO_CIPHER_SNOW3G_UEA2
Authentication algorithm:
-* RTE_CRYPTO_SYM_AUTH_SNOW3G_UIA2
+* RTE_CRYPTO_AUTH_SNOW3G_UIA2
Limitations
---
--
2.5.5
[dpdk-dev] [PATCH v4 4/4] app/test: add Kasumi tests in QAT test suite
This patch adds KASUMI tests in the QAT testsuite.
Alg-Chaining tests have also been added in the KASUMI
SW PMD.
Signed-off-by: Deepak Kumar Jain
Acked-by: Fiona Trahe
---
app/test/test_cryptodev.c | 210 -
app/test/test_cryptodev_kasumi_hash_test_vectors.h | 77
app/test/test_cryptodev_kasumi_test_vectors.h | 105 ++-
3 files changed, 385 insertions(+), 7 deletions(-)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 61a474c..6c6e141 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -1571,7 +1571,6 @@ create_snow3g_kasumi_auth_cipher_operation(const unsigned
auth_tag_len,
aad_buffer_len = ALIGN_POW2_ROUNDUP(aad_len, 8);
else
aad_buffer_len = ALIGN_POW2_ROUNDUP(aad_len, 16);
-
sym_op->auth.aad.data = (uint8_t *)rte_pktmbuf_prepend(
ut_params->ibuf, aad_buffer_len);
TEST_ASSERT_NOT_NULL(sym_op->auth.aad.data,
@@ -1579,10 +1578,8 @@ create_snow3g_kasumi_auth_cipher_operation(const
unsigned auth_tag_len,
sym_op->auth.aad.phys_addr = rte_pktmbuf_mtophys(
ut_params->ibuf);
sym_op->auth.aad.length = aad_len;
-
memset(sym_op->auth.aad.data, 0, aad_buffer_len);
rte_memcpy(sym_op->auth.aad.data, aad, aad_len);
-
TEST_HEXDUMP(stdout, "aad:",
sym_op->auth.aad.data, aad_len);
@@ -1959,6 +1956,12 @@ test_kasumi_hash_generate_test_case_5(void)
}
static int
+test_kasumi_hash_generate_test_case_6(void)
+{
+ return test_kasumi_authentication(&kasumi_hash_test_case_6);
+}
+
+static int
test_kasumi_hash_verify_test_case_1(void)
{
return test_kasumi_authentication_verify(&kasumi_hash_test_case_1);
@@ -2816,6 +2819,174 @@ test_snow3g_auth_cipher(const struct snow3g_test_data
*tdata)
}
static int
+test_kasumi_auth_cipher(const struct kasumi_test_data *tdata)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ struct crypto_unittest_params *ut_params = &unittest_params;
+
+ int retval;
+
+ uint8_t *plaintext, *ciphertext;
+ unsigned plaintext_pad_len;
+ unsigned plaintext_len;
+
+ /* Create KASUMI session */
+ retval = create_snow3g_kasumi_auth_cipher_session(
+ ts_params->valid_devs[0],
+ RTE_CRYPTO_CIPHER_OP_ENCRYPT,
+ RTE_CRYPTO_AUTH_OP_GENERATE,
+ RTE_CRYPTO_AUTH_KASUMI_F9,
+ RTE_CRYPTO_CIPHER_KASUMI_F8,
+ tdata->key.data, tdata->key.len,
+ tdata->aad.len, tdata->digest.len);
+ if (retval < 0)
+ return retval;
+ ut_params->ibuf = rte_pktmbuf_alloc(ts_params->mbuf_pool);
+
+ /* clear mbuf payload */
+ memset(rte_pktmbuf_mtod(ut_params->ibuf, uint8_t *), 0,
+ rte_pktmbuf_tailroom(ut_params->ibuf));
+
+ plaintext_len = ceil_byte_length(tdata->plaintext.len);
+ /* Append data which is padded to a multiple of */
+ /* the algorithms block size */
+ plaintext_pad_len = RTE_ALIGN_CEIL(plaintext_len, 16);
+ plaintext = (uint8_t *)rte_pktmbuf_append(ut_params->ibuf,
+ plaintext_pad_len);
+ memcpy(plaintext, tdata->plaintext.data, plaintext_len);
+
+ TEST_HEXDUMP(stdout, "plaintext:", plaintext, plaintext_len);
+
+ /* Create KASUMI operation */
+ retval = create_snow3g_kasumi_auth_cipher_operation(tdata->digest.len,
+ tdata->iv.data, tdata->iv.len,
+ tdata->aad.data, tdata->aad.len,
+ plaintext_pad_len,
+ tdata->validCipherLenInBits.len,
+ tdata->validCipherOffsetLenInBits.len,
+ tdata->validAuthLenInBits.len,
+ tdata->validAuthOffsetLenInBits.len,
+ RTE_CRYPTO_AUTH_KASUMI_F9,
+ RTE_CRYPTO_CIPHER_KASUMI_F8
+ );
+
+ if (retval < 0)
+ return retval;
+
+ ut_params->op = process_crypto_request(ts_params->valid_devs[0],
+ ut_params->op);
+ TEST_ASSERT_NOT_NULL(ut_params->op, "failed to retrieve obuf");
+ ut_params->obuf = ut_params->op->sym->m_src;
+ if (ut_params->obuf)
+ ciphertext = rte_pktmbuf_mtod(ut_params->obuf, uint8_t *)
+ + tdata->iv.len + tdata->aad.len;
+ else
+ ciphertext = plaintext;
+
+ /* Validate obuf */
+ TEST_ASSERT_BUFFERS_ARE_EQUAL_BIT(
+
[dpdk-dev] [PATCH v4 3/4] crypto/qat: add Kasumi support in Intel(R) QAT driver
This patch add kasumi support in Intel(R)
QuickAssist driver.
Signed-off-by: Deepak Kumar Jain
Acked-by: Fiona Trahe
---
doc/guides/cryptodevs/qat.rst| 10 +--
doc/guides/rel_notes/release_16_11.rst | 2 +-
drivers/crypto/qat/qat_adf/qat_algs.h| 10 ++-
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 72 +++--
drivers/crypto/qat/qat_crypto.c | 79 ++--
5 files changed, 158 insertions(+), 15 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 78cadc4..4b87c21 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -51,6 +51,7 @@ Cipher algorithms:
* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
* ``RTE_CRYPTO_CIPHER_AES_GCM``
* ``RTE_CRYPTO_CIPHER_NULL``
+* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
Hash algorithms:
@@ -63,17 +64,18 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
* ``RTE_CRYPTO_AUTH_MD5_HMAC``
* ``RTE_CRYPTO_AUTH_NULL``
+* ``RTE_CRYPTO_AUTH_KASUMI_F9``
Limitations
---
* Chained mbufs are not supported.
-* Hash only is not supported except Snow3G UIA2.
-* Cipher only is not supported except Snow3G UEA2.
+* Hash only is not supported except Snow3G UIA2 and KASUMI F9.
+* Cipher only is not supported except Snow3G UEA2 and KASUMI F8.
* Only supports the session-oriented API implementation (session-less APIs are
not supported).
* Not performance tuned.
-* Snow3g(UEA2) supported only if cipher length, cipher offset fields are
byte-aligned.
-* Snow3g(UIA2) supported only if hash length, hash offset fields are
byte-aligned.
+* Snow3g(UEA2) and KASUMI(F8) supported only if cipher length, cipher offset
fields are byte-aligned.
+* Snow3g(UIA2) and KASUMI(F9) supported only if hash length, hash offset
fields are byte-aligned.
* No BSD support as BSD QAT kernel driver not available.
* Snow3g (UIA2) not supported in the PMD of **Intel QuickAssist Technology
C3xxx** device.
diff --git a/doc/guides/rel_notes/release_16_11.rst
b/doc/guides/rel_notes/release_16_11.rst
index 4bc67e0..1dd0e6a 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -50,7 +50,7 @@ New Features
* Added support for SHA224-HMAC algorithm.
* Added support for SHA384-HMAC algorithm.
* Added support for NULL algorithm.
-
+ * Added support for KASUMI (F8 and F9) algorithm.
Resolved Issues
---
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index 6a86053..fad8471 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -51,6 +51,14 @@
#include "icp_qat_fw.h"
#include "icp_qat_fw_la.h"
+/*
+ * Key Modifier (KM) value used in Kasumi algorithm in F9 mode to XOR
+ * Integrity Key (IK)
+ */
+#define KASUMI_F9_KEY_MODIFIER_4_BYTES 0x
+
+#define KASUMI_F8_KEY_MODIFIER_4_BYTES 0x
+
#define QAT_AES_HW_CONFIG_CBC_ENC(alg) \
ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \
ICP_QAT_HW_CIPHER_NO_CONVERT, \
@@ -130,5 +138,5 @@ void qat_alg_ablkcipher_init_dec(struct
qat_alg_ablkcipher_cd *cd,
int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
-
+int qat_alg_validate_kasumi_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
#endif
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index d9437bc..131800c 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -96,6 +96,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo
qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_MD5:
return QAT_HW_ROUND_UP(ICP_QAT_HW_MD5_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
+ case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
+ return QAT_HW_ROUND_UP(ICP_QAT_HW_KASUMI_F9_STATE1_SZ,
+ QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum state1 size in this case */
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
@@ -454,7 +457,8 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
uint32_t total_key_size;
uint16_t proto = ICP_QAT_FW_LA_NO_PROTO;/* no CCM/GCM/Snow3G */
uint16_t cipher_offset, cd_size;
-
+ uint32_t wordIndex = 0;
+ uint32_t *temp_key = NULL;
PMD_INIT_FUNC_TRACE();
if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
@@ -504,6 +508,11 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
cipher_cd_ctrl->cipher_state_sz =
ICP
[dpdk-dev] [PATCH v4 2/4] app/test: rename functions name
Renamed authenticated encryption and encrypted authentication
with easily recognixation names.
Signed-off-by: Deepak Kumar Jain
Acked-by: Fiona Trahe
---
app/test/test_cryptodev.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 70606e6..61a474c 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -2647,7 +2647,7 @@ static int test_snow3g_decryption_oop(const struct
snow3g_test_data *tdata)
}
static int
-test_snow3g_authenticated_encryption(const struct snow3g_test_data *tdata)
+test_snow3g_cipher_auth(const struct snow3g_test_data *tdata)
{
struct crypto_testsuite_params *ts_params = &testsuite_params;
struct crypto_unittest_params *ut_params = &unittest_params;
@@ -2730,7 +2730,7 @@ test_snow3g_authenticated_encryption(const struct
snow3g_test_data *tdata)
return 0;
}
static int
-test_snow3g_encrypted_authentication(const struct snow3g_test_data *tdata)
+test_snow3g_auth_cipher(const struct snow3g_test_data *tdata)
{
struct crypto_testsuite_params *ts_params = &testsuite_params;
struct crypto_unittest_params *ut_params = &unittest_params;
@@ -2964,15 +2964,15 @@ test_snow3g_decryption_test_case_5(void)
return test_snow3g_decryption(&snow3g_test_case_5);
}
static int
-test_snow3g_authenticated_encryption_test_case_1(void)
+test_snow3g_cipher_auth_test_case_1(void)
{
- return test_snow3g_authenticated_encryption(&snow3g_test_case_3);
+ return test_snow3g_cipher_auth(&snow3g_test_case_3);
}
static int
-test_snow3g_encrypted_authentication_test_case_1(void)
+test_snow3g_auth_cipher_test_case_1(void)
{
- return test_snow3g_encrypted_authentication(&snow3g_test_case_6);
+ return test_snow3g_auth_cipher(&snow3g_test_case_6);
}
/* * AES-GCM Tests * */
@@ -4113,9 +4113,9 @@ static struct unit_test_suite cryptodev_qat_testsuite = {
TEST_CASE_ST(ut_setup, ut_teardown,
test_snow3g_hash_verify_test_case_3),
TEST_CASE_ST(ut_setup, ut_teardown,
- test_snow3g_authenticated_encryption_test_case_1),
+ test_snow3g_cipher_auth_test_case_1),
TEST_CASE_ST(ut_setup, ut_teardown,
- test_snow3g_encrypted_authentication_test_case_1),
+ test_snow3g_auth_cipher_test_case_1),
/** HMAC_MD5 Authentication */
TEST_CASE_ST(ut_setup, ut_teardown,
@@ -4314,9 +4314,9 @@ static struct unit_test_suite
cryptodev_sw_snow3g_testsuite = {
TEST_CASE_ST(ut_setup, ut_teardown,
test_snow3g_hash_verify_test_case_6),
TEST_CASE_ST(ut_setup, ut_teardown,
- test_snow3g_authenticated_encryption_test_case_1),
+ test_snow3g_cipher_auth_test_case_1),
TEST_CASE_ST(ut_setup, ut_teardown,
- test_snow3g_encrypted_authentication_test_case_1),
+ test_snow3g_auth_cipher_test_case_1),
TEST_CASES_END() /**< NULL terminate unit test array */
}
--
2.5.5
[dpdk-dev] [PATCH v4 1/4] app/test: crypto test code cleanup
Cleanup the code for code design consistency. Signed-off-by: Deepak Kumar Jain Acked-by: Fiona Trahe --- app/test/test_cryptodev.c | 111 +- 1 file changed, 51 insertions(+), 60 deletions(-) diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c index 67ca912..70606e6 100644 --- a/app/test/test_cryptodev.c +++ b/app/test/test_cryptodev.c @@ -1448,25 +1448,24 @@ create_snow3g_kasumi_cipher_hash_operation(const uint8_t *auth_tag, /* set crypto operation source mbuf */ sym_op->m_src = ut_params->ibuf; + /* digest */ + sym_op->auth.digest.data = (uint8_t *)rte_pktmbuf_append( + ut_params->ibuf, auth_tag_len); - /* iv */ - if (cipher_algo == RTE_CRYPTO_CIPHER_KASUMI_F8) - iv_pad_len = RTE_ALIGN_CEIL(iv_len, 8); + TEST_ASSERT_NOT_NULL(sym_op->auth.digest.data, + "no room to append auth tag"); + ut_params->digest = sym_op->auth.digest.data; + sym_op->auth.digest.phys_addr = rte_pktmbuf_mtophys_offset( + ut_params->ibuf, data_pad_len); + sym_op->auth.digest.length = auth_tag_len; + if (op == RTE_CRYPTO_AUTH_OP_GENERATE) + memset(sym_op->auth.digest.data, 0, auth_tag_len); else - iv_pad_len = RTE_ALIGN_CEIL(iv_len, 16); - - sym_op->cipher.iv.data = (uint8_t *)rte_pktmbuf_prepend( - ut_params->ibuf, iv_pad_len); - TEST_ASSERT_NOT_NULL(sym_op->cipher.iv.data, "no room to prepend iv"); - - memset(sym_op->cipher.iv.data, 0, iv_pad_len); - sym_op->cipher.iv.phys_addr = rte_pktmbuf_mtophys(ut_params->ibuf); - sym_op->cipher.iv.length = iv_pad_len; - - rte_memcpy(sym_op->cipher.iv.data, iv, iv_len); + rte_memcpy(sym_op->auth.digest.data, auth_tag, auth_tag_len); - sym_op->cipher.data.length = cipher_len; - sym_op->cipher.data.offset = cipher_offset; + TEST_HEXDUMP(stdout, "digest:", + sym_op->auth.digest.data, + sym_op->auth.digest.length); /* aad */ /* @@ -1480,42 +1479,35 @@ create_snow3g_kasumi_cipher_hash_operation(const uint8_t *auth_tag, aad_buffer_len = ALIGN_POW2_ROUNDUP(aad_len, 8); else aad_buffer_len = ALIGN_POW2_ROUNDUP(aad_len, 16); - sym_op->auth.aad.data = - (uint8_t *)rte_pktmbuf_mtod(ut_params->ibuf, uint8_t *); + (uint8_t *)rte_pktmbuf_prepend( + ut_params->ibuf, aad_buffer_len); TEST_ASSERT_NOT_NULL(sym_op->auth.aad.data, "no room to prepend aad"); sym_op->auth.aad.phys_addr = rte_pktmbuf_mtophys( ut_params->ibuf); sym_op->auth.aad.length = aad_len; - memset(sym_op->auth.aad.data, 0, aad_buffer_len); rte_memcpy(sym_op->auth.aad.data, aad, aad_len); + TEST_HEXDUMP(stdout, "aad:", sym_op->auth.aad.data, aad_len); - TEST_HEXDUMP(stdout, "aad:", - sym_op->auth.aad.data, aad_len); - - /* digest */ - sym_op->auth.digest.data = (uint8_t *)rte_pktmbuf_append( - ut_params->ibuf, auth_tag_len); - - TEST_ASSERT_NOT_NULL(sym_op->auth.digest.data, - "no room to append auth tag"); - ut_params->digest = sym_op->auth.digest.data; - sym_op->auth.digest.phys_addr = rte_pktmbuf_mtophys_offset( - ut_params->ibuf, data_pad_len + aad_len); - sym_op->auth.digest.length = auth_tag_len; - if (op == RTE_CRYPTO_AUTH_OP_GENERATE) - memset(sym_op->auth.digest.data, 0, auth_tag_len); + /* iv */ + if (cipher_algo == RTE_CRYPTO_CIPHER_KASUMI_F8) + iv_pad_len = RTE_ALIGN_CEIL(iv_len, 8); else - rte_memcpy(sym_op->auth.digest.data, auth_tag, auth_tag_len); - - TEST_HEXDUMP(stdout, "digest:", - sym_op->auth.digest.data, - sym_op->auth.digest.length); + iv_pad_len = RTE_ALIGN_CEIL(iv_len, 16); + sym_op->cipher.iv.data = (uint8_t *)rte_pktmbuf_prepend( + ut_params->ibuf, iv_pad_len); - sym_op->auth.data.length = auth_len; - sym_op->auth.data.offset = auth_offset; + TEST_ASSERT_NOT_NULL(sym_op->cipher.iv.data, "no room to prepend iv"); + memset(sym_op->cipher.iv.data, 0, iv_pad_len); + sym_op->cipher.iv.phys_addr = rte_pktmbuf_mtophys(ut_params->ibuf); + sym_op->cipher.iv.length = iv_pad_len; + rte_memcpy(sym_op->cipher.iv.data, iv, iv_len); + sym_
[dpdk-dev] [PATCH v4 0/4] add kasumi in Intel(R) QuickAssist driver
This patchset depends on following patch: "crypto/qat: add Intel(R) QuickAssist C3xxx device" (http://dpdk.org/dev/patchwork/patch/15794/ Changes in v4: * Split cleanup patch into two smaller patches. * Fixed indentation issues. Changes in v3: * Merged Cipher only and hash only patches into one patch. * Code cleaup for clear understanding. Changes in v2: * Updated Test code to apply cleanly on driver code * Added relevant documentation Deepak Kumar Jain (4): app/test: crypto test code cleanup app/test: rename functions name crypto/qat: add Kasumi support in Intel(R) QAT driver app/test: add Kasumi tests in QAT test suite app/test/test_cryptodev.c | 341 - app/test/test_cryptodev_kasumi_hash_test_vectors.h | 77 + app/test/test_cryptodev_kasumi_test_vectors.h | 105 ++- doc/guides/cryptodevs/qat.rst | 10 +- doc/guides/rel_notes/release_16_11.rst | 2 +- drivers/crypto/qat/qat_adf/qat_algs.h | 10 +- drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 72 - drivers/crypto/qat/qat_crypto.c| 79 - 8 files changed, 604 insertions(+), 92 deletions(-) -- 2.5.5
[dpdk-dev] [PATCH] crypto/null: fix key size increment value
This patch fixes the values of increment in key size.
Fixes: 94b0ad8e0a ("null_crypto_pmd: PMD to support null crypto
operations")
Signed-off-by: Deepak Kumar Jain
---
drivers/crypto/null/null_crypto_pmd_ops.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/null/null_crypto_pmd_ops.c
b/drivers/crypto/null/null_crypto_pmd_ops.c
index cf1a519..26ff631 100644
--- a/drivers/crypto/null/null_crypto_pmd_ops.c
+++ b/drivers/crypto/null/null_crypto_pmd_ops.c
@@ -70,7 +70,7 @@ static const struct rte_cryptodev_capabilities
null_crypto_pmd_capabilities[] =
.key_size = {
.min = 0,
.max = 0,
- .increment = 8
+ .increment = 0
},
.iv_size = {
.min = 0,
--
2.5.5
[dpdk-dev] [PATCH v4 2/2] app/test: add test cases for NULL for Intel QAT driver
From: Deepak Kumar JAIN
Added NULL algorithm to test file for Intel(R) QuickAssist
Technology Driver
Signed-off-by: Deepak Kumar Jain
Acked-by: Fiona Trahe
---
app/test/test_cryptodev.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 8553759..67ca912 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -4136,6 +4136,16 @@ static struct unit_test_suite cryptodev_qat_testsuite =
{
TEST_CASE_ST(ut_setup, ut_teardown,
test_MD5_HMAC_verify_case_2),
+ /** NULL tests */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_auth_only_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_cipher_only_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_cipher_auth_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_auth_cipher_operation),
+
TEST_CASES_END() /**< NULL terminate unit test array */
}
};
--
2.5.5
[dpdk-dev] [PATCH v4 1/2] crypto/qat: add NULL capability to Intel QAT driver
From: Deepak Kumar JAIN
enabled NULL crypto for Intel(R) QuickAssist Technology
Signed-off-by: Deepak Kumar Jain
Acked-by: Fiona Trahe
---
doc/guides/cryptodevs/qat.rst| 3 +-
doc/guides/rel_notes/release_16_11.rst | 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++
drivers/crypto/qat/qat_crypto.c | 45
4 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 78a734f..bb62f22 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -49,6 +49,7 @@ Cipher algorithms:
* ``RTE_CRYPTO_SYM_CIPHER_AES256_CTR``
* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2``
* ``RTE_CRYPTO_CIPHER_AES_GCM``
+* ``RTE_CRYPTO_CIPHER_NULL``
Hash algorithms:
@@ -60,7 +61,7 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
* ``RTE_CRYPTO_AUTH_MD5_HMAC``
-
+* ``RTE_CRYPTO_AUTH_NULL``
Limitations
---
diff --git a/doc/guides/rel_notes/release_16_11.rst
b/doc/guides/rel_notes/release_16_11.rst
index 9b2f102..9b2c775 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -42,6 +42,7 @@ New Features
* Added support for MD5_HMAC algorithm.
* Added support for SHA224-HMAC algorithm.
* Added support for SHA384-HMAC algorithm.
+ * Added support for NULL algorithm.
Resolved Issues
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index af8c176..d9437bc 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -720,6 +720,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
}
state2_size = ICP_QAT_HW_MD5_STATE2_SZ;
break;
+ case ICP_QAT_HW_AUTH_ALGO_NULL:
+ break;
default:
PMD_DRV_LOG(ERR, "Invalid HASH alg %u", cdesc->qat_hash_alg);
return -EFAULT;
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 60e2ba2..67af596 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -346,6 +346,47 @@ static const struct rte_cryptodev_capabilities
qat_pmd_capabilities[] = {
}, }
}, }
},
+ { /* NULL (AUTH) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_NULL,
+ .block_size = 1,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .aad_size = { 0 }
+ }, },
+ }, },
+ },
+ { /* NULL (CIPHER) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_NULL,
+ .block_size = 1,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ }
+ }, },
+ }, }
+ },
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
@@ -469,6 +510,8 @@ qat_crypto_sym_configure_session_cipher(struct
rte_cryptodev *dev,
session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
break;
case RTE_CRYPTO_CIPHER_NULL:
+ session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
+ break;
case RTE_CRYPTO_CIPHER_3DES_ECB:
case RTE_CRYPTO_CIPHER_3DES_CBC:
case RTE_CRYPTO_CIPHER_AES_ECB:
@@ -600,6 +643,8 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev
*dev,
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
break;
case RTE_CRYPTO_AUTH_NULL:
+ session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NU
[dpdk-dev] [PATCH v4 0/2] add NULL crypto support in Intel QAT driver
This patchset adds support of NULL crypto in Intel(R) QuickAssist Technology driver. This patchset depends on following patchset: "crypto/qat: add aes-sha384-hmac capability to Intel QAT driver" (http://dpdk.org/dev/patchwork/patch/15778/) Deepak Kumar JAIN (2): crypto/qat: add NULL capability to Intel QAT driver app/test: add test cases for NULL for Intel QAT driver Changes in v4: * Correct increment of key size in capabilities. Changes in v3: * Added information in capability structure. Changes in v2: * Added new feature information in release_16_11.rst file. app/test/test_cryptodev.c| 10 ++ doc/guides/cryptodevs/qat.rst| 3 +- doc/guides/rel_notes/release_16_11.rst | 1 + drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++ drivers/crypto/qat/qat_crypto.c | 45 5 files changed, 60 insertions(+), 1 deletion(-) -- 2.5.5
[dpdk-dev] [PATCH v3 2/2] app/test: add test cases for aes-sha224-hmac for Intel QAT driver
From: "Jain, Deepak K"
Added aes-sha224-hmac algorithm to test file for Intel(R) QuickAssist
Technology Driver
Signed-off-by: Deepak Kumar Jain
Acked-by: Fiona Trahe
---
app/test/test_cryptodev_aes.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/app/test/test_cryptodev_aes.c b/app/test/test_cryptodev_aes.c
index bf832b6..6ad2674 100644
--- a/app/test/test_cryptodev_aes.c
+++ b/app/test/test_cryptodev_aes.c
@@ -211,14 +211,16 @@ static const struct aes_test_case aes_test_cases[] = {
.test_descr = "AES-128-CBC HMAC-SHA224 Encryption Digest",
.test_data = &aes_test_data_8,
.op_mask = AES_TEST_OP_ENC_AUTH_GEN,
- .pmd_mask = AES_TEST_TARGET_PMD_MB
+ .pmd_mask = AES_TEST_TARGET_PMD_MB |
+ AES_TEST_TARGET_PMD_QAT
},
{
.test_descr = "AES-128-CBC HMAC-SHA224 Decryption Digest "
"Verify",
.test_data = &aes_test_data_8,
.op_mask = AES_TEST_OP_AUTH_VERIFY_DEC,
- .pmd_mask = AES_TEST_TARGET_PMD_MB
+ .pmd_mask = AES_TEST_TARGET_PMD_MB |
+ AES_TEST_TARGET_PMD_QAT
},
{
.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
--
2.5.5
[dpdk-dev] [PATCH v3 1/2] crypto/qat: add aes-sha224-hmac capability to Intel QAT driver
From: "Jain, Deepak K"
Added support of aes-sha224-hmac in Intel(R) QuickAssist driver
Signed-off-by: Deepak Kumar Jain
Acked-by: Fiona Trahe
---
doc/guides/cryptodevs/qat.rst| 1 +
doc/guides/rel_notes/release_16_11.rst | 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33
drivers/crypto/qat/qat_crypto.c | 25 +-
4 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 485abb4..7f630be 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -53,6 +53,7 @@ Cipher algorithms:
Hash algorithms:
* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
diff --git a/doc/guides/rel_notes/release_16_11.rst
b/doc/guides/rel_notes/release_16_11.rst
index 4f7d784..040e250 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -40,6 +40,7 @@ New Features
The QAT PMD was updated with changes including the following:
* Added support for MD5_HMAC algorithm.
+ * Added support for SHA224-HMAC algorithm.
Resolved Issues
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 521a9c4..77e6548 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -71,6 +71,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo
qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_SHA1:
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA1_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA224_STATE1_SZ,
+ QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA256_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
@@ -107,6 +110,8 @@ static int qat_hash_get_digest_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
switch (qat_hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SHA1:
return ICP_QAT_HW_SHA1_STATE1_SZ;
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ return ICP_QAT_HW_SHA224_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return ICP_QAT_HW_SHA256_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
@@ -129,6 +134,8 @@ static int qat_hash_get_block_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
switch (qat_hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SHA1:
return SHA_CBLOCK;
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ return SHA256_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return SHA256_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
@@ -158,6 +165,17 @@ static int partial_hash_sha1(uint8_t *data_in, uint8_t
*data_out)
return 0;
}
+static int partial_hash_sha224(uint8_t *data_in, uint8_t *data_out)
+{
+ SHA256_CTX ctx;
+
+ if (!SHA224_Init(&ctx))
+ return -EFAULT;
+ SHA256_Transform(&ctx, data_in);
+ rte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);
+ return 0;
+}
+
static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)
{
SHA256_CTX ctx;
@@ -220,6 +238,13 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo
hash_alg,
*hash_state_out_be32 =
rte_bswap32(*(((uint32_t *)digest)+i));
break;
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ if (partial_hash_sha224(data_in, digest))
+ return -EFAULT;
+ for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
+ *hash_state_out_be32 =
+ rte_bswap32(*(((uint32_t *)digest)+i));
+ break;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
if (partial_hash_sha256(data_in, digest))
return -EFAULT;
@@ -575,6 +600,14 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
}
state2_size = RTE_ALIGN_CEIL(ICP_QAT_HW_SHA1_STATE2_SZ, 8);
break;
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224,
+ authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ PMD_DRV_LOG(ERR, "(SHA)precompute failed");
+ return -EFAULT;
+ }
+ state2_size = ICP_QAT_HW_SHA224_STATE2_SZ;
+ break;
case ICP_QAT_HW_AUTH_ALGO_SH
[dpdk-dev] [PATCH v3 0/2] add aes-sha224-hmac support to Intel QAT driver
This patchset adds support of aes-sha224-hmac in Intel(R) QuickAssist Technology driver. This patchset depends on following patchset: "crypto/qat: add MD5 HMAC capability to Intel QAT driver" (http://dpdk.org/dev/patchwork/patch/15754/) Jain, Deepak K (2): crypto/qat: add aes-sha224-hmac capability to Intel QAT driver app/test: add test cases for aes-sha224-hmac for Intel QAT driver Changes in v3: * Cover letter updated with correct information about sha224-hmac. Changes in v2: * Added new feature information in release_16_11.rst file. * Added information about sha224-hmac in capabilities. app/test/test_cryptodev_aes.c| 6 +++-- doc/guides/cryptodevs/qat.rst| 1 + doc/guides/rel_notes/release_16_11.rst | 1 + drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 drivers/crypto/qat/qat_crypto.c | 25 +- 5 files changed, 63 insertions(+), 3 deletions(-) -- 2.5.5
[dpdk-dev] [PATCH v3 3/3] app/test: add Kasumi tests in QAT test suite
This patch adds Kausmi tests in the QAT tesuite.
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev.c | 244 +++--
app/test/test_cryptodev_kasumi_hash_test_vectors.h | 76 +++
app/test/test_cryptodev_kasumi_test_vectors.h | 103 -
3 files changed, 401 insertions(+), 22 deletions(-)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 89d627f..4751467 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -1560,22 +1560,6 @@ create_snow3g_kasumi_auth_cipher_operation(const
unsigned auth_tag_len,
sym_op->auth.digest.data,
sym_op->auth.digest.length);
- /* iv */
- if (cipher_algo == RTE_CRYPTO_CIPHER_KASUMI_F8)
- iv_pad_len = RTE_ALIGN_CEIL(iv_len, 8);
- else
- iv_pad_len = RTE_ALIGN_CEIL(iv_len, 16);
-
- sym_op->cipher.iv.data = (uint8_t *)rte_pktmbuf_prepend(
- ut_params->ibuf, iv_pad_len);
- TEST_ASSERT_NOT_NULL(sym_op->cipher.iv.data, "no room to prepend iv");
-
- memset(sym_op->cipher.iv.data, 0, iv_pad_len);
- sym_op->cipher.iv.phys_addr = rte_pktmbuf_mtophys(ut_params->ibuf);
- sym_op->cipher.iv.length = iv_pad_len;
-
- rte_memcpy(sym_op->cipher.iv.data, iv, iv_len);
-
/* aad */
/*
* Always allocate the aad up to the block size.
@@ -1588,7 +1572,6 @@ create_snow3g_kasumi_auth_cipher_operation(const unsigned
auth_tag_len,
aad_buffer_len = ALIGN_POW2_ROUNDUP(aad_len, 8);
else
aad_buffer_len = ALIGN_POW2_ROUNDUP(aad_len, 16);
-
sym_op->auth.aad.data = (uint8_t *)rte_pktmbuf_prepend(
ut_params->ibuf, aad_buffer_len);
TEST_ASSERT_NOT_NULL(sym_op->auth.aad.data,
@@ -1596,13 +1579,27 @@ create_snow3g_kasumi_auth_cipher_operation(const
unsigned auth_tag_len,
sym_op->auth.aad.phys_addr = rte_pktmbuf_mtophys(
ut_params->ibuf);
sym_op->auth.aad.length = aad_len;
-
memset(sym_op->auth.aad.data, 0, aad_buffer_len);
rte_memcpy(sym_op->auth.aad.data, aad, aad_len);
-
TEST_HEXDUMP(stdout, "aad:",
sym_op->auth.aad.data, aad_len);
+ /* iv */
+ if (cipher_algo == RTE_CRYPTO_CIPHER_KASUMI_F8)
+ iv_pad_len = RTE_ALIGN_CEIL(iv_len, 8);
+ else
+ iv_pad_len = RTE_ALIGN_CEIL(iv_len, 16);
+
+ sym_op->cipher.iv.data = (uint8_t *)rte_pktmbuf_prepend(
+ ut_params->ibuf, iv_pad_len);
+ TEST_ASSERT_NOT_NULL(sym_op->cipher.iv.data, "no room to prepend iv");
+
+ memset(sym_op->cipher.iv.data, 0, iv_pad_len);
+ sym_op->cipher.iv.phys_addr = rte_pktmbuf_mtophys(ut_params->ibuf);
+ sym_op->cipher.iv.length = iv_pad_len;
+
+ rte_memcpy(sym_op->cipher.iv.data, iv, iv_len);
+
sym_op->cipher.data.length = cipher_len;
sym_op->cipher.data.offset = auth_offset + cipher_offset;
@@ -1960,6 +1957,12 @@ test_kasumi_hash_generate_test_case_5(void)
}
static int
+test_kasumi_hash_generate_test_case_6(void)
+{
+ return test_kasumi_authentication(&kasumi_hash_test_case_6);
+}
+
+static int
test_kasumi_hash_verify_test_case_1(void)
{
return test_kasumi_authentication_verify(&kasumi_hash_test_case_1);
@@ -2818,6 +2821,174 @@ test_snow3g_auth_cipher(const struct snow3g_test_data
*tdata)
}
static int
+test_kasumi_auth_cipher(const struct kasumi_test_data *tdata)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ struct crypto_unittest_params *ut_params = &unittest_params;
+
+ int retval;
+
+ uint8_t *plaintext, *ciphertext;
+ unsigned plaintext_pad_len;
+ unsigned plaintext_len;
+
+ /* Create KASUMI session */
+ retval = create_snow3g_kasumi_auth_cipher_session(
+ ts_params->valid_devs[0],
+ RTE_CRYPTO_CIPHER_OP_ENCRYPT,
+ RTE_CRYPTO_AUTH_OP_GENERATE,
+ RTE_CRYPTO_AUTH_KASUMI_F9,
+ RTE_CRYPTO_CIPHER_KASUMI_F8,
+ tdata->key.data, tdata->key.len,
+ tdata->aad.len, tdata->digest.len);
+ if (retval < 0)
+ return retval;
+ ut_params->ibuf = rte_pktmbuf_alloc(ts_params->mbuf_pool);
+
+ /* clear mbuf payload */
+ memset(rte_pktmbuf_mtod(ut_params->ibuf, uint8_t *), 0,
+ rte_pktmbuf_tailroom(ut_params->ibuf));
+
+ plaintext_len = ceil_byte_length(tdata->plaintext.len);
+ /* Append data which is padded to a multiple of */
+ /* the algorithms block size */
+ plaintext_pad_len = RTE_ALIGN_CEIL(plaintext_len, 16);
+ plainte
[dpdk-dev] [PATCH v3 2/3] crypto/qat: add Kasumi support in Intel(R) QAT driver
This patch add kasumi support in Intel(R)
QuickAssist driver.
Signed-off-by: Deepak Kumar Jain
---
doc/guides/cryptodevs/qat.rst| 10 +--
doc/guides/rel_notes/release_16_11.rst | 2 +-
drivers/crypto/qat/qat_adf/qat_algs.h| 10 ++-
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 72 +++--
drivers/crypto/qat/qat_crypto.c | 79 ++--
5 files changed, 158 insertions(+), 15 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 78cadc4..6cdfb93 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -51,6 +51,7 @@ Cipher algorithms:
* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
* ``RTE_CRYPTO_CIPHER_AES_GCM``
* ``RTE_CRYPTO_CIPHER_NULL``
+* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
Hash algorithms:
@@ -63,17 +64,18 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
* ``RTE_CRYPTO_AUTH_MD5_HMAC``
* ``RTE_CRYPTO_AUTH_NULL``
+* ``RTE_CRYPTO_AUTH_KASUMI_F9``
Limitations
---
* Chained mbufs are not supported.
-* Hash only is not supported except Snow3G UIA2.
-* Cipher only is not supported except Snow3G UEA2.
+* Hash only is not supported except Snow3G UIA2 and Kasumi F9.
+* Cipher only is not supported except Snow3G UEA2 and Kasumi F8.
* Only supports the session-oriented API implementation (session-less APIs are
not supported).
* Not performance tuned.
-* Snow3g(UEA2) supported only if cipher length, cipher offset fields are
byte-aligned.
-* Snow3g(UIA2) supported only if hash length, hash offset fields are
byte-aligned.
+* Snow3g(UEA2) and Kasumi(F8) supported only if cipher length, cipher offset
fields are byte-aligned.
+* Snow3g(UIA2) and kasumi(F9) supported only if hash length, hash offset
fields are byte-aligned.
* No BSD support as BSD QAT kernel driver not available.
* Snow3g (UIA2) not supported in the PMD of **Intel QuickAssist Technology
C3xxx** device.
diff --git a/doc/guides/rel_notes/release_16_11.rst
b/doc/guides/rel_notes/release_16_11.rst
index 4bc67e0..1dd0e6a 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -50,7 +50,7 @@ New Features
* Added support for SHA224-HMAC algorithm.
* Added support for SHA384-HMAC algorithm.
* Added support for NULL algorithm.
-
+ * Added support for KASUMI (F8 and F9) algorithm.
Resolved Issues
---
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index 6a86053..fad8471 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -51,6 +51,14 @@
#include "icp_qat_fw.h"
#include "icp_qat_fw_la.h"
+/*
+ * Key Modifier (KM) value used in Kasumi algorithm in F9 mode to XOR
+ * Integrity Key (IK)
+ */
+#define KASUMI_F9_KEY_MODIFIER_4_BYTES 0x
+
+#define KASUMI_F8_KEY_MODIFIER_4_BYTES 0x
+
#define QAT_AES_HW_CONFIG_CBC_ENC(alg) \
ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \
ICP_QAT_HW_CIPHER_NO_CONVERT, \
@@ -130,5 +138,5 @@ void qat_alg_ablkcipher_init_dec(struct
qat_alg_ablkcipher_cd *cd,
int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
-
+int qat_alg_validate_kasumi_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
#endif
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index d9437bc..131800c 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -96,6 +96,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo
qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_MD5:
return QAT_HW_ROUND_UP(ICP_QAT_HW_MD5_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
+ case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
+ return QAT_HW_ROUND_UP(ICP_QAT_HW_KASUMI_F9_STATE1_SZ,
+ QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum state1 size in this case */
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
@@ -454,7 +457,8 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
uint32_t total_key_size;
uint16_t proto = ICP_QAT_FW_LA_NO_PROTO;/* no CCM/GCM/Snow3G */
uint16_t cipher_offset, cd_size;
-
+ uint32_t wordIndex = 0;
+ uint32_t *temp_key = NULL;
PMD_INIT_FUNC_TRACE();
if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
@@ -504,6 +508,11 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
cipher_cd_ctrl->cipher_state_sz =
ICP_QAT_
[dpdk-dev] [PATCH v3 1/3] app/test: cleanup of test code for kasumi
Cleanup for easier kasumi enabling. Changed name of funcitons for clear understanding. Signed-off-by: Deepak Kumar Jain --- app/test/test_cryptodev.c | 117 ++ 1 file changed, 55 insertions(+), 62 deletions(-) diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c index 67ca912..89d627f 100644 --- a/app/test/test_cryptodev.c +++ b/app/test/test_cryptodev.c @@ -1448,74 +1448,67 @@ create_snow3g_kasumi_cipher_hash_operation(const uint8_t *auth_tag, /* set crypto operation source mbuf */ sym_op->m_src = ut_params->ibuf; + /* digest */ + sym_op->auth.digest.data = (uint8_t *)rte_pktmbuf_append( + ut_params->ibuf, auth_tag_len); - /* iv */ - if (cipher_algo == RTE_CRYPTO_CIPHER_KASUMI_F8) - iv_pad_len = RTE_ALIGN_CEIL(iv_len, 8); + TEST_ASSERT_NOT_NULL(sym_op->auth.digest.data, + "no room to append auth tag"); + ut_params->digest = sym_op->auth.digest.data; + sym_op->auth.digest.phys_addr = rte_pktmbuf_mtophys_offset( + ut_params->ibuf, data_pad_len); + sym_op->auth.digest.length = auth_tag_len; + if (op == RTE_CRYPTO_AUTH_OP_GENERATE) + memset(sym_op->auth.digest.data, 0, auth_tag_len); else - iv_pad_len = RTE_ALIGN_CEIL(iv_len, 16); - - sym_op->cipher.iv.data = (uint8_t *)rte_pktmbuf_prepend( - ut_params->ibuf, iv_pad_len); - TEST_ASSERT_NOT_NULL(sym_op->cipher.iv.data, "no room to prepend iv"); - - memset(sym_op->cipher.iv.data, 0, iv_pad_len); - sym_op->cipher.iv.phys_addr = rte_pktmbuf_mtophys(ut_params->ibuf); - sym_op->cipher.iv.length = iv_pad_len; - - rte_memcpy(sym_op->cipher.iv.data, iv, iv_len); + rte_memcpy(sym_op->auth.digest.data, auth_tag, auth_tag_len); - sym_op->cipher.data.length = cipher_len; - sym_op->cipher.data.offset = cipher_offset; + TEST_HEXDUMP(stdout, "digest:", + sym_op->auth.digest.data, + sym_op->auth.digest.length); /* aad */ - /* - * Always allocate the aad up to the block size. - * The cryptodev API calls out - - * - the array must be big enough to hold the AAD, plus any - * space to round this up to the nearest multiple of the - * block size (8 bytes for KASUMI and 16 bytes for SNOW3G). - */ + /* + * Always allocate the aad up to the block size. + * The cryptodev API calls out - + * - the array must be big enough to hold the AAD, plus any + * space to round this up to the nearest multiple of the + * block size (8 bytes for KASUMI and 16 bytes for SNOW3G). + */ if (auth_algo == RTE_CRYPTO_AUTH_KASUMI_F9) aad_buffer_len = ALIGN_POW2_ROUNDUP(aad_len, 8); else aad_buffer_len = ALIGN_POW2_ROUNDUP(aad_len, 16); - sym_op->auth.aad.data = - (uint8_t *)rte_pktmbuf_mtod(ut_params->ibuf, uint8_t *); + (uint8_t *)rte_pktmbuf_prepend( + ut_params->ibuf, aad_buffer_len); TEST_ASSERT_NOT_NULL(sym_op->auth.aad.data, "no room to prepend aad"); sym_op->auth.aad.phys_addr = rte_pktmbuf_mtophys( ut_params->ibuf); sym_op->auth.aad.length = aad_len; - - memset(sym_op->auth.aad.data, 0, aad_buffer_len); + memset(sym_op->auth.aad.data, 0, aad_buffer_len); rte_memcpy(sym_op->auth.aad.data, aad, aad_len); + TEST_HEXDUMP(stdout, "aad:", + sym_op->auth.aad.data, aad_len); - TEST_HEXDUMP(stdout, "aad:", - sym_op->auth.aad.data, aad_len); - - /* digest */ - sym_op->auth.digest.data = (uint8_t *)rte_pktmbuf_append( - ut_params->ibuf, auth_tag_len); - - TEST_ASSERT_NOT_NULL(sym_op->auth.digest.data, - "no room to append auth tag"); - ut_params->digest = sym_op->auth.digest.data; - sym_op->auth.digest.phys_addr = rte_pktmbuf_mtophys_offset( - ut_params->ibuf, data_pad_len + aad_len); - sym_op->auth.digest.length = auth_tag_len; - if (op == RTE_CRYPTO_AUTH_OP_GENERATE) - memset(sym_op->auth.digest.data, 0, auth_tag_len); + /* iv */ + if (cipher_algo == RTE_CRYPTO_CIPHER_KASUMI_F8) + iv_pad_len = RTE_ALIGN_CEIL(iv_len, 8); else - rte_memcpy(sym_op->auth.digest.data, auth_tag, auth_tag_len); - - TEST_HEXDUMP(stdout, "dige
[dpdk-dev] [PATCH v3 0/3] add kasumi in Intel(R) QuickAssist driver
This patchset contains patches to enable kasumi functionality in Intel(R) QuickAsisst Technology Driver. This patchset depends on following patch: "crypto/qat: add Intel(R) QuickAssist C3xxx device" (http://dpdk.org/dev/patchwork/patch/15794/ Deepak Kumar Jain (3): app/test: cleanup of test code for kasumi crypto/qat: add Kasumi support in Intel(R) QAT driver app/test: add Kasumi tests in QAT test suite Changes in v3: * Merged Cipher only and hash only patches into one patch. * Code cleaup for clear understanding. Changes in v2: * Updated Test code to apply cleanly on driver code * Added relevant documentation app/test/test_cryptodev.c | 361 - app/test/test_cryptodev_kasumi_hash_test_vectors.h | 76 + app/test/test_cryptodev_kasumi_test_vectors.h | 103 +- doc/guides/cryptodevs/qat.rst | 10 +- doc/guides/rel_notes/release_16_11.rst | 2 +- drivers/crypto/qat/qat_adf/qat_algs.h | 10 +- drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 72 +++- drivers/crypto/qat/qat_crypto.c| 79 - 8 files changed, 614 insertions(+), 99 deletions(-) -- 2.5.5
[dpdk-dev] [PATCH v2] crypto/qat: add Intel(R) QuickAssist C3xxx device
From: Deepak Kumar JAIN Signed-off-by: Deepak Kumar Jain Acked-by: Fiona Trahe --- Changes in v2: Added new feature information in release_16_11.rst file. doc/guides/cryptodevs/qat.rst | 76 +++--- doc/guides/rel_notes/release_16_11.rst | 3 ++ drivers/crypto/qat/rte_qat_cryptodev.c | 3 ++ 3 files changed, 76 insertions(+), 6 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 3819e51..78cadc4 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -31,8 +31,8 @@ Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver == The QAT PMD provides poll mode crypto driver support for **Intel QuickAssist -Technology DH895xxC** and **Intel QuickAssist Technology C62x** -hardware accelerator. +Technology DH895xxC** , **Intel QuickAssist Technology C62x** and +**Intel QuickAssist Technology C3xxx** hardware accelerator. Features @@ -75,6 +75,7 @@ Limitations * Snow3g(UEA2) supported only if cipher length, cipher offset fields are byte-aligned. * Snow3g(UIA2) supported only if hash length, hash offset fields are byte-aligned. * No BSD support as BSD QAT kernel driver not available. +* Snow3g (UIA2) not supported in the PMD of **Intel QuickAssist Technology C3xxx** device. Installation @@ -98,14 +99,16 @@ If you are running on kernel 4.4 or greater, see instructions for `Installation using kernel.org driver`_ below. If you are on a kernel earlier than 4.4, see `Installation using 01.org QAT driver`_. -For **Intel QuickAssist Technology C62x** device, kernel 4.5 or greater is -needed. See instructions for `Installation using kernel.org driver`_ below. +For **Intel QuickAssist Technology C62x** and **Intel QuickAssist Technology C3xxx** +device, kernel 4.5 or greater is needed. +See instructions for `Installation using kernel.org driver`_ below. Installation using 01.org QAT driver -NOTE: There is no driver available for **Intel QuickAssist Technology C62x** on 01.org. +NOTE: There is no driver available for **Intel QuickAssist Technology C62x** and +**Intel QuickAssist Technology C3xxx** devices on 01.org. Download the latest QuickAssist Technology Driver from `01.org <https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_ @@ -184,6 +187,7 @@ Installation using kernel.org driver For **Intel QuickAssist Technology DH895xxC**: + Assuming you are running on at least a 4.4 kernel, you can use the stock kernel.org QAT driver to start the QAT hardware. @@ -242,7 +246,6 @@ cd to your linux source root directory and start the qat kernel modules: **Note**:The following warning in /var/log/messages can be ignored: ``IOMMU should be enabled for SR-IOV to work correctly`` - For **Intel QuickAssist Technology C62x**: Assuming you are running on at least a 4.5 kernel, you can use the stock kernel.org QAT driver to start the QAT hardware. @@ -287,6 +290,47 @@ the bdf of the 48 VF devices are available per ``C62x`` device. To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_. +For **Intel QuickAssist Technology C3xxx**: +Assuming you are running on at least a 4.5 kernel, you can use the stock kernel.org QAT +driver to start the QAT hardware. + +The steps below assume you are: + +* Running DPDK on a platform with one ``C3xxx`` device. +* On a kernel at least version 4.5. + +In BIOS ensure that SRIOV is enabled and VT-d is disabled. + +Ensure the QAT driver is loaded on your system, by executing:: + +lsmod | grep qat + +You should see the following output:: + +qat_c3xxx 16384 0 +intel_qat 122880 1 qat_c3xxx + +Next, you need to expose the Virtual Functions (VFs) using the sysfs file system. + +First find the bdf of the physical function (PF) of the C3xxx device + +lspci -d:19e2 + +You should see output similar to:: + +01:00.0 Co-processor: Intel Corporation Device 19e2 + +For c3xxx device there is 1 PFs. +Using the sysfs, enable the 16 VFs:: + +echo 16 > /sys/bus/pci/drivers/c3xxx/\:01\:00.0/sriov_numvfs + +If you get an error, it's likely you're using a QAT kernel driver earlier than kernel 4.5. + +To verify that the VFs are available for use - use ``lspci -d:19e3`` to confirm +the bdf of the 16 VF devices are available per ``C3xxx`` device. +To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_. + Binding the available VFs to the DPDK UIO driver @@ -332,3 +376,23 @@ if yours are different adjust the unbind command below:: echo "8086 37c9" > /sys/bus/pci/drivers/igb_uio/new_id You can use ``lspci -vvd:37c9`` to confirm that all devices are now in use by igb_uio
[dpdk-dev] [PATCH v3] doc/guides: add info on how to enable QAT
From: Eoin Breen Signed-off-by: Eoin Breen Signed-off-by: Deepak Kumar Jain --- Changes in v3: * Add console code-block * Modified the command to replace n with y in build/.config Changes in v2: * Incorporated comments received on v1. doc/guides/cryptodevs/qat.rst | 11 +++ 1 file changed, 11 insertions(+) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 3ee2312..2480ce2 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -83,6 +83,17 @@ Installation To use the DPDK QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF devices exposed by this driver will be used by QAT PMD. +To enable QAT in DPDK, follow the instructions mentioned in +http://dpdk.org/doc/guides/linux_gsg/build_dpdk.html + +Quick instructions as follows: + +.. code-block:: console + + make config T=x86_64-native-linuxapp-gcc + sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT\)=n,\1=y,' build/.config + make + If you are running on kernel 4.4 or greater, see instructions for `Installation using kernel.org driver`_ below. If you are on a kernel earlier than 4.4, see `Installation using 01.org QAT driver`_. -- 2.5.5
[dpdk-dev] [PATCH] doc/guides: fix name of algorithm
Update documentation with correct names of algorithm supported.
Fixes: 1703e94ac5cee ("qat: add driver for QuickAssist devices")
Signed-off-by: Deepak Kumar Jain
---
doc/guides/cryptodevs/qat.rst | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 325004c..72c116a 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -42,13 +42,13 @@ The QAT PMD has support for:
Cipher algorithms:
-* ``RTE_CRYPTO_SYM_CIPHER_AES128_CBC``
-* ``RTE_CRYPTO_SYM_CIPHER_AES192_CBC``
-* ``RTE_CRYPTO_SYM_CIPHER_AES256_CBC``
-* ``RTE_CRYPTO_SYM_CIPHER_AES128_CTR``
-* ``RTE_CRYPTO_SYM_CIPHER_AES192_CTR``
-* ``RTE_CRYPTO_SYM_CIPHER_AES256_CTR``
-* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2``
+* ``RTE_CRYPTO_CIPHER_AES128_CBC``
+* ``RTE_CRYPTO_CIPHER_AES192_CBC``
+* ``RTE_CRYPTO_CIPHER_AES256_CBC``
+* ``RTE_CRYPTO_CIPHER_AES128_CTR``
+* ``RTE_CRYPTO_CIPHER_AES192_CTR``
+* ``RTE_CRYPTO_CIPHER_AES256_CTR``
+* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
* ``RTE_CRYPTO_CIPHER_AES_GCM``
* ``RTE_CRYPTO_CIPHER_NULL``
--
2.5.5
[dpdk-dev] [PATCH v2] doc/guides: add info on how to enable QAT
From: Eoin Breen Signed-off-by: Eoin Breen Signed-off-by: Deepak Kumar Jain --- Changes in v2: Incorporated comments received on v1. doc/guides/cryptodevs/qat.rst | 10 ++ 1 file changed, 10 insertions(+) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 3ee2312..325004c 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -83,6 +83,16 @@ Installation To use the DPDK QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF devices exposed by this driver will be used by QAT PMD. +To enable QAT in DPDK, follow the instructions mentioned in +http://dpdk.org/doc/guides/linux_gsg/build_dpdk.html + +Quick instructions as follows: + +#. ``make config T=x86_64-native-linuxapp-gcc`` +#. Open the ``./build/.config`` file +#. Replace ``CONFIG_RTE_LIBRTE_PMD_QAT=n`` with ``CONFIG_RTE_LIBRTE_PMD_QAT=y`` +#. ``make`` + If you are running on kernel 4.4 or greater, see instructions for `Installation using kernel.org driver`_ below. If you are on a kernel earlier than 4.4, see `Installation using 01.org QAT driver`_. -- 2.5.5
[dpdk-dev] [PATCH v4] crypto/qat: add Intel QuickAssist C62x device
From: Deepak Kumar JAIN Signed-off-by: Deepak Kumar Jain Acked-by: Fiona Trahe --- Changes in v4: Fixed the issues in qat.rst file. Changes in v3: Added new feature information Changes in v2: Removed trialing white spaces doc/guides/cryptodevs/qat.rst | 86 -- doc/guides/rel_notes/release_16_11.rst | 4 ++ drivers/crypto/qat/rte_qat_cryptodev.c | 3 ++ 3 files changed, 88 insertions(+), 5 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index bb62f22..3ee2312 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -27,11 +27,12 @@ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -Quick Assist Crypto Poll Mode Driver - +Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver +== The QAT PMD provides poll mode crypto driver support for **Intel QuickAssist -Technology DH895xxC** hardware accelerator. +Technology DH895xxC** and **Intel QuickAssist Technology C62x** +hardware accelerator. Features @@ -86,10 +87,15 @@ If you are running on kernel 4.4 or greater, see instructions for `Installation using kernel.org driver`_ below. If you are on a kernel earlier than 4.4, see `Installation using 01.org QAT driver`_. +For **Intel QuickAssist Technology C62x** device, kernel 4.5 or greater is +needed. See instructions for `Installation using kernel.org driver`_ below. + Installation using 01.org QAT driver +NOTE: There is no driver available for **Intel QuickAssist Technology C62x** on 01.org. + Download the latest QuickAssist Technology Driver from `01.org <https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_ Consult the *Getting Started Guide* at the same URL for further information. @@ -166,6 +172,7 @@ If the build or install fails due to mismatching kernel sources you may need to Installation using kernel.org driver +For **Intel QuickAssist Technology DH895xxC**: Assuming you are running on at least a 4.4 kernel, you can use the stock kernel.org QAT driver to start the QAT hardware. @@ -185,9 +192,9 @@ You should see the following output:: qat_dh895xcc5626 0 intel_qat 82336 1 qat_dh895xcc -Next, you need to expose the VFs using the sysfs file system. +Next, you need to expose the Virtual Functions (VFs) using the sysfs file system. -First find the bdf of the DH895xCC device:: +First find the bdf of the physical function (PF) of the DH895xCC device:: lspci -d : 435 @@ -225,10 +232,54 @@ cd to your linux source root directory and start the qat kernel modules: ``IOMMU should be enabled for SR-IOV to work correctly`` +For **Intel QuickAssist Technology C62x**: +Assuming you are running on at least a 4.5 kernel, you can use the stock kernel.org QAT +driver to start the QAT hardware. + +The steps below assume you are: + +* Running DPDK on a platform with one ``C62x`` device. +* On a kernel at least version 4.5. + +In BIOS ensure that SRIOV is enabled and VT-d is disabled. + +Ensure the QAT driver is loaded on your system, by executing:: + +lsmod | grep qat + +You should see the following output:: + +qat_c62x 16384 0 +intel_qat 122880 1 qat_c62x + +Next, you need to expose the VFs using the sysfs file system. + +First find the bdf of the C62x device:: + +lspci -d:37c8 + +You should see output similar to:: + +1a:00.0 Co-processor: Intel Corporation Device 37c8 +3d:00.0 Co-processor: Intel Corporation Device 37c8 +3f:00.0 Co-processor: Intel Corporation Device 37c8 + +For each c62x device there are 3 PFs. +Using the sysfs, for each PF, enable the 16 VFs:: + +echo 16 > /sys/bus/pci/drivers/c6xx/\:1a\:00.0/sriov_numvfs + +If you get an error, it's likely you're using a QAT kernel driver earlier than kernel 4.5. + +To verify that the VFs are available for use - use ``lspci -d:37c9`` to confirm +the bdf of the 48 VF devices are available per ``C62x`` device. + +To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_. Binding the available VFs to the DPDK UIO driver +For **Intel(R) QuickAssist Technology DH895xcc** device: The unbind command below assumes ``bdfs`` of ``03:01.00-03:04.07``, if yours are different adjust the unbind command below:: cd $RTE_SDK @@ -245,3 +296,28 @@ The unbind command below assumes ``bdfs`` of ``03:01.00-03:04.07``, if yours are echo "8086 0443" > /sys/bus/pci/drivers/igb_uio/new_id You can use ``lspci -vvd:443`` to confirm that all devices are now in use by igb_uio kernel driver. + +For **Intel(R) Quic
[dpdk-dev] [PATCH v3] crypto/qat: add Intel QuickAssist C62x device
From: Deepak Kumar JAIN Signed-off-by: Deepak Kumar Jain Acked-by: Fiona Trahe --- Changes in v3: Added new feature information Changes in v2: Removed trialing white spaces doc/guides/cryptodevs/qat.rst | 82 -- doc/guides/rel_notes/release_16_11.rst | 4 ++ drivers/crypto/qat/rte_qat_cryptodev.c | 3 ++ 3 files changed, 85 insertions(+), 4 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index bb62f22..f6091dd 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -27,11 +27,12 @@ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -Quick Assist Crypto Poll Mode Driver +Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver The QAT PMD provides poll mode crypto driver support for **Intel QuickAssist -Technology DH895xxC** hardware accelerator. +Technology DH895xxC** and **Intel QuickAssist Technology C62x** +hardware accelerator. Features @@ -86,9 +87,13 @@ If you are running on kernel 4.4 or greater, see instructions for `Installation using kernel.org driver`_ below. If you are on a kernel earlier than 4.4, see `Installation using 01.org QAT driver`_. +For **Intel QuickAssist Technology C62x** device, kernel 4.5 or greater is +needed. See instructions for `instructions using kernel.org driver`_ below. + Installation using 01.org QAT driver +NOTE: There is no driver available for **Intel QuickAssist Technology C62x** on 01.org. Download the latest QuickAssist Technology Driver from `01.org <https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_ @@ -166,6 +171,7 @@ If the build or install fails due to mismatching kernel sources you may need to Installation using kernel.org driver +For **Intel QuickAssist Technology DH895xxC**: Assuming you are running on at least a 4.4 kernel, you can use the stock kernel.org QAT driver to start the QAT hardware. @@ -185,9 +191,9 @@ You should see the following output:: qat_dh895xcc5626 0 intel_qat 82336 1 qat_dh895xcc -Next, you need to expose the VFs using the sysfs file system. +Next, you need to expose the Virtual Functions (VFs) using the sysfs file system. -First find the bdf of the DH895xCC device:: +First find the bdf of the physical function (PF) of the DH895xCC device:: lspci -d : 435 @@ -225,10 +231,53 @@ cd to your linux source root directory and start the qat kernel modules: ``IOMMU should be enabled for SR-IOV to work correctly`` +For **Intel QuickAssist Technology C62x**: +Assuming you are running on at least a 4.5 kernel, you can use the stock kernel.org QAT +driver to start the QAT hardware. + +The steps below assume you are: + +* Running DPDK on a platform with one ``C62x`` device. +* On a kernel at least version 4.5. + +In BIOS ensure that SRIOV is enabled and VT-d is disabled. + +Ensure the QAT driver is loaded on your system, by executing:: + +lsmod | grep qat + +You should see the following output:: + +qat_c62x 16384 0 +intel_qat 122880 1 qat_c62x + +Next, you need to expose the VFs using the sysfs file system. + +First find the bdf of the C62x device:: + +lspci -d:37c8 + +You should see output similar to:: + +1a:00.0 Co-processor: Intel Corporation Device 37c8 +3d:00.0 Co-processor: Intel Corporation Device 37c8 +3f:00.0 Co-processor: Intel Corporation Device 37c8 + +For each c62x device there are 3 PFs. +Using the sysfs, for each PF, enable the 16 VFs:: + +echo 16 > /sys/bus/pci/drivers/c6xx/\:1a\:00.0/sriov_numvfs + +If you get an error, it's likely you're using a QAT kernel driver earlier than kernel 4.5. +To verify that the VFs are available for use - use ``lspci -d:37c9`` to confirm +the bdf of the 48 VF devices are available per ``C62x`` device. + +To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_. Binding the available VFs to the DPDK UIO driver +For **Intel(R) QuickAssist Technology DH895xcc** device: The unbind command below assumes ``bdfs`` of ``03:01.00-03:04.07``, if yours are different adjust the unbind command below:: cd $RTE_SDK @@ -245,3 +294,28 @@ The unbind command below assumes ``bdfs`` of ``03:01.00-03:04.07``, if yours are echo "8086 0443" > /sys/bus/pci/drivers/igb_uio/new_id You can use ``lspci -vvd:443`` to confirm that all devices are now in use by igb_uio kernel driver. + +For **Intel(R) QuickAssist Technology C62x** device: +The unbind command below assumes ``bdfs`` of ``1a:01.00-1a:02.07``, ``3d:01.00-3d:02.07`` and ``3f:01.00-3f:02.07``, +if yours are different
[dpdk-dev] [PATCH v3 2/2] app/test: add test cases for NULL for Intel QAT driver
From: Deepak Kumar JAIN
Added NULL algorithm to test file for Intel(R) QuickAssist
Technology Driver
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 8553759..67ca912 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -4136,6 +4136,16 @@ static struct unit_test_suite cryptodev_qat_testsuite =
{
TEST_CASE_ST(ut_setup, ut_teardown,
test_MD5_HMAC_verify_case_2),
+ /** NULL tests */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_auth_only_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_cipher_only_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_cipher_auth_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_auth_cipher_operation),
+
TEST_CASES_END() /**< NULL terminate unit test array */
}
};
--
2.5.5
[dpdk-dev] [PATCH v3 1/2] crypto/qat: add NULL capability to Intel QAT driver
From: Deepak Kumar JAIN
enabled NULL crypto for Intel(R) QuickAssist Technology
Signed-off-by: Deepak Kumar Jain
---
doc/guides/cryptodevs/qat.rst| 3 +-
doc/guides/rel_notes/release_16_11.rst | 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++
drivers/crypto/qat/qat_crypto.c | 45
4 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 78a734f..bb62f22 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -49,6 +49,7 @@ Cipher algorithms:
* ``RTE_CRYPTO_SYM_CIPHER_AES256_CTR``
* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2``
* ``RTE_CRYPTO_CIPHER_AES_GCM``
+* ``RTE_CRYPTO_CIPHER_NULL``
Hash algorithms:
@@ -60,7 +61,7 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
* ``RTE_CRYPTO_AUTH_MD5_HMAC``
-
+* ``RTE_CRYPTO_AUTH_NULL``
Limitations
---
diff --git a/doc/guides/rel_notes/release_16_11.rst
b/doc/guides/rel_notes/release_16_11.rst
index 9b2f102..9b2c775 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -42,6 +42,7 @@ New Features
* Added support for MD5_HMAC algorithm.
* Added support for SHA224-HMAC algorithm.
* Added support for SHA384-HMAC algorithm.
+ * Added support for NULL algorithm.
Resolved Issues
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index af8c176..d9437bc 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -720,6 +720,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
}
state2_size = ICP_QAT_HW_MD5_STATE2_SZ;
break;
+ case ICP_QAT_HW_AUTH_ALGO_NULL:
+ break;
default:
PMD_DRV_LOG(ERR, "Invalid HASH alg %u", cdesc->qat_hash_alg);
return -EFAULT;
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 60e2ba2..bc8d5b1 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -346,6 +346,47 @@ static const struct rte_cryptodev_capabilities
qat_pmd_capabilities[] = {
}, }
}, }
},
+ { /* NULL (AUTH) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_NULL,
+ .block_size = 1,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .aad_size = { 0 }
+ }, },
+ }, },
+ },
+ { /* NULL (CIPHER) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_NULL,
+ .block_size = 1,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 8
+ },
+ .iv_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ }
+ }, },
+ }, }
+ },
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
@@ -469,6 +510,8 @@ qat_crypto_sym_configure_session_cipher(struct
rte_cryptodev *dev,
session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
break;
case RTE_CRYPTO_CIPHER_NULL:
+ session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
+ break;
case RTE_CRYPTO_CIPHER_3DES_ECB:
case RTE_CRYPTO_CIPHER_3DES_CBC:
case RTE_CRYPTO_CIPHER_AES_ECB:
@@ -600,6 +643,8 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev
*dev,
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
break;
case RTE_CRYPTO_AUTH_NULL:
+ session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
+
[dpdk-dev] [PATCH v3 0/2] add NULL crypto support in Intel QAT driver
This patchset adds support of NULL crypto in Intel(R) QuickAssist Technology driver. This patchset depends on following patchset: "crypto/qat: add aes-sha384-hmac capability to Intel QAT driver" (http://dpdk.org/dev/patchwork/patch/15778/) Deepak Kumar JAIN (2): crypto/qat: add NULL capability to Intel QAT driver app/test: add test cases for NULL for Intel QAT driver Changes in v3: * Added information in capability structure. Changes in v2: * Added new feature information in release_16_11.rst file. app/test/test_cryptodev.c| 10 ++ doc/guides/cryptodevs/qat.rst| 3 +- doc/guides/rel_notes/release_16_11.rst | 1 + drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++ drivers/crypto/qat/qat_crypto.c | 45 5 files changed, 60 insertions(+), 1 deletion(-) -- 2.5.5
[dpdk-dev] [PATCH v2 2/2] app/test: add test cases for NULL for Intel QAT driver
From: Deepak Kumar JAIN
Added NULL algorithm to test file for Intel(R) QuickAssist
Technology Driver
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 8553759..67ca912 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -4136,6 +4136,16 @@ static struct unit_test_suite cryptodev_qat_testsuite =
{
TEST_CASE_ST(ut_setup, ut_teardown,
test_MD5_HMAC_verify_case_2),
+ /** NULL tests */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_auth_only_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_cipher_only_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_cipher_auth_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_auth_cipher_operation),
+
TEST_CASES_END() /**< NULL terminate unit test array */
}
};
--
2.5.5
[dpdk-dev] [PATCH v2 1/2] crypto/qat: add NULL capability to Intel QAT driver
From: Deepak Kumar JAIN enabled NULL crypto for Intel(R) QuickAssist Technology Signed-off-by: Deepak Kumar Jain --- doc/guides/cryptodevs/qat.rst| 3 ++- doc/guides/rel_notes/release_16_11.rst | 1 + drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++ drivers/crypto/qat/qat_crypto.c | 4 4 files changed, 9 insertions(+), 1 deletion(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 78a734f..bb62f22 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -49,6 +49,7 @@ Cipher algorithms: * ``RTE_CRYPTO_SYM_CIPHER_AES256_CTR`` * ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2`` * ``RTE_CRYPTO_CIPHER_AES_GCM`` +* ``RTE_CRYPTO_CIPHER_NULL`` Hash algorithms: @@ -60,7 +61,7 @@ Hash algorithms: * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC`` * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2`` * ``RTE_CRYPTO_AUTH_MD5_HMAC`` - +* ``RTE_CRYPTO_AUTH_NULL`` Limitations --- diff --git a/doc/guides/rel_notes/release_16_11.rst b/doc/guides/rel_notes/release_16_11.rst index 9b2f102..9b2c775 100644 --- a/doc/guides/rel_notes/release_16_11.rst +++ b/doc/guides/rel_notes/release_16_11.rst @@ -42,6 +42,7 @@ New Features * Added support for MD5_HMAC algorithm. * Added support for SHA224-HMAC algorithm. * Added support for SHA384-HMAC algorithm. + * Added support for NULL algorithm. Resolved Issues diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c index af8c176..d9437bc 100644 --- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c +++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c @@ -720,6 +720,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc, } state2_size = ICP_QAT_HW_MD5_STATE2_SZ; break; + case ICP_QAT_HW_AUTH_ALGO_NULL: + break; default: PMD_DRV_LOG(ERR, "Invalid HASH alg %u", cdesc->qat_hash_alg); return -EFAULT; diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c index 60e2ba2..be2b9be 100644 --- a/drivers/crypto/qat/qat_crypto.c +++ b/drivers/crypto/qat/qat_crypto.c @@ -469,6 +469,8 @@ qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev, session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE; break; case RTE_CRYPTO_CIPHER_NULL: + session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE; + break; case RTE_CRYPTO_CIPHER_3DES_ECB: case RTE_CRYPTO_CIPHER_3DES_CBC: case RTE_CRYPTO_CIPHER_AES_ECB: @@ -600,6 +602,8 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev, session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5; break; case RTE_CRYPTO_AUTH_NULL: + session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL; + break; case RTE_CRYPTO_AUTH_SHA1: case RTE_CRYPTO_AUTH_SHA256: case RTE_CRYPTO_AUTH_SHA512: -- 2.5.5
[dpdk-dev] [PATCH v2 0/2] add NULL crypto support in Intel QAT driver
This patchset adds support of NULL crypto in Intel(R) QuickAssist Technology driver. This patchset depends on following patchset: "crypto/qat: add aes-sha384-hmac capability to Intel QAT driver" (http://dpdk.org/dev/patchwork/patch/15778/) Deepak Kumar JAIN (2): crypto/qat: add NULL capability to Intel QAT driver app/test: add test cases for NULL for Intel QAT driver Changes in V1: * Added new feature information in release_16_11.rst file. app/test/test_cryptodev.c| 10 ++ doc/guides/cryptodevs/qat.rst| 3 ++- doc/guides/rel_notes/release_16_11.rst | 1 + drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++ drivers/crypto/qat/qat_crypto.c | 4 5 files changed, 19 insertions(+), 1 deletion(-) -- 2.5.5
[dpdk-dev] [PATCH v2 2/2] app/test: add test cases for aes-sha384-hmac for Intel QAT driver
From: "Jain, Deepak K"
Added aes-sha384-hmac algorithm to test file for Intel(R) QuickAssist
Technology Driver
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev_aes.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/app/test/test_cryptodev_aes.c b/app/test/test_cryptodev_aes.c
index 6ad2674..e19c45b 100644
--- a/app/test/test_cryptodev_aes.c
+++ b/app/test/test_cryptodev_aes.c
@@ -226,14 +226,16 @@ static const struct aes_test_case aes_test_cases[] = {
.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
.test_data = &aes_test_data_9,
.op_mask = AES_TEST_OP_ENC_AUTH_GEN,
- .pmd_mask = AES_TEST_TARGET_PMD_MB
+ .pmd_mask = AES_TEST_TARGET_PMD_MB |
+ AES_TEST_TARGET_PMD_QAT
},
{
.test_descr = "AES-128-CBC HMAC-SHA384 Decryption Digest "
"Verify",
.test_data = &aes_test_data_9,
.op_mask = AES_TEST_OP_AUTH_VERIFY_DEC,
- .pmd_mask = AES_TEST_TARGET_PMD_MB
+ .pmd_mask = AES_TEST_TARGET_PMD_MB |
+ AES_TEST_TARGET_PMD_QAT
},
};
--
2.5.5
[dpdk-dev] [PATCH v2 1/2] crypto/qat: add aes-sha384-hmac capability to Intel QAT driver
From: "Jain, Deepak K"
enabled support of aes-sha384-hmac in Intel(R) QuickAssist driver
Signed-off-by: Deepak Kumar Jain
---
doc/guides/cryptodevs/qat.rst| 1 +
doc/guides/rel_notes/release_16_11.rst | 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33
drivers/crypto/qat/qat_crypto.c | 31 +++---
4 files changed, 62 insertions(+), 4 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 7f630be..78a734f 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -55,6 +55,7 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
diff --git a/doc/guides/rel_notes/release_16_11.rst
b/doc/guides/rel_notes/release_16_11.rst
index 040e250..9b2f102 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -41,6 +41,7 @@ New Features
* Added support for MD5_HMAC algorithm.
* Added support for SHA224-HMAC algorithm.
+ * Added support for SHA384-HMAC algorithm.
Resolved Issues
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 77e6548..af8c176 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -77,6 +77,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo
qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA256_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
+ case ICP_QAT_HW_AUTH_ALGO_SHA384:
+ return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA384_STATE1_SZ,
+ QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_SHA512:
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
@@ -114,6 +117,8 @@ static int qat_hash_get_digest_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
return ICP_QAT_HW_SHA224_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return ICP_QAT_HW_SHA256_STATE1_SZ;
+ case ICP_QAT_HW_AUTH_ALGO_SHA384:
+ return ICP_QAT_HW_SHA384_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
return ICP_QAT_HW_SHA512_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_MD5:
@@ -138,6 +143,8 @@ static int qat_hash_get_block_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
return SHA256_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return SHA256_CBLOCK;
+ case ICP_QAT_HW_AUTH_ALGO_SHA384:
+ return SHA512_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
return SHA512_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
@@ -187,6 +194,17 @@ static int partial_hash_sha256(uint8_t *data_in, uint8_t
*data_out)
return 0;
}
+static int partial_hash_sha384(uint8_t *data_in, uint8_t *data_out)
+{
+ SHA512_CTX ctx;
+
+ if (!SHA384_Init(&ctx))
+ return -EFAULT;
+ SHA512_Transform(&ctx, data_in);
+ rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
+ return 0;
+}
+
static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)
{
SHA512_CTX ctx;
@@ -252,6 +270,13 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo
hash_alg,
*hash_state_out_be32 =
rte_bswap32(*(((uint32_t *)digest)+i));
break;
+ case ICP_QAT_HW_AUTH_ALGO_SHA384:
+ if (partial_hash_sha384(data_in, digest))
+ return -EFAULT;
+ for (i = 0; i < digest_size >> 3; i++, hash_state_out_be64++)
+ *hash_state_out_be64 =
+ rte_bswap64(*(((uint64_t *)digest)+i));
+ break;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
if (partial_hash_sha512(data_in, digest))
return -EFAULT;
@@ -616,6 +641,14 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
}
state2_size = ICP_QAT_HW_SHA256_STATE2_SZ;
break;
+ case ICP_QAT_HW_AUTH_ALGO_SHA384:
+ if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384,
+ authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ PMD_DRV_LOG(ERR, "(SHA)precompute failed");
+ return -EFAULT;
+ }
+ state2_size = ICP_QAT_HW_SHA384_STATE2_SZ;
+ break;
case
[dpdk-dev] [PATCH v2 0/2] add aes-sha384-hmac support to Intel QAT driver
This patchset adds support of aes-sha384-hmac in Intel(R) QuickAssist Technology driver. This patchset depends on following patchset: "crypto/qat: add aes-sha224-hmac capability to Intel QAT driver" (http://dpdk.org/dev/patchwork/patch/15776/) Jain, Deepak K (2): crypto/qat: add aes-sha384-hmac capability to Intel QAT driver app/test: add test cases for aes-sha384-hmac for Intel QAT driver Changes from V1: * Added new feature information in release_16_11.rst file. * Added information about sha384-hmac in capabilities. app/test/test_cryptodev_aes.c| 6 +++-- doc/guides/cryptodevs/qat.rst| 1 + doc/guides/rel_notes/release_16_11.rst | 1 + drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 drivers/crypto/qat/qat_crypto.c | 31 +++--- 5 files changed, 66 insertions(+), 6 deletions(-) -- 2.5.5
[dpdk-dev] [PATCH v2 2/2] app/test: add test cases for aes-sha224-hmac for Intel QAT driver
From: "Jain, Deepak K"
Added aes-sha224-hmac algorithm to test file for Intel(R) QuickAssist
Technology Driver
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev_aes.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/app/test/test_cryptodev_aes.c b/app/test/test_cryptodev_aes.c
index bf832b6..6ad2674 100644
--- a/app/test/test_cryptodev_aes.c
+++ b/app/test/test_cryptodev_aes.c
@@ -211,14 +211,16 @@ static const struct aes_test_case aes_test_cases[] = {
.test_descr = "AES-128-CBC HMAC-SHA224 Encryption Digest",
.test_data = &aes_test_data_8,
.op_mask = AES_TEST_OP_ENC_AUTH_GEN,
- .pmd_mask = AES_TEST_TARGET_PMD_MB
+ .pmd_mask = AES_TEST_TARGET_PMD_MB |
+ AES_TEST_TARGET_PMD_QAT
},
{
.test_descr = "AES-128-CBC HMAC-SHA224 Decryption Digest "
"Verify",
.test_data = &aes_test_data_8,
.op_mask = AES_TEST_OP_AUTH_VERIFY_DEC,
- .pmd_mask = AES_TEST_TARGET_PMD_MB
+ .pmd_mask = AES_TEST_TARGET_PMD_MB |
+ AES_TEST_TARGET_PMD_QAT
},
{
.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
--
2.5.5
[dpdk-dev] [PATCH v2 1/2] crypto/qat: add aes-sha224-hmac capability to Intel QAT driver
From: "Jain, Deepak K"
Added support of aes-sha224-hmac in Intel(R) QuickAssist driver
Signed-off-by: Deepak Kumar Jain
---
doc/guides/cryptodevs/qat.rst| 1 +
doc/guides/rel_notes/release_16_11.rst | 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33
drivers/crypto/qat/qat_crypto.c | 25 +-
4 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 485abb4..7f630be 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -53,6 +53,7 @@ Cipher algorithms:
Hash algorithms:
* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
diff --git a/doc/guides/rel_notes/release_16_11.rst
b/doc/guides/rel_notes/release_16_11.rst
index 4f7d784..040e250 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -40,6 +40,7 @@ New Features
The QAT PMD was updated with changes including the following:
* Added support for MD5_HMAC algorithm.
+ * Added support for SHA224-HMAC algorithm.
Resolved Issues
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 521a9c4..77e6548 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -71,6 +71,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo
qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_SHA1:
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA1_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA224_STATE1_SZ,
+ QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA256_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
@@ -107,6 +110,8 @@ static int qat_hash_get_digest_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
switch (qat_hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SHA1:
return ICP_QAT_HW_SHA1_STATE1_SZ;
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ return ICP_QAT_HW_SHA224_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return ICP_QAT_HW_SHA256_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
@@ -129,6 +134,8 @@ static int qat_hash_get_block_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
switch (qat_hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SHA1:
return SHA_CBLOCK;
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ return SHA256_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return SHA256_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
@@ -158,6 +165,17 @@ static int partial_hash_sha1(uint8_t *data_in, uint8_t
*data_out)
return 0;
}
+static int partial_hash_sha224(uint8_t *data_in, uint8_t *data_out)
+{
+ SHA256_CTX ctx;
+
+ if (!SHA224_Init(&ctx))
+ return -EFAULT;
+ SHA256_Transform(&ctx, data_in);
+ rte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);
+ return 0;
+}
+
static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)
{
SHA256_CTX ctx;
@@ -220,6 +238,13 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo
hash_alg,
*hash_state_out_be32 =
rte_bswap32(*(((uint32_t *)digest)+i));
break;
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ if (partial_hash_sha224(data_in, digest))
+ return -EFAULT;
+ for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
+ *hash_state_out_be32 =
+ rte_bswap32(*(((uint32_t *)digest)+i));
+ break;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
if (partial_hash_sha256(data_in, digest))
return -EFAULT;
@@ -575,6 +600,14 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
}
state2_size = RTE_ALIGN_CEIL(ICP_QAT_HW_SHA1_STATE2_SZ, 8);
break;
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224,
+ authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ PMD_DRV_LOG(ERR, "(SHA)precompute failed");
+ return -EFAULT;
+ }
+ state2_size = ICP_QAT_HW_SHA224_STATE2_SZ;
+ break;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
if (qa
[dpdk-dev] [PATCH v2 0/2] add aes-sha384-hmac support to Intel QAT driver
This patchset adds support of aes-sha384-hmac in Intel(R) QuickAssist Technology driver. This patchset depends on following patchset: "crypto/qat: add aes-sha224-hmac capability to Intel QAT driver" (http://dpdk.org/dev/patchwork/patch/15754/) Jain, Deepak K (2): crypto/qat: add aes-sha224-hmac capability to Intel QAT driver app/test: add test cases for aes-sha224-hmac for Intel QAT driver Changes from V1: * Added new feature information in release_16_11.rst file. * Added information about sha224-hmac in capabilities. app/test/test_cryptodev_aes.c| 6 +++-- doc/guides/cryptodevs/qat.rst| 1 + doc/guides/rel_notes/release_16_11.rst | 1 + drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 drivers/crypto/qat/qat_crypto.c | 25 +- 5 files changed, 63 insertions(+), 3 deletions(-) -- 2.5.5
[dpdk-dev] [PATCH v2 2/2] app/test: add test cases for MD5 HMAC for Intel QAT driver
From: Arkadiusz Kusztal
Added MD5 HMAC hash algorithm to test file for Intel QuickAssist
Technology Driver
Signed-off-by: Arek Kusztal
Acked-by: Fiona Trahe
---
app/test/test_cryptodev.c | 185
app/test/test_cryptodev_hmac_test_vectors.h | 121 ++
2 files changed, 306 insertions(+)
create mode 100644 app/test/test_cryptodev_hmac_test_vectors.h
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 647787d..8553759 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -49,6 +49,7 @@
#include "test_cryptodev_snow3g_test_vectors.h"
#include "test_cryptodev_snow3g_hash_test_vectors.h"
#include "test_cryptodev_gcm_test_vectors.h"
+#include "test_cryptodev_hmac_test_vectors.h"
static enum rte_cryptodev_type gbl_cryptodev_type;
@@ -3431,6 +3432,179 @@ test_stats(void)
return TEST_SUCCESS;
}
+static int MD5_HMAC_create_session(struct crypto_testsuite_params *ts_params,
+ struct crypto_unittest_params *ut_params,
+ enum rte_crypto_auth_operation op,
+ const struct HMAC_MD5_vector *test_case)
+{
+ uint8_t key[64];
+
+ memcpy(key, test_case->key.data, test_case->key.len);
+
+ ut_params->auth_xform.type = RTE_CRYPTO_SYM_XFORM_AUTH;
+ ut_params->auth_xform.next = NULL;
+ ut_params->auth_xform.auth.op = op;
+
+ ut_params->auth_xform.auth.algo = RTE_CRYPTO_AUTH_MD5_HMAC;
+
+ ut_params->auth_xform.auth.digest_length = MD5_DIGEST_LEN;
+ ut_params->auth_xform.auth.add_auth_data_length = 0;
+ ut_params->auth_xform.auth.key.length = test_case->key.len;
+ ut_params->auth_xform.auth.key.data = key;
+
+ ut_params->sess = rte_cryptodev_sym_session_create(
+ ts_params->valid_devs[0], &ut_params->auth_xform);
+
+ if (ut_params->sess == NULL)
+ return TEST_FAILED;
+
+ ut_params->ibuf = rte_pktmbuf_alloc(ts_params->mbuf_pool);
+
+ memset(rte_pktmbuf_mtod(ut_params->ibuf, uint8_t *), 0,
+ rte_pktmbuf_tailroom(ut_params->ibuf));
+
+ return 0;
+}
+
+static int MD5_HMAC_create_op(struct crypto_unittest_params *ut_params,
+ const struct HMAC_MD5_vector *test_case,
+ uint8_t **plaintext)
+{
+ uint16_t plaintext_pad_len;
+
+ struct rte_crypto_sym_op *sym_op = ut_params->op->sym;
+
+ plaintext_pad_len = RTE_ALIGN_CEIL(test_case->plaintext.len,
+ 16);
+
+ *plaintext = (uint8_t *)rte_pktmbuf_append(ut_params->ibuf,
+ plaintext_pad_len);
+ memcpy(*plaintext, test_case->plaintext.data,
+ test_case->plaintext.len);
+
+ sym_op->auth.digest.data = (uint8_t *)rte_pktmbuf_append(
+ ut_params->ibuf, MD5_DIGEST_LEN);
+ TEST_ASSERT_NOT_NULL(sym_op->auth.digest.data,
+ "no room to append digest");
+ sym_op->auth.digest.phys_addr = rte_pktmbuf_mtophys_offset(
+ ut_params->ibuf, plaintext_pad_len);
+ sym_op->auth.digest.length = MD5_DIGEST_LEN;
+
+ if (ut_params->auth_xform.auth.op == RTE_CRYPTO_AUTH_OP_VERIFY) {
+ rte_memcpy(sym_op->auth.digest.data, test_case->auth_tag.data,
+ test_case->auth_tag.len);
+ }
+
+ sym_op->auth.data.offset = 0;
+ sym_op->auth.data.length = test_case->plaintext.len;
+
+ rte_crypto_op_attach_sym_session(ut_params->op, ut_params->sess);
+ ut_params->op->sym->m_src = ut_params->ibuf;
+
+ return 0;
+}
+
+static int
+test_MD5_HMAC_generate(const struct HMAC_MD5_vector *test_case)
+{
+ uint16_t plaintext_pad_len;
+ uint8_t *plaintext, *auth_tag;
+
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ struct crypto_unittest_params *ut_params = &unittest_params;
+
+ if (MD5_HMAC_create_session(ts_params, ut_params,
+ RTE_CRYPTO_AUTH_OP_GENERATE, test_case))
+ return TEST_FAILED;
+
+ /* Generate Crypto op data structure */
+ ut_params->op = rte_crypto_op_alloc(ts_params->op_mpool,
+ RTE_CRYPTO_OP_TYPE_SYMMETRIC);
+ TEST_ASSERT_NOT_NULL(ut_params->op,
+ "Failed to allocate symmetric crypto operation struct");
+
+ plaintext_pad_len = RTE_ALIGN_CEIL(test_case->plaintext.len,
+ 16);
+
+ if (MD5_HMAC_create_op(ut_params, test_case, &plaintext))
+ return TEST_FAILED;
+
+ TEST_ASSERT_NOT_NULL(process_crypto_request(ts_params->valid_devs[0],
+ ut_params->op), "failed to process sym crypto op");
+
+ TEST_ASSERT_EQUAL(ut_params->op->status, RTE_CRYPTO_OP_STATUS_SUCCESS,
+ "crypto op processing failed");
+
+ if
[dpdk-dev] [PATCH v2 1/2] crypto/qat: add MD5 HMAC capability to Intel QAT driver
From: Arkadiusz Kusztal
Added posibility to compute MD5 HMAC digest with Intel QuickAssist
Technology Driver
Signed-off-by: Arek Kusztal
Signed-off-by: Deepak Kumar Jain
Acked-by: Fiona Trahe
---
doc/guides/cryptodevs/qat.rst| 1 +
doc/guides/rel_notes/release_16_11.rst | 5
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 34
drivers/crypto/qat/qat_crypto.c | 28 +--
4 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index cae1958..485abb4 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -57,6 +57,7 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
+* ``RTE_CRYPTO_AUTH_MD5_HMAC``
Limitations
diff --git a/doc/guides/rel_notes/release_16_11.rst
b/doc/guides/rel_notes/release_16_11.rst
index 66916af..4f7d784 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -36,6 +36,11 @@ New Features
This section is a comment. Make sure to start the actual text at the
margin.
+* **Updated the QAT PMD.**
+ The QAT PMD was updated with changes including the following:
+
+ * Added support for MD5_HMAC algorithm.
+
Resolved Issues
---
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index c658f6e..521a9c4 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -58,6 +58,7 @@
#include/* Needed to calculate pre-compute values */
#include/* Needed to calculate pre-compute values */
+#include/* Needed to calculate pre-compute values */
/*
@@ -86,6 +87,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo
qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:
return QAT_HW_ROUND_UP(ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
+ case ICP_QAT_HW_AUTH_ALGO_MD5:
+ return QAT_HW_ROUND_UP(ICP_QAT_HW_MD5_STATE1_SZ,
+ QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum state1 size in this case */
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
@@ -107,6 +111,8 @@ static int qat_hash_get_digest_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
return ICP_QAT_HW_SHA256_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
return ICP_QAT_HW_SHA512_STATE1_SZ;
+ case ICP_QAT_HW_AUTH_ALGO_MD5:
+ return ICP_QAT_HW_MD5_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum digest size in this case */
return ICP_QAT_HW_SHA512_STATE1_SZ;
@@ -129,6 +135,8 @@ static int qat_hash_get_block_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
return SHA512_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
return 16;
+ case ICP_QAT_HW_AUTH_ALGO_MD5:
+ return MD5_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum block size in this case */
return SHA512_CBLOCK;
@@ -172,6 +180,19 @@ static int partial_hash_sha512(uint8_t *data_in, uint8_t
*data_out)
return 0;
}
+static int partial_hash_md5(uint8_t *data_in, uint8_t *data_out)
+{
+
+ MD5_CTX ctx;
+
+ if (!MD5_Init(&ctx))
+ return -EFAULT;
+ MD5_Transform(&ctx, data_in);
+ rte_memcpy(data_out, &ctx, MD5_DIGEST_LENGTH);
+
+ return 0;
+}
+
static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
uint8_t *data_in,
uint8_t *data_out)
@@ -213,6 +234,10 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo
hash_alg,
*hash_state_out_be64 =
rte_bswap64(*(((uint64_t *)digest)+i));
break;
+ case ICP_QAT_HW_AUTH_ALGO_MD5:
+ if (partial_hash_md5(data_in, data_out))
+ return -EFAULT;
+ break;
default:
PMD_DRV_LOG(ERR, "invalid hash alg %u", hash_alg);
return -EFAULT;
@@ -620,6 +645,15 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
auth_param->hash_state_sz =
RTE_ALIGN_CEIL(add_auth_data_length, 16) >> 3;
break;
+ case ICP_QAT_HW_AUTH_ALGO_MD5:
+ if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5,
+ authkey, authkeylen, cdesc->cd_cur_ptr,
+ &state1_size)) {
+ PM
[dpdk-dev] [PATCH v2 0/2] Add HMAC_MD5 to Intel QuickAssist Technology driver
This patchset add capability to use HMAC_MD5 hash algorithm to Intel QuickAssist Technology driver and test cases to cryptodev test files. This patchset depends on the following patches/patchsets: "crypto/qat: make the session struct variable in size" (http://dpdk.org/dev/patchwork/patch/15125/) Arkadiusz Kusztal (2): crypto/qat: add MD5 HMAC capability to Intel QAT driver app/test: add test cases for MD5 HMAC for Intel QAT driver Changes from v1: * Added new feature information in release_16_11.rst file. app/test/test_cryptodev.c| 185 +++ app/test/test_cryptodev_hmac_test_vectors.h | 121 +++ doc/guides/cryptodevs/qat.rst| 1 + doc/guides/rel_notes/release_16_11.rst | 5 + drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 34 + drivers/crypto/qat/qat_crypto.c | 28 +++- 6 files changed, 372 insertions(+), 2 deletions(-) create mode 100644 app/test/test_cryptodev_hmac_test_vectors.h -- 2.5.5
[dpdk-dev] [PATCH] crypto/qat: add Intel(R) QuickAssist C3xxx device
Signed-off-by: Deepak Kumar Jain
---
doc/guides/cryptodevs/qat.rst | 71 --
drivers/crypto/qat/rte_qat_cryptodev.c | 3 ++
2 files changed, 71 insertions(+), 3 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index f6cc1fa..21486cd 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -77,6 +77,7 @@ Limitations
* Snow3g(UEA2) supported only if cipher length, cipher offset fields are
byte-aligned.
* Snow3g(UIA2) supported only if hash length, hash offset fields are
byte-aligned.
* No BSD support as BSD QAT kernel driver not available.
+* Snow3g (UIA2) not supported in the PMD of **Intel QuickAssist Technology
C3xxx** device.
Installation
@@ -89,13 +90,15 @@ If you are running on kernel 4.4 or greater, see
instructions for
`Installation using kernel.org driver`_ below. If you are on a kernel earlier
than 4.4, see `Installation using 01.org QAT driver`_.
-For **Intel QuickAssist Technology C62x** device, kernel 4.5 or greater is
+For **Intel QuickAssist Technology C62x** and **Intel QuickAssist Technology
C3xxx**
+device, kernel 4.5 or greater is
needed. See instructions for `instructions using kernel.org driver`_ below.
Installation using 01.org QAT driver
-NOTE: There is no driver available for **Intel QuickAssist Technology C62x**
on 01.org.
+NOTE: There is no driver available for **Intel QuickAssist Technology C62x**
and
+**Intel QuickAssist Technology C3xxx** devices on 01.org.
Download the latest QuickAssist Technology Driver from `01.org
<https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_
@@ -265,7 +268,7 @@ You should see output similar to::
3d:00.0 Co-processor: Intel Corporation Device 37c8
3f:00.0 Co-processor: Intel Corporation Device 37c8
-For each c62x device there are 3 PFs.
+For each c62x device there are 3 PFs.
Using the sysfs, for each PF, enable the 16 VFs::
echo 16 > /sys/bus/pci/drivers/c6xx/\:1a\:00.0/sriov_numvfs
@@ -276,6 +279,48 @@ To verify that the VFs are available for use - use ``lspci
-d:37c9`` to confirm
the bdf of the 48 VF devices are available per ``C62x`` device.
To complete the installation - follow instructions in `Binding the available
VFs to the DPDK UIO driver`_.
+
+For **Intel QuickAssist Technology C3xxx**:
+Assuming you are running on at least a 4.5 kernel, you can use the stock
kernel.org QAT
+driver to start the QAT hardware.
+
+The steps below assume you are:
+
+* Running DPDK on a platform with one ``C3xxx`` device.
+* On a kernel at least version 4.5.
+
+In BIOS ensure that SRIOV is enabled and VT-d is disabled.
+
+Ensure the QAT driver is loaded on your system, by executing::
+
+lsmod | grep qat
+
+You should see the following output::
+
+qat_c3xxx 16384 0
+intel_qat 122880 1 qat_c3xxx
+
+Next, you need to expose the Virtual Functions (VFs) using the sysfs file
system.
+
+First find the bdf of the physical function (PF) of the C3xxx device
+
+lspci -d:19e2
+
+You should see output similar to::
+
+01:00.0 Co-processor: Intel Corporation Device 19e2
+
+For c3xxx device there is 1 PFs.
+Using the sysfs, enable the 16 VFs::
+
+echo 16 > /sys/bus/pci/drivers/c3xxx/\:01\:00.0/sriov_numvfs
+
+If you get an error, it's likely you're using a QAT kernel driver earlier than
kernel 4.5.
+
+To verify that the VFs are available for use - use ``lspci -d:19e3`` to confirm
+the bdf of the 16 VF devices are available per ``C3xxx`` device.
+To complete the installation - follow instructions in `Binding the available
VFs to the DPDK UIO driver`_.
+
Binding the available VFs to the DPDK UIO driver
@@ -321,3 +366,23 @@ if yours are different adjust the unbind command below::
echo "8086 37c9" > /sys/bus/pci/drivers/igb_uio/new_id
You can use ``lspci -vvd:37c9`` to confirm that all devices are now in use by
igb_uio kernel driver.
+
+For **Intel(R) QuickAssist Technology C3xxx** device:
+The unbind command below assumes ``bdfs`` of ``01:01.00-01:02.07``,
+if yours are different adjust the unbind command below::
+
+ cd $RTE_SDK
+ modprobe uio
+ insmod ./build/kmod/igb_uio.ko
+
+ for device in $(seq 1 2); do \
+ for fn in $(seq 0 7); do \
+ echo -n :01:0${device}.${fn} > \
+ /sys/bus/pci/devices/\:01\:0${device}.${fn}/driver/unbind; \
+
+ done; \
+ done
+
+ echo "8086 19e3" > /sys/bus/pci/drivers/igb_uio/new_id
+
+You can use ``lspci -vvd:19e3`` to confirm that all devices are now in use by
igb_uio kernel driver.
diff --git a/drivers/crypto/qat/rte_qat_cryptodev.c
b/drivers/crypto/qat/rte_qat_cryptodev.c
index e606eb5..eb929b5 100644
--- a/drivers/crypto/qat/rte_qat_cryptodev.c
+++ b/drivers/crypto/qat/rte_qat_cryptodev.c
@@ -74
[dpdk-dev] [PATCH v2 4/4] app/test: add kasumi f8 test into QAT testsuite
From: Deepak Kumar JAIN
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev.c | 4
1 file changed, 4 insertions(+)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index a0dae4f..fa16d32 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -4156,6 +4156,10 @@ static struct unit_test_suite cryptodev_qat_testsuite =
{
TEST_CASE_ST(ut_setup, ut_teardown,
test_kasumi_hash_generate_test_case_6),
+ /** KASUMI encrypt only (F8) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_1),
+
TEST_CASES_END() /**< NULL terminate unit test array */
}
};
--
2.5.5
[dpdk-dev] [PATCH v2 3/4] crypto/qat: enable support of Kasumi F8 in QAT cryptodev
From: Deepak Kumar JAIN
This patch enables the support of Kasumi F8
for Intel Quick Assist Technology.
Signed-off-by: Deepak Kumar Jain
---
doc/guides/cryptodevs/qat.rst| 5 +--
drivers/crypto/qat/qat_adf/qat_algs.h| 3 +-
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 44 +---
drivers/crypto/qat/qat_crypto.c | 39 +++--
4 files changed, 81 insertions(+), 10 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 6b73d95..0502483 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -51,6 +51,7 @@ Cipher algorithms:
* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2``
* ``RTE_CRYPTO_CIPHER_AES_GCM``
* ``RTE_CRYPTO_CIPHER_NULL``
+* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
Hash algorithms:
@@ -70,10 +71,10 @@ Limitations
* Chained mbufs are not supported.
* Hash only is not supported except Snow3G UIA2 and KASUMI F9.
-* Cipher only is not supported except Snow3G UEA2.
+* Cipher only is not supported except Snow3G UEA2 and KASUMI F8.
* Only supports the session-oriented API implementation (session-less APIs are
not supported).
* Not performance tuned.
-* Snow3g(UEA2) supported only if cipher length, cipher offset fields are
byte-aligned.
+* Snow3g(UEA2) and KAUSMI(F8) supported only if cipher length, cipher offset
fields are byte-aligned.
* Snow3g(UIA2) and KASUMI(F9) supported only if hash length, hash offset
fields are byte-aligned.
* No BSD support as BSD QAT kernel driver not available.
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index 0cc176f..fad8471 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -57,6 +57,7 @@
*/
#define KASUMI_F9_KEY_MODIFIER_4_BYTES 0x
+#define KASUMI_F8_KEY_MODIFIER_4_BYTES 0x
#define QAT_AES_HW_CONFIG_CBC_ENC(alg) \
ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \
@@ -137,5 +138,5 @@ void qat_alg_ablkcipher_init_dec(struct
qat_alg_ablkcipher_cd *cd,
int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
-
+int qat_alg_validate_kasumi_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
#endif
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 085a652..9d1df56 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -457,7 +457,8 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
uint32_t total_key_size;
uint16_t proto = ICP_QAT_FW_LA_NO_PROTO;/* no CCM/GCM/Snow3G */
uint16_t cipher_offset, cd_size;
-
+ uint32_t wordIndex = 0;
+ uint32_t *temp_key = NULL;
PMD_INIT_FUNC_TRACE();
if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
@@ -507,6 +508,11 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
cipher_cd_ctrl->cipher_state_sz =
ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ >> 3;
proto = ICP_QAT_FW_LA_SNOW_3G_PROTO;
+ } else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
+ total_key_size = ICP_QAT_HW_KASUMI_F8_KEY_SZ;
+ cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_KASUMI_BLK_SZ >> 3;
+ cipher_cd_ctrl->cipher_padding_sz =
+ (2 * ICP_QAT_HW_KASUMI_BLK_SZ) >> 3;
} else {
total_key_size = cipherkeylen;
cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;
@@ -524,9 +530,27 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
ICP_QAT_HW_CIPHER_CONFIG_BUILD(cdesc->qat_mode,
cdesc->qat_cipher_alg, key_convert,
cdesc->qat_dir);
- memcpy(cipher->aes.key, cipherkey, cipherkeylen);
- cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +
- cipherkeylen;
+
+ if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
+ temp_key = (uint32_t *)(cdesc->cd_cur_ptr +
+ sizeof(struct icp_qat_hw_cipher_config)
+ + cipherkeylen);
+ memcpy(cipher->aes.key, cipherkey, cipherkeylen);
+ memcpy(temp_key, cipherkey, cipherkeylen);
+
+ /* XOR Key with KASUMI F8 key modifier at 4 bytes level */
+ for (wordIndex = 0; wordIndex < (cipherkeylen >> 2);
+ wordIndex++)
+ temp_key[wordIndex] ^= KASUMI_F8
[dpdk-dev] [PATCH v2 2/4] app/test: add Kasumi f9 tests in QAT test suite
From: Deepak Kumar JAIN
This patch adds Kausmi f9 tests in the QAT tesuite and add
an additional test for Kasumi F9.
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev.c | 12 ++
app/test/test_cryptodev_kasumi_hash_test_vectors.h | 43 ++
2 files changed, 55 insertions(+)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 67ca912..a0dae4f 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -1967,6 +1967,12 @@ test_kasumi_hash_generate_test_case_5(void)
}
static int
+test_kasumi_hash_generate_test_case_6(void)
+{
+ return test_kasumi_authentication(&kasumi_hash_test_case_6);
+}
+
+static int
test_kasumi_hash_verify_test_case_1(void)
{
return test_kasumi_authentication_verify(&kasumi_hash_test_case_1);
@@ -4146,6 +4152,10 @@ static struct unit_test_suite cryptodev_qat_testsuite =
{
TEST_CASE_ST(ut_setup, ut_teardown,
test_null_auth_cipher_operation),
+ /** KASUMI F9 Authentication only **/
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_6),
+
TEST_CASES_END() /**< NULL terminate unit test array */
}
};
@@ -4247,6 +4257,8 @@ static struct unit_test_suite
cryptodev_sw_kasumi_testsuite = {
TEST_CASE_ST(ut_setup, ut_teardown,
test_kasumi_hash_generate_test_case_5),
TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
test_kasumi_hash_verify_test_case_1),
TEST_CASE_ST(ut_setup, ut_teardown,
test_kasumi_hash_verify_test_case_2),
diff --git a/app/test/test_cryptodev_kasumi_hash_test_vectors.h
b/app/test/test_cryptodev_kasumi_hash_test_vectors.h
index c080b9f..fc48355 100644
--- a/app/test/test_cryptodev_kasumi_hash_test_vectors.h
+++ b/app/test/test_cryptodev_kasumi_hash_test_vectors.h
@@ -257,4 +257,47 @@ struct kasumi_hash_test_data kasumi_hash_test_case_5 = {
.len = 4
}
};
+struct kasumi_hash_test_data kasumi_hash_test_case_6 = {
+ .key = {
+ .data = {
+ 0x83, 0xFD, 0x23, 0xA2, 0x44, 0xA7, 0x4C, 0xF3,
+ 0x58, 0xDA, 0x30, 0x19, 0xF1, 0x72, 0x26, 0x35
+ },
+ .len = 16
+ },
+ .aad = {
+ .data = {
+ 0x36, 0xAF, 0x61, 0x44, 0x4F, 0x30, 0x2A, 0xD2
+ },
+ .len = 8
+ },
+ .plaintext = {
+ .data = {
+ 0x35, 0xC6, 0x87, 0x16, 0x63, 0x3C, 0x66, 0xFB,
+ 0x75, 0x0C, 0x26, 0x68, 0x65, 0xD5, 0x3C, 0x11,
+ 0xEA, 0x05, 0xB1, 0xE9, 0xFA, 0x49, 0xC8, 0x39,
+ 0x8D, 0x48, 0xE1, 0xEF, 0xA5, 0x90, 0x9D, 0x39,
+ 0x47, 0x90, 0x28, 0x37, 0xF5, 0xAE, 0x96, 0xD5,
+ 0xA0, 0x5B, 0xC8, 0xD6, 0x1C, 0xA8, 0xDB, 0xEF,
+ 0x1B, 0x13, 0xA4, 0xB4, 0xAB, 0xFE, 0x4F, 0xB1,
+ 0x00, 0x60, 0x45, 0xB6, 0x74, 0xBB, 0x54, 0x72,
+ 0x93, 0x04, 0xC3, 0x82, 0xBE, 0x53, 0xA5, 0xAF,
+ 0x05, 0x55, 0x61, 0x76, 0xF6, 0xEA, 0xA2, 0xEF,
+ 0x1D, 0x05, 0xE4, 0xB0, 0x83, 0x18, 0x1E, 0xE6,
+ 0x74, 0xCD, 0xA5, 0xA4, 0x85, 0xF7, 0x4D, 0x7A,
+ 0xC0
+ },
+ .len = 776
+ },
+ .validAuthLenInBits = {
+ .len = 768
+ },
+ .validAuthOffsetLenInBits = {
+ .len = 64
+ },
+ .digest = {
+ .data = {0x95, 0xAE, 0x41, 0xBA},
+ .len = 4
+ }
+};
#endif /* TEST_CRYPTODEV_KASUMI_HASH_TEST_VECTORS_H_ */
--
2.5.5
[dpdk-dev] [PATCH v2 1/4] crypto/qat: enable Kasumi F9 support in QAT driver
From: Deepak Kumar JAIN The changes in this patch enables the Kasumi F9 functionality for Intel Quick Assist Technology Signed-off-by: Deepak Kumar Jain --- doc/guides/cryptodevs/qat.rst| 5 ++-- drivers/crypto/qat/qat_adf/qat_algs.h| 7 ++ drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 30 ++-- drivers/crypto/qat/qat_crypto.c | 30 +++- 4 files changed, 67 insertions(+), 5 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index f6091dd..6b73d95 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -63,17 +63,18 @@ Hash algorithms: * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2`` * ``RTE_CRYPTO_AUTH_MD5_HMAC`` * ``RTE_CRYPTO_AUTH_NULL`` +* ``RTE_CRYPTO_AUTH_KASUMI_F9`` Limitations --- * Chained mbufs are not supported. -* Hash only is not supported except Snow3G UIA2. +* Hash only is not supported except Snow3G UIA2 and KASUMI F9. * Cipher only is not supported except Snow3G UEA2. * Only supports the session-oriented API implementation (session-less APIs are not supported). * Not performance tuned. * Snow3g(UEA2) supported only if cipher length, cipher offset fields are byte-aligned. -* Snow3g(UIA2) supported only if hash length, hash offset fields are byte-aligned. +* Snow3g(UIA2) and KASUMI(F9) supported only if hash length, hash offset fields are byte-aligned. * No BSD support as BSD QAT kernel driver not available. diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h b/drivers/crypto/qat/qat_adf/qat_algs.h index 6a86053..0cc176f 100644 --- a/drivers/crypto/qat/qat_adf/qat_algs.h +++ b/drivers/crypto/qat/qat_adf/qat_algs.h @@ -51,6 +51,13 @@ #include "icp_qat_fw.h" #include "icp_qat_fw_la.h" +/* + * Key Modifier (KM) value used in Kasumi algorithm in F9 mode to XOR + * Integrity Key (IK) + */ +#define KASUMI_F9_KEY_MODIFIER_4_BYTES 0x + + #define QAT_AES_HW_CONFIG_CBC_ENC(alg) \ ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \ ICP_QAT_HW_CIPHER_NO_CONVERT, \ diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c index d9437bc..085a652 100644 --- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c +++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c @@ -96,6 +96,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg) case ICP_QAT_HW_AUTH_ALGO_MD5: return QAT_HW_ROUND_UP(ICP_QAT_HW_MD5_STATE1_SZ, QAT_HW_DEFAULT_ALIGNMENT); + case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9: + return QAT_HW_ROUND_UP(ICP_QAT_HW_KASUMI_F9_STATE1_SZ, + QAT_HW_DEFAULT_ALIGNMENT); case ICP_QAT_HW_AUTH_ALGO_DELIMITER: /* return maximum state1 size in this case */ return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ, @@ -559,6 +562,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc, uint16_t state1_size = 0, state2_size = 0; uint16_t hash_offset, cd_size; uint32_t *aad_len = NULL; + uint32_t wordIndex = 0; + uint32_t *pTempKey; PMD_INIT_FUNC_TRACE(); @@ -605,7 +610,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc, ICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE1, cdesc->qat_hash_alg, digestsize); - if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) + if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 + || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) hash->auth_counter.counter = 0; else hash->auth_counter.counter = rte_bswap32( @@ -722,12 +728,32 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc, break; case ICP_QAT_HW_AUTH_ALGO_NULL: break; + case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9: + state1_size = qat_hash_get_state1_size( + ICP_QAT_HW_AUTH_ALGO_KASUMI_F9); + state2_size = ICP_QAT_HW_KASUMI_F9_STATE2_SZ; + memset(cdesc->cd_cur_ptr, 0, state1_size + state2_size); + pTempKey = (uint32_t *)(cdesc->cd_cur_ptr + state1_size + + authkeylen); + /* + ** The Inner Hash Initial State2 block must contain IK + ** (Initialisation Key), followed by IK XOR-ed with KM + ** (Key Modifier): IK||(IK^KM). + **/ + /* write the auth key */ + memcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen); +
[dpdk-dev] [PATCH v2 0/4] add kasumi in Intel(R) QuickAssist driver
This patchset contains patches to enable kasumi cipher only and hash only functionality in Intel(R) QuickAsisst Technology Driver. This patchset depends on following patch: "crypto/qat: add NULL capability to Intel QAT driver" (http://dpdk.org/dev/patchwork/patch/15230/) Changes since V1: * Updated Test code to apply cleanly on driver code * Added relevant documentation Deepak Kumar JAIN (4): crypto/qat: enable Kasumi F9 support in QAT driver app/test: add Kasumi f9 tests in QAT test suite crypto/qat: enable support of Kasumi F8 in QAT cryptodev app/test: add kasumi f8 test into QAT testsuite app/test/test_cryptodev.c | 16 + app/test/test_cryptodev_kasumi_hash_test_vectors.h | 43 + doc/guides/cryptodevs/qat.rst | 10 +-- drivers/crypto/qat/qat_adf/qat_algs.h | 10 ++- drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 74 -- drivers/crypto/qat/qat_crypto.c| 69 ++-- 6 files changed, 207 insertions(+), 15 deletions(-) -- 2.5.5
[dpdk-dev] [PATCH v2] crypto/qat: add Intel QuickAssist C62x device
From: Deepak Kumar JAIN Signed-off-by: Deepak Kumar Jain --- Changes since V1: Removed trialing white spaces doc/guides/cryptodevs/qat.rst | 82 -- drivers/crypto/qat/rte_qat_cryptodev.c | 3 ++ 2 files changed, 81 insertions(+), 4 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index bb62f22..f6091dd 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -27,11 +27,12 @@ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -Quick Assist Crypto Poll Mode Driver +Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver The QAT PMD provides poll mode crypto driver support for **Intel QuickAssist -Technology DH895xxC** hardware accelerator. +Technology DH895xxC** and **Intel QuickAssist Technology C62x** +hardware accelerator. Features @@ -86,9 +87,13 @@ If you are running on kernel 4.4 or greater, see instructions for `Installation using kernel.org driver`_ below. If you are on a kernel earlier than 4.4, see `Installation using 01.org QAT driver`_. +For **Intel QuickAssist Technology C62x** device, kernel 4.5 or greater is +needed. See instructions for `instructions using kernel.org driver`_ below. + Installation using 01.org QAT driver +NOTE: There is no driver available for **Intel QuickAssist Technology C62x** on 01.org. Download the latest QuickAssist Technology Driver from `01.org <https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_ @@ -166,6 +171,7 @@ If the build or install fails due to mismatching kernel sources you may need to Installation using kernel.org driver +For **Intel QuickAssist Technology DH895xxC**: Assuming you are running on at least a 4.4 kernel, you can use the stock kernel.org QAT driver to start the QAT hardware. @@ -185,9 +191,9 @@ You should see the following output:: qat_dh895xcc5626 0 intel_qat 82336 1 qat_dh895xcc -Next, you need to expose the VFs using the sysfs file system. +Next, you need to expose the Virtual Functions (VFs) using the sysfs file system. -First find the bdf of the DH895xCC device:: +First find the bdf of the physical function (PF) of the DH895xCC device:: lspci -d : 435 @@ -225,10 +231,53 @@ cd to your linux source root directory and start the qat kernel modules: ``IOMMU should be enabled for SR-IOV to work correctly`` +For **Intel QuickAssist Technology C62x**: +Assuming you are running on at least a 4.5 kernel, you can use the stock kernel.org QAT +driver to start the QAT hardware. + +The steps below assume you are: + +* Running DPDK on a platform with one ``C62x`` device. +* On a kernel at least version 4.5. + +In BIOS ensure that SRIOV is enabled and VT-d is disabled. + +Ensure the QAT driver is loaded on your system, by executing:: + +lsmod | grep qat + +You should see the following output:: + +qat_c62x 16384 0 +intel_qat 122880 1 qat_c62x + +Next, you need to expose the VFs using the sysfs file system. + +First find the bdf of the C62x device:: + +lspci -d:37c8 + +You should see output similar to:: + +1a:00.0 Co-processor: Intel Corporation Device 37c8 +3d:00.0 Co-processor: Intel Corporation Device 37c8 +3f:00.0 Co-processor: Intel Corporation Device 37c8 + +For each c62x device there are 3 PFs. +Using the sysfs, for each PF, enable the 16 VFs:: + +echo 16 > /sys/bus/pci/drivers/c6xx/\:1a\:00.0/sriov_numvfs + +If you get an error, it's likely you're using a QAT kernel driver earlier than kernel 4.5. +To verify that the VFs are available for use - use ``lspci -d:37c9`` to confirm +the bdf of the 48 VF devices are available per ``C62x`` device. + +To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_. Binding the available VFs to the DPDK UIO driver +For **Intel(R) QuickAssist Technology DH895xcc** device: The unbind command below assumes ``bdfs`` of ``03:01.00-03:04.07``, if yours are different adjust the unbind command below:: cd $RTE_SDK @@ -245,3 +294,28 @@ The unbind command below assumes ``bdfs`` of ``03:01.00-03:04.07``, if yours are echo "8086 0443" > /sys/bus/pci/drivers/igb_uio/new_id You can use ``lspci -vvd:443`` to confirm that all devices are now in use by igb_uio kernel driver. + +For **Intel(R) QuickAssist Technology C62x** device: +The unbind command below assumes ``bdfs`` of ``1a:01.00-1a:02.07``, ``3d:01.00-3d:02.07`` and ``3f:01.00-3f:02.07``, +if yours are different adjust the unbind command below:: + + cd $RTE_SDK + modprobe uio + insmod ./build/kmod/igb_uio.ko + + for device in
[dpdk-dev] [PATCH 4/4] app/test: add kasumi f8 test into QAT testsuite
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 9cf4504..fdcdbeb 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -4145,6 +4145,11 @@ static struct unit_test_suite cryptodev_qat_testsuite =
{
/** KASUMI F9 Authentication only **/
TEST_CASE_ST(ut_setup, ut_teardown,
test_kasumi_hash_generate_test_case_6),
+
+ /** KASUMI encrypt only (F8) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_1),
+
TEST_CASES_END() /**< NULL terminate unit test array */
}
};
--
2.5.5
[dpdk-dev] [PATCH 3/4] crypto/qat: enable support of Kasumi F8 in QAT cryptodev
This patch enables the support of Kasumi F8
for Intel Quick Assist Technology.
Signed-off-by: Deepak Kumar Jain
---
drivers/crypto/qat/qat_adf/qat_algs.h| 3 +-
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 44 +---
drivers/crypto/qat/qat_crypto.c | 39 +++--
3 files changed, 78 insertions(+), 8 deletions(-)
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index 0cc176f..fad8471 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -57,6 +57,7 @@
*/
#define KASUMI_F9_KEY_MODIFIER_4_BYTES 0x
+#define KASUMI_F8_KEY_MODIFIER_4_BYTES 0x
#define QAT_AES_HW_CONFIG_CBC_ENC(alg) \
ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \
@@ -137,5 +138,5 @@ void qat_alg_ablkcipher_init_dec(struct
qat_alg_ablkcipher_cd *cd,
int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
-
+int qat_alg_validate_kasumi_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
#endif
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 085a652..9d1df56 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -457,7 +457,8 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
uint32_t total_key_size;
uint16_t proto = ICP_QAT_FW_LA_NO_PROTO;/* no CCM/GCM/Snow3G */
uint16_t cipher_offset, cd_size;
-
+ uint32_t wordIndex = 0;
+ uint32_t *temp_key = NULL;
PMD_INIT_FUNC_TRACE();
if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
@@ -507,6 +508,11 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
cipher_cd_ctrl->cipher_state_sz =
ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ >> 3;
proto = ICP_QAT_FW_LA_SNOW_3G_PROTO;
+ } else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
+ total_key_size = ICP_QAT_HW_KASUMI_F8_KEY_SZ;
+ cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_KASUMI_BLK_SZ >> 3;
+ cipher_cd_ctrl->cipher_padding_sz =
+ (2 * ICP_QAT_HW_KASUMI_BLK_SZ) >> 3;
} else {
total_key_size = cipherkeylen;
cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;
@@ -524,9 +530,27 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
ICP_QAT_HW_CIPHER_CONFIG_BUILD(cdesc->qat_mode,
cdesc->qat_cipher_alg, key_convert,
cdesc->qat_dir);
- memcpy(cipher->aes.key, cipherkey, cipherkeylen);
- cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +
- cipherkeylen;
+
+ if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
+ temp_key = (uint32_t *)(cdesc->cd_cur_ptr +
+ sizeof(struct icp_qat_hw_cipher_config)
+ + cipherkeylen);
+ memcpy(cipher->aes.key, cipherkey, cipherkeylen);
+ memcpy(temp_key, cipherkey, cipherkeylen);
+
+ /* XOR Key with KASUMI F8 key modifier at 4 bytes level */
+ for (wordIndex = 0; wordIndex < (cipherkeylen >> 2);
+ wordIndex++)
+ temp_key[wordIndex] ^= KASUMI_F8_KEY_MODIFIER_4_BYTES;
+
+ cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +
+ cipherkeylen + cipherkeylen;
+ } else {
+ memcpy(cipher->aes.key, cipherkey, cipherkeylen);
+ cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +
+ cipherkeylen;
+ }
+
if (total_key_size > cipherkeylen) {
uint32_t padding_size = total_key_size-cipherkeylen;
@@ -859,3 +883,15 @@ int qat_alg_validate_snow3g_key(int key_len, enum
icp_qat_hw_cipher_algo *alg)
}
return 0;
}
+
+int qat_alg_validate_kasumi_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
+{
+ switch (key_len) {
+ case ICP_QAT_HW_KASUMI_KEY_SZ:
+ *alg = ICP_QAT_HW_CIPHER_ALGO_KASUMI;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 1de95f1..1282312 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@
[dpdk-dev] [PATCH 2/4] app/test: add Kasumi f9 tests in QAT test suite
This patch adds Kausmi f9 tests in the QAT tesuite and add
an additional test for Kasumi F9.
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev.c | 11 ++
app/test/test_cryptodev_kasumi_hash_test_vectors.h | 43 ++
2 files changed, 54 insertions(+)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 8553759..9cf4504 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -1967,6 +1967,12 @@ test_kasumi_hash_generate_test_case_5(void)
}
static int
+test_kasumi_hash_generate_test_case_6(void)
+{
+ return test_kasumi_authentication(&kasumi_hash_test_case_6);
+}
+
+static int
test_kasumi_hash_verify_test_case_1(void)
{
return test_kasumi_authentication_verify(&kasumi_hash_test_case_1);
@@ -4136,6 +4142,9 @@ static struct unit_test_suite cryptodev_qat_testsuite = {
TEST_CASE_ST(ut_setup, ut_teardown,
test_MD5_HMAC_verify_case_2),
+ /** KASUMI F9 Authentication only **/
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_6),
TEST_CASES_END() /**< NULL terminate unit test array */
}
};
@@ -4237,6 +4246,8 @@ static struct unit_test_suite
cryptodev_sw_kasumi_testsuite = {
TEST_CASE_ST(ut_setup, ut_teardown,
test_kasumi_hash_generate_test_case_5),
TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
test_kasumi_hash_verify_test_case_1),
TEST_CASE_ST(ut_setup, ut_teardown,
test_kasumi_hash_verify_test_case_2),
diff --git a/app/test/test_cryptodev_kasumi_hash_test_vectors.h
b/app/test/test_cryptodev_kasumi_hash_test_vectors.h
index c080b9f..fc48355 100644
--- a/app/test/test_cryptodev_kasumi_hash_test_vectors.h
+++ b/app/test/test_cryptodev_kasumi_hash_test_vectors.h
@@ -257,4 +257,47 @@ struct kasumi_hash_test_data kasumi_hash_test_case_5 = {
.len = 4
}
};
+struct kasumi_hash_test_data kasumi_hash_test_case_6 = {
+ .key = {
+ .data = {
+ 0x83, 0xFD, 0x23, 0xA2, 0x44, 0xA7, 0x4C, 0xF3,
+ 0x58, 0xDA, 0x30, 0x19, 0xF1, 0x72, 0x26, 0x35
+ },
+ .len = 16
+ },
+ .aad = {
+ .data = {
+ 0x36, 0xAF, 0x61, 0x44, 0x4F, 0x30, 0x2A, 0xD2
+ },
+ .len = 8
+ },
+ .plaintext = {
+ .data = {
+ 0x35, 0xC6, 0x87, 0x16, 0x63, 0x3C, 0x66, 0xFB,
+ 0x75, 0x0C, 0x26, 0x68, 0x65, 0xD5, 0x3C, 0x11,
+ 0xEA, 0x05, 0xB1, 0xE9, 0xFA, 0x49, 0xC8, 0x39,
+ 0x8D, 0x48, 0xE1, 0xEF, 0xA5, 0x90, 0x9D, 0x39,
+ 0x47, 0x90, 0x28, 0x37, 0xF5, 0xAE, 0x96, 0xD5,
+ 0xA0, 0x5B, 0xC8, 0xD6, 0x1C, 0xA8, 0xDB, 0xEF,
+ 0x1B, 0x13, 0xA4, 0xB4, 0xAB, 0xFE, 0x4F, 0xB1,
+ 0x00, 0x60, 0x45, 0xB6, 0x74, 0xBB, 0x54, 0x72,
+ 0x93, 0x04, 0xC3, 0x82, 0xBE, 0x53, 0xA5, 0xAF,
+ 0x05, 0x55, 0x61, 0x76, 0xF6, 0xEA, 0xA2, 0xEF,
+ 0x1D, 0x05, 0xE4, 0xB0, 0x83, 0x18, 0x1E, 0xE6,
+ 0x74, 0xCD, 0xA5, 0xA4, 0x85, 0xF7, 0x4D, 0x7A,
+ 0xC0
+ },
+ .len = 776
+ },
+ .validAuthLenInBits = {
+ .len = 768
+ },
+ .validAuthOffsetLenInBits = {
+ .len = 64
+ },
+ .digest = {
+ .data = {0x95, 0xAE, 0x41, 0xBA},
+ .len = 4
+ }
+};
#endif /* TEST_CRYPTODEV_KASUMI_HASH_TEST_VECTORS_H_ */
--
2.5.5
[dpdk-dev] [PATCH 1/4] crypto/qat: enable Kasumi F9 support in QAT driver
The changes in this patch enables the Kasumi F9 functionality
for Intel Quick Assist Technology
Signed-off-by: Deepak Kumar Jain
---
drivers/crypto/qat/qat_adf/qat_algs.h| 7 ++
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 30 ++--
drivers/crypto/qat/qat_crypto.c | 30 +++-
3 files changed, 64 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index 6a86053..0cc176f 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -51,6 +51,13 @@
#include "icp_qat_fw.h"
#include "icp_qat_fw_la.h"
+/*
+ * Key Modifier (KM) value used in Kasumi algorithm in F9 mode to XOR
+ * Integrity Key (IK)
+ */
+#define KASUMI_F9_KEY_MODIFIER_4_BYTES 0x
+
+
#define QAT_AES_HW_CONFIG_CBC_ENC(alg) \
ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \
ICP_QAT_HW_CIPHER_NO_CONVERT, \
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index d9437bc..085a652 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -96,6 +96,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo
qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_MD5:
return QAT_HW_ROUND_UP(ICP_QAT_HW_MD5_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
+ case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
+ return QAT_HW_ROUND_UP(ICP_QAT_HW_KASUMI_F9_STATE1_SZ,
+ QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum state1 size in this case */
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
@@ -559,6 +562,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
uint16_t state1_size = 0, state2_size = 0;
uint16_t hash_offset, cd_size;
uint32_t *aad_len = NULL;
+ uint32_t wordIndex = 0;
+ uint32_t *pTempKey;
PMD_INIT_FUNC_TRACE();
@@ -605,7 +610,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
ICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE1,
cdesc->qat_hash_alg, digestsize);
- if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2)
+ if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2
+ || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9)
hash->auth_counter.counter = 0;
else
hash->auth_counter.counter = rte_bswap32(
@@ -722,12 +728,32 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
break;
case ICP_QAT_HW_AUTH_ALGO_NULL:
break;
+ case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
+ state1_size = qat_hash_get_state1_size(
+ ICP_QAT_HW_AUTH_ALGO_KASUMI_F9);
+ state2_size = ICP_QAT_HW_KASUMI_F9_STATE2_SZ;
+ memset(cdesc->cd_cur_ptr, 0, state1_size + state2_size);
+ pTempKey = (uint32_t *)(cdesc->cd_cur_ptr + state1_size
+ + authkeylen);
+ /*
+ ** The Inner Hash Initial State2 block must contain IK
+ ** (Initialisation Key), followed by IK XOR-ed with KM
+ ** (Key Modifier): IK||(IK^KM).
+ **/
+ /* write the auth key */
+ memcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen);
+ /* initialise temp key with auth key */
+ memcpy(pTempKey, authkey, authkeylen);
+ /* XOR Key with KASUMI F9 key modifier at 4 bytes level */
+ for (wordIndex = 0; wordIndex < (authkeylen >> 2); wordIndex++)
+ pTempKey[wordIndex] ^= KASUMI_F9_KEY_MODIFIER_4_BYTES;
+ break;
default:
PMD_DRV_LOG(ERR, "Invalid HASH alg %u", cdesc->qat_hash_alg);
return -EFAULT;
}
- /* Request template setup */
+ /* Request templat setup */
qat_alg_init_common_hdr(header, proto);
header->service_cmd_id = cdesc->qat_cmd;
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 434ff81..1de95f1 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -304,6 +304,26 @@ static const struct rte_cryptodev_capabilities
qat_pmd_capabilities[] = {
}, }
}, }
},
+ { /* SNOW3G (UEA2) */
+ .op = RTE_CRYPTO_OP_TY
[dpdk-dev] [PATCH 0/4] add kasumi in Intel(R) QuickAssist driver
This patchset contains patches to enable kasumi cipher only and hash only functionality in Intel(R) QuickAsisst Technology Driver. This patchset depends on following patch: "crypto/qat: add NULL capability to Intel QAT driver" (http://dpdk.org/dev/patchwork/patch/15230/) Deepak Kumar Jain (4): crypto/qat: enable Kasumi F9 support in QAT driver app/test: add Kasumi f9 tests in QAT test suite crypto/qat: enable support of Kasumi F8 in QAT cryptodev app/test: add kasumi f8 test into QAT testsuite app/test/test_cryptodev.c | 16 + app/test/test_cryptodev_kasumi_hash_test_vectors.h | 43 + drivers/crypto/qat/qat_adf/qat_algs.h | 10 ++- drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 74 -- drivers/crypto/qat/qat_crypto.c| 69 ++-- 5 files changed, 201 insertions(+), 11 deletions(-) -- 2.5.5
[dpdk-dev] [PATCH] crypto/qat: add Intel QuickAssist C62x device
Signed-off-by: Deepak Kumar Jain --- doc/guides/cryptodevs/qat.rst | 82 -- drivers/crypto/qat/rte_qat_cryptodev.c | 3 ++ 2 files changed, 81 insertions(+), 4 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index af66569..f6cc1fa 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -27,11 +27,12 @@ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -Quick Assist Crypto Poll Mode Driver +Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver The QAT PMD provides poll mode crypto driver support for **Intel QuickAssist -Technology DH895xxC** hardware accelerator. +Technology DH895xxC** and **Intel QuickAssist Technology C62x** +hardware accelerator. Features @@ -88,9 +89,13 @@ If you are running on kernel 4.4 or greater, see instructions for `Installation using kernel.org driver`_ below. If you are on a kernel earlier than 4.4, see `Installation using 01.org QAT driver`_. +For **Intel QuickAssist Technology C62x** device, kernel 4.5 or greater is +needed. See instructions for `instructions using kernel.org driver`_ below. + Installation using 01.org QAT driver +NOTE: There is no driver available for **Intel QuickAssist Technology C62x** on 01.org. Download the latest QuickAssist Technology Driver from `01.org <https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_ @@ -168,6 +173,7 @@ If the build or install fails due to mismatching kernel sources you may need to Installation using kernel.org driver +For **Intel QuickAssist Technology DH895xxC**: Assuming you are running on at least a 4.4 kernel, you can use the stock kernel.org QAT driver to start the QAT hardware. @@ -187,9 +193,9 @@ You should see the following output:: qat_dh895xcc5626 0 intel_qat 82336 1 qat_dh895xcc -Next, you need to expose the VFs using the sysfs file system. +Next, you need to expose the Virtual Functions (VFs) using the sysfs file system. -First find the bdf of the DH895xCC device:: +First find the bdf of the physical function (PF) of the DH895xCC device:: lspci -d : 435 @@ -227,10 +233,53 @@ cd to your linux source root directory and start the qat kernel modules: ``IOMMU should be enabled for SR-IOV to work correctly`` +For **Intel QuickAssist Technology C62x**: +Assuming you are running on at least a 4.5 kernel, you can use the stock kernel.org QAT +driver to start the QAT hardware. + +The steps below assume you are: + +* Running DPDK on a platform with one ``C62x`` device. +* On a kernel at least version 4.5. + +In BIOS ensure that SRIOV is enabled and VT-d is disabled. + +Ensure the QAT driver is loaded on your system, by executing:: + +lsmod | grep qat + +You should see the following output:: + +qat_c62x 16384 0 +intel_qat 122880 1 qat_c62x + +Next, you need to expose the VFs using the sysfs file system. + +First find the bdf of the C62x device:: + +lspci -d:37c8 +You should see output similar to:: + +1a:00.0 Co-processor: Intel Corporation Device 37c8 +3d:00.0 Co-processor: Intel Corporation Device 37c8 +3f:00.0 Co-processor: Intel Corporation Device 37c8 + +For each c62x device there are 3 PFs. +Using the sysfs, for each PF, enable the 16 VFs:: + +echo 16 > /sys/bus/pci/drivers/c6xx/\:1a\:00.0/sriov_numvfs + +If you get an error, it's likely you're using a QAT kernel driver earlier than kernel 4.5. + +To verify that the VFs are available for use - use ``lspci -d:37c9`` to confirm +the bdf of the 48 VF devices are available per ``C62x`` device. + +To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_. Binding the available VFs to the DPDK UIO driver +For **Intel(R) QuickAssist Technology DH895xcc** device: The unbind command below assumes ``bdfs`` of ``03:01.00-03:04.07``, if yours are different adjust the unbind command below:: cd $RTE_SDK @@ -247,3 +296,28 @@ The unbind command below assumes ``bdfs`` of ``03:01.00-03:04.07``, if yours are echo "8086 0443" > /sys/bus/pci/drivers/igb_uio/new_id You can use ``lspci -vvd:443`` to confirm that all devices are now in use by igb_uio kernel driver. + +For **Intel(R) QuickAssist Technology C62x** device: +The unbind command below assumes ``bdfs`` of ``1a:01.00-1a:02.07``, ``3d:01.00-3d:02.07`` and ``3f:01.00-3f:02.07``, +if yours are different adjust the unbind command below:: + + cd $RTE_SDK + modprobe uio + insmod ./build/kmod/igb_uio.ko + + for device in $(seq 1 2); do \ + for fn in $(seq 0 7); do \ +
[dpdk-dev] [PATCH 2/2] app/test: add test cases for NULL for Intel QAT driver
Added NULL algorithm to test file for Intel(R) QuickAssist
Technology Driver
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 8553759..67ca912 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -4136,6 +4136,16 @@ static struct unit_test_suite cryptodev_qat_testsuite =
{
TEST_CASE_ST(ut_setup, ut_teardown,
test_MD5_HMAC_verify_case_2),
+ /** NULL tests */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_auth_only_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_cipher_only_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_cipher_auth_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_auth_cipher_operation),
+
TEST_CASES_END() /**< NULL terminate unit test array */
}
};
--
2.5.5
[dpdk-dev] [PATCH 1/2] crypto/qat: add NULL capability to Intel QAT driver
enabled NULL crypto for Intel(R) QuickAssist Technology Signed-off-by: Deepak Kumar Jain --- doc/guides/cryptodevs/qat.rst| 3 ++- drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++ drivers/crypto/qat/qat_crypto.c | 4 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 78a734f..bb62f22 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -49,6 +49,7 @@ Cipher algorithms: * ``RTE_CRYPTO_SYM_CIPHER_AES256_CTR`` * ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2`` * ``RTE_CRYPTO_CIPHER_AES_GCM`` +* ``RTE_CRYPTO_CIPHER_NULL`` Hash algorithms: @@ -60,7 +61,7 @@ Hash algorithms: * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC`` * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2`` * ``RTE_CRYPTO_AUTH_MD5_HMAC`` - +* ``RTE_CRYPTO_AUTH_NULL`` Limitations --- diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c index af8c176..d9437bc 100644 --- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c +++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c @@ -720,6 +720,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc, } state2_size = ICP_QAT_HW_MD5_STATE2_SZ; break; + case ICP_QAT_HW_AUTH_ALGO_NULL: + break; default: PMD_DRV_LOG(ERR, "Invalid HASH alg %u", cdesc->qat_hash_alg); return -EFAULT; diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c index a474512..434ff81 100644 --- a/drivers/crypto/qat/qat_crypto.c +++ b/drivers/crypto/qat/qat_crypto.c @@ -427,6 +427,8 @@ qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev, session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE; break; case RTE_CRYPTO_CIPHER_NULL: + session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE; + break; case RTE_CRYPTO_CIPHER_3DES_ECB: case RTE_CRYPTO_CIPHER_3DES_CBC: case RTE_CRYPTO_CIPHER_AES_ECB: @@ -558,6 +560,8 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev, session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5; break; case RTE_CRYPTO_AUTH_NULL: + session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL; + break; case RTE_CRYPTO_AUTH_SHA1: case RTE_CRYPTO_AUTH_SHA256: case RTE_CRYPTO_AUTH_SHA512: -- 2.5.5
[dpdk-dev] [PATCH 0/2] add NULL crypto support in Intel QAT driver
This patchset adds support of NULL crypto in Intel(R) QuickAssist Technology driver. This patchset depends on following patchset: "crypto/qat: add aes-sha384-hmac capability to Intel QAT driver" (http://dpdk.org/dev/patchwork/patch/15228/) Deepak Kumar Jain (2): crypto/qat: add NULL capability to Intel QAT driver app/test: add test cases for NULL for Intel QAT driver app/test/test_cryptodev.c| 10 ++ doc/guides/cryptodevs/qat.rst| 3 ++- drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++ drivers/crypto/qat/qat_crypto.c | 4 4 files changed, 18 insertions(+), 1 deletion(-) -- 2.5.5
[dpdk-dev] [PATCH 2/2] app/test: add test cases for aes-sha384-hmac for Intel QAT driver
From: "Jain, Deepak K"
Added aes-sha384-hmac algorithm to test file for Intel(R) QuickAssist
Technology Driver
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev_aes.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/app/test/test_cryptodev_aes.c b/app/test/test_cryptodev_aes.c
index 6ad2674..e19c45b 100644
--- a/app/test/test_cryptodev_aes.c
+++ b/app/test/test_cryptodev_aes.c
@@ -226,14 +226,16 @@ static const struct aes_test_case aes_test_cases[] = {
.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
.test_data = &aes_test_data_9,
.op_mask = AES_TEST_OP_ENC_AUTH_GEN,
- .pmd_mask = AES_TEST_TARGET_PMD_MB
+ .pmd_mask = AES_TEST_TARGET_PMD_MB |
+ AES_TEST_TARGET_PMD_QAT
},
{
.test_descr = "AES-128-CBC HMAC-SHA384 Decryption Digest "
"Verify",
.test_data = &aes_test_data_9,
.op_mask = AES_TEST_OP_AUTH_VERIFY_DEC,
- .pmd_mask = AES_TEST_TARGET_PMD_MB
+ .pmd_mask = AES_TEST_TARGET_PMD_MB |
+ AES_TEST_TARGET_PMD_QAT
},
};
--
2.5.5
[dpdk-dev] [PATCH 1/2] crypto/qat: add aes-sha384-hmac capability to Intel QAT driver
From: "Jain, Deepak K"
enabled support of aes-sha384-hmac in Intel(R) QuickAssist driver
Signed-off-by: Deepak Kumar Jain
---
doc/guides/cryptodevs/qat.rst| 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33
drivers/crypto/qat/qat_crypto.c | 10 ---
3 files changed, 40 insertions(+), 4 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 7f630be..78a734f 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -55,6 +55,7 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 77e6548..af8c176 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -77,6 +77,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo
qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA256_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
+ case ICP_QAT_HW_AUTH_ALGO_SHA384:
+ return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA384_STATE1_SZ,
+ QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_SHA512:
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
@@ -114,6 +117,8 @@ static int qat_hash_get_digest_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
return ICP_QAT_HW_SHA224_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return ICP_QAT_HW_SHA256_STATE1_SZ;
+ case ICP_QAT_HW_AUTH_ALGO_SHA384:
+ return ICP_QAT_HW_SHA384_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
return ICP_QAT_HW_SHA512_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_MD5:
@@ -138,6 +143,8 @@ static int qat_hash_get_block_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
return SHA256_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return SHA256_CBLOCK;
+ case ICP_QAT_HW_AUTH_ALGO_SHA384:
+ return SHA512_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
return SHA512_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
@@ -187,6 +194,17 @@ static int partial_hash_sha256(uint8_t *data_in, uint8_t
*data_out)
return 0;
}
+static int partial_hash_sha384(uint8_t *data_in, uint8_t *data_out)
+{
+ SHA512_CTX ctx;
+
+ if (!SHA384_Init(&ctx))
+ return -EFAULT;
+ SHA512_Transform(&ctx, data_in);
+ rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
+ return 0;
+}
+
static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)
{
SHA512_CTX ctx;
@@ -252,6 +270,13 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo
hash_alg,
*hash_state_out_be32 =
rte_bswap32(*(((uint32_t *)digest)+i));
break;
+ case ICP_QAT_HW_AUTH_ALGO_SHA384:
+ if (partial_hash_sha384(data_in, digest))
+ return -EFAULT;
+ for (i = 0; i < digest_size >> 3; i++, hash_state_out_be64++)
+ *hash_state_out_be64 =
+ rte_bswap64(*(((uint64_t *)digest)+i));
+ break;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
if (partial_hash_sha512(data_in, digest))
return -EFAULT;
@@ -616,6 +641,14 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
}
state2_size = ICP_QAT_HW_SHA256_STATE2_SZ;
break;
+ case ICP_QAT_HW_AUTH_ALGO_SHA384:
+ if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384,
+ authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ PMD_DRV_LOG(ERR, "(SHA)precompute failed");
+ return -EFAULT;
+ }
+ state2_size = ICP_QAT_HW_SHA384_STATE2_SZ;
+ break;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512,
authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index e872759..a474512 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -533,15 +533,18 @@ qat_crypto_sym_configure_session_auth(struct
rte_cryptodev *dev,
[dpdk-dev] [PATCH 0/2] add aes-sha384-hmac support to Intel QAT driver
This patchset adds support of aes-sha384-hmac in Intel(R) QuickAssist Technology driver. This patchset depends on following patchset: "crypto/qat: add aes-sha224-hmac capability to Intel QAT driver" (http://dpdk.org/dev/patchwork/patch/15226/) Jain, Deepak K (2): crypto/qat: add aes-sha384-hmac capability to Intel QAT driver app/test: add test cases for aes-sha384-hmac for Intel QAT driver app/test/test_cryptodev_aes.c| 6 +++-- doc/guides/cryptodevs/qat.rst| 1 + drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 drivers/crypto/qat/qat_crypto.c | 10 --- 4 files changed, 44 insertions(+), 6 deletions(-) -- 2.5.5
[dpdk-dev] [PATCH 2/2] app/test: add test cases for aes-sha224-hmac for Intel QAT driver
From: "Jain, Deepak K"
Added aes-sha224-hmac algorithm to test file for Intel(R) QuickAssist
Technology Driver
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev_aes.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/app/test/test_cryptodev_aes.c b/app/test/test_cryptodev_aes.c
index bf832b6..6ad2674 100644
--- a/app/test/test_cryptodev_aes.c
+++ b/app/test/test_cryptodev_aes.c
@@ -211,14 +211,16 @@ static const struct aes_test_case aes_test_cases[] = {
.test_descr = "AES-128-CBC HMAC-SHA224 Encryption Digest",
.test_data = &aes_test_data_8,
.op_mask = AES_TEST_OP_ENC_AUTH_GEN,
- .pmd_mask = AES_TEST_TARGET_PMD_MB
+ .pmd_mask = AES_TEST_TARGET_PMD_MB |
+ AES_TEST_TARGET_PMD_QAT
},
{
.test_descr = "AES-128-CBC HMAC-SHA224 Decryption Digest "
"Verify",
.test_data = &aes_test_data_8,
.op_mask = AES_TEST_OP_AUTH_VERIFY_DEC,
- .pmd_mask = AES_TEST_TARGET_PMD_MB
+ .pmd_mask = AES_TEST_TARGET_PMD_MB |
+ AES_TEST_TARGET_PMD_QAT
},
{
.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
--
2.5.5
[dpdk-dev] [PATCH 1/2] crypto/qat: add aes-sha224-hmac capability to Intel QAT driver
From: "Jain, Deepak K"
Added support of aes-sha224-hmac in Intel(R) QuickAssist driver
Signed-off-by: Deepak Kumar Jain
---
doc/guides/cryptodevs/qat.rst| 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33
drivers/crypto/qat/qat_crypto.c | 4 ++-
3 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 485abb4..7f630be 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -53,6 +53,7 @@ Cipher algorithms:
Hash algorithms:
* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 521a9c4..77e6548 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -71,6 +71,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo
qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_SHA1:
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA1_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA224_STATE1_SZ,
+ QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA256_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
@@ -107,6 +110,8 @@ static int qat_hash_get_digest_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
switch (qat_hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SHA1:
return ICP_QAT_HW_SHA1_STATE1_SZ;
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ return ICP_QAT_HW_SHA224_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return ICP_QAT_HW_SHA256_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
@@ -129,6 +134,8 @@ static int qat_hash_get_block_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
switch (qat_hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SHA1:
return SHA_CBLOCK;
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ return SHA256_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
return SHA256_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
@@ -158,6 +165,17 @@ static int partial_hash_sha1(uint8_t *data_in, uint8_t
*data_out)
return 0;
}
+static int partial_hash_sha224(uint8_t *data_in, uint8_t *data_out)
+{
+ SHA256_CTX ctx;
+
+ if (!SHA224_Init(&ctx))
+ return -EFAULT;
+ SHA256_Transform(&ctx, data_in);
+ rte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);
+ return 0;
+}
+
static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)
{
SHA256_CTX ctx;
@@ -220,6 +238,13 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo
hash_alg,
*hash_state_out_be32 =
rte_bswap32(*(((uint32_t *)digest)+i));
break;
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ if (partial_hash_sha224(data_in, digest))
+ return -EFAULT;
+ for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
+ *hash_state_out_be32 =
+ rte_bswap32(*(((uint32_t *)digest)+i));
+ break;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
if (partial_hash_sha256(data_in, digest))
return -EFAULT;
@@ -575,6 +600,14 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
}
state2_size = RTE_ALIGN_CEIL(ICP_QAT_HW_SHA1_STATE2_SZ, 8);
break;
+ case ICP_QAT_HW_AUTH_ALGO_SHA224:
+ if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224,
+ authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ PMD_DRV_LOG(ERR, "(SHA)precompute failed");
+ return -EFAULT;
+ }
+ state2_size = ICP_QAT_HW_SHA224_STATE2_SZ;
+ break;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256,
authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index b9558d0..e872759 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -539,6 +539,9 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev
*dev,
case RTE_CRYPTO_AUTH_SHA512_HMAC:
session->qat_hash_alg = ICP_QA
[dpdk-dev] [PATCH 0/2] add aes-sha224-hmac support to Intel QAT driver
This patchset adds support of aes-sha224-hmac in Intel(R) QuickAssist Technology driver. This patchset depends on following patchset: "crypto/qat: add MD5 HMAC capability to Intel QAT driver" (http://dpdk.org/dev/patchwork/patch/15165/) Jain, Deepak K (2): crypto/qat: add aes-sha224-hmac capability to Intel QAT driver app/test: add test cases for aes-sha224-hmac for Intel QAT driver app/test/test_cryptodev_aes.c| 6 +++-- doc/guides/cryptodevs/qat.rst| 1 + drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 drivers/crypto/qat/qat_crypto.c | 4 ++- 4 files changed, 41 insertions(+), 3 deletions(-) -- 2.5.5
[dpdk-dev] [PATCH v2] app/test: fix hexdump length of cipher/plaintexts
From: Pablo de Lara
Plaintexts and ciphertexts are dumped when debugging is enabled,
using TEST_HEXDUMP. For Snow3G and KASUMI, their lengths are in bits,
but TEST_HEXDUMP uses bytes, so lenghts are passed in bytes now.
Fixes: 47df73a1a62f ("app/test: use hexdump if debug log is enabled")
Signed-off-by: Pablo de Lara
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index dac3b93..33325a8 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -2295,7 +2295,7 @@ test_snow3g_encryption(const struct snow3g_test_data
*tdata)
plaintext_pad_len);
memcpy(plaintext, tdata->plaintext.data, plaintext_len);
- TEST_HEXDUMP(stdout, "plaintext:", plaintext, tdata->plaintext.len);
+ TEST_HEXDUMP(stdout, "plaintext:", plaintext, plaintext_len);
/* Create SNOW3G operation */
retval = create_snow3g_kasumi_cipher_operation(tdata->iv.data,
tdata->iv.len,
@@ -2316,7 +2316,7 @@ test_snow3g_encryption(const struct snow3g_test_data
*tdata)
else
ciphertext = plaintext;
- TEST_HEXDUMP(stdout, "ciphertext:", ciphertext, tdata->ciphertext.len);
+ TEST_HEXDUMP(stdout, "ciphertext:", ciphertext, plaintext_len);
/* Validate obuf */
TEST_ASSERT_BUFFERS_ARE_EQUAL_BIT(
@@ -2368,7 +2368,7 @@ test_snow3g_encryption_oop(const struct snow3g_test_data
*tdata)
rte_pktmbuf_append(ut_params->obuf, plaintext_pad_len);
memcpy(plaintext, tdata->plaintext.data, plaintext_len);
- TEST_HEXDUMP(stdout, "plaintext:", plaintext, tdata->plaintext.len);
+ TEST_HEXDUMP(stdout, "plaintext:", plaintext, plaintext_len);
/* Create SNOW3G operation */
retval = create_snow3g_kasumi_cipher_operation_oop(tdata->iv.data,
@@ -2390,7 +2390,7 @@ test_snow3g_encryption_oop(const struct snow3g_test_data
*tdata)
else
ciphertext = plaintext;
- TEST_HEXDUMP(stdout, "ciphertext:", ciphertext, tdata->ciphertext.len);
+ TEST_HEXDUMP(stdout, "ciphertext:", ciphertext, plaintext_len);
/* Validate obuf */
TEST_ASSERT_BUFFERS_ARE_EQUAL_BIT(
@@ -2549,7 +2549,7 @@ static int test_snow3g_decryption(const struct
snow3g_test_data *tdata)
ciphertext_pad_len);
memcpy(ciphertext, tdata->ciphertext.data, ciphertext_len);
- TEST_HEXDUMP(stdout, "ciphertext:", ciphertext, tdata->ciphertext.len);
+ TEST_HEXDUMP(stdout, "ciphertext:", ciphertext, ciphertext_len);
/* Create SNOW3G operation */
retval = create_snow3g_kasumi_cipher_operation(tdata->iv.data,
tdata->iv.len,
@@ -2569,7 +2569,7 @@ static int test_snow3g_decryption(const struct
snow3g_test_data *tdata)
else
plaintext = ciphertext;
- TEST_HEXDUMP(stdout, "plaintext:", plaintext, tdata->plaintext.len);
+ TEST_HEXDUMP(stdout, "plaintext:", plaintext, ciphertext_len);
/* Validate obuf */
TEST_ASSERT_BUFFERS_ARE_EQUAL_BIT(plaintext,
@@ -2622,7 +2622,7 @@ static int test_snow3g_decryption_oop(const struct
snow3g_test_data *tdata)
rte_pktmbuf_append(ut_params->obuf, ciphertext_pad_len);
memcpy(ciphertext, tdata->ciphertext.data, ciphertext_len);
- TEST_HEXDUMP(stdout, "ciphertext:", ciphertext, tdata->ciphertext.len);
+ TEST_HEXDUMP(stdout, "ciphertext:", ciphertext, ciphertext_len);
/* Create SNOW3G operation */
retval = create_snow3g_kasumi_cipher_operation_oop(tdata->iv.data,
@@ -2643,7 +2643,7 @@ static int test_snow3g_decryption_oop(const struct
snow3g_test_data *tdata)
else
plaintext = ciphertext;
- TEST_HEXDUMP(stdout, "plaintext:", plaintext, tdata->plaintext.len);
+ TEST_HEXDUMP(stdout, "plaintext:", plaintext, ciphertext_len);
/* Validate obuf */
TEST_ASSERT_BUFFERS_ARE_EQUAL_BIT(plaintext,
@@ -2689,7 +2689,7 @@ test_snow3g_authenticated_encryption(const struct
snow3g_test_data *tdata)
plaintext_pad_len);
memcpy(plaintext, tdata->plaintext.data, plaintext_len);
- TEST_HEXDUMP(stdout, "plaintext:", plaintext, tdata->plaintext.len);
+ TEST_HEXDUMP(stdout, "plaintext:", plaintext, plaintext_len);
/* Create SNOW3G operation */
retval = create_snow3g_kasumi_cipher_hash_operation(tdata->digest.data,
@@ -2717,7 +2717,7 @@ test_snow3g_authenticated_encryption(const struct
snow3g_test_data *tdata)
else
ciphertext = plaintext;
- TEST_HEXDUMP(stdout,
[dpdk-dev] [PATCH] qat: fix for digest verification use case
This fixes the cases in which operation was Digest verify.
Fixes: e25200fbb45df ("crypto: add cipher/auth only support")
Signed-off-by: Deepak Kumar Jain
---
drivers/crypto/qat/qat_adf/qat_algs.h| 3 ++-
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 10 +-
drivers/crypto/qat/qat_crypto.c | 6 --
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index b47dbc2..243c1b4 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -112,7 +112,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
uint8_t *authkey,
uint32_t authkeylen,
uint32_t add_auth_data_length,
- uint32_t digestsize);
+ uint32_t digestsize,
+ unsigned int operation);
void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header);
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index aa108d4..185bb33 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -51,6 +51,7 @@
#include
#include
#include
+#include
#include "../qat_logs.h"
#include "qat_algs.h"
@@ -502,7 +503,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
uint8_t *authkey,
uint32_t authkeylen,
uint32_t add_auth_data_length,
- uint32_t digestsize)
+ uint32_t digestsize,
+ unsigned int operation)
{
struct icp_qat_hw_cipher_algo_blk *cipher;
struct icp_qat_hw_auth_algo_blk *hash;
@@ -654,6 +656,12 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
}
+ if (operation == RTE_CRYPTO_AUTH_OP_VERIFY) {
+ ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
+ ICP_QAT_FW_LA_NO_RET_AUTH_RES);
+ ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
+ ICP_QAT_FW_LA_CMP_AUTH_RES);
+ }
/* Cipher CD config setup */
cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 940b2b6..d51ca96 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -560,14 +560,16 @@ qat_crypto_sym_configure_session_auth(struct
rte_cryptodev *dev,
cipher_xform->key.data,
cipher_xform->key.length,
auth_xform->add_auth_data_length,
- auth_xform->digest_length))
+ auth_xform->digest_length,
+ auth_xform->op))
goto error_out;
} else {
if (qat_alg_aead_session_create_content_desc_auth(session,
auth_xform->key.data,
auth_xform->key.length,
auth_xform->add_auth_data_length,
- auth_xform->digest_length))
+ auth_xform->digest_length,
+ auth_xform->op))
goto error_out;
}
return session;
--
2.5.5
[dpdk-dev] [PATCH] app/test: fix missing operation initialization
Initializing the authentication op parameter.
Fixes: eec136f3c54f ("aesni_gcm: add driver for AES-GCM crypto operations")
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 9dfe34f..72f768b 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -3002,6 +3002,7 @@ create_gcm_session(uint8_t dev_id, enum
rte_crypto_cipher_operation op,
ut_params->cipher_xform.next = NULL;
ut_params->cipher_xform.cipher.algo = RTE_CRYPTO_CIPHER_AES_GCM;
+ ut_params->auth_xform.auth.op = RTE_CRYPTO_AUTH_OP_GENERATE;
ut_params->cipher_xform.cipher.op = op;
ut_params->cipher_xform.cipher.key.data = cipher_key;
ut_params->cipher_xform.cipher.key.length = key_len;
--
2.5.5
[dpdk-dev] [PATCH] app/test: fix for icc compilation error
Icc complains about variable may be used without setting.
Fixes: 97fe6461c7cbfb ("app/test: add SNOW 3G performance test)
Signed-off-by: Deepak Kumar Jain
---
app/test/test_cryptodev_perf.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/app/test/test_cryptodev_perf.c b/app/test/test_cryptodev_perf.c
index e1adc99..e484cbb 100644
--- a/app/test/test_cryptodev_perf.c
+++ b/app/test/test_cryptodev_perf.c
@@ -2458,18 +2458,17 @@ test_perf_aes_sha(uint8_t dev_id, uint16_t queue_id,
/* Generate a burst of crypto operations */
for (i = 0; i < (pparams->burst_size * NUM_MBUF_SETS); i++) {
- struct rte_mbuf *m = test_perf_create_pktmbuf(
+ mbufs[i] = test_perf_create_pktmbuf(
ts_params->mbuf_mp,
pparams->buf_size);
- if (m == NULL) {
+ if (mbufs[i] == NULL) {
printf("\nFailed to get mbuf - freeing the rest.\n");
for (k = 0; k < i; k++)
rte_pktmbuf_free(mbufs[k]);
return -1;
}
- mbufs[i] = m;
}
@@ -2587,18 +2586,17 @@ test_perf_snow3g(uint8_t dev_id, uint16_t queue_id,
/* Generate a burst of crypto operations */
for (i = 0; i < (pparams->burst_size * NUM_MBUF_SETS); i++) {
- struct rte_mbuf *m = test_perf_create_pktmbuf(
+ mbufs[i] = test_perf_create_pktmbuf(
ts_params->mbuf_mp,
pparams->buf_size);
- if (m == NULL) {
+ if (mbufs[i] == NULL) {
printf("\nFailed to get mbuf - freeing the rest.\n");
for (k = 0; k < i; k++)
rte_pktmbuf_free(mbufs[k]);
return -1;
}
- mbufs[i] = m;
}
tsc_start = rte_rdtsc_precise();
--
2.5.5
[dpdk-dev] [PATCH v3] qat: fix for VFs not getting recognized
From: "Jain, Deepak K"
Updated the code to use RTE_PCI_DEVICE.
Fixes: 701c8d80c820 ("pci: support class id probing")
Signed-off-by: Jain, Deepak K
---
v3: kept PCI id in the driver file
v2: updated code to use RTE_PCI_DEVICE
drivers/crypto/qat/rte_qat_cryptodev.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/crypto/qat/rte_qat_cryptodev.c
b/drivers/crypto/qat/rte_qat_cryptodev.c
index a7912f5..f46ec85 100644
--- a/drivers/crypto/qat/rte_qat_cryptodev.c
+++ b/drivers/crypto/qat/rte_qat_cryptodev.c
@@ -69,10 +69,7 @@ static struct rte_cryptodev_ops crypto_qat_ops = {
static struct rte_pci_id pci_id_qat_map[] = {
{
- .vendor_id = 0x8086,
- .device_id = 0x0443,
- .subsystem_vendor_id = PCI_ANY_ID,
- .subsystem_device_id = PCI_ANY_ID
+ RTE_PCI_DEVICE(0x8086, 0x0443),
},
{.device_id = 0},
};
--
2.5.5
[dpdk-dev] [PATCH] crypto: fix null pointer dereferencing
From: "Jain, Deepak K"
Fix null pointer dereferencing by reporing if null and
exiting the function.
Fixes: c0f87eb5252b ("cryptodev: change burst API to be crypto op oriented")
Coverity issue: 126584
Signed-off-by: Deepak Kumar Jain
---
drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
index 9c42f88..31784e1 100644
--- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
+++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
@@ -379,9 +379,11 @@ process_crypto_op(struct aesni_mb_qp *qp, struct
rte_crypto_op *op,
/* append space for output data to mbuf */
char *odata = rte_pktmbuf_append(m_dst,
rte_pktmbuf_data_len(op->sym->m_src));
- if (odata == NULL)
+ if (odata == NULL) {
MB_LOG_ERR("failed to allocate space in destination "
"mbuf for source data");
+ return NULL;
+ }
memcpy(odata, rte_pktmbuf_mtod(op->sym->m_src, void*),
rte_pktmbuf_data_len(op->sym->m_src));
--
2.5.5
[dpdk-dev] [PATCH] crypto: fix control issues in aesni pmd
From: "Jain, Deepak K"
Fix the control issues for return value
Fixes: 924e84f87306 ("aesni_mb: add driver for multi buffer based crypto")
Coverity ID 126585
Signed-off-by: Deepak Kumar Jain
---
drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
index 3415ac1..9c42f88 100644
--- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
+++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
@@ -560,7 +560,7 @@ aesni_mb_pmd_enqueue_burst(void *queue_pair, struct
rte_crypto_op **ops,
goto flush_jobs;
else
qp->stats.enqueued_count += processed_jobs;
- return i;
+ return i;
flush_jobs:
/*
--
2.5.5
[dpdk-dev] [PATCH] qat: fix null pointer dereferencing
Fix null pointer dereferencing while
clearing session
Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")
Coverity ID 126586
Signed-off-by: Deepak kumar JAIN
---
drivers/crypto/qat/qat_crypto.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 495ea1c..a084692 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -276,14 +276,15 @@ void qat_crypto_sym_clear_session(struct rte_cryptodev
*dev,
void *session)
{
struct qat_session *sess = session;
- phys_addr_t cd_paddr = sess->cd_paddr;
+ phys_addr_t cd_paddr;
PMD_INIT_FUNC_TRACE();
if (session) {
+ cd_paddr = sess->cd_paddr;
memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
-
sess->cd_paddr = cd_paddr;
- }
+ } else
+ PMD_DRV_LOG(ERR, "NULL session");
}
static int
--
2.5.5
[dpdk-dev] [PATCH] snow3g: Bit-wise handling for Wireless Algorithm
Wireless algorithms like Snow3G needs input in bits.
In this patch, changes have been made to incorporate this requirement
in both QAT and SW PMD.
Signed-off-by: Deepak Kumar JAIN
---
This patch depends on "pmd/snow3g: add new SNOW 3G SW PMD" patch
(http://dpdk.org/ml/archives/dev/2016-March/035466.html)
app/test/test_cryptodev.c | 118 -
app/test/test_cryptodev_snow3g_hash_test_vectors.h | 34 +-
app/test/test_cryptodev_snow3g_test_vectors.h | 92 +---
doc/guides/cryptodevs/qat.rst | 2 +
doc/guides/cryptodevs/snow3g.rst | 2 +
drivers/crypto/qat/qat_crypto.c| 26 -
drivers/crypto/snow3g/rte_snow3g_pmd.c | 33 --
lib/librte_cryptodev/rte_crypto_sym.h | 16 +++
8 files changed, 247 insertions(+), 76 deletions(-)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 595b9f9..c432c05 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -1828,7 +1828,8 @@ create_snow3g_cipher_session(uint8_t dev_id,
static int
create_snow3g_cipher_operation(const uint8_t *iv, const unsigned iv_len,
- const unsigned data_len)
+ const unsigned cipher_len,
+ const unsigned cipher_offset)
{
struct crypto_testsuite_params *ts_params = &testsuite_params;
struct crypto_unittest_params *ut_params = &unittest_params;
@@ -1860,8 +1861,8 @@ create_snow3g_cipher_operation(const uint8_t *iv, const
unsigned iv_len,
sym_op->cipher.iv.length = iv_pad_len;
rte_memcpy(sym_op->cipher.iv.data, iv, iv_len);
- sym_op->cipher.data.length = data_len;
- sym_op->cipher.data.offset = iv_pad_len;
+ sym_op->cipher.data.length = cipher_len;
+ sym_op->cipher.data.offset = cipher_offset;
return 0;
}
@@ -1958,8 +1959,9 @@ static int
create_snow3g_hash_operation(const uint8_t *auth_tag,
const unsigned auth_tag_len,
const uint8_t *aad, const unsigned aad_len,
- const unsigned data_len, unsigned data_pad_len,
- enum rte_crypto_auth_operation op)
+ unsigned data_pad_len,
+ enum rte_crypto_auth_operation op,
+ const unsigned auth_len, const unsigned auth_offset)
{
struct crypto_testsuite_params *ts_params = &testsuite_params;
@@ -2027,8 +2029,8 @@ create_snow3g_hash_operation(const uint8_t *auth_tag,
sym_op->auth.digest.length);
#endif
- sym_op->auth.data.length = data_len;
- sym_op->auth.data.offset = aad_buffer_len;
+ sym_op->auth.data.length = auth_len;
+ sym_op->auth.data.offset = auth_offset;
return 0;
}
@@ -2037,9 +2039,11 @@ static int
create_snow3g_cipher_hash_operation(const uint8_t *auth_tag,
const unsigned auth_tag_len,
const uint8_t *aad, const unsigned aad_len,
- const unsigned data_len, unsigned data_pad_len,
+ unsigned data_pad_len,
enum rte_crypto_auth_operation op,
- const uint8_t *iv, const unsigned iv_len)
+ const uint8_t *iv, const unsigned iv_len,
+ const unsigned cipher_len, const unsigned cipher_offset,
+ const unsigned auth_len, const unsigned auth_offset)
{
struct crypto_testsuite_params *ts_params = &testsuite_params;
struct crypto_unittest_params *ut_params = &unittest_params;
@@ -2074,8 +2078,8 @@ create_snow3g_cipher_hash_operation(const uint8_t
*auth_tag,
rte_memcpy(sym_op->cipher.iv.data, iv, iv_len);
- sym_op->cipher.data.length = data_len;
- sym_op->cipher.data.offset = iv_pad_len;
+ sym_op->cipher.data.length = cipher_len;
+ sym_op->cipher.data.offset = cipher_offset;
/* aad */
/*
@@ -2124,8 +2128,8 @@ create_snow3g_cipher_hash_operation(const uint8_t
*auth_tag,
sym_op->auth.digest.length);
#endif
- sym_op->auth.data.length = data_len;
- sym_op->auth.data.offset = aad_buffer_len;
+ sym_op->auth.data.length = auth_len;
+ sym_op->auth.data.offset = auth_offset;
return 0;
}
@@ -2134,7 +2138,9 @@ static int
create_snow3g_auth_cipher_operation(const unsigned auth_tag_len,
const uint8_t *iv, const unsigned iv_len,
const uint8_t *aad, const unsigned aad_len,
- const unsigned data_len, unsigned data_pad_len)
+ unsigned data_pad_len,
+ const unsigned cipher_len, const unsigned cipher_offset,
+ const unsigned auth_len, const unsigned auth_offset)
{
struct crypto_testsuite_params *ts_params = &testsuite_params;
struct crypto_unittest_params *ut_params = &unit
[dpdk-dev] [PATCH v4 3/3] app/test: add Snow3G tests
Signed-off-by: Deepak Kumar JAIN
---
app/test/test_cryptodev.c | 1037 +++-
app/test/test_cryptodev.h |3 +-
app/test/test_cryptodev_snow3g_hash_test_vectors.h | 415
app/test/test_cryptodev_snow3g_test_vectors.h | 379 +++
4 files changed, 1831 insertions(+), 3 deletions(-)
create mode 100644 app/test/test_cryptodev_snow3g_hash_test_vectors.h
create mode 100644 app/test/test_cryptodev_snow3g_test_vectors.h
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 3240ecd..0fe47b9 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -42,7 +42,8 @@
#include "test.h"
#include "test_cryptodev.h"
-
+#include "test_cryptodev_snow3g_test_vectors.h"
+#include "test_cryptodev_snow3g_hash_test_vectors.h"
static enum rte_cryptodev_type gbl_cryptodev_type;
struct crypto_testsuite_params {
@@ -68,6 +69,9 @@ struct crypto_unittest_params {
uint8_t *digest;
};
+#define ALIGN_POW2_ROUNDUP(num, align) \
+ (((num) + (align) - 1) & ~((align) - 1))
+
/*
* Forward declarations.
*/
@@ -1747,6 +1751,997 @@ test_AES_CBC_HMAC_AES_XCBC_decrypt_digest_verify(void)
return TEST_SUCCESS;
}
+/* * Snow3G Tests * */
+static int
+create_snow3g_hash_session(uint8_t dev_id,
+ const uint8_t *key, const uint8_t key_len,
+ const uint8_t aad_len, const uint8_t auth_len,
+ enum rte_crypto_auth_operation op)
+{
+ uint8_t hash_key[key_len];
+
+ struct crypto_unittest_params *ut_params = &unittest_params;
+
+ memcpy(hash_key, key, key_len);
+#ifdef RTE_APP_TEST_DEBUG
+ rte_hexdump(stdout, "key:", key, key_len);
+#endif
+ /* Setup Authentication Parameters */
+ ut_params->auth_xform.type = RTE_CRYPTO_SYM_XFORM_AUTH;
+ ut_params->auth_xform.next = NULL;
+
+ ut_params->auth_xform.auth.op = op;
+ ut_params->auth_xform.auth.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2;
+ ut_params->auth_xform.auth.key.length = key_len;
+ ut_params->auth_xform.auth.key.data = hash_key;
+ ut_params->auth_xform.auth.digest_length = auth_len;
+ ut_params->auth_xform.auth.add_auth_data_length = aad_len;
+ ut_params->sess = rte_cryptodev_sym_session_create(dev_id,
+ &ut_params->auth_xform);
+ TEST_ASSERT_NOT_NULL(ut_params->sess, "Session creation failed");
+ return 0;
+}
+static int
+create_snow3g_cipher_session(uint8_t dev_id,
+ enum rte_crypto_cipher_operation op,
+ const uint8_t *key, const uint8_t key_len)
+{
+ uint8_t cipher_key[key_len];
+
+ struct crypto_unittest_params *ut_params = &unittest_params;
+
+ memcpy(cipher_key, key, key_len);
+
+ /* Setup Cipher Parameters */
+ ut_params->cipher_xform.type = RTE_CRYPTO_SYM_XFORM_CIPHER;
+ ut_params->cipher_xform.next = NULL;
+
+ ut_params->cipher_xform.cipher.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2;
+ ut_params->cipher_xform.cipher.op = op;
+ ut_params->cipher_xform.cipher.key.data = cipher_key;
+ ut_params->cipher_xform.cipher.key.length = key_len;
+
+#ifdef RTE_APP_TEST_DEBUG
+ rte_hexdump(stdout, "key:", key, key_len);
+#endif
+ /* Create Crypto session */
+ ut_params->sess = rte_cryptodev_sym_session_create(dev_id,
+ &ut_params->
+ cipher_xform);
+ TEST_ASSERT_NOT_NULL(ut_params->sess, "Session creation failed");
+ return 0;
+}
+
+static int
+create_snow3g_cipher_operation(const uint8_t *iv, const unsigned iv_len,
+ const unsigned data_len)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ struct crypto_unittest_params *ut_params = &unittest_params;
+ unsigned iv_pad_len = 0;
+
+ /* Generate Crypto op data structure */
+ ut_params->op = rte_crypto_op_alloc(ts_params->op_mpool,
+ RTE_CRYPTO_OP_TYPE_SYMMETRIC);
+ TEST_ASSERT_NOT_NULL(ut_params->op,
+ "Failed to allocate pktmbuf offload");
+
+ /* Set crypto operation data parameters */
+ rte_crypto_op_attach_sym_session(ut_params->op, ut_params->sess);
+
+ struct rte_crypto_sym_op *sym_op = ut_params->op->sym;
+
+ /* set crypto operation source mbuf */
+ sym_op->m_src = ut_params->ibuf;
+
+ /* iv */
+ iv_pad_len = RTE_ALIGN_CEIL(iv_len, 16);
+ sym_op->cipher.iv.data = (uint8_t *)rte_pktmbuf_prepend(ut_params->ibuf
+ , iv_pad_len);
+
+ TEST_ASSERT_NOT_NULL(sym_op->cipher.iv.data, "no room to prepend iv");
+
+ m
[dpdk-dev] [PATCH v4 2/3] qat: add support for Snow3G
Signed-off-by: Deepak Kumar JAIN
---
doc/guides/cryptodevs/qat.rst| 8 ++-
doc/guides/rel_notes/release_16_04.rst | 6 ++
drivers/crypto/qat/qat_adf/qat_algs.h| 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 86 ++--
drivers/crypto/qat/qat_crypto.c | 12 +++-
5 files changed, 104 insertions(+), 9 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 23402b4..af52047 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -1,5 +1,5 @@
.. BSD LICENSE
-Copyright(c) 2015 Intel Corporation. All rights reserved.
+Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
@@ -47,6 +47,7 @@ Cipher algorithms:
* ``RTE_CRYPTO_SYM_CIPHER_AES128_CBC``
* ``RTE_CRYPTO_SYM_CIPHER_AES192_CBC``
* ``RTE_CRYPTO_SYM_CIPHER_AES256_CBC``
+* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2``
Hash algorithms:
@@ -54,14 +55,15 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
+* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
Limitations
---
* Chained mbufs are not supported.
-* Hash only is not supported.
-* Cipher only is not supported.
+* Hash only is not supported except Snow3G UIA2.
+* Cipher only is not supported except Snow3G UEA2.
* Only in-place is currently supported (destination address is the same as
source address).
* Only supports the session-oriented API implementation (session-less APIs are
not supported).
* Not performance tuned.
diff --git a/doc/guides/rel_notes/release_16_04.rst
b/doc/guides/rel_notes/release_16_04.rst
index aa9eabc..4f41e63 100644
--- a/doc/guides/rel_notes/release_16_04.rst
+++ b/doc/guides/rel_notes/release_16_04.rst
@@ -35,6 +35,12 @@ This section should contain new features added in this
release. Sample format:
Refer to the previous release notes for examples.
+* **Added support of Snow3G (UEA2 and UIA2) for Intel Quick Assist Devices.**
+
+ Enabled support for Snow3g Wireless algorithm for Intel Quick Assist devices.
+ Support for cipher only, Hash only is also provided
+ along with alg-chaining operations.
+
* **Added function to check primary process state.**
A new function ``rte_eal_primary_proc_alive()`` has been added
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index b73a5d0..b47dbc2 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -125,5 +125,6 @@ void qat_alg_ablkcipher_init_dec(struct
qat_alg_ablkcipher_cd *cd,
unsigned int keylen);
int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
+int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
#endif
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 534eda0..bcccdf4 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -82,6 +82,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo
qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_GALOIS_64:
return QAT_HW_ROUND_UP(ICP_QAT_HW_GALOIS_128_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
+ case ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:
+ return QAT_HW_ROUND_UP(ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ,
+ QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum state1 size in this case */
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
@@ -376,7 +379,8 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
PMD_INIT_FUNC_TRACE();
- if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER) {
+ if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER &&
+ cdesc->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
cipher =
(struct icp_qat_hw_cipher_algo_blk *)((char *)&cdesc->cd +
sizeof(struct icp_qat_hw_auth_algo_blk));
@@ -409,13 +413,20 @@ int
qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
else
key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
+ if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2)
+ key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
+
/* For Snow3G, set key convert and other bits */
if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
ICP
[dpdk-dev] [PATCH v4 1/3] crypto: add cipher/auth only support
Refactored the existing functionality into
modular form to support the cipher/auth only
functionalities.
Signed-off-by: Deepak Kumar JAIN
---
drivers/crypto/qat/qat_adf/qat_algs.h| 18 +-
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 208 ---
drivers/crypto/qat/qat_crypto.c | 137 +++
drivers/crypto/qat/qat_crypto.h | 10 ++
4 files changed, 306 insertions(+), 67 deletions(-)
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index 76c08c0..b73a5d0 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -3,7 +3,7 @@
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -17,7 +17,7 @@
* qat-linux at intel.com
*
* BSD LICENSE
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -104,11 +104,15 @@ struct qat_alg_ablkcipher_cd {
int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg);
-int qat_alg_aead_session_create_content_desc(struct qat_session *cd,
- uint8_t *enckey, uint32_t enckeylen,
- uint8_t *authkey, uint32_t authkeylen,
- uint32_t add_auth_data_length,
- uint32_t digestsize);
+int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cd,
+ uint8_t *enckey,
+ uint32_t enckeylen);
+
+int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
+ uint8_t *authkey,
+ uint32_t authkeylen,
+ uint32_t add_auth_data_length,
+ uint32_t digestsize);
void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header);
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index ceaffb7..534eda0 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -3,7 +3,7 @@
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -17,7 +17,7 @@
* qat-linux at intel.com
*
* BSD LICENSE
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -359,15 +359,139 @@ void qat_alg_init_common_hdr(struct
icp_qat_fw_comn_req_hdr *header)
ICP_QAT_FW_LA_NO_UPDATE_STATE);
}
-int qat_alg_aead_session_create_content_desc(struct qat_session *cdesc,
- uint8_t *cipherkey, uint32_t cipherkeylen,
- uint8_t *authkey, uint32_t authkeylen,
- uint32_t add_auth_data_length,
- uint32_t digestsize)
+int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
+ uint8_t *cipherkey,
+ uint32_t cipherkeylen)
{
- struct qat_alg_cd *content_desc = &cdesc->cd;
- struct icp_qat_hw_cipher_algo_blk *cipher = &content_desc->cipher;
- struct icp_qat_hw_auth_algo_blk *hash = &content_desc->hash;
+ struct icp_qat_hw_cipher_algo_blk *cipher;
+ struct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req;
+ struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
+ struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
+ void *ptr = &req_tmpl->cd_ctrl;
+ struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
+ struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;
+ enum icp_qat_hw_cipher_convert key_convert;
+ uint16_t proto = ICP_QAT_FW_LA_NO_PROTO;/* no CCM
[dpdk-dev] [PATCH v4 0/3] Snow3G support for Intel Quick Assist Devices
This patchset contains fixes and refactoring for Snow3G(UEA2 and UIA2) wireless algorithm for Intel Quick Assist devices. QAT PMD previously supported only cipher/hash alg-chaining for AES/SHA. The code has been refactored to also support cipher-only and hash only (for Snow3G only) functionality along with alg-chaining. Changes from V3: 1) Rebase based on below mentioned patchset. 2) Fixes test failure which happens only after applying patch 1 only. Changes from v2: 1) Rebasing based on below mentioned patchset. This patchset depends on cryptodev API changes http://dpdk.org/ml/archives/dev/2016-March/035451.html Deepak Kumar JAIN (3): crypto: add cipher/auth only support qat: add support for Snow3G app/test: add Snow3G tests app/test/test_cryptodev.c | 1037 +++- app/test/test_cryptodev.h |3 +- app/test/test_cryptodev_snow3g_hash_test_vectors.h | 415 app/test/test_cryptodev_snow3g_test_vectors.h | 379 +++ doc/guides/cryptodevs/qat.rst |8 +- doc/guides/rel_notes/release_16_04.rst |6 + drivers/crypto/qat/qat_adf/qat_algs.h | 19 +- drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 284 +- drivers/crypto/qat/qat_crypto.c| 149 ++- drivers/crypto/qat/qat_crypto.h| 10 + 10 files changed, 2236 insertions(+), 74 deletions(-) create mode 100644 app/test/test_cryptodev_snow3g_hash_test_vectors.h create mode 100644 app/test/test_cryptodev_snow3g_test_vectors.h -- 2.1.0
[dpdk-dev] [PATCH v3 3/3] app/test: add Snow3G tests
Signed-off-by: Deepak Kumar JAIN
---
app/test/test_cryptodev.c | 1037 +++-
app/test/test_cryptodev.h |3 +-
app/test/test_cryptodev_snow3g_hash_test_vectors.h | 415
app/test/test_cryptodev_snow3g_test_vectors.h | 379 +++
4 files changed, 1831 insertions(+), 3 deletions(-)
create mode 100644 app/test/test_cryptodev_snow3g_hash_test_vectors.h
create mode 100644 app/test/test_cryptodev_snow3g_test_vectors.h
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index acba98a..a37018c 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -42,7 +42,8 @@
#include "test.h"
#include "test_cryptodev.h"
-
+#include "test_cryptodev_snow3g_test_vectors.h"
+#include "test_cryptodev_snow3g_hash_test_vectors.h"
static enum rte_cryptodev_type gbl_cryptodev_type;
struct crypto_testsuite_params {
@@ -68,6 +69,9 @@ struct crypto_unittest_params {
uint8_t *digest;
};
+#define ALIGN_POW2_ROUNDUP(num, align) \
+ (((num) + (align) - 1) & ~((align) - 1))
+
/*
* Forward declarations.
*/
@@ -1748,6 +1752,997 @@ test_AES_CBC_HMAC_AES_XCBC_decrypt_digest_verify(void)
return TEST_SUCCESS;
}
+/* * Snow3G Tests * */
+static int
+create_snow3g_hash_session(uint8_t dev_id,
+ const uint8_t *key, const uint8_t key_len,
+ const uint8_t aad_len, const uint8_t auth_len,
+ enum rte_crypto_auth_operation op)
+{
+ uint8_t hash_key[key_len];
+
+ struct crypto_unittest_params *ut_params = &unittest_params;
+
+ memcpy(hash_key, key, key_len);
+#ifdef RTE_APP_TEST_DEBUG
+ rte_hexdump(stdout, "key:", key, key_len);
+#endif
+ /* Setup Authentication Parameters */
+ ut_params->auth_xform.type = RTE_CRYPTO_SYM_XFORM_AUTH;
+ ut_params->auth_xform.next = NULL;
+
+ ut_params->auth_xform.auth.op = op;
+ ut_params->auth_xform.auth.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2;
+ ut_params->auth_xform.auth.key.length = key_len;
+ ut_params->auth_xform.auth.key.data = hash_key;
+ ut_params->auth_xform.auth.digest_length = auth_len;
+ ut_params->auth_xform.auth.add_auth_data_length = aad_len;
+ ut_params->sess = rte_cryptodev_sym_session_create(dev_id,
+ &ut_params->auth_xform);
+ TEST_ASSERT_NOT_NULL(ut_params->sess, "Session creation failed");
+ return 0;
+}
+static int
+create_snow3g_cipher_session(uint8_t dev_id,
+ enum rte_crypto_cipher_operation op,
+ const uint8_t *key, const uint8_t key_len)
+{
+ uint8_t cipher_key[key_len];
+
+ struct crypto_unittest_params *ut_params = &unittest_params;
+
+ memcpy(cipher_key, key, key_len);
+
+ /* Setup Cipher Parameters */
+ ut_params->cipher_xform.type = RTE_CRYPTO_SYM_XFORM_CIPHER;
+ ut_params->cipher_xform.next = NULL;
+
+ ut_params->cipher_xform.cipher.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2;
+ ut_params->cipher_xform.cipher.op = op;
+ ut_params->cipher_xform.cipher.key.data = cipher_key;
+ ut_params->cipher_xform.cipher.key.length = key_len;
+
+#ifdef RTE_APP_TEST_DEBUG
+ rte_hexdump(stdout, "key:", key, key_len);
+#endif
+ /* Create Crypto session */
+ ut_params->sess = rte_cryptodev_sym_session_create(dev_id,
+ &ut_params->
+ cipher_xform);
+ TEST_ASSERT_NOT_NULL(ut_params->sess, "Session creation failed");
+ return 0;
+}
+
+static int
+create_snow3g_cipher_operation(const uint8_t *iv, const unsigned iv_len,
+ const unsigned data_len)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ struct crypto_unittest_params *ut_params = &unittest_params;
+ unsigned iv_pad_len = 0;
+
+ /* Generate Crypto op data structure */
+ ut_params->op = rte_crypto_op_alloc(ts_params->op_mpool,
+ RTE_CRYPTO_OP_TYPE_SYMMETRIC);
+ TEST_ASSERT_NOT_NULL(ut_params->op,
+ "Failed to allocate pktmbuf offload");
+
+ /* Set crypto operation data parameters */
+ rte_crypto_op_attach_sym_session(ut_params->op, ut_params->sess);
+
+ struct rte_crypto_sym_op *sym_op = ut_params->op->sym;
+
+ /* set crypto operation source mbuf */
+ sym_op->m_src = ut_params->ibuf;
+
+ /* iv */
+ iv_pad_len = RTE_ALIGN_CEIL(iv_len, 16);
+ sym_op->cipher.iv.data = (uint8_t *)rte_pktmbuf_prepend(ut_params->ibuf
+ , iv_pad_len);
+
+ TEST_ASSERT_NOT_NULL(sym_op->cipher.iv.data, "no room to prepend iv");
+
+ m
[dpdk-dev] [PATCH v3 2/3] qat: add support for Snow3G
Signed-off-by: Deepak Kumar JAIN
---
doc/guides/cryptodevs/qat.rst| 8 ++-
doc/guides/rel_notes/release_16_04.rst | 6 ++
drivers/crypto/qat/qat_adf/qat_algs.h| 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 86 +---
drivers/crypto/qat/qat_crypto.c | 12 +++-
5 files changed, 100 insertions(+), 13 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 23402b4..af52047 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -1,5 +1,5 @@
.. BSD LICENSE
-Copyright(c) 2015 Intel Corporation. All rights reserved.
+Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
@@ -47,6 +47,7 @@ Cipher algorithms:
* ``RTE_CRYPTO_SYM_CIPHER_AES128_CBC``
* ``RTE_CRYPTO_SYM_CIPHER_AES192_CBC``
* ``RTE_CRYPTO_SYM_CIPHER_AES256_CBC``
+* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2``
Hash algorithms:
@@ -54,14 +55,15 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
+* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
Limitations
---
* Chained mbufs are not supported.
-* Hash only is not supported.
-* Cipher only is not supported.
+* Hash only is not supported except Snow3G UIA2.
+* Cipher only is not supported except Snow3G UEA2.
* Only in-place is currently supported (destination address is the same as
source address).
* Only supports the session-oriented API implementation (session-less APIs are
not supported).
* Not performance tuned.
diff --git a/doc/guides/rel_notes/release_16_04.rst
b/doc/guides/rel_notes/release_16_04.rst
index 64e913d..d8ead62 100644
--- a/doc/guides/rel_notes/release_16_04.rst
+++ b/doc/guides/rel_notes/release_16_04.rst
@@ -35,6 +35,12 @@ This section should contain new features added in this
release. Sample format:
Refer to the previous release notes for examples.
+* **Added support of Snow3G (UEA2 and UIA2) for Intel Quick Assist Devices.**
+
+ Enabled support for Snow3g Wireless algorithm for Intel Quick Assist devices.
+ Support for cipher only, Hash only is also provided
+ along with alg-chaining operations.
+
* **Enabled bulk allocation of mbufs.**
A new function ``rte_pktmbuf_alloc_bulk()`` has been added to allow the user
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index b73a5d0..b47dbc2 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -125,5 +125,6 @@ void qat_alg_ablkcipher_init_dec(struct
qat_alg_ablkcipher_cd *cd,
unsigned int keylen);
int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
+int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
#endif
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index bef444b..dd27476 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -376,7 +376,8 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
PMD_INIT_FUNC_TRACE();
- if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER) {
+ if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER &&
+ cdesc->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
cipher =
(struct icp_qat_hw_cipher_algo_blk *)((char *)&cdesc->cd +
sizeof(struct icp_qat_hw_auth_algo_blk));
@@ -409,13 +410,20 @@ int
qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
else
key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
+ if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2)
+ key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
+
/* For Snow3G, set key convert and other bits */
if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
ICP_QAT_FW_LA_NO_RET_AUTH_RES);
- ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
- ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
+ if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER) {
+ ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
+ ICP_QAT_FW_LA_RET_AUTH_RES);
+ ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
+ ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
+ }
[dpdk-dev] [PATCH v3 1/3] crypto: add cipher/auth only support
Refactored the existing functionality into
modular form to support the cipher/auth only
functionalities.
Signed-off-by: Deepak Kumar JAIN
---
drivers/crypto/qat/qat_adf/qat_algs.h| 18 +-
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 210 ---
drivers/crypto/qat/qat_crypto.c | 137 +++
drivers/crypto/qat/qat_crypto.h | 10 ++
4 files changed, 308 insertions(+), 67 deletions(-)
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index 76c08c0..b73a5d0 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -3,7 +3,7 @@
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -17,7 +17,7 @@
* qat-linux at intel.com
*
* BSD LICENSE
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -104,11 +104,15 @@ struct qat_alg_ablkcipher_cd {
int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg);
-int qat_alg_aead_session_create_content_desc(struct qat_session *cd,
- uint8_t *enckey, uint32_t enckeylen,
- uint8_t *authkey, uint32_t authkeylen,
- uint32_t add_auth_data_length,
- uint32_t digestsize);
+int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cd,
+ uint8_t *enckey,
+ uint32_t enckeylen);
+
+int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
+ uint8_t *authkey,
+ uint32_t authkeylen,
+ uint32_t add_auth_data_length,
+ uint32_t digestsize);
void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header);
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index ceaffb7..bef444b 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -3,7 +3,7 @@
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -17,7 +17,7 @@
* qat-linux at intel.com
*
* BSD LICENSE
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -359,15 +359,139 @@ void qat_alg_init_common_hdr(struct
icp_qat_fw_comn_req_hdr *header)
ICP_QAT_FW_LA_NO_UPDATE_STATE);
}
-int qat_alg_aead_session_create_content_desc(struct qat_session *cdesc,
- uint8_t *cipherkey, uint32_t cipherkeylen,
- uint8_t *authkey, uint32_t authkeylen,
- uint32_t add_auth_data_length,
- uint32_t digestsize)
+int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
+ uint8_t *cipherkey,
+ uint32_t cipherkeylen)
{
- struct qat_alg_cd *content_desc = &cdesc->cd;
- struct icp_qat_hw_cipher_algo_blk *cipher = &content_desc->cipher;
- struct icp_qat_hw_auth_algo_blk *hash = &content_desc->hash;
+ struct icp_qat_hw_cipher_algo_blk *cipher;
+ struct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req;
+ struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
+ struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
+ void *ptr = &req_tmpl->cd_ctrl;
+ struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
+ struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;
+ enum icp_qat_hw_cipher_convert key_convert;
+ uint16_t proto = ICP_QAT_FW_LA_NO_PROTO;/* no CCM
[dpdk-dev] [PATCH v3 0/3] Snow3G support for Intel Quick Assist Devices
This patchset contains fixes and refactoring for Snow3G(UEA2 and UIA2) wireless algorithm for Intel Quick Assist devices. QAT PMD previously supported only cipher/hash alg-chaining for AES/SHA. The code has been refactored to also support cipher-only and hash only (for Snow3G only) functionality along with alg-chaining. Changes from v2: 1) Rebasing based on below mentioned patchset. This patchset depends on cryptodev API changes http://dpdk.org/ml/archives/dev/2016-February/034212.html Deepak Kumar JAIN (3): crypto: add cipher/auth only support qat: add support for Snow3G app/test: add Snow3G tests app/test/test_cryptodev.c | 1037 +++- app/test/test_cryptodev.h |3 +- app/test/test_cryptodev_snow3g_hash_test_vectors.h | 415 app/test/test_cryptodev_snow3g_test_vectors.h | 379 +++ doc/guides/cryptodevs/qat.rst |8 +- doc/guides/rel_notes/release_16_04.rst |6 + drivers/crypto/qat/qat_adf/qat_algs.h | 19 +- drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 280 +- drivers/crypto/qat/qat_crypto.c| 149 ++- drivers/crypto/qat/qat_crypto.h| 10 + 10 files changed, 2231 insertions(+), 75 deletions(-) create mode 100644 app/test/test_cryptodev_snow3g_hash_test_vectors.h create mode 100644 app/test/test_cryptodev_snow3g_test_vectors.h -- 2.1.0
[dpdk-dev] [PATCH] app/test: fix qat autotest failure
This patch fix the QAT autotest failure when run for multiple times.
it was caused as mbuf was not freed.
Fixes: 202d375c60b (app/test: add cryptodev unit and performance tests)
This patch depends on following patch:
cryptodev API changes
http://dpdk.org/ml/archives/dev/2016-February/034212.html
Signed-off-by: Deepak Kumar JAIN
---
app/test/test_cryptodev.c | 12
1 file changed, 12 insertions(+)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 208fc14..acba98a 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -1845,6 +1845,18 @@ test_multi_session(void)
sessions[i], ut_params, ts_params),
"Failed to perform decrypt on request "
"number %u.", i);
+ /* free crypto operation structure */
+ if (ut_params->op)
+ rte_crypto_op_free(ut_params->op);
+
+ /*
+* free mbuf - both obuf and ibuf are usually the same,
+* but rte copes even if we call free twice
+*/
+ if (ut_params->obuf) {
+ rte_pktmbuf_free(ut_params->obuf);
+ ut_params->obuf = 0;
+ }
}
/* Next session create should fail */
--
2.1.0
[dpdk-dev] [PATCH v2 3/3] app/test: add Snow3G tests
Signed-off-by: Deepak Kumar JAIN
---
app/test/test_cryptodev.c | 1037 +++-
app/test/test_cryptodev.h |3 +-
app/test/test_cryptodev_snow3g_hash_test_vectors.h | 415
app/test/test_cryptodev_snow3g_test_vectors.h | 379 +++
4 files changed, 1831 insertions(+), 3 deletions(-)
create mode 100644 app/test/test_cryptodev_snow3g_hash_test_vectors.h
create mode 100644 app/test/test_cryptodev_snow3g_test_vectors.h
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 29e4b29..1983184 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -42,7 +42,8 @@
#include "test.h"
#include "test_cryptodev.h"
-
+#include "test_cryptodev_snow3g_test_vectors.h"
+#include "test_cryptodev_snow3g_hash_test_vectors.h"
static enum rte_cryptodev_type gbl_cryptodev_type;
struct crypto_testsuite_params {
@@ -68,6 +69,9 @@ struct crypto_unittest_params {
uint8_t *digest;
};
+#define ALIGN_POW2_ROUNDUP(num, align) \
+ (((num) + (align) - 1) & ~((align) - 1))
+
/*
* Forward declarations.
*/
@@ -1748,6 +1752,997 @@ test_AES_CBC_HMAC_AES_XCBC_decrypt_digest_verify(void)
return TEST_SUCCESS;
}
+/* * Snow3G Tests * */
+static int
+create_snow3g_hash_session(uint8_t dev_id,
+ const uint8_t *key, const uint8_t key_len,
+ const uint8_t aad_len, const uint8_t auth_len,
+ enum rte_crypto_auth_operation op)
+{
+ uint8_t hash_key[key_len];
+
+ struct crypto_unittest_params *ut_params = &unittest_params;
+
+ memcpy(hash_key, key, key_len);
+#ifdef RTE_APP_TEST_DEBUG
+ rte_hexdump(stdout, "key:", key, key_len);
+#endif
+ /* Setup Authentication Parameters */
+ ut_params->auth_xform.type = RTE_CRYPTO_SYM_XFORM_AUTH;
+ ut_params->auth_xform.next = NULL;
+
+ ut_params->auth_xform.auth.op = op;
+ ut_params->auth_xform.auth.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2;
+ ut_params->auth_xform.auth.key.length = key_len;
+ ut_params->auth_xform.auth.key.data = hash_key;
+ ut_params->auth_xform.auth.digest_length = auth_len;
+ ut_params->auth_xform.auth.add_auth_data_length = aad_len;
+ ut_params->sess = rte_cryptodev_sym_session_create(dev_id,
+ &ut_params->auth_xform);
+ TEST_ASSERT_NOT_NULL(ut_params->sess, "Session creation failed");
+ return 0;
+}
+static int
+create_snow3g_cipher_session(uint8_t dev_id,
+ enum rte_crypto_cipher_operation op,
+ const uint8_t *key, const uint8_t key_len)
+{
+ uint8_t cipher_key[key_len];
+
+ struct crypto_unittest_params *ut_params = &unittest_params;
+
+ memcpy(cipher_key, key, key_len);
+
+ /* Setup Cipher Parameters */
+ ut_params->cipher_xform.type = RTE_CRYPTO_SYM_XFORM_CIPHER;
+ ut_params->cipher_xform.next = NULL;
+
+ ut_params->cipher_xform.cipher.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2;
+ ut_params->cipher_xform.cipher.op = op;
+ ut_params->cipher_xform.cipher.key.data = cipher_key;
+ ut_params->cipher_xform.cipher.key.length = key_len;
+
+#ifdef RTE_APP_TEST_DEBUG
+ rte_hexdump(stdout, "key:", key, key_len);
+#endif
+ /* Create Crypto session */
+ ut_params->sess = rte_cryptodev_sym_session_create(dev_id,
+ &ut_params->
+ cipher_xform);
+ TEST_ASSERT_NOT_NULL(ut_params->sess, "Session creation failed");
+ return 0;
+}
+
+static int
+create_snow3g_cipher_operation(const uint8_t *iv, const unsigned iv_len,
+ const unsigned data_len)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ struct crypto_unittest_params *ut_params = &unittest_params;
+ unsigned iv_pad_len = 0;
+
+ /* Generate Crypto op data structure */
+ ut_params->op = rte_crypto_op_alloc(ts_params->op_mpool,
+ RTE_CRYPTO_OP_TYPE_SYMMETRIC);
+ TEST_ASSERT_NOT_NULL(ut_params->op,
+ "Failed to allocate pktmbuf offload");
+
+ /* Set crypto operation data parameters */
+ rte_crypto_op_attach_sym_session(ut_params->op, ut_params->sess);
+
+ struct rte_crypto_sym_op *sym_op = ut_params->op->sym;
+
+ /* set crypto operation source mbuf */
+ sym_op->m_src = ut_params->ibuf;
+
+ /* iv */
+ iv_pad_len = RTE_ALIGN_CEIL(iv_len, 16);
+ sym_op->cipher.iv.data = (uint8_t *)rte_pktmbuf_prepend(ut_params->ibuf
+ , iv_pad_len);
+
+ TEST_ASSERT_NOT_NULL(sym_op->cipher.iv.data, "no room to prepend iv");
+
+ m
[dpdk-dev] [PATCH v2 2/3] qat: add support for Snow3G
Signed-off-by: Deepak Kumar JAIN
---
doc/guides/cryptodevs/qat.rst| 8 ++-
doc/guides/rel_notes/release_16_04.rst | 4 ++
drivers/crypto/qat/qat_adf/qat_algs.h| 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 86 +---
drivers/crypto/qat/qat_crypto.c | 10 +++
5 files changed, 97 insertions(+), 12 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 1901842..b5a48ec 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -1,5 +1,5 @@
.. BSD LICENSE
-Copyright(c) 2015 Intel Corporation. All rights reserved.
+Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
@@ -47,6 +47,7 @@ Cipher algorithms:
* ``RTE_CRYPTO_SYM_CIPHER_AES128_CBC``
* ``RTE_CRYPTO_SYM_CIPHER_AES192_CBC``
* ``RTE_CRYPTO_SYM_CIPHER_AES256_CBC``
+* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2``
Hash algorithms:
@@ -54,14 +55,15 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
+* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UIA2``
Limitations
---
* Chained mbufs are not supported.
-* Hash only is not supported.
-* Cipher only is not supported.
+* Hash only is not supported except Snow3G UIA2.
+* Cipher only is not supported except Snow3G UEA2.
* Only in-place is currently supported (destination address is the same as
source address).
* Only supports the session-oriented API implementation (session-less APIs are
not supported).
* Not performance tuned.
diff --git a/doc/guides/rel_notes/release_16_04.rst
b/doc/guides/rel_notes/release_16_04.rst
index 123a6fd..ee59bcf 100644
--- a/doc/guides/rel_notes/release_16_04.rst
+++ b/doc/guides/rel_notes/release_16_04.rst
@@ -39,6 +39,10 @@ This section should contain new features added in this
release. Sample format:
Enabled virtio 1.0 support for virtio pmd driver.
+* **Added the support of Snow3g UEA2 Cipher operation for Intel Quick Assist
Devices.**
+
+ Enabled support for Snow3g Wireless algorithm for Intel Quick Assist
devices.
+ Support for cipher only, Hash only is also provided laong with alg-chaing
operations.
Resolved Issues
---
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index b73a5d0..b47dbc2 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -125,5 +125,6 @@ void qat_alg_ablkcipher_init_dec(struct
qat_alg_ablkcipher_cd *cd,
unsigned int keylen);
int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
+int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
#endif
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index bef444b..dd27476 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -376,7 +376,8 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
PMD_INIT_FUNC_TRACE();
- if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER) {
+ if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER &&
+ cdesc->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
cipher =
(struct icp_qat_hw_cipher_algo_blk *)((char *)&cdesc->cd +
sizeof(struct icp_qat_hw_auth_algo_blk));
@@ -409,13 +410,20 @@ int
qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
else
key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
+ if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2)
+ key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
+
/* For Snow3G, set key convert and other bits */
if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
ICP_QAT_FW_LA_NO_RET_AUTH_RES);
- ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
- ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
+ if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER) {
+ ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
+ ICP_QAT_FW_LA_RET_AUTH_RES);
+ ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
+ ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
+ }
}
cipher->aes.cipher_config.val =
@@ -431,7 +439,6 @@ int qat_al
[dpdk-dev] [PATCH v2 1/3] crypto: add cipher/auth only support
Refactored the existing functionality into
modular form to support the cipher/auth only
functionalities.
Signed-off-by: Deepak Kumar JAIN
---
drivers/crypto/qat/qat_adf/qat_algs.h| 18 +-
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 210 ---
drivers/crypto/qat/qat_crypto.c | 137 +++
drivers/crypto/qat/qat_crypto.h | 10 ++
4 files changed, 308 insertions(+), 67 deletions(-)
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index 76c08c0..b73a5d0 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -3,7 +3,7 @@
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -17,7 +17,7 @@
* qat-linux at intel.com
*
* BSD LICENSE
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -104,11 +104,15 @@ struct qat_alg_ablkcipher_cd {
int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg);
-int qat_alg_aead_session_create_content_desc(struct qat_session *cd,
- uint8_t *enckey, uint32_t enckeylen,
- uint8_t *authkey, uint32_t authkeylen,
- uint32_t add_auth_data_length,
- uint32_t digestsize);
+int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cd,
+ uint8_t *enckey,
+ uint32_t enckeylen);
+
+int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
+ uint8_t *authkey,
+ uint32_t authkeylen,
+ uint32_t add_auth_data_length,
+ uint32_t digestsize);
void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header);
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index ceaffb7..bef444b 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -3,7 +3,7 @@
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -17,7 +17,7 @@
* qat-linux at intel.com
*
* BSD LICENSE
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -359,15 +359,139 @@ void qat_alg_init_common_hdr(struct
icp_qat_fw_comn_req_hdr *header)
ICP_QAT_FW_LA_NO_UPDATE_STATE);
}
-int qat_alg_aead_session_create_content_desc(struct qat_session *cdesc,
- uint8_t *cipherkey, uint32_t cipherkeylen,
- uint8_t *authkey, uint32_t authkeylen,
- uint32_t add_auth_data_length,
- uint32_t digestsize)
+int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
+ uint8_t *cipherkey,
+ uint32_t cipherkeylen)
{
- struct qat_alg_cd *content_desc = &cdesc->cd;
- struct icp_qat_hw_cipher_algo_blk *cipher = &content_desc->cipher;
- struct icp_qat_hw_auth_algo_blk *hash = &content_desc->hash;
+ struct icp_qat_hw_cipher_algo_blk *cipher;
+ struct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req;
+ struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
+ struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
+ void *ptr = &req_tmpl->cd_ctrl;
+ struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
+ struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;
+ enum icp_qat_hw_cipher_convert key_convert;
+ uint16_t proto = ICP_QAT_FW_LA_NO_PROTO;/* no CCM
[dpdk-dev] [PATCH v2 0/3] Snow3G support for Intel Quick Assist Devices
This patchset contains fixes and refactoring for Snow3G(UEA2 and UIA2) wireless algorithm for Intel Quick Assist devices. QAT PMD previously supported only cipher/hash alg-chaining for AES/SHA. The code has been refactored to also support cipher-only and hash only (for Snow3G only) functionality along with alg-chaining. Changes from v1: 1) Hash only fix and alg chainging fix 2) Added hash test vectors for snow3g UIA2 functionality. This patchset depends on Cryptodev API changes http://dpdk.org/ml/archives/dev/2016-February/033551.html Deepak Kumar JAIN (3): crypto: add cipher/auth only support qat: add support for Snow3G app/test: add Snow3G tests app/test/test_cryptodev.c | 1037 +++- app/test/test_cryptodev.h |3 +- app/test/test_cryptodev_snow3g_hash_test_vectors.h | 415 app/test/test_cryptodev_snow3g_test_vectors.h | 379 +++ doc/guides/cryptodevs/qat.rst |8 +- doc/guides/rel_notes/release_16_04.rst |4 + drivers/crypto/qat/qat_adf/qat_algs.h | 19 +- drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 280 +- drivers/crypto/qat/qat_crypto.c| 147 ++- drivers/crypto/qat/qat_crypto.h| 10 + 10 files changed, 2228 insertions(+), 74 deletions(-) create mode 100644 app/test/test_cryptodev_snow3g_hash_test_vectors.h create mode 100644 app/test/test_cryptodev_snow3g_test_vectors.h -- 2.1.0
[dpdk-dev] [PATCH 3/3] app/test: add Snow3G UEA2 tests
Added encryption and decryption tests with input test vectors
from Snow3G UEA2 specifications.
Signed-off-by: Deepak Kumar JAIN
---
app/test/test_cryptodev.c | 318 -
app/test/test_cryptodev.h | 2 +-
app/test/test_cryptodev_snow3g_test_vectors.h | 323 ++
3 files changed, 641 insertions(+), 2 deletions(-)
create mode 100644 app/test/test_cryptodev_snow3g_test_vectors.h
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index fd5b7ec..0809b0f 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -1,7 +1,7 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2015 Intel Corporation. All rights reserved.
+ * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -43,6 +43,7 @@
#include "test.h"
#include "test_cryptodev.h"
+#include "test_cryptodev_snow3g_test_vectors.h"
static enum rte_cryptodev_type gbl_cryptodev_type;
@@ -188,6 +189,23 @@ testsuite_setup(void)
}
}
+ /* Create 2 Snow3G devices if required */
+ if (gbl_cryptodev_type == RTE_CRYPTODEV_SNOW3G_PMD) {
+ nb_devs = rte_cryptodev_count_devtype(RTE_CRYPTODEV_SNOW3G_PMD);
+ if (nb_devs < 2) {
+ for (i = nb_devs; i < 2; i++) {
+ int dev_id =
+
rte_eal_vdev_init(CRYPTODEV_NAME_SNOW3G_PMD,
+ NULL);
+
+ TEST_ASSERT(dev_id >= 0,
+ "Failed to create instance %u of"
+ " pmd : %s",
+ i, CRYPTODEV_NAME_SNOW3G_PMD);
+ }
+ }
+ }
+
nb_devs = rte_cryptodev_count();
if (nb_devs < 1) {
RTE_LOG(ERR, USER1, "No crypto devices found?");
@@ -1681,7 +1699,283 @@ test_AES_CBC_HMAC_AES_XCBC_decrypt_digest_verify(void)
return TEST_SUCCESS;
}
+/* * Snow3G Tests * */
+static int
+create_snow3g_cipher_session(uint8_t dev_id,
+ enum rte_crypto_cipher_operation op,
+ const uint8_t *key, const uint8_t key_len)
+{
+ uint8_t cipher_key[key_len];
+
+ struct crypto_unittest_params *ut_params = &unittest_params;
+
+ memcpy(cipher_key, key, key_len);
+
+ /* Setup Cipher Parameters */
+ ut_params->cipher_xform.type = RTE_CRYPTO_XFORM_CIPHER;
+ ut_params->cipher_xform.next = NULL;
+
+ ut_params->cipher_xform.cipher.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2;
+ ut_params->cipher_xform.cipher.op = op;
+ ut_params->cipher_xform.cipher.key.data = cipher_key;
+ ut_params->cipher_xform.cipher.key.length = key_len;
+
+#ifdef RTE_APP_TEST_DEBUG
+ rte_hexdump(stdout, "key:", key, key_len);
+#endif
+ /* Create Crypto session */
+ ut_params->sess = rte_cryptodev_session_create(dev_id,
+ &ut_params->
+ cipher_xform);
+
+ TEST_ASSERT_NOT_NULL(ut_params->sess, "Session creation failed");
+
+ return 0;
+}
+
+static int
+create_snow3g_cipher_operation(const uint8_t *iv, const unsigned iv_len,
+ const unsigned data_len)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ struct crypto_unittest_params *ut_params = &unittest_params;
+
+ unsigned iv_pad_len = 0;
+
+ /* Generate Crypto op data structure */
+ ut_params->ol = rte_pktmbuf_offload_alloc(ts_params->mbuf_ol_pool,
+ RTE_PKTMBUF_OL_CRYPTO);
+ TEST_ASSERT_NOT_NULL(ut_params->ol,
+"Failed to allocate pktmbuf offload");
+
+ ut_params->op = &ut_params->ol->op.crypto;
+
+ /* iv */
+ iv_pad_len = RTE_ALIGN_CEIL(iv_len, 16);
+
+ ut_params->op->iv.data =
+ (uint8_t *) rte_pktmbuf_prepend(ut_params->ibuf, iv_pad_len);
+ TEST_ASSERT_NOT_NULL(ut_params->op->iv.data, "no room to prepend iv");
+
+ memset(ut_params->op->iv.data, 0, iv_pad_len);
+ ut_params->op->iv.phys_addr = rte_pktmbuf_mtophys(ut_params->ibuf);
+ ut_params->op->iv.length = iv_pad_len;
+
+ rte_memcpy(ut_params->op->iv.data, iv, iv_len);
+
+ rte_hexdump(stdout, "iv:", ut_params->op->iv.data, iv_pad_len);
+ ut_params->op->data.to_cipher.length = data_len;
+ ut_params->op->data.to
[dpdk-dev] [PATCH 2/3] qat: add Snow3G UEA2 support
Added support for wireless Snow3G cipher only,
for the Intel Quick Assist device.
Signed-off-by: Deepak Kumar JAIN
---
doc/guides/cryptodevs/qat.rst| 5 +++--
doc/guides/rel_notes/release_2_3.rst | 1 +
drivers/crypto/qat/qat_adf/qat_algs.h| 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 12
drivers/crypto/qat/qat_crypto.c | 8
5 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 1901842..eda5de2 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -1,5 +1,5 @@
.. BSD LICENSE
-Copyright(c) 2015 Intel Corporation. All rights reserved.
+Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
@@ -47,6 +47,7 @@ Cipher algorithms:
* ``RTE_CRYPTO_SYM_CIPHER_AES128_CBC``
* ``RTE_CRYPTO_SYM_CIPHER_AES192_CBC``
* ``RTE_CRYPTO_SYM_CIPHER_AES256_CBC``
+* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2``
Hash algorithms:
@@ -61,7 +62,7 @@ Limitations
* Chained mbufs are not supported.
* Hash only is not supported.
-* Cipher only is not supported.
+* Cipher only is not supported except Snow3G UEA2.
* Only in-place is currently supported (destination address is the same as
source address).
* Only supports the session-oriented API implementation (session-less APIs are
not supported).
* Not performance tuned.
diff --git a/doc/guides/rel_notes/release_2_3.rst
b/doc/guides/rel_notes/release_2_3.rst
index 99de186..0e1f1ff 100644
--- a/doc/guides/rel_notes/release_2_3.rst
+++ b/doc/guides/rel_notes/release_2_3.rst
@@ -3,6 +3,7 @@ DPDK Release 2.3
New Features
+* **Added the support of Snow3g UEA2 Cipher operation for Intel Quick Assist
Devices.*
Resolved Issues
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index d4aa087..54eeb23 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -127,5 +127,6 @@ void qat_alg_ablkcipher_init_dec(struct
qat_alg_ablkcipher_cd *cd,
unsigned int keylen);
int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
+int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
#endif
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 88fd803..200371d 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -755,3 +755,15 @@ int qat_alg_validate_aes_key(int key_len, enum
icp_qat_hw_cipher_algo *alg)
}
return 0;
}
+
+int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
+{
+ switch (key_len) {
+ case ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ:
+ *alg = ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index e524638..9ae6715 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -168,6 +168,14 @@ qat_crypto_sym_configure_session_cipher(struct
rte_cryptodev *dev,
}
session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
break;
+ case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
+ if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
+ &session->qat_cipher_alg) != 0) {
+ PMD_DRV_LOG(ERR, "Invalid SNOW3G cipher key size");
+ goto error_out;
+ }
+ session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
+ break;
case RTE_CRYPTO_CIPHER_NULL:
case RTE_CRYPTO_CIPHER_3DES_ECB:
case RTE_CRYPTO_CIPHER_3DES_CBC:
--
2.1.0
[dpdk-dev] [PATCH 1/3] crypto: add cipher/auth only support
Refactored the existing functionality into
modular form to support the cipher/auth only
functionalities.
Signed-off-by: Deepak Kumar JAIN
---
drivers/crypto/qat/qat_adf/qat_algs.h| 20 ++-
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 206 ---
drivers/crypto/qat/qat_crypto.c | 136 +++
drivers/crypto/qat/qat_crypto.h | 12 +-
4 files changed, 308 insertions(+), 66 deletions(-)
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index 76c08c0..d4aa087 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -3,7 +3,7 @@
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -17,7 +17,7 @@
* qat-linux at intel.com
*
* BSD LICENSE
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -104,11 +104,17 @@ struct qat_alg_ablkcipher_cd {
int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg);
-int qat_alg_aead_session_create_content_desc(struct qat_session *cd,
- uint8_t *enckey, uint32_t enckeylen,
- uint8_t *authkey, uint32_t authkeylen,
- uint32_t add_auth_data_length,
- uint32_t digestsize);
+int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cd,
+ uint8_t *enckey,
+ uint32_t enckeylen);
+
+int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
+ uint8_t *cipherkey,
+ uint32_t cipherkeylen,
+ uint8_t *authkey,
+ uint32_t authkeylen,
+ uint32_t add_auth_data_length,
+ uint32_t digestsize);
void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header);
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index ceaffb7..88fd803 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -3,7 +3,7 @@
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -17,7 +17,7 @@
* qat-linux at intel.com
*
* BSD LICENSE
- * Copyright(c) 2015 Intel Corporation.
+ * Copyright(c) 2015-2016 Intel Corporation.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -359,15 +359,141 @@ void qat_alg_init_common_hdr(struct
icp_qat_fw_comn_req_hdr *header)
ICP_QAT_FW_LA_NO_UPDATE_STATE);
}
-int qat_alg_aead_session_create_content_desc(struct qat_session *cdesc,
- uint8_t *cipherkey, uint32_t cipherkeylen,
- uint8_t *authkey, uint32_t authkeylen,
- uint32_t add_auth_data_length,
- uint32_t digestsize)
+int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
+ uint8_t *cipherkey,
+ uint32_t cipherkeylen)
{
- struct qat_alg_cd *content_desc = &cdesc->cd;
- struct icp_qat_hw_cipher_algo_blk *cipher = &content_desc->cipher;
- struct icp_qat_hw_auth_algo_blk *hash = &content_desc->hash;
+ struct icp_qat_hw_cipher_algo_blk *cipher;
+ struct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req;
+ struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
+ struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
+ void *ptr = &req_tmpl->cd_ctrl;
+ struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
+ struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_c
[dpdk-dev] [PATCH 0/3] Snow3G UEA2 support for Intel Quick Assist Devices
This patchset contains support for snow3g UEA2 wireless algorithm for Intel Quick Assist devices. (cipher-only) ? QAT PMD previously supported only cipher/hash chaining for AES/SHA. The code has been refactored to also support cipher-only functionality for Snow3g algorithms. Cipher/hash only functionality is only supported for Snow3g and not for AES/SHA. Deepak Kumar JAIN (3): crypto: add cipher/auth only support qat: add Snow3G UEA2 support app/test: add Snow3G UEA2 tests app/test/test_cryptodev.c| 318 +- app/test/test_cryptodev.h| 2 +- app/test/test_cryptodev_snow3g_test_vectors.h| 323 +++ doc/guides/cryptodevs/qat.rst| 5 +- doc/guides/rel_notes/release_2_3.rst | 1 + drivers/crypto/qat/qat_adf/qat_algs.h| 21 +- drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 218 +-- drivers/crypto/qat/qat_crypto.c | 144 +++--- drivers/crypto/qat/qat_crypto.h | 12 +- 9 files changed, 974 insertions(+), 70 deletions(-) create mode 100644 app/test/test_cryptodev_snow3g_test_vectors.h -- 2.1.0
