[dpdk-dev] [PATCH 6/7] virtio: fix pci accesses for ppc64 in legacy mode

[Olivier Matz]

Hi David,

On 05/13/2016 04:28 PM, David Marchand wrote:
>> +#ifdef RTE_ARCH_PPC_64
>> +   switch (length) {
>> +   case 4:
>> +   *(uint32_t *)dst = rte_be_to_cpu_32(*(uint32_t *)dst);
>> +   break;
>> +   case 2:
>> +   *(uint16_t *)dst = rte_be_to_cpu_16(*(uint16_t *)dst);
>> +   break;
>> +   default:
>> +   break;
>> +   }
>> +#endif
>>  }
> 
> I think that, in the original patch, I was handling lengths different
> than 1, 2 and 4 ;-)
> Idem for write.

Oh oh, spotted :)
I'll fix that in the v2.

[dpdk-dev] [PATCH 6/7] virtio: fix pci accesses for ppc64 in legacy mode

[David Marchand]

Hello Olivier,

On Fri, May 13, 2016 at 2:50 PM, Olivier Matz  wrote:
> From: David Marchand 
>
> Although ppc supports both endianesses, qemu supposes that the cpu is
> big endian and enforces this for the virtio-net stuff.
>
> Fix PCI accesses in legacy mode. Only ppc64le is supported at the moment.
>
> Signed-off-by: David Marchand 
> Signed-off-by: Olivier Matz 
> ---
>  drivers/net/virtio/virtio_pci.c | 44 
> +
>  1 file changed, 44 insertions(+)
>
> diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c
> index 9cdca06..bdb89fd 100644
> --- a/drivers/net/virtio/virtio_pci.c
> +++ b/drivers/net/virtio/virtio_pci.c
> @@ -55,18 +55,62 @@
>   */
>  #define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20)
>
> +/*
> + * Since we are in legacy mode:
> + * http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf
> + *
> + * "Note that this is possible because while the virtio header is PCI (i.e.
> + * little) endian, the device-specific region is encoded in the native 
> endian of
> + * the guest (where such distinction is applicable)."
> + *
> + * For powerpc which supports both, qemu supposes that cpu is big endian and
> + * enforces this for the virtio-net stuff.
> + */
> +
>  static void
>  legacy_read_dev_config(struct virtio_hw *hw, size_t offset,
>void *dst, int length)
>  {
> rte_eal_pci_ioport_read(>io, dst, length,
> VIRTIO_PCI_CONFIG(hw) + offset);
> +#ifdef RTE_ARCH_PPC_64
> +   switch (length) {
> +   case 4:
> +   *(uint32_t *)dst = rte_be_to_cpu_32(*(uint32_t *)dst);
> +   break;
> +   case 2:
> +   *(uint16_t *)dst = rte_be_to_cpu_16(*(uint16_t *)dst);
> +   break;
> +   default:
> +   break;
> +   }
> +#endif
>  }

I think that, in the original patch, I was handling lengths different
than 1, 2 and 4 ;-)
Idem for write.


-- 
David Marchand

[dpdk-dev] [PATCH 6/7] virtio: fix pci accesses for ppc64 in legacy mode

[Olivier Matz]

From: David Marchand 

Although ppc supports both endianesses, qemu supposes that the cpu is
big endian and enforces this for the virtio-net stuff.

Fix PCI accesses in legacy mode. Only ppc64le is supported at the moment.

Signed-off-by: David Marchand 
Signed-off-by: Olivier Matz 
---
 drivers/net/virtio/virtio_pci.c | 44 +
 1 file changed, 44 insertions(+)

diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c
index 9cdca06..bdb89fd 100644
--- a/drivers/net/virtio/virtio_pci.c
+++ b/drivers/net/virtio/virtio_pci.c
@@ -55,18 +55,62 @@
  */
 #define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20)

+/*
+ * Since we are in legacy mode:
+ * http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf
+ *
+ * "Note that this is possible because while the virtio header is PCI (i.e.
+ * little) endian, the device-specific region is encoded in the native endian 
of
+ * the guest (where such distinction is applicable)."
+ *
+ * For powerpc which supports both, qemu supposes that cpu is big endian and
+ * enforces this for the virtio-net stuff.
+ */
+
 static void
 legacy_read_dev_config(struct virtio_hw *hw, size_t offset,
   void *dst, int length)
 {
rte_eal_pci_ioport_read(>io, dst, length,
VIRTIO_PCI_CONFIG(hw) + offset);
+#ifdef RTE_ARCH_PPC_64
+   switch (length) {
+   case 4:
+   *(uint32_t *)dst = rte_be_to_cpu_32(*(uint32_t *)dst);
+   break;
+   case 2:
+   *(uint16_t *)dst = rte_be_to_cpu_16(*(uint16_t *)dst);
+   break;
+   default:
+   break;
+   }
+#endif
 }

 static void
 legacy_write_dev_config(struct virtio_hw *hw, size_t offset,
const void *src, int length)
 {
+#ifdef RTE_ARCH_PPC_64
+   union {
+   uint32_t u32;
+   uint16_t u16;
+   } tmp;
+   switch (length) {
+   case 4:
+   tmp.u32 = *(const uint32_t *)src;
+   tmp.u32 = rte_cpu_to_be_32(tmp.u32);
+   src = 
+   break;
+   case 2:
+   tmp.u16 = *(const uint16_t *)src;
+   tmp.u16 = rte_cpu_to_be_16(tmp.u16);
+   src = 
+   break;
+   default:
+   break;
+   }
+#endif
rte_eal_pci_ioport_write(>io, src, length,
 VIRTIO_PCI_CONFIG(hw) + offset);
 }
-- 
2.8.0.rc3