Hi, I'm very interested in getting accurate timestamps for received packets. What is the best way to do it? I found here: http://www.wand.net.nz/trac/libtrace/browser/Intel%20DPDK%20Patches/ some patch to enable timestamping but only on e1000 driver (and honestly I don't know if that patch works with latest DPDK version!)
I have tried using the timesync feature of DPDK 2.1.0 but I never get valid RX timestamp: in my app using DPDK I call rte_eth_timesync_enable() at config time and then later when a packet arrives I call rte_eth_timesync_read_tx_timestamp(). Here's what I get: .... Aug 28 11:07:48 MSP101 HwEmul[19774]: EAL: PCI memory mapped at 0x7fff80080000 Aug 28 11:07:48 MSP101 HwEmul[19774]: EAL: PCI memory mapped at 0x7fff80100000 Aug 28 11:07:48 MSP101 HwEmul[19774]: PMD: eth_ixgbe_dev_init(): MAC: 2, PHY: 18, SFP+: 5 Aug 28 11:07:48 MSP101 HwEmul[19774]: PMD: eth_ixgbe_dev_init(): port 2 vendorID=0x8086 deviceID=0x10fb Aug 28 11:07:48 MSP101 HwEmul[19774]: EAL: PCI device 0000:86:00.1 on NUMA socket 1 Aug 28 11:07:48 MSP101 HwEmul[19774]: EAL: probe driver: 8086:10fb rte_ixgbe_pmd Aug 28 11:07:48 MSP101 HwEmul[19774]: EAL: PCI memory mapped at 0x7fff80104000 Aug 28 11:07:48 MSP101 HwEmul[19774]: EAL: PCI memory mapped at 0x7fff80184000 Aug 28 11:07:48 MSP101 HwEmul[19774]: PMD: eth_ixgbe_dev_init(): MAC: 2, PHY: 15, SFP+: 10 Aug 28 11:07:48 MSP101 HwEmul[19774]: PMD: eth_ixgbe_dev_init(): port 3 vendorID=0x8086 deviceID=0x10fb .... Aug 28 11:07:51 MSP101 HwEmul[19774]: PMD: eth_em_rx_queue_setup(): sw_ring=0x7fff62f9cfc0 hw_ring=0x7fff62f9d4c0 dma_addr=0x17a2f9d4c0 Aug 28 11:07:51 MSP101 HwEmul[19774]: PMD: eth_em_tx_queue_setup(): sw_ring=0x7fff62f8ca80 hw_ring=0x7fff62f8cf80 dma_addr=0x17a2f8cf80 Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: eth_em_start(): << Aug 28 11:07:52 MSP101 HwEmul[19774]: ERROR HwEmulCaptureDPDK::init() rte_eth_timesync_enable:err=-95, port=0: Unknown error -95 Aug 28 11:07:52 MSP101 HwEmul[19774]: ALERT HwEmulCaptureDPDK::init() Initializing port 1... Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: eth_em_rx_queue_setup(): sw_ring=0x7fff62f7c440 hw_ring=0x7fff62f7c940 dma_addr=0x17a2f7c940 Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: eth_em_tx_queue_setup(): sw_ring=0x7fff62f6bf00 hw_ring=0x7fff62f6c400 dma_addr=0x17a2f6c400 Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: eth_em_start(): << Aug 28 11:07:52 MSP101 HwEmul[19774]: ERROR HwEmulCaptureDPDK::init() rte_eth_timesync_enable:err=-95, port=1: Unknown error -95 Aug 28 11:07:52 MSP101 HwEmul[19774]: ALERT HwEmulCaptureDPDK::init() Initializing port 2... Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: ixgbe_dev_rx_queue_setup(): sw_ring=0x7ffebffef6c0 sw_sc_ring=0x7ffebffef180 hw_ring=0x7ffebffefc00 dma_addr=0x2fbffefc00 Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: ixgbe_dev_tx_queue_setup(): sw_ring=0x7ffebffdebc0 hw_ring=0x7ffebffdf000 dma_addr=0x2fbffdf000 Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: ixgbe_set_tx_function(): Using simple tx code path Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: ixgbe_set_tx_function(): Vector tx enabled. Aug 28 11:09:06 MSP101 HwEmul[19774]: PMD: ixgbe_set_rx_function(): Port[2] doesn't meet Vector Rx preconditions or RTE_IXGBE_INC_VECTOR is not enabled Aug 28 11:09:06 MSP101 HwEmul[19774]: PMD: ixgbe_set_rx_function(): Rx Burst Bulk Alloc Preconditions are satisfied. Rx Burst Bulk Alloc function will be used on port=2. Aug 28 11:09:07 MSP101 HwEmul[19774]: PMD: ixgbe_dev_rx_queue_setup(): sw_ring=0x7ffebffce2c0 sw_sc_ring=0x7ffebffcdd80 hw_ring=0x7ffebffce800 dma_addr=0x2fbffce800 Aug 28 11:09:07 MSP101 HwEmul[19774]: PMD: ixgbe_dev_tx_queue_setup(): sw_ring=0x7ffebffbd7c0 hw_ring=0x7ffebffbdc00 dma_addr=0x2fbffbdc00 Aug 28 11:09:07 MSP101 HwEmul[19774]: PMD: ixgbe_set_tx_function(): Using simple tx code path Aug 28 11:09:07 MSP101 HwEmul[19774]: PMD: ixgbe_set_tx_function(): Vector tx enabled. Aug 28 11:09:09 MSP101 HwEmul[19774]: PMD: ixgbe_set_rx_function(): Port[3] doesn't meet Vector Rx preconditions or RTE_IXGBE_INC_VECTOR is not enabled Aug 28 11:09:09 MSP101 HwEmul[19774]: PMD: ixgbe_set_rx_function(): Rx Burst Bulk Alloc Preconditions are satisfied. Rx Burst Bulk Alloc function will be used on port=3. Here rte_eth_timesync_enable() failed on 2 ports (they are 1G Intel ports) and is successful on other 2 ports. But then when I send 1 packet on the port with timesync enabled I get an error from rte_eth_timesync_read_tx_timestamp(): Aug 28 13:23:18 MSP101 HwEmul[25381]: [25416] ERROR Port 3 RX timestamp registers not valid: -22 Does the port need IEEE1588 messages in order to setup its timestamp registers? Can I use IEEE1588 to just get some timestamp from the NIC (ideally, I would like to have 1timestamp for each received packet)? Thanks a lot, Francesco Montorsi