Re: fcntl F_SETLK, F_SETLKW, F_GETLK
Cool. Is there a possibility to share your work via PM? This way I can test the solution on my side also. Jernej On Tue, Feb 20, 2024 at 8:23 AM Xiang Xiao wrote: > We have implemented file lock to support the database engine like sqlite > and unqlite. The implementation will go upstream soon. > > On Tue, Feb 20, 2024 at 3:04 PM Jernej Turnsek > wrote: > > > Hi, > > I would like to use Sqlite on NuttX and I have managed to successfully > > build the Sqlite3 library. When running the library, I have noticed that > > Sqlite is using fcntl F_SETLK and F_SETLKW for locking and those are not > > implemented on NuttX. Is there a plan to implement this in the future? > > > > Regards, > > Jernej > > >
Re: fcntl F_SETLK, F_SETLKW, F_GETLK
We have implemented file lock to support the database engine like sqlite and unqlite. The implementation will go upstream soon. On Tue, Feb 20, 2024 at 3:04 PM Jernej Turnsek wrote: > Hi, > I would like to use Sqlite on NuttX and I have managed to successfully > build the Sqlite3 library. When running the library, I have noticed that > Sqlite is using fcntl F_SETLK and F_SETLKW for locking and those are not > implemented on NuttX. Is there a plan to implement this in the future? > > Regards, > Jernej >
Assert macro causing problems when building Sqlite
Hi, the same problem as new UNUSED macro was causing me problems when building external libraries, like LuaJIT, an assert macro is also causing problems when building Sqlite3 library. Sqlite code has a lot of assert statements which are usually excluded when NDEBUG is set. But when assert is defined as: #ifdef NDEBUG # define assert(f) ((void)(1 || (f))) # define VERIFY(f) assert(f) #else compiler throws undefined variable errors all the time. With simple (void)0 definition there is no problem. Yet another reason to evaluate this change of UNUSED and assert macro? Jernej
fcntl F_SETLK, F_SETLKW, F_GETLK
Hi, I would like to use Sqlite on NuttX and I have managed to successfully build the Sqlite3 library. When running the library, I have noticed that Sqlite is using fcntl F_SETLK and F_SETLKW for locking and those are not implemented on NuttX. Is there a plan to implement this in the future? Regards, Jernej
Re: Better FPGA support on NuttX //was Re: [OT] Projects for GSoC 2024
Reference to cheap FPGA boards (< $20) were added to the new repo, more docs will follow there: https://github.com/cederom/nuttx-fpga So, FPGA is not strictly related to $$$
Re: [OT] Projects for GSoC 2024
FPGA development boards are indeed not cheap, as the chips themselves are expensive. But those of us who are in the field know some solutions. Indeed I'm working on designing a low cost FPGA board right now. Until mine is ready, a useful alternative is to reuse some mass marketed products that are cheap, like LED controllers boards. This one for example cost $11.50 and includes SDRAM and ethernet: https://www.ledcontrollercard.com/english/colorlight-n6-led-mini-receiving-card.html Best, Victor
Re: [OT] Projects for GSoC 2024
Okay, this may be too complex and too early, true I also had lots of issues and was not able to work on my FreeBSD with Open-Source only tools, lets start step by step from simple things first then more complex ones, will try again with NuttX+FPGA funding next round, thank you guys, I will be in touch with Victor he does amazing things with FPGA it would be really nice to have him in our team :-) -- CeDeROM, SQ7MHZ, http://www.tomek.cedro.info On Mon, Feb 19, 2024 at 5:09 PM Alan C. Assis wrote: > > Hi Victor, > > Yes, as I said before I also think this is a very important field, but at > least for this chinese board I realized that things are not there yet. > > Maybe using a Lattice FPGA could work better, but anyway, a good FPGA board > to run a RISC-V is not too low cost. > > Tang Primer 20K is lower cost, but the open-source tools are not that great. > > I found a good discussion here: > https://www.reddit.com/r/RISCV/comments/z9v6f8/which_fpga_for_getting_into_riscv/ > > Someone suggested ULX3S as a good board to work with open-source tools, but > the board version with Lattice ECP5 85F costs more than U$ 300 on > Aliexpress. > > That is not a low cost for someone that just wants to try an FPGA. > > Best Regards, > > Alan > > On Mon, Feb 19, 2024 at 12:08 PM Victor Suarez Rovere < > suarezvic...@gmail.com> wrote: > > > Hi > > I have experience doing FPGA development including graphics (micropython > > port, ImGUI port, USB mouse/keyboard etc.) > > I think the open-source tool ecosystem for FPGA development is mature > > enough not to depend on proprietary tools and IP, mainly related to Lattice > > devices but also for most Xilinx devices. > > And I fully agree with what Tomek said in every aspect with regards to the > > convenience of mailined FPGA support. > > > > Best, > > Victor. > > > > > > > > On Mon, Feb 19, 2024 at 11:50 AM Alan C. Assis wrote: > > > > > No, as we pointed out, it is a long term project that needs to be well > > > thought out. > > > > > > You listed many possibilities, we need to define a goal and focus on it. > > > > > > Let me share my (bad) experience with FPGA: > > > Sometime ago I bought a low cost Tang Primer 20K board expecting to start > > > using open-source tools to program it (many places said it was > > supported). > > > > > > Then when I installed the software I discovered that I need to download > > the > > > proprietary SDK and copy many files from it to get things working. > > > > > > It was a show stopper for me! > > > > > > Imagine if you wanted to compile NuttX and had to download the vendor SDK > > > and copy their files to inside NuttX. > > > > > > Best Regards, > > > > > > Alan > > > > > > On Sun, Feb 18, 2024 at 8:02 PM Tomek CEDRO wrote: > > > > > > > Closed, okay, and the FPGA part did not get in? > > > > > > > > -- > > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info > > > > > > > > On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis > > > wrote: > > > > > > > > > > Hi Tomek, > > > > > Thank you for raising these concerns. > > > > > > > > > > BTW, I suggest you change the Subject to something related to NuttX > > and > > > > > FPGA, since the GSoC 2024 proposal is already closed (on Feb 6). > > > > > > > > > > Best Regards, > > > > > > > > > > Alan > > > > > > > > > > On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO > > wrote: > > > > > > > > > > > After some more considerations I am pro this "generic" NuttX@FPGA > > > > > > Reference Design on GSoC proposal, 10 resons below :-) > > > > > > > > > > > > I kindly ask to add this one to the proposals list :-) > > > > > > > > > > > > 1. We do not have a reference FPGA design for NuttX. > > > > > > 2. We do not have a reference fully Open-Source toolchain for > > > > FPGA+NuttX. > > > > > > 3. Yes someone did that before, and anyone can do that, but we can > > > > > > provide generic out-of-the-box solution that most people are > > looking > > > > > > for. Creating / repeating one yourself costs time. > > > > > > 4. We can gather smart community around NuttX that way (i.e. > > Victor). > > > > > > 5. FPGA are getting smaller and cheaper close to a price range of > > MCU > > > > > > (i.e. $5+) [1][2]. > > > > > > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO > > > > > > nMHz vs nnnMHz). I can see unique benefit for having custom > > > > > > peripherals created that way. I once did an R on new type of ADC > > > > > > where MCU GPIO was not fast enough and I have to switch to FPGA + > > > > > > external control MCU board. > > > > > > 7. Using propietary tools was quite painful because I had to use > > big > > > > > > Xilinx Vivado while there are fully Open-Source toolchains already > > > out > > > > > > there we can use like Yosys / OSS CAD Suite [3] etc. > > > > > > 8. Scaling to bigger FPGA gives more possibilities like new > > > > > > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of > > cores) > > > > > > [4], emulation [5], machine learning, etc. > > > > > > 9. My initial
Better FPGA support on NuttX //was Re: [OT] Projects for GSoC 2024
Let's follow the discussion here to avoid polluting the previous thread. On 2/18/24, Tomek CEDRO wrote: > Closed, okay, and the FPGA part did not get in? > > -- > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info > > On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis wrote: >> >> Hi Tomek, >> Thank you for raising these concerns. >> >> BTW, I suggest you change the Subject to something related to NuttX and >> FPGA, since the GSoC 2024 proposal is already closed (on Feb 6). >> >> Best Regards, >> >> Alan >> >> On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO wrote: >> >> > After some more considerations I am pro this "generic" NuttX@FPGA >> > Reference Design on GSoC proposal, 10 resons below :-) >> > >> > I kindly ask to add this one to the proposals list :-) >> > >> > 1. We do not have a reference FPGA design for NuttX. >> > 2. We do not have a reference fully Open-Source toolchain for >> > FPGA+NuttX. >> > 3. Yes someone did that before, and anyone can do that, but we can >> > provide generic out-of-the-box solution that most people are looking >> > for. Creating / repeating one yourself costs time. >> > 4. We can gather smart community around NuttX that way (i.e. Victor). >> > 5. FPGA are getting smaller and cheaper close to a price range of MCU >> > (i.e. $5+) [1][2]. >> > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO >> > nMHz vs nnnMHz). I can see unique benefit for having custom >> > peripherals created that way. I once did an R on new type of ADC >> > where MCU GPIO was not fast enough and I have to switch to FPGA + >> > external control MCU board. >> > 7. Using propietary tools was quite painful because I had to use big >> > Xilinx Vivado while there are fully Open-Source toolchains already out >> > there we can use like Yosys / OSS CAD Suite [3] etc. >> > 8. Scaling to bigger FPGA gives more possibilities like new >> > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of cores) >> > [4], emulation [5], machine learning, etc. >> > 9. My initial proposal was highly experimental and could easily fail. >> > Victor's proposal is merit and result based. It will for sure serve >> > many people out there for bigger and smaller projects. >> > 10. Other ideas like Xorg port could be tested on FPGA implementation >> > too.. I already saw Victor's working windows manager with >> > chip-mod-player running on FPGA :-) >> > >> > I can be mentor of that project because I would like to grow in that >> > field too as I have some ideas to test :-) >> > >> > Thanks for considering :-) >> > Tomek >> > >> > [1] https://tinyfpga.com/ >> > [2] >> > https://www.cnx-software.com/2019/10/15/5-tang-nano-fpga-board-gowin-gw1n-littlebee-fpga/ >> > [3] https://github.com/YosysHQ/oss-cad-suite-build >> > [4] >> > https://riscv.org/news/2021/08/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator-sally-ward-foxton-ee-times/ >> > [5] https://www.retrorgb.com/mister.html >> > >> > -- >> > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info >> > >> > On Sat, Jan 27, 2024 at 10:58 PM Victor Suarez Rovere >> > wrote: >> > > >> > > The innovation won't be to run NuttX in a RISC-V (soft-core or not) >> > > but >> > > using a FPGA for its flexibility to add any kind of peripherals, one >> > > of >> > the >> > > main ones to be useful in my view will be a high-resolution >> > > framebuffer >> > and >> > > USB mouse/keyboard for a complete UI >> > > >> > > On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt >> > wrote: >> > > >> > > > Aren't most CPUs available as soft cores? Certainly Xtensa was >> > intended >> > > > for that purpose. ARM and MIPS have been common soft cores in >> > > > ASICs >> > for >> > > > more than a decade. As is RISC-V soft core in FPGAs. >> > > > https://en.wikipedia.org/wiki/Soft_microprocessor >> > > > >> > > > In the past, there was some interest in ports of NuttX to >> > > > softcore's >> > > > like MicroBlaze. But there hasn't been that kind of interest in >> > > > recent >> > > > times. >> > > > >> > > > This would have been an innovation a decade or so ago, but I wonder >> > > > about that now. >> > > > >> > > > >> > > > >> > > > On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote: >> > > > > Tomek, as I clarified, porting NuttX to a FPGA will require a >> > soft-core >> > > > > CPU. I don't envision an opertaing system without a CPU, I see >> > > > > that >> > like >> > > > a >> > > > > bad design choice if possible at all >> > > > > Using a soft core and custom peripherals seems more valuable, >> > > > > even >> > > > > including video output and USB host for mouse/keyboard handling. >> > > > > I've >> > > > done >> > > > > that for Micropython >> > > > > >> > > > > El sáb., 27 ene. 2024 13:23, Tomek CEDRO >> > escribió: >> > > > > >> > > > >> Okay Victor, I was thinking about toolchain that you present in >> > > > >> "Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA >> > > > >> conversion >> > > > >> without a CPU design.. could you please send your full detailed >> > >
Re: [OT] Projects for GSoC 2024
Hi Victor, Yes, as I said before I also think this is a very important field, but at least for this chinese board I realized that things are not there yet. Maybe using a Lattice FPGA could work better, but anyway, a good FPGA board to run a RISC-V is not too low cost. Tang Primer 20K is lower cost, but the open-source tools are not that great. I found a good discussion here: https://www.reddit.com/r/RISCV/comments/z9v6f8/which_fpga_for_getting_into_riscv/ Someone suggested ULX3S as a good board to work with open-source tools, but the board version with Lattice ECP5 85F costs more than U$ 300 on Aliexpress. That is not a low cost for someone that just wants to try an FPGA. Best Regards, Alan On Mon, Feb 19, 2024 at 12:08 PM Victor Suarez Rovere < suarezvic...@gmail.com> wrote: > Hi > I have experience doing FPGA development including graphics (micropython > port, ImGUI port, USB mouse/keyboard etc.) > I think the open-source tool ecosystem for FPGA development is mature > enough not to depend on proprietary tools and IP, mainly related to Lattice > devices but also for most Xilinx devices. > And I fully agree with what Tomek said in every aspect with regards to the > convenience of mailined FPGA support. > > Best, > Victor. > > > > On Mon, Feb 19, 2024 at 11:50 AM Alan C. Assis wrote: > > > No, as we pointed out, it is a long term project that needs to be well > > thought out. > > > > You listed many possibilities, we need to define a goal and focus on it. > > > > Let me share my (bad) experience with FPGA: > > Sometime ago I bought a low cost Tang Primer 20K board expecting to start > > using open-source tools to program it (many places said it was > supported). > > > > Then when I installed the software I discovered that I need to download > the > > proprietary SDK and copy many files from it to get things working. > > > > It was a show stopper for me! > > > > Imagine if you wanted to compile NuttX and had to download the vendor SDK > > and copy their files to inside NuttX. > > > > Best Regards, > > > > Alan > > > > On Sun, Feb 18, 2024 at 8:02 PM Tomek CEDRO wrote: > > > > > Closed, okay, and the FPGA part did not get in? > > > > > > -- > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info > > > > > > On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis > > wrote: > > > > > > > > Hi Tomek, > > > > Thank you for raising these concerns. > > > > > > > > BTW, I suggest you change the Subject to something related to NuttX > and > > > > FPGA, since the GSoC 2024 proposal is already closed (on Feb 6). > > > > > > > > Best Regards, > > > > > > > > Alan > > > > > > > > On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO > wrote: > > > > > > > > > After some more considerations I am pro this "generic" NuttX@FPGA > > > > > Reference Design on GSoC proposal, 10 resons below :-) > > > > > > > > > > I kindly ask to add this one to the proposals list :-) > > > > > > > > > > 1. We do not have a reference FPGA design for NuttX. > > > > > 2. We do not have a reference fully Open-Source toolchain for > > > FPGA+NuttX. > > > > > 3. Yes someone did that before, and anyone can do that, but we can > > > > > provide generic out-of-the-box solution that most people are > looking > > > > > for. Creating / repeating one yourself costs time. > > > > > 4. We can gather smart community around NuttX that way (i.e. > Victor). > > > > > 5. FPGA are getting smaller and cheaper close to a price range of > MCU > > > > > (i.e. $5+) [1][2]. > > > > > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO > > > > > nMHz vs nnnMHz). I can see unique benefit for having custom > > > > > peripherals created that way. I once did an R on new type of ADC > > > > > where MCU GPIO was not fast enough and I have to switch to FPGA + > > > > > external control MCU board. > > > > > 7. Using propietary tools was quite painful because I had to use > big > > > > > Xilinx Vivado while there are fully Open-Source toolchains already > > out > > > > > there we can use like Yosys / OSS CAD Suite [3] etc. > > > > > 8. Scaling to bigger FPGA gives more possibilities like new > > > > > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of > cores) > > > > > [4], emulation [5], machine learning, etc. > > > > > 9. My initial proposal was highly experimental and could easily > fail. > > > > > Victor's proposal is merit and result based. It will for sure serve > > > > > many people out there for bigger and smaller projects. > > > > > 10. Other ideas like Xorg port could be tested on FPGA > implementation > > > > > too.. I already saw Victor's working windows manager with > > > > > chip-mod-player running on FPGA :-) > > > > > > > > > > I can be mentor of that project because I would like to grow in > that > > > > > field too as I have some ideas to test :-) > > > > > > > > > > Thanks for considering :-) > > > > > Tomek > > > > > > > > > > [1] https://tinyfpga.com/ > > > > > [2] > > > > > > > > > > >
Re: [OT] Projects for GSoC 2024
Hi I have experience doing FPGA development including graphics (micropython port, ImGUI port, USB mouse/keyboard etc.) I think the open-source tool ecosystem for FPGA development is mature enough not to depend on proprietary tools and IP, mainly related to Lattice devices but also for most Xilinx devices. And I fully agree with what Tomek said in every aspect with regards to the convenience of mailined FPGA support. Best, Victor. On Mon, Feb 19, 2024 at 11:50 AM Alan C. Assis wrote: > No, as we pointed out, it is a long term project that needs to be well > thought out. > > You listed many possibilities, we need to define a goal and focus on it. > > Let me share my (bad) experience with FPGA: > Sometime ago I bought a low cost Tang Primer 20K board expecting to start > using open-source tools to program it (many places said it was supported). > > Then when I installed the software I discovered that I need to download the > proprietary SDK and copy many files from it to get things working. > > It was a show stopper for me! > > Imagine if you wanted to compile NuttX and had to download the vendor SDK > and copy their files to inside NuttX. > > Best Regards, > > Alan > > On Sun, Feb 18, 2024 at 8:02 PM Tomek CEDRO wrote: > > > Closed, okay, and the FPGA part did not get in? > > > > -- > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info > > > > On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis > wrote: > > > > > > Hi Tomek, > > > Thank you for raising these concerns. > > > > > > BTW, I suggest you change the Subject to something related to NuttX and > > > FPGA, since the GSoC 2024 proposal is already closed (on Feb 6). > > > > > > Best Regards, > > > > > > Alan > > > > > > On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO wrote: > > > > > > > After some more considerations I am pro this "generic" NuttX@FPGA > > > > Reference Design on GSoC proposal, 10 resons below :-) > > > > > > > > I kindly ask to add this one to the proposals list :-) > > > > > > > > 1. We do not have a reference FPGA design for NuttX. > > > > 2. We do not have a reference fully Open-Source toolchain for > > FPGA+NuttX. > > > > 3. Yes someone did that before, and anyone can do that, but we can > > > > provide generic out-of-the-box solution that most people are looking > > > > for. Creating / repeating one yourself costs time. > > > > 4. We can gather smart community around NuttX that way (i.e. Victor). > > > > 5. FPGA are getting smaller and cheaper close to a price range of MCU > > > > (i.e. $5+) [1][2]. > > > > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO > > > > nMHz vs nnnMHz). I can see unique benefit for having custom > > > > peripherals created that way. I once did an R on new type of ADC > > > > where MCU GPIO was not fast enough and I have to switch to FPGA + > > > > external control MCU board. > > > > 7. Using propietary tools was quite painful because I had to use big > > > > Xilinx Vivado while there are fully Open-Source toolchains already > out > > > > there we can use like Yosys / OSS CAD Suite [3] etc. > > > > 8. Scaling to bigger FPGA gives more possibilities like new > > > > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of cores) > > > > [4], emulation [5], machine learning, etc. > > > > 9. My initial proposal was highly experimental and could easily fail. > > > > Victor's proposal is merit and result based. It will for sure serve > > > > many people out there for bigger and smaller projects. > > > > 10. Other ideas like Xorg port could be tested on FPGA implementation > > > > too.. I already saw Victor's working windows manager with > > > > chip-mod-player running on FPGA :-) > > > > > > > > I can be mentor of that project because I would like to grow in that > > > > field too as I have some ideas to test :-) > > > > > > > > Thanks for considering :-) > > > > Tomek > > > > > > > > [1] https://tinyfpga.com/ > > > > [2] > > > > > > > https://www.cnx-software.com/2019/10/15/5-tang-nano-fpga-board-gowin-gw1n-littlebee-fpga/ > > > > [3] https://github.com/YosysHQ/oss-cad-suite-build > > > > [4] > > > > > > > https://riscv.org/news/2021/08/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator-sally-ward-foxton-ee-times/ > > > > [5] https://www.retrorgb.com/mister.html > > > > > > > > -- > > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info > > > > > > > > On Sat, Jan 27, 2024 at 10:58 PM Victor Suarez Rovere > > > > wrote: > > > > > > > > > > The innovation won't be to run NuttX in a RISC-V (soft-core or not) > > but > > > > > using a FPGA for its flexibility to add any kind of peripherals, > one > > of > > > > the > > > > > main ones to be useful in my view will be a high-resolution > > framebuffer > > > > and > > > > > USB mouse/keyboard for a complete UI > > > > > > > > > > On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt > > > > wrote: > > > > > > > > > > > Aren't most CPUs available as soft cores? Certainly Xtensa was > > > > intended > > > > > > for that purpose. ARM and
Re: [OT] Projects for GSoC 2024
Tomek, The list with all GSoC 2024 from Apache Foundation is here: https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list Until now we have two contributors interested in participating, but we proposed 6 projects. Best Regards, Alan On Sun, Feb 18, 2024 at 8:02 PM Tomek CEDRO wrote: > Closed, okay, and the FPGA part did not get in? > > -- > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info > > On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis wrote: > > > > Hi Tomek, > > Thank you for raising these concerns. > > > > BTW, I suggest you change the Subject to something related to NuttX and > > FPGA, since the GSoC 2024 proposal is already closed (on Feb 6). > > > > Best Regards, > > > > Alan > > > > On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO wrote: > > > > > After some more considerations I am pro this "generic" NuttX@FPGA > > > Reference Design on GSoC proposal, 10 resons below :-) > > > > > > I kindly ask to add this one to the proposals list :-) > > > > > > 1. We do not have a reference FPGA design for NuttX. > > > 2. We do not have a reference fully Open-Source toolchain for > FPGA+NuttX. > > > 3. Yes someone did that before, and anyone can do that, but we can > > > provide generic out-of-the-box solution that most people are looking > > > for. Creating / repeating one yourself costs time. > > > 4. We can gather smart community around NuttX that way (i.e. Victor). > > > 5. FPGA are getting smaller and cheaper close to a price range of MCU > > > (i.e. $5+) [1][2]. > > > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO > > > nMHz vs nnnMHz). I can see unique benefit for having custom > > > peripherals created that way. I once did an R on new type of ADC > > > where MCU GPIO was not fast enough and I have to switch to FPGA + > > > external control MCU board. > > > 7. Using propietary tools was quite painful because I had to use big > > > Xilinx Vivado while there are fully Open-Source toolchains already out > > > there we can use like Yosys / OSS CAD Suite [3] etc. > > > 8. Scaling to bigger FPGA gives more possibilities like new > > > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of cores) > > > [4], emulation [5], machine learning, etc. > > > 9. My initial proposal was highly experimental and could easily fail. > > > Victor's proposal is merit and result based. It will for sure serve > > > many people out there for bigger and smaller projects. > > > 10. Other ideas like Xorg port could be tested on FPGA implementation > > > too.. I already saw Victor's working windows manager with > > > chip-mod-player running on FPGA :-) > > > > > > I can be mentor of that project because I would like to grow in that > > > field too as I have some ideas to test :-) > > > > > > Thanks for considering :-) > > > Tomek > > > > > > [1] https://tinyfpga.com/ > > > [2] > > > > https://www.cnx-software.com/2019/10/15/5-tang-nano-fpga-board-gowin-gw1n-littlebee-fpga/ > > > [3] https://github.com/YosysHQ/oss-cad-suite-build > > > [4] > > > > https://riscv.org/news/2021/08/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator-sally-ward-foxton-ee-times/ > > > [5] https://www.retrorgb.com/mister.html > > > > > > -- > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info > > > > > > On Sat, Jan 27, 2024 at 10:58 PM Victor Suarez Rovere > > > wrote: > > > > > > > > The innovation won't be to run NuttX in a RISC-V (soft-core or not) > but > > > > using a FPGA for its flexibility to add any kind of peripherals, one > of > > > the > > > > main ones to be useful in my view will be a high-resolution > framebuffer > > > and > > > > USB mouse/keyboard for a complete UI > > > > > > > > On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt > > > wrote: > > > > > > > > > Aren't most CPUs available as soft cores? Certainly Xtensa was > > > intended > > > > > for that purpose. ARM and MIPS have been common soft cores in > ASICs > > > for > > > > > more than a decade. As is RISC-V soft core in FPGAs. > > > > > https://en.wikipedia.org/wiki/Soft_microprocessor > > > > > > > > > > In the past, there was some interest in ports of NuttX to > softcore's > > > > > like MicroBlaze. But there hasn't been that kind of interest in > recent > > > > > times. > > > > > > > > > > This would have been an innovation a decade or so ago, but I wonder > > > > > about that now. > > > > > > > > > > > > > > > > > > > > On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote: > > > > > > Tomek, as I clarified, porting NuttX to a FPGA will require a > > > soft-core > > > > > > CPU. I don't envision an opertaing system without a CPU, I see > that > > > like > > > > > a > > > > > > bad design choice if possible at all > > > > > > Using a soft core and custom peripherals seems more valuable, > even > > > > > > including video output and USB host for mouse/keyboard handling. > I've > > > > > done > > > > > > that for Micropython > > > > > > > > > > > > El sáb., 27 ene. 2024 13:23, Tomek CEDRO > > > escribió: > > > > > > > >
Re: [OT] Projects for GSoC 2024
No, as we pointed out, it is a long term project that needs to be well thought out. You listed many possibilities, we need to define a goal and focus on it. Let me share my (bad) experience with FPGA: Sometime ago I bought a low cost Tang Primer 20K board expecting to start using open-source tools to program it (many places said it was supported). Then when I installed the software I discovered that I need to download the proprietary SDK and copy many files from it to get things working. It was a show stopper for me! Imagine if you wanted to compile NuttX and had to download the vendor SDK and copy their files to inside NuttX. Best Regards, Alan On Sun, Feb 18, 2024 at 8:02 PM Tomek CEDRO wrote: > Closed, okay, and the FPGA part did not get in? > > -- > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info > > On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis wrote: > > > > Hi Tomek, > > Thank you for raising these concerns. > > > > BTW, I suggest you change the Subject to something related to NuttX and > > FPGA, since the GSoC 2024 proposal is already closed (on Feb 6). > > > > Best Regards, > > > > Alan > > > > On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO wrote: > > > > > After some more considerations I am pro this "generic" NuttX@FPGA > > > Reference Design on GSoC proposal, 10 resons below :-) > > > > > > I kindly ask to add this one to the proposals list :-) > > > > > > 1. We do not have a reference FPGA design for NuttX. > > > 2. We do not have a reference fully Open-Source toolchain for > FPGA+NuttX. > > > 3. Yes someone did that before, and anyone can do that, but we can > > > provide generic out-of-the-box solution that most people are looking > > > for. Creating / repeating one yourself costs time. > > > 4. We can gather smart community around NuttX that way (i.e. Victor). > > > 5. FPGA are getting smaller and cheaper close to a price range of MCU > > > (i.e. $5+) [1][2]. > > > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO > > > nMHz vs nnnMHz). I can see unique benefit for having custom > > > peripherals created that way. I once did an R on new type of ADC > > > where MCU GPIO was not fast enough and I have to switch to FPGA + > > > external control MCU board. > > > 7. Using propietary tools was quite painful because I had to use big > > > Xilinx Vivado while there are fully Open-Source toolchains already out > > > there we can use like Yosys / OSS CAD Suite [3] etc. > > > 8. Scaling to bigger FPGA gives more possibilities like new > > > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of cores) > > > [4], emulation [5], machine learning, etc. > > > 9. My initial proposal was highly experimental and could easily fail. > > > Victor's proposal is merit and result based. It will for sure serve > > > many people out there for bigger and smaller projects. > > > 10. Other ideas like Xorg port could be tested on FPGA implementation > > > too.. I already saw Victor's working windows manager with > > > chip-mod-player running on FPGA :-) > > > > > > I can be mentor of that project because I would like to grow in that > > > field too as I have some ideas to test :-) > > > > > > Thanks for considering :-) > > > Tomek > > > > > > [1] https://tinyfpga.com/ > > > [2] > > > > https://www.cnx-software.com/2019/10/15/5-tang-nano-fpga-board-gowin-gw1n-littlebee-fpga/ > > > [3] https://github.com/YosysHQ/oss-cad-suite-build > > > [4] > > > > https://riscv.org/news/2021/08/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator-sally-ward-foxton-ee-times/ > > > [5] https://www.retrorgb.com/mister.html > > > > > > -- > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info > > > > > > On Sat, Jan 27, 2024 at 10:58 PM Victor Suarez Rovere > > > wrote: > > > > > > > > The innovation won't be to run NuttX in a RISC-V (soft-core or not) > but > > > > using a FPGA for its flexibility to add any kind of peripherals, one > of > > > the > > > > main ones to be useful in my view will be a high-resolution > framebuffer > > > and > > > > USB mouse/keyboard for a complete UI > > > > > > > > On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt > > > wrote: > > > > > > > > > Aren't most CPUs available as soft cores? Certainly Xtensa was > > > intended > > > > > for that purpose. ARM and MIPS have been common soft cores in > ASICs > > > for > > > > > more than a decade. As is RISC-V soft core in FPGAs. > > > > > https://en.wikipedia.org/wiki/Soft_microprocessor > > > > > > > > > > In the past, there was some interest in ports of NuttX to > softcore's > > > > > like MicroBlaze. But there hasn't been that kind of interest in > recent > > > > > times. > > > > > > > > > > This would have been an innovation a decade or so ago, but I wonder > > > > > about that now. > > > > > > > > > > > > > > > > > > > > On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote: > > > > > > Tomek, as I clarified, porting NuttX to a FPGA will require a > > > soft-core > > > > > > CPU. I don't envision an opertaing system
