Re: [edk2-devel] [PATCH v6 2/4] SourceLevelDebugPkg: SourceLevelDebugPkg.dsc add UefiCpuLib LibraryClass

[Wu, Hao A]

> -Original Message-
> From: Garrett Kirkendall 
> Sent: Monday, June 22, 2020 9:18 PM
> To: devel@edk2.groups.io
> Cc: Wu, Hao A 
> Subject: [PATCH v6 2/4] SourceLevelDebugPkg: SourceLevelDebugPkg.dsc
> add UefiCpuLib LibraryClass
> 
> In preparation for moving StandardSignatureIsAuthenticAMD to UefiCpuLib
> in UefiCpuPkg, SourceLevelDebugPkg/SourceLevelDebugPkg.dsc needs
> LibraryClass UefiCpuLib.
> LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf will need
> UefiCpuLib LibraryClass.  Likely most "real" platforms will be using
> BaseX2XApicLib instance which already required UefiCpuLib.
> 
> Cc: Hao A Wu 
> Signed-off-by: Garrett Kirkendall 
> ---
>  SourceLevelDebugPkg/SourceLevelDebugPkg.dsc | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/SourceLevelDebugPkg/SourceLevelDebugPkg.dsc
> b/SourceLevelDebugPkg/SourceLevelDebugPkg.dsc
> index a1a1b81d03cb..20eb10ba07f8 100644
> --- a/SourceLevelDebugPkg/SourceLevelDebugPkg.dsc
> +++ b/SourceLevelDebugPkg/SourceLevelDebugPkg.dsc
> @@ -2,6 +2,7 @@
>  # Source Level Debug Package.
>  #
>  # Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2020, AMD Incorporated. All rights reserved.
>  #
>  #SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> @@ -32,6 +33,7 @@ [LibraryClasses.common]
>IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> 
> SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniz
> ationLib.inf
>LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
> +  UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf


Really sorry for the delayed response.
Reviewed-by: Hao A Wu 

Best Regards,
Hao Wu


> 
> PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BaseP
> eCoffGetEntryPointLib.inf
> 
> SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPor
> tLib16550.inf
> 
> PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibD
> ebug/PeCoffExtraActionLibDebug.inf
> --
> 2.27.0


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Re: [edk2-devel] [PATCH v6 3/4] UefiCpuPkg: Move StandardSignatureIsAuthenticAMD to BaseUefiCpuLib

[Dong, Eric]

Reviewed-by: Eric Dong 

> -Original Message-
> From: Garrett Kirkendall 
> Sent: Monday, June 22, 2020 9:18 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Laszlo
> Ersek 
> Subject: [PATCH v6 3/4] UefiCpuPkg: Move
> StandardSignatureIsAuthenticAMD to BaseUefiCpuLib
> 
> Refactor StandardSignatureIsAuthenticAMD into BaseUefiCpuLib from
> separate copies in BaseXApicLib, BaseXApicX2ApicLib, and MpInitLib.
> This allows for future use of StandarSignatureIsAuthinticAMD without
> creating more instances in other modules.
> 
> This function allows IA32/X64 code to determine if it is running on an AMD
> brand processor.
> 
> UefiCpuLib is already included directly or indirectly in all modified modules.
> Complete move is made in this change.
> 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Laszlo Ersek 
> Signed-off-by: Garrett Kirkendall 
> Reviewed-by: Laszlo Ersek 
> Reviewed-by: Eric Dong 
> ---
>  UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf |  7 
>  UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf |  2 ++
>  UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf |  2 ++
>  UefiCpuPkg/Include/Library/UefiCpuLib.h  | 14 
>  UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c   | 38
> 
>  UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c   | 25 
> ++---
>  UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c   | 25 ++--
> -
>  UefiCpuPkg/Library/MpInitLib/MpLib.c | 23 
> 
>  8 files changed, 67 insertions(+), 69 deletions(-)
> 
> diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
> b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
> index 006b7acbf14e..34d3a7bb4303 100644
> --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
> +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
> @@ -4,6 +4,7 @@
>  #  The library routines are UEFI specification compliant.
>  #
>  #  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
> +#  Copyright (c) 2020, AMD Inc. All rights reserved.
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent  #  ## @@ -29,6 +30,12 @@
> [Sources.IA32]  [Sources.X64]
>X64/InitializeFpu.nasm
> 
> +[Sources]
> +  BaseUefiCpuLib.c
> +
>  [Packages]
>MdePkg/MdePkg.dec
>UefiCpuPkg/UefiCpuPkg.dec
> +
> +[LibraryClasses]
> +  BaseLib
> diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
> b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
> index bdb2ff372677..561baa44b0e6 100644
> --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
> +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
> @@ -5,6 +5,7 @@
>  #  where local APIC is disabled.
>  #
>  #  Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
> +#  Copyright (c) 2020, AMD Inc. All rights reserved.
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent  #  ## @@ -37,6 +38,7 @@
> [LibraryClasses]
>TimerLib
>IoLib
>PcdLib
> +  UefiCpuLib
> 
>  [Pcd]
>gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds  ##
> SOMETIMES_CONSUMES diff --git
> a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
> b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
> index ac1e0a1c9896..1e2a4f8b790f 100644
> --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
> +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
> @@ -5,6 +5,7 @@
>  #  where local APIC is disabled.
>  #
>  #  Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
> +#  Copyright (c) 2020, AMD Inc. All rights reserved.
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent  #  ## @@ -37,6 +38,7 @@
> [LibraryClasses]
>TimerLib
>IoLib
>PcdLib
> +  UefiCpuLib
> 
>  [Pcd]
>gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds  ##
> SOMETIMES_CONSUMES diff --git
> a/UefiCpuPkg/Include/Library/UefiCpuLib.h
> b/UefiCpuPkg/Include/Library/UefiCpuLib.h
> index 82e53bab3a0f..5326e7246301 100644
> --- a/UefiCpuPkg/Include/Library/UefiCpuLib.h
> +++ b/UefiCpuPkg/Include/Library/UefiCpuLib.h
> @@ -5,6 +5,7 @@
>to be UEFI specification compliant.
> 
>Copyright (c) 2009, Intel Corporation. All rights reserved.
> +  Copyright (c) 2020, AMD Inc. All rights reserved.
>SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  **/
> @@ -29,4 +30,17 @@ InitializeFloatingPointUnits (
>VOID
>);
> 
> +/**
> +  Determine if the standard CPU signature is "AuthenticAMD".
> +
> +  @retval TRUE  The CPU signature matches.
> +  @retval FALSE The CPU signature does not match.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +StandardSignatureIsAuthenticAMD (
> +  VOID
> +  );
> +
>  #endif
> diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
> b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
> new file mode 100644
> index ..c2cc3ff9a709
> --- /dev/null
> +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
> @@ -0,0 +1,38 @@
> +/** @file
> +  This li

Re: [edk2-devel] [PATCH v6 4/4] UefiCpuPkg: PiSmmCpuDxeSmm skip MSR_IA32_MISC_ENABLE manipulation on AMD

[Dong, Eric]

Reviewed-by: Eric Dong 

> -Original Message-
> From: Garrett Kirkendall 
> Sent: Monday, June 22, 2020 9:18 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Laszlo
> Ersek 
> Subject: [PATCH v6 4/4] UefiCpuPkg: PiSmmCpuDxeSmm skip
> MSR_IA32_MISC_ENABLE manipulation on AMD
> 
> AMD does not support MSR_IA32_MISC_ENABLE.  Accessing that register
> causes and exception on AMD processors.  If Execution Disable is supported,
> but if the processor is an AMD processor, skip manipulating
> MSR_IA32_MISC_ENABLE[34] XD Disable bit.
> 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Laszlo Ersek 
> Signed-off-by: Garrett Kirkendall 
> ---
> 
> Notes:
> Tested on Intel hardware with Laszlo Ersek's help
> 
> (1) downloaded two Linux images from provided links.
> (2) Test using a 32-bit guest on an Intel host (standing in your edk2 
> tree,
> with the patches applied):
> 
> $ build -a IA32 -b DEBUG -p OvmfPkg/OvmfPkgIa32.dsc -t GCC5 -D
> SMM_REQUIRE
> 
> $ qemu-system-i386 \
> -cpu coreduo,-nx \
> -machine q35,smm=on,accel=kvm \
> -m 4096 \
> -smp 4 \
> -global driver=cfi.pflash01,property=secure,value=on \
> -drive
> if=pflash,format=raw,unit=0,readonly=on,file=Build/OvmfIa32/DEBUG_GCC
> 5/FV/OVMF_CODE.fd \
> -drive
> if=pflash,format=raw,unit=1,snapshot=on,file=Build/OvmfIa32/DEBUG_GCC
> 5/FV/OVMF_VARS.fd \
> -drive id=hdd,if=none,format=qcow2,snapshot=on,file=fedora-30-efi-
> systemd-i686.qcow2 \
> -device virtio-scsi-pci,id=scsi0 \
> -device scsi-hd,drive=hdd,bus=scsi0.0,bootindex=1
> 
> (Once you get a login prompt, feel free to interrupt QEMU with Ctrl-C.)
> 
> (3) Test using a 64-bit guest on an Intel host:
> 
> $ build -a IA32 -a X64 -b DEBUG -p OvmfPkg/OvmfPkgIa32X64.dsc -t GCC5 -
> D SMM_REQUIRE
> 
> $ qemu-system-x86_64 \
> -cpu host \
> -machine q35,smm=on,accel=kvm \
> -m 4096 \
> -smp 4 \
> -global driver=cfi.pflash01,property=secure,value=on \
> -drive
> if=pflash,format=raw,unit=0,readonly=on,file=Build/Ovmf3264/DEBUG_GCC
> 5/FV/OVMF_CODE.fd \
> -drive
> if=pflash,format=raw,unit=1,snapshot=on,file=Build/Ovmf3264/DEBUG_GCC
> 5/FV/OVMF_VARS.fd \
> -drive id=hdd,if=none,format=qcow2,snapshot=on,file=fedora-31-efi-
> grub2-x86_64.qcow2 \
> -device virtio-scsi-pci,id=scsi0 \
> -device scsi-hd,drive=hdd,bus=scsi0.0,bootindex=1
> 
> Tested on real AMD Hardware
> 
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h |  3 +++
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c |  9 -
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm   | 19
> +--
>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm| 20
> ++--
>  4 files changed, 46 insertions(+), 5 deletions(-)
> 
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
> b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
> index 43f6935cf9dc..993360a8a8c1 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
> @@ -2,6 +2,7 @@
>  SMM profile internal header file.
> 
>  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2020, AMD Incorporated. All rights reserved.
>  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  **/
> @@ -13,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent  #include
> 
>  #include   #include 
> +#include 
>  #include 
> 
>  #include "SmmProfileArch.h"
> @@ -99,6 +101,7 @@ extern SMM_S3_RESUME_STATE
> *mSmmS3ResumeState;
>  extern UINTN gSmiExceptionHandlers[];
>  extern BOOLEAN   mXdSupported;
>  X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported;
> +X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported;
>  extern UINTN *mPFEntryCount;
>  extern UINT64(*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
>  extern UINT64*(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
> index c47b5573e366..d7ed9ab7a770 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
> @@ -2,7 +2,7 @@
>  Enable SMM profile.
> 
>  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved. -
> Copyright (c) 2017, AMD Incorporated. All rights reserved.
> +Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.
> 
>  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> @@ -1015,6 +1015,13 @@ CheckFeatureSupported (
>mXdSupported = FALSE;
>PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1);
>  }
> +
> +if (StandardSignatureIsAuthenticAMD ()) {
> +  //
> +  // AMD processors do not support MSR_IA32_MISC_ENABLE
> +  //
> +  PatchInstructionX86 (gPatchMsrIa32MiscEnableSupported, FALSE, 1);
> +}
>}
> 
>if (mBtsSupported) {
> diff --git 

Re: [edk2-devel] [PATCH v6 0/4] AMD processor MSR_IA32_MISC_ENABLE

[Dong, Eric]

Hi Laszlo,

I have fixed the issue reported by Guomin in below change.

SHA-1: 0060e0a694f3f249c3ec081b0e61287c36f64ebb

* IntelFsp2Pkg/FspSecCore: Use UefiCpuLib.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2825

UefiCpuLib has API InitializeFloatingPointUnits.
Remove internal copy of InitializeFloatingPointUnits
in FspSecCoreM, use UefiCpuLib API.

This change also avoid later potential conflict when
use UefiCpuLib for FspSecCoreM module.

Signed-off-by: Eric Dong 
Reviewed-by: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 

Thanks,
Eric
From: Laszlo Ersek 
Sent: Wednesday, June 24, 2020 4:54 PM
To: Kirkendall, Garrett ; devel@edk2.groups.io
Cc: Dong, Eric ; Ni, Ray ; Wu, Hao A 
; Jiang, Guomin 
Subject: Re: [edk2-devel] [PATCH v6 0/4] AMD processor MSR_IA32_MISC_ENABLE

On 06/24/20 03:04, Kirkendall, Garrett wrote:
> [AMD Public Use]
>
> Is there anything else needed from me for this patch at this time?

I think we still have an open question here:

  https://edk2.groups.io/g/devel/message/61583

To clarify: I'm not suggesting that we should fix that issue. I'm saying
that we should *understand* Guomin's report enough so we can decide
*whether* this series needs a further update, or not.

If there is no feedback (clarification) from Guomin in a few days, I
think Eric or Ray (the UefiCpuPkg maintainers) should merge v6 -- for
example, on Friday.

Thanks,
Laszlo

>
> GARRETT KIRKENDALL
> SMTS Firmware Engineer | CTE
> 7171 Southwest Parkway, Austin, TX 78735 USA
> AMD   facebook  |  amd.com
>
> -Original Message-
> From: devel@edk2.groups.io 
> mailto:devel@edk2.groups.io>> On Behalf Of Kirkendall, 
> Garrett via groups.io
> Sent: Monday, June 22, 2020 8:18 AM
> To: devel@edk2.groups.io
> Cc: Eric Dong mailto:eric.d...@intel.com>>; Ray Ni 
> mailto:ray...@intel.com>>; Laszlo Ersek 
> mailto:ler...@redhat.com>>; Hao A Wu 
> mailto:hao.a...@intel.com>>
> Subject: [edk2-devel] [PATCH v6 0/4] AMD processor MSR_IA32_MISC_ENABLE
>
> [CAUTION: External Email]
>
> AMD processor does not support MSR_IA32_MISC_ENABLE register.  Accessing this 
> register on AMD causes an unhandled exception in SmmEntry.nasm and a 
> subsequent failure to boot since this is too early in SMM path for the 
> exception handler to be loaded.
>
> 1. Prepare PcAtChipsetPkg/PcAtChipsetPkg.dsc to move 
> StandardSignatureIsAuthenticAMD into UefiCpuLib LibraryClass BaseUefiCpuLib 
> in UefiCpuPkg.
>
> 2. To distinguish between AMD and other processors, refactor 
> StandardSignatureIsAuthenticAMD into BaseUefiCpuLib.  So there is only one 
> copy in the source.
>
> 3. Skip manipulation of MSR_IA32_MISC_ENABLE register if running on an AMD 
> processor.
>
> Tested on AMD X64 hardware.
> OvmfIa32 and OvmfIa32X64 on Intel hardware.
>
> v1: Move StandardSignatureIsAuthenticAMD. Handle MSR_IA32_MISC_ENABLE
> v2: Incorporate Laszlo's feedback
> v3: Typo, not sent
> v4: Patch in to add UefiCpuLib to PcAtChipsetPkg.dsc
> v5: Patch in to add UefiCpuLib to SourceLevelDebugPkg.dsc
> v6: Hopefully reformat patch when sending
>
> Garrett Kirkendall (4):
>   PcAtChipsetPkg: PcAtChipsetPkg.dsc add UefiCpuLib LibraryClass
>   SourceLevelDebugPkg: SourceLevelDebugPkg.dsc add UefiCpuLib
> LibraryClass
>   UefiCpuPkg: Move StandardSignatureIsAuthenticAMD to BaseUefiCpuLib
>   UefiCpuPkg: PiSmmCpuDxeSmm skip MSR_IA32_MISC_ENABLE manipulation on
> AMD
>
>  PcAtChipsetPkg/PcAtChipsetPkg.dsc|  2 ++
>  SourceLevelDebugPkg/SourceLevelDebugPkg.dsc  |  2 ++
>  UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf |  7 
>  UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf |  2 ++
>  UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf |  2 ++
>  UefiCpuPkg/Include/Library/UefiCpuLib.h  | 14 
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h   |  3 ++
>  UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c   | 38 
> 
>  UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c   | 25 
> ++---
>  UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c   | 25 
> ++---
>  UefiCpuPkg/Library/MpInitLib/MpLib.c | 23 
> 
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c   |  9 -
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 19 --
>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm  | 20 +--
>  14 files changed, 117 insertions(+), 74 deletions(-)  create mode 100644 
> UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
>
> Changes at:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fgkirkendall-amd%2Fedk2%2Ftree%2Fsmmentry_nasm_skip_msr_xd_bit_on_amd_v6&data=02%7C01%7Cgarrett.kirkendall%40amd.com%7C5b2918ff7a2345a5ce7f08d816af8e23%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637284290553548804&sdata=F9ktro2r

Re: [edk2-devel] [PATCH v7 00/16] Add a plugin to check Ecc issues for edk2 on open ci

[Zhang, Shenglei]

Comments below.

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Leif
> Lindholm
> Sent: Monday, July 6, 2020 4:55 PM
> To: devel@edk2.groups.io; Zhang, Shenglei 
> Cc: Feng, Bob C ; Bret Barkelew
> ; Kinney, Michael D
> ; Gao, Liming ; Sean
> Brogan 
> Subject: Re: [edk2-devel] [PATCH v7 00/16] Add a plugin to check Ecc issues
> for edk2 on open ci
> 
> On Mon, Jul 06, 2020 at 16:48:30 +0800, Zhang, Shenglei wrote:
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2606
> > As planed we will enable Ecc check for edk2 on open ci. And they are
> > ready now. I appreciate receiving feedback and comments if someone
> > find errors or false positive issues.
> >
> > I created a pipline of EccCheck for my forked edk2. Welcome everyone to
> > create pull request to test the quality of this plugin.
> > My forked tree: https://github.com/shenglei10/edk2
> >
> > And I also created some test cases for ECC plugin. Below are test cases.
> > https://github.com/shenglei10/edk2/tree/ECC
> > Results can be view in below azure server.
> >
> https://dev.azure.com/shengleizhang/shengleizhang/_build?definitionId=12
> &_a=summary
> >
> > Patches
> > 1/16: It's a lib necessary for py3 to run Ecc on azure servers.
> >
> > 2/16: EccCheck.py is a plugin to report Ecc issues for commits. It can be 
> > run
> >  on azure servers for open ci, or a local virtual environment.
> >
> > 3/16~16/16: We consider some cases that will report out Ecc issues but they
> won't
> >  be fixed, like submodule and industry standard related things. So we
> >  add two configuration fields "Exception" and "IgnoreFiles" for people
> >  to use. These patches add configuration in yaml files for Ecc check.
> >
> > Cc: Bob Feng 
> > Cc: Bret Barkelew 
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Sean Brogan 
> >
> > v2: Update 1/17, fix the bug that the script can't hanlde multiple commits.
> >
> > v3: Update 1/17, set the only workalbe workspace is edk2 root directory.
> > Update 2/17, designate the version of antlr4 is 4.7.1.
> > Add 4/17~17/17.
> >
> > v4. Update 1/17, remove the function EdksetupRebuild(), instead add
> > function SetupEnvironment(). Update variables' format and type hints
> > to pass flake8 and mypy.
> >
> > v5. Conver the former method to plugin solution, to align with
> > other check points on open ci.
> >
> > v6. The 1/16 patch is missed in v5 series. Now add it in v6.
> >
> > v7. Fix a bug that Ecc plugin can not be run correctly under Linux OS.
> 
> What is the bug? Where is it fixed?

V6 plugin pipeline link:
https://dev.azure.com/shengleizhang/shengleizhang/_build/results?buildId=282&view=logs&j=9b8d87a5-bd93-5358-8ffa-588e312c4376&t=282a77bb-da29-5801-6299-2bbe15d5aabb
v7 plugin pipeline link:
https://dev.azure.com/shengleizhang/shengleizhang/_build/results?buildId=316&view=logs&j=5e3952f2-9c8a-5394-82c1-a803bcab3ca3&t=7ea9e85e-5c3d-5fcf-865e-8449f16cc745

For the same pull request, v6 plugin can't report out the Ecc issues under 
Linux OS.

Thanks,
Shenglei

> 
> /
> Leif
> 
> > Shenglei Zhang (16):
> >   pip-requirements.txt: Add Ecc required lib
> >   .pytool/Plugin: Add a plugin EccCheck
> >   MdeModulePkg/MdeModulePkg.ci.yaml: Add configuration for Ecc check
> >   ArmVirtPkg/ArmVirtPkg.ci.yaml: Add configuration for Ecc check
> >   CryptoPkg/CryptoPkg.ci.yaml: Add configuration for Ecc check
> >   EmulatorPkg/EmulatorPkg.ci.yaml: Add configuration for Ecc check
> >   FatPkg/FatPkg.ci.yaml: Add configuration for Ecc check
> >   FmpDevicePkg/FmpDevicePkg.ci.yaml: Add configuration for Ecc check
> >   MdePkg/MdePkg.ci.yaml: Add configuration for Ecc check
> >   NetworkPkg/NetworkPkg.ci.yaml: Add configuration for Ecc check
> >   OvmfPkg/OvmfPkg.ci.yaml: Add configuration for Ecc check
> >   PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml: Add configuration for Ecc check
> >   SecurityPkg/SecurityPkg.ci.yaml: Add configuration for Ecc check
> >   ShellPkg/ShellPkg.ci.yaml: Add configuration for Ecc check
> >   UefiCpuPkg/UefiCpuPkg.ci.yaml: Add configuration for Ecc check
> >   UnitTestFrameworkPkg: Add configuration for Ecc check in yaml file
> >
> >  .pytool/Plugin/EccCheck/EccCheck.py   | 267 ++
> >  .pytool/Plugin/EccCheck/EccCheck_plug_in.yaml |  11 +
> >  .pytool/Plugin/EccCheck/Readme.md |  15 +
> >  ArmVirtPkg/ArmVirtPkg.ci.yaml |  11 +
> >  CryptoPkg/CryptoPkg.ci.yaml   |  11 +
> >  EmulatorPkg/EmulatorPkg.ci.yaml   |  11 +
> >  FatPkg/FatPkg.ci.yaml |  11 +
> >  FmpDevicePkg/FmpDevicePkg.ci.yaml |  11 +
> >  MdeModulePkg/MdeModulePkg.ci.yaml |  11 +
> >  MdePkg/MdePkg.ci.yaml |  11 +
> >  NetworkPkg/NetworkPkg.ci.yaml |  11 +
> >  OvmfPkg/OvmfPkg.ci.yaml   |  11 +
> >  PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml |  11 +
> >  SecurityPkg/SecurityPkg.ci.yaml  

[edk2-devel] Upcoming Event: TianoCore Bug Triage - APAC / NAMO - Tue, 07/07/2020 6:30pm-7:30pm #cal-reminder

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View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=816015 )

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brian.richard...@intel.com?subject=Re:%20Event:%20TianoCore%20Bug%20Triage%20-%20APAC%20%2F%20NAMO
 )

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Re: [edk2-devel] [PATCH] FmpDevicePkg: Enhance capsule verification with secure boot keys

[Liming Sun]

Thanks Michael. Below is the use case:

- Device vendor provides devices with UEFI preinstalled;
- Customer gets the device in non-secure-boot mode by default, and would like 
to enroll the secure boot keys themselves in some automatic way (such as using 
capsule). 

PcdFmpDevicePkcs7CertBufferXdr is not used for two reasons for this use case:
1. Simplicity. So vendor doesn't need to be involved in the key management, and 
customer could create and sign the capsule themselves.
2. Secure reasons. Once customer fully own the device and put it into 
secure-boot mode, even the capsule from the device vendor couldn't be applied 
without being signed by customer. (The hardcoded PcdFmpDevicePkcs7CertBufferXdr 
couldn't achieve this goal).

Thanks,
Liming

> -Original Message-
> From: Kinney, Michael D 
> Sent: Wednesday, July 1, 2020 1:43 PM
> To: devel@edk2.groups.io; Liming Sun ; Jiang, Guomin 
> ; Xu, Wei6
> ; Gao, Liming ; Kinney, Michael D 
> 
> Cc: Sean Brogan 
> Subject: RE: [edk2-devel] [PATCH] FmpDevicePkg: Enhance capsule verification 
> with secure boot keys
> 
> Liming Sun,
> 
> Can you explain why you cannot use PcdFmpDevicePkcs7CertBufferXdr
> for your use case?  I want to understand the use case to see if
> that feature can be applied or if a minor enhancement to this
> feature can work.
> 
> Using the UEFI Secure Boot DB for anything other than authentication
> of UEFI boot loaders is not recommended.
> 
> Thanks,
> 
> Mike
> 
> > -Original Message-
> > From: devel@edk2.groups.io  On
> > Behalf Of Liming Sun
> > Sent: Wednesday, July 1, 2020 9:27 AM
> > To: Jiang, Guomin ;
> > devel@edk2.groups.io; Xu, Wei6 ; Gao,
> > Liming ; Kinney, Michael D
> > 
> > Cc: Sean Brogan 
> > Subject: Re: [edk2-devel] [PATCH] FmpDevicePkg: Enhance
> > capsule verification with secure boot keys
> >
> > >> But if your customer indeed want it, you can add it
> > to your customization code.
> > Thanks. Yes, this is a behavior customer expects. This
> > change just tries to provide a handy way to enroll
> > initial keys.
> > So the initial keys could be carried in the capsule
> > itself.
> > It also has "PcdFmpDeviceAllowSecureBootKeys" disabled
> > by default, so it behaves the same as before.
> >
> > We'll try to use customization code instead as
> > suggested.
> >
> > Thanks,
> > Liming
> >
> > > -Original Message-
> > > From: Jiang, Guomin 
> > > Sent: Tuesday, June 30, 2020 8:56 PM
> > > To: Liming Sun ;
> > devel@edk2.groups.io; Xu, Wei6 ; Gao,
> > Liming ;
> > > Kinney, Michael D 
> > > Cc: Sean Brogan 
> > > Subject: RE: [edk2-devel] [PATCH] FmpDevicePkg:
> > Enhance capsule verification with secure boot keys
> > >
> > > I want to ask your one question: are you sure that
> > every mother board which deliver to customer will enable
> > the secure boot mode?
> > >
> > > I just emphasize that I want to make sure that the
> > device firmware come from the device vendor.
> > >
> > > Thanks for your effort, the patch is good, I just
> > think it is not suitable for common solution.
> > >
> > > But if your customer indeed want it, you can add it to
> > your customization code.
> > >
> > > Thanks
> > > Guomin
> > >
> > > > -Original Message-
> > > > From: Liming Sun 
> > > > Sent: Tuesday, June 30, 2020 8:47 PM
> > > > To: devel@edk2.groups.io; Jiang, Guomin
> > ; Xu,
> > > > Wei6 ; Gao, Liming
> > ; Kinney,
> > > > Michael D 
> > > > Cc: Sean Brogan 
> > > > Subject: RE: [edk2-devel] [PATCH] FmpDevicePkg:
> > Enhance capsule
> > > > verification with secure boot keys
> > > >
> > > > Thanks Guomin.
> > > >
> > > > I still have one question. Let's assume we're the
> > device vendor and we let
> > > > customer to enroll their keys. Once the keys are
> > enrolled, the device will be
> > > > in secure boot mode. Are you saying that the end
> > user could "have the ability
> > > > to enroll their DB without too many effort" even
> > after the secure boot has
> > > > been enabled already?
> > > >
> > > > Please correct me if I misunderstood it.
> > > >
> > > > - Liming
> > > >
> > > > > -Original Message-
> > > > > From: devel@edk2.groups.io 
> > On Behalf Of
> > > > Guomin
> > > > > Jiang via groups.io
> > > > > Sent: Tuesday, June 30, 2020 3:33 AM
> > > > > To: devel@edk2.groups.io; Liming Sun
> > ; Xu, Wei6
> > > > > ; Gao, Liming
> > ; Kinney,
> > > > > Michael D 
> > > > > Cc: Sean Brogan 
> > > > > Subject: Re: [edk2-devel] [PATCH] FmpDevicePkg:
> > Enhance capsule
> > > > > verification with secure boot keys
> > > > >
> > > > > Liming,
> > > > >
> > > > > The end user have the ability to enroll their DB
> > without too many effort.
> > > > >
> > > > > And I think some end user also have the ability to
> > get insecure firmware
> > > > which not from the device vendor.
> > > > >
> > > > > I suggest that tell the device vendor that it is
> > critical that set the
> > > > PcdFmpDevicePkcs7CertBufferXdr rather than decrease
> > the security.
> > > > >
> > > > > Best Regards
> > > > > 

Re: [edk2-devel] [PATCH v9 06/46] MdePkg/BaseLib: Add support for the XGETBV instruction

[Lendacky, Thomas]

On 7/2/20 9:39 PM, Liu, Zhiguang wrote:
> Hi Tom,

Hi Zhiguang,

> I notice that you create a nasm file, which is good for cross-OS.
> Why do you need to create a c file for the same function for GCC compiler 
> when we can use nasm file in Linux?

I was just following convention. I noticed that many of the instructions
are implemented in both a nasm file and added to the GccInline.c file, so
I did the same. On my Linux builds, the GccInline.c file is used.

Thanks,
Tom

> Thanks
> Zhiguang
> 
> 
>> -Original Message-
>> From: devel@edk2.groups.io  On Behalf Of
>> Lendacky, Thomas
>> Sent: Friday, June 5, 2020 9:27 PM
>> To: devel@edk2.groups.io
>> Cc: Brijesh Singh ; Ard Biesheuvel
>> ; Dong, Eric ; Justen,
>> Jordan L ; Laszlo Ersek ;
>> Gao, Liming ; Kinney, Michael D
>> ; Ni, Ray 
>> Subject: [edk2-devel] [PATCH v9 06/46] MdePkg/BaseLib: Add support for
>> the XGETBV instruction
>>
>> BZ: 
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D2198&data=02%7C01%7Cthomas.lendacky%40amd.com%7C2372d38165954f1aa53908d81efa4f45%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637293407713911481&sdata=DDC3mR7wrER3vL9xKLBKnyrXJRxm4BUqqehksVLieD4%3D&reserved=0
>>
>> Under SEV-ES, a CPUID instruction requires the current value of the XCR0
>> register. In order to retrieve that value, the XGETBV instruction needs
>> to be executed.
>>
>> Provide the necessary support to execute the XGETBV instruction.
>>
>> Cc: Michael D Kinney 
>> Cc: Liming Gao 
>> Signed-off-by: Tom Lendacky 
>> ---
>>  MdePkg/Library/BaseLib/BaseLib.inf  |  2 ++
>>  MdePkg/Include/Library/BaseLib.h| 17 ++
>>  MdePkg/Library/BaseLib/Ia32/GccInline.c | 28 
>>  MdePkg/Library/BaseLib/X64/GccInline.c  | 30 +
>>  MdePkg/Library/BaseLib/Ia32/XGetBv.nasm | 31 ++
>>  MdePkg/Library/BaseLib/X64/XGetBv.nasm  | 34 
>>  6 files changed, 142 insertions(+)
>>
>> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
>> b/MdePkg/Library/BaseLib/BaseLib.inf
>> index a57ae2da31f3..da6bc22a3e2b 100644
>> --- a/MdePkg/Library/BaseLib/BaseLib.inf
>> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
>> @@ -153,6 +153,7 @@ [Sources.Ia32]
>>Ia32/ARShiftU64.c | MSFT
>>
>>
>>Ia32/EnableCache.c | MSFT
>>
>>
>>Ia32/DisableCache.c | MSFT
>>
>>
>> +  Ia32/XGetBv.nasm | MSFT
>>
>>
>>
>>
>>
>>
>>
>>
>>Ia32/GccInline.c | GCC
>>
>>
>> @@ -287,6 +288,7 @@ [Sources.X64]
>>X64/ReadCr2.nasm| MSFT
>>
>>
>>X64/ReadCr0.nasm| MSFT
>>
>>
>>X64/ReadEflags.nasm| MSFT
>>
>>
>> +  X64/XGetBv.nasm | MSFT
>>
>>
>>
>>
>>
>>
>>
>>
>>X64/Non-existing.c
>>
>>
>> diff --git a/MdePkg/Include/Library/BaseLib.h
>> b/MdePkg/Include/Library/BaseLib.h
>> index 8e7b87cbda4e..7edf0051a0a0 100644
>> --- a/MdePkg/Include/Library/BaseLib.h
>> +++ b/MdePkg/Include/Library/BaseLib.h
>> @@ -7831,6 +7831,23 @@ AsmLfence (
>>VOID
>>
>>
>>);
>>
>>
>>
>>
>>
>> +/**
>>
>>
>> +  Executes a XGETBV instruction
>>
>>
>> +
>>
>>
>> +  Executes a XGETBV instruction. This function is only available on IA-32 
>> and
>>
>>
>> +  x64.
>>
>>
>> +
>>
>>
>> +  @param[in] IndexExtended control register index
>>
>>
>> +
>>
>>
>> +  @return The current value of the extended control register
>>
>>
>> +**/
>>
>>
>> +UINT64
>>
>>
>> +EFIAPI
>>
>>
>> +AsmXGetBv (
>>
>>
>> +  IN UINT32  Index
>>
>>
>> +  );
>>
>>
>> +
>>
>>
>> +
>>
>>
>>  /**
>>
>>
>>Patch the immediate operand of an IA32 or X64 instruction such that the
>> byte,
>>
>>
>>word, dword or qword operand is encoded at the end of the instruction's
>>
>>
>> diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c
>> b/MdePkg/Library/BaseLib/Ia32/GccInline.c
>> index 5287200f8754..c962bcfa4617 100644
>> --- a/MdePkg/Library/BaseLib/Ia32/GccInline.c
>> +++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c
>> @@ -1763,3 +1763,31 @@ AsmFlushCacheLine (
>>  }
>>
>>
>>
>>
>>
>>
>>
>>
>> +/**
>>
>>
>> +  Executes a XGETBV instruction
>>
>>
>> +
>>
>>
>> +  Executes a XGETBV instruction. This function is only available on IA-32 
>> and
>>
>>
>> +  x64.
>>
>>
>> +
>>
>>
>> +  @param[in] IndexExtended control register index
>>
>>
>> +
>>
>>
>> +  @return The current value of the extended control register
>>
>>
>> +**/
>>
>>
>> +UINT64
>>
>>
>> +EFIAPI
>>
>>
>> +AsmXGetBv (
>>
>>
>> +  IN UINT32 Index
>>
>>
>> +  )
>>
>>
>> +{
>>
>>
>> +  UINT64 Data;
>>
>>
>> +
>>
>>
>> +  __asm__ __volatile__ (
>>
>>
>> +"xgetbv"
>>
>>
>> +: "=A" (Data)
>>
>>
>> +: "c"  (Index)
>>
>>
>> +);
>>
>>
>> +
>>
>>
>> +  return Data;
>>
>>
>> +}
>>
>>
>> +
>>
>>
>> +
>>
>>
>> diff --git a/MdePkg/Library/BaseLib/X64/GccInline.c
>> b/MdePkg/Library/BaseLib/X64/GccInline.c
>> index 154ce1f57e92..91198f9f 100644
>> --- a/MdePkg/Library/BaseLib/X64/GccInline.c
>> +++ b/MdePkg/Library/BaseLib/X64/GccInline.c
>> @@ -1798,3 +1798,33 @@ AsmFlushCacheLine (
>>  }
>>
>>
>>
>>
>>
>>

Re: [edk2-devel] [PATCH v9 08/46] UefiCpuPkg: Implement library support for VMGEXIT

[Lendacky, Thomas]

On 7/2/20 2:04 AM, Dong, Eric wrote:
> Hi Tom,

Hi Eric,

> 
> We have root cause this Mac file format issue. The patch mail from your side 
> include extra two "=0D=0D" , and our test tool convert them to "\r\r". This 
> is Mac file line ending format. So this issue been reported. We have updated 
> our tool to handle this special case.

Good to know, thanks!

> 
> With that change, now I met below error when use VS2015 tool chain. Can you 
> help to fix it?
> 
> Building ... 
> g:\edk2-open-source\edk2\MdePkg\Library\PeiCoreEntryPoint\PeiCoreEntryPoint.inf
>  [X64]
> PeCoffLoaderEx.c
> g:\edk2-open-source\edk2\OvmfPkg\Library\VmgExitLib\VmgExitVcHandler.c(386): 
> warning C4334: '<<': result of 32-bit shift implicitly converted to 64 bits 
> (was 64-bit shift intended?)
> NMAKE : fatal error U1077: '"C:\Program Files (x86)\Microsoft Visual Studio 
> 14.0\Vc\bin\x86_amd64\cl.exe"' : return code '0x2'

Yup, looks like that needs to be a "1ULL <<" instead of "1 <<".
I have verified that fixes the issue.

One thing I noticed is that the 32-bit builds
(PlatformCI_OvmfPkg_Windows_VS2019_PR, Platform_CI OVMF_IA32_NOOPT and
Platform_CI OVMF_IA32X64_NOOPT) encounter an error:

ERROR - Linker #2001 from SecMain.lib(SecMain.obj) :   unresolved external 
symbol __allshl
ERROR - Linker #1120 from 
d:\a\1\s\Build\Ovmf3264\NOOPT_VS2019\IA32\OvmfPkg\Sec\SecMain\DEBUG\SecMain.dll 
: fatal   1 unresolved externals
ERROR - Compiler #1077 from NMAKE : fatal   '"C:\Program Files (x86)\Microsoft 
Visual 
Studio\2019\Enterprise\VC\Tools\MSVC\14.26.28801\bin\Hostx86\x86\link.exe"' : 
return code '0x460'

Any idea what is causing this error?

Thanks,
Tom

> 
> Thanks,
> Eric
>> -Original Message-
>> From: devel@edk2.groups.io  On Behalf Of
>> Lendacky, Thomas
>> Sent: Tuesday, June 23, 2020 8:58 PM
>> To: devel@edk2.groups.io; Dong, Eric ;
>> ler...@redhat.com
>> Cc: Brijesh Singh ; Ard Biesheuvel
>> ; Justen, Jordan L ;
>> Gao, Liming ; Kinney, Michael D
>> ; Ni, Ray 
>> Subject: Re: [edk2-devel] [PATCH v9 08/46] UefiCpuPkg: Implement library
>> support for VMGEXIT
>>
>> On 6/22/20 8:16 PM, Dong, Eric via groups.io wrote:
>>>
>>>
 -Original Message-
 From: devel@edk2.groups.io  On Behalf Of
>> Laszlo
 Ersek
 Sent: Friday, June 19, 2020 11:39 PM
 To: Tom Lendacky ; devel@edk2.groups.io;
 Dong, Eric 
 Cc: Brijesh Singh ; Ard Biesheuvel
 ; Justen, Jordan L
 ; Gao, Liming ;
 Kinney, Michael D ; Ni, Ray
 
 Subject: Re: [edk2-devel] [PATCH v9 08/46] UefiCpuPkg: Implement
 library support for VMGEXIT

 On 06/19/20 15:50, Tom Lendacky wrote:
> On 6/19/20 2:47 AM, Dong, Eric via groups.io wrote:
>>
>>
>>> -Original Message-
>>> From: devel@edk2.groups.io  On Behalf Of
>>> Lendacky, Thomas
>>> Sent: Thursday, June 18, 2020 10:09 PM
>>> To: Dong, Eric ; devel@edk2.groups.io
>>> Cc: Brijesh Singh ; Ard Biesheuvel
>>> ; Justen, Jordan L
 ;
>>> Laszlo Ersek ; Gao, Liming
>>> ; Kinney, Michael D
>>> ; Ni, Ray 
>>> Subject: Re: [edk2-devel] [PATCH v9 08/46] UefiCpuPkg: Implement
 library
>>> support for VMGEXIT
>>>
>>> On 6/18/20 2:23 AM, Dong, Eric wrote:
 Hi Tom,

 When use VS2015 to build this code, it reports below error.
 Please help to
>>> fix it.

 k:\edk2\UefiCpuPkg\Include\Library/VmgExitLib.h: error C2220:
 warning
 treated as error - no 'object' file generated
 k:\edk2\UefiCpuPkg\Include\Library/VmgExitLib.h: warning C4335:
 Mac
 file format detected: please convert the source file to either
 DOS or UNIX format
>>>
>>> That is strange...  I didn't see this when I ran through the CI.
>>> When I do a file command against the file it reports:
>>>
>>> UefiCpuPkg/Include/Library/VmgExitLib.h: C source, ASCII text,
>>> with
 CRLF
>>> line terminators
>>>
>>> I'll investigate this and try and figure out what's going on, but
>>> if anyone else has some ideas, please let me know.
>>
>> Hi Tom,
>>
>> I met this error again when I trig below patch from AMD again for
>> CPU change.
>> "UefiCpuPkg: Move StandardSignatureIsAuthenticAMD to
 BaseUefiCpuLib"
>
> Hmmm... I think we could be running into issues with sending patches
> through our mail servers. Let me send you the patch series directly
> using some changes I made to my git config file to see if that helps.
> Would that be ok?

 both sender and recipient git clones should have

 [core]
 whitespace = cr-at-eol

 and the recipient clone should have

 [am]
 keepcr = true


>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit
 hub.com%2Ftianocore%2Ftianocore.github.io%2Fwiki%2FLaszlo%27s-
>> unkempt
 -git-
>> &data=02%7C01%7Cthomas.lendacky%40amd.com%7Cd4619562362

Re: [edk2-devel] UefiPayloadPkg: assert error in PciHostBridgeDxe

[King Sumo]

On Fri, Jul 3, 2020 at 11:30 AM, Andrew Fish wrote:

> 
> At the same time, the platform's PciHostBridgeLib instance reported a
> root bridge with an MMIO aperture at [D400, FE10), with
> capabilities 1.
> 
> This is a conflict. The capabilities don't even matter (we don't even
> check whether the existent GCD descriptor's capabilities are a superset
> of the aperture's), because the aperture requires GCD memory type
> EfiGcdMemoryTypeMemoryMappedIo, but the GCD descriptor has type
> EfiGcdMemoryTypeReserved.
> 
> In brief, the failure is due to the platform reporting a PCI root bridge
> aperture such that it overlaps an area that is already listed as
> "reserved" in the GCD memory space map. So this is a platform bug;
> either in the "PciHostBridgeLib" instance, or in the module that
> populates the GCD memory space map.

Thanks Andrew and Laszlo!

The map (E000, F000) is the PCIE Base Address, maybe BlSupportPeim of 
UefiPayloadPkg have added this in the GCD - I'm not sure if this is correct / 
normal. Looks like BlSupportPeim is adding to GCD several memory regions during 
the initialization.
Anyway, the PCIe root bridge MMIO aperture (D400, FE10) looks pretty 
weird, I'll double check if coreboot is configuring the root port correctly.

Thanks,
Sumo

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Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix

[De Leon Vazquez, Lorena R]

Hi Liming,
I've attached the patch

Thanks,
Lorena

From: Gao, Liming 
Sent: Thursday, July 2, 2020 8:54 PM
To: devel@edk2.groups.io; Lohr, Paul A ; Yao, Jiewen 
; De Leon Vazquez, Lorena R 

Cc: Kinney, Michael D 
Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU 
generic bug fix

Paul:
  This patch is missing to be merged.

Lorena:
  I can't extract the patch from the mail. Can you send the patch to me? I can 
help merge it.

Thanks
Liming
From: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>> On Behalf Of Lohr, Paul A
Sent: Thursday, July 2, 2020 9:56 PM
To: devel@edk2.groups.io; Yao, Jiewen 
mailto:jiewen@intel.com>>; De Leon Vazquez, Lorena R 
mailto:lorena.r.de.leon.vazq...@intel.com>>
Cc: Kinney, Michael D 
mailto:michael.d.kin...@intel.com>>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU 
generic bug fix

Hello,

It seems this did not get checked in.  Is there something wrong with the patch 
itself?  Or was this simply submitted incorrectly?  I don't see a Bugzilla 
associated with it is why I ask.

Paul A. Lohr - Server Firmware Enabling
512.239.9073 (cell)
512.794.5044 (work)

From: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>> On Behalf Of Yao, Jiewen
Sent: Monday, March 2, 2020 5:46 PM
To: De Leon Vazquez, Lorena R 
mailto:lorena.r.de.leon.vazq...@intel.com>>;
 devel@edk2.groups.io
Cc: Kinney, Michael D 
mailto:michael.d.kin...@intel.com>>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU 
generic bug fix

Reviewed-by: jiewen@intel.com

From: De Leon Vazquez, Lorena R 
mailto:lorena.r.de.leon.vazq...@intel.com>>
Sent: Tuesday, March 3, 2020 7:04 AM
To: devel@edk2.groups.io
Cc: Yao, Jiewen mailto:jiewen@intel.com>>; Kinney, 
Michael D mailto:michael.d.kin...@intel.com>>
Subject: [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix

Looks like Addresswidth is BIT wise values. Right now these values are not used 
any

Suggested-by: Star Zeng star.z...@intel.com
Signed-off-by: 
lorena.r.de.leon.vazq...@intel.com

--
.../Feature/VTd/IntelVTdDxe/TranslationTable.c| 11 ---
.../Feature/VTd/IntelVTdDxe/TranslationTableEx.c  | 11 ---
2 files changed, 8 insertions(+), 14 deletions(-)

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c 
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index cc970c0..61fbb4a 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
@@ -128,14 +128,11 @@ CreateContextEntry (

 DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n", 
mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, 
SourceId.Bits.Function));

-switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {
-case BIT1:
-  ContextEntry->Bits.AddressWidth = 0x1;
-  break;
-case BIT2:
-  ContextEntry->Bits.AddressWidth = 0x2;
-  break;
+if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
+  DEBUG((DEBUG_ERROR, " 4-level page-table is not supported on VTD %d 
\n", VtdIndex));
+  return error;
 }
+ContextEntry->Bits.AddressWidth = 0x2;
   }

   FlushPageTableMemory (VtdIndex, 
(UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable, 
EFI_PAGES_TO_SIZE(EntryTablePages));
diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c 
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
index 0da1611..6bd31b7 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
@@ -78,14 +78,11 @@ CreateExtContextEntry (

 DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F%02x\n", 
mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, 
SourceId.Bits.Function));

-switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {
-case BIT1:
-  ExtContextEntry->Bits.AddressWidth = 0x1;
-  break;
-case BIT2:
-  ExtContextEntry->Bits.AddressWidth = 0x2;
-  break;
+if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
+  DEBUG((DEBUG_ERROR, " 4-level page-table is not supported on VTD %d 
\n", VtdIndex));
+  return error;
 }
+ContextEntry->Bits.AddressWidth = 0x2;
   }

   FlushPageTableMemory (VtdIndex, 
(UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable, 
EFI_PAGES_TO_SIZE(EntryTablePages));
--
2.21.0.windows.1



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Re: [edk2-devel] [PATCH] uefi-sct/SctPkg: Remove gEfiFormBrowserExProtocolGuid

[Irene Park]

Hello Eric,
Would you please kindly review this change?
Thank you,
Irene

From: G Edhaya Chandran 
mailto:edhaya.chand...@arm.com>>
Sent: Monday, June 22, 2020 3:06 PM
To: Jin, Eric mailto:eric@intel.com>>
Cc: Irene Park mailto:ip...@nvidia.com>>
Subject: RE: [edk2-devel] [PATCH] uefi-sct/SctPkg: Remove 
gEfiFormBrowserExProtocolGuid

External email: Use caution opening links or attachments

Hello Eric,

   Could you please review this change too.
Once complete, I will mainline it.

With Warm Regards,
Edhay


From: Irene Park mailto:ip...@nvidia.com>>
Sent: 23 June 2020 00:00
To: devel@edk2.groups.io; G Edhaya Chandran 
mailto:edhaya.chand...@arm.com>>
Subject: RE: [edk2-devel] [PATCH] uefi-sct/SctPkg: Remove 
gEfiFormBrowserExProtocolGuid

Hi Edhaya,
Thank you for the review.
By the way, I don’t see it got mainlined yet.
Do you mind to share when you’re going to pick it up ?
Thank you,
Irene

From: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>> On Behalf Of G Edhaya 
Chandran
Sent: Friday, June 5, 2020 4:12 AM
To: Irene Park mailto:ip...@nvidia.com>>; 
devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH] uefi-sct/SctPkg: Remove 
gEfiFormBrowserExProtocolGuid

External email: Use caution opening links or attachments


Reviewed-by: G Edhaya 
Chandranmailto:edhaya.chand...@arm.com>>

IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.

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Re: [edk2-devel] [edk2-platforms][PATCH v3 0/4] Platform: Add initial support for N1SDP board

[Thomas Abraham]

On Fri, Jul 3, 2020 at 4:49 PM Pranav Madhu  wrote:
>
> Changes since v2:
> - Addressed comments from Thomas.
> - Renamed Silicon/ARM/N1SDP to Silicon/ARM/NeoverseN1Soc.
>
> Changes since v1:
> - Addressed comments from Ard.
> - Split the code between Silicon and Platform directories.
>
> Arm's N1SDP is a Arm v8.2-A Neoverse N1 CPU based reference design platform
> primariliy intended for development on Arm64 based platform. This patch series
> adds initial platform support for this board.
>
> The first patch in this series adds the platform libary implementation. The
> second patch adds a custom implementation of the PciExpressLib due to a PCIe
> integration issue which results in all config space accesses to non-existing
> BDFs resulting in a Serror (bus abort). To avoid this, the N1SDP specific
> PciExpressLib implementation provides a workaround for this issue. The third
> patch in this series adds the platform library for the PciHostBridge. The
> fourth patch adds the initial platform support for the N1SDP platform.
>
> Deepak Pandey (4):
>   Silicon/ARM/N1SoC: Add platform library implementation
>   Silicon/ARM/N1SoC: Implement Neoverse N1 Soc specific PciExpressLib
>   Silicon/ARM/N1SoC: Implement the PciHostBridgeLib library
>   Platform/ARM/N1SDP: Add initial N1SDP platform support

For this series:
Reviewed-by: Thomas Abraham 

>
>  Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec  
>|   46 +
>  Platform/ARM/N1Sdp/N1SdpPlatform.dsc 
>|  245 
>  Platform/ARM/N1Sdp/N1SdpPlatform.fdf 
>|  294 
>  
> Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.inf
>  |   39 +
>  Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf  
>|   49 +
>  Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
>|   54 +
>  Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h
>|   68 +
>  
> Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.c
>| 1545 
>  Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
>|  187 +++
>  Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c  
>|   67 +
>  Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c   
>|  152 ++
>  Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S   
>|   84 ++
>  12 files changed, 2830 insertions(+)
>  create mode 100644 Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec
>  create mode 100644 Platform/ARM/N1Sdp/N1SdpPlatform.dsc
>  create mode 100644 Platform/ARM/N1Sdp/N1SdpPlatform.fdf
>  create mode 100644 
> Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.inf
>  create mode 100644 
> Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>  create mode 100644 
> Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
>  create mode 100644 Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h
>  create mode 100644 
> Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.c
>  create mode 100644 
> Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
>  create mode 100644 
> Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
>  create mode 100644 
> Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
>  create mode 100644 
> Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
>
> --
> 2.7.4
>
>
> 
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Re: [edk2-devel] [PATCH v6 0/4] AMD processor MSR_IA32_MISC_ENABLE

[Laszlo Ersek]

Ray, Hao, Eric,

On 06/22/20 15:18, Kirkendall, Garrett wrote:
> AMD processor does not support MSR_IA32_MISC_ENABLE register.  Accessing
> this register on AMD causes an unhandled exception in SmmEntry.nasm and
> a subsequent failure to boot since this is too early in SMM path for the
> exception handler to be loaded.
> 
> 1. Prepare PcAtChipsetPkg/PcAtChipsetPkg.dsc to move
> StandardSignatureIsAuthenticAMD into UefiCpuLib LibraryClass
> BaseUefiCpuLib in UefiCpuPkg.
> 
> 2. To distinguish between AMD and other processors, refactor
> StandardSignatureIsAuthenticAMD into BaseUefiCpuLib.  So there is only
> one copy in the source.
> 
> 3. Skip manipulation of MSR_IA32_MISC_ENABLE register if running
> on an AMD processor.
> 
> Tested on AMD X64 hardware.
> OvmfIa32 and OvmfIa32X64 on Intel hardware.
> 
> v1: Move StandardSignatureIsAuthenticAMD. Handle MSR_IA32_MISC_ENABLE
> v2: Incorporate Laszlo's feedback
> v3: Typo, not sent
> v4: Patch in to add UefiCpuLib to PcAtChipsetPkg.dsc
> v5: Patch in to add UefiCpuLib to SourceLevelDebugPkg.dsc
> v6: Hopefully reformat patch when sending

With  fixed (commit
0060e0a694f3), this patch set should be merged now.

I was about to do just that, but the review status of the series is
still incomplete. Even though this patch series has been on the list for
two weeks now.

- Ray, can you please review patch#1 immediately?

- Hao, can you please review patch#2 immediately?

- Ray and Eric, can one of you please review patch #4 at once?

Thanks
Laszlo


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[edk2-devel] acpiview error handling patches

[Tomas Pilar (tpilar)]

Hi Ray, Zhichao,

Did you have any opinions on my acpiview error handling patches?

Cheers,
Tom

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Re: [edk2-devel] [PATCH V3 0/4] Add New Memory Attributes

[Laszlo Ersek]

On 07/02/20 22:50, Oleksiy Yakovlev wrote:
> This series of patches add usage of new memory
> attributes EFI_MEMORY_SP and EFI_MEMORY_CPU_CRYPTO,
> introduced in UEFI2.8 (mantis 1919 and 1872).
> First patch fix typos in description and introduce two 
> bitmasks for all memory type attributes.
> Second and fourth patches get rid of multiple memory attributes
> bitmasks definitions trough multiple files and headers,
> and replace them with new common definitions from MdePkg.
> Third patch includes WP attribute into cache type mask in
> CpuDexe.h to make next change in this file more clear.
> 
> Oleksiy Yakovlev (4):
>   MdePkg: Add New Memory Attributes
>   MdeModulePkg: Add New Memory Attributes
>   UefiCpuPkg: Update EFI_MEMORY_CACHETYPE_MASK definition
>   UefiCpuPkg: Add New Memory Attributes
> 
>  MdeModulePkg/Core/Dxe/Gcd/Gcd.c| 11 ++-
>  MdeModulePkg/Core/Dxe/Mem/Page.c   |  9 +++--
>  MdeModulePkg/Core/Dxe/Misc/MemoryProtection.c  |  7 ++-
>  MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c | 10 ++
>  MdePkg/Include/Uefi/UefiSpec.h | 10 --
>  UefiCpuPkg/CpuDxe/CpuDxe.c | 11 ---
>  UefiCpuPkg/CpuDxe/CpuDxe.h | 12 
>  UefiCpuPkg/CpuDxe/CpuPageTable.c   |  6 +++---
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c |  2 +-
>  9 files changed, 25 insertions(+), 53 deletions(-)
> 

series
Tested-by: Laszlo Ersek 

Meaning my usual OVMF regression tests, and (due to patch#2) an
ArmVirtQemu boot test on AARCH64 KVM too.

Thanks
Laszlo


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Re: [edk2-devel] [PATCH] IntelFsp2Pkg/FspSecCore: Use UefiCpuLib.

[Laszlo Ersek]

On 06/29/20 02:44, Chiu, Chasel wrote:
> 
> Reviewed-by: Chasel Chiu 

This was merged as commit 0060e0a694f3f249c3ec081b0e61287c36f64ebb.

Laszlo

>> -Original Message-
>> From: Dong, Eric 
>> Sent: Saturday, June 27, 2020 9:52 AM
>> To: devel@edk2.groups.io
>> Cc: Chiu, Chasel ; Desimone, Nathaniel L
>> ; Zeng, Star 
>> Subject: [PATCH] IntelFsp2Pkg/FspSecCore: Use UefiCpuLib.
>>
>> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2825
>>
>> UefiCpuLib has API InitializeFloatingPointUnits.
>> Remove internal copy of InitializeFloatingPointUnits in FspSecCoreM, use
>> UefiCpuLib API.
>>
>> This change also avoid later potential conflict when use UefiCpuLib for
>> FspSecCoreM module.
>>
>> Signed-off-by: Eric Dong 
>> Cc: Chasel Chiu 
>> Cc: Nate DeSimone 
>> Cc: Star Zeng 
>> ---
>>  IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf   |  3 +-
>>  IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf   |  1 -
>>  .../FspSecCore/Ia32/InitializeFpu.nasm| 72 ---
>>  IntelFsp2Pkg/FspSecCore/SecMain.h | 15 +---
>>  IntelFsp2Pkg/IntelFsp2Pkg.dsc |  1 +
>>  5 files changed, 4 insertions(+), 88 deletions(-)  delete mode 100644
>> IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
>>
>> diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
>> b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
>> index 25f2a109ab..61b7ddca4c 100644
>> --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
>> +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
>> @@ -29,7 +29,6 @@
>>
>>  [Sources.IA32]
>>Ia32/Stack.nasm
>> -  Ia32/InitializeFpu.nasm
>>Ia32/FspApiEntryM.nasm
>>Ia32/FspApiEntryCommon.nasm
>>Ia32/FspHelper.nasm
>> @@ -41,6 +40,7 @@
>>  [Packages]
>>MdePkg/MdePkg.dec
>>IntelFsp2Pkg/IntelFsp2Pkg.dec
>> +  UefiCpuPkg/UefiCpuPkg.dec
>>
>>  [LibraryClasses]
>>BaseMemoryLib
>> @@ -51,6 +51,7 @@
>>FspSwitchStackLib
>>FspCommonLib
>>FspSecPlatformLib
>> +  UefiCpuLib
>>
>>  [Pcd]
>>gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ##
>> CONSUMES
>> diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
>> b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
>> index 971b311e42..664bde5678 100644
>> --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
>> +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
>> @@ -25,7 +25,6 @@
>>
>>  [Sources.IA32]
>>Ia32/Stack.nasm
>> -  Ia32/InitializeFpu.nasm
>>Ia32/FspApiEntryT.nasm
>>Ia32/FspHelper.nasm
>>
>> diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
>> b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
>> deleted file mode 100644
>> index ebc91c41e4..00
>> --- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
>> +++ /dev/null
>> @@ -1,72 +0,0 @@
>> -;--
>> -;
>> -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. -;
>> SPDX-License-Identifier: BSD-2-Clause-Patent -; -; Abstract:
>> -;
>> -;--
>> -
>> -
>> -SECTION .data
>> -;
>> -; Float control word initial value:
>> -; all exceptions masked, double-precision, round-to-nearest -;
>> -ASM_PFX(mFpuControlWord):
>> -dw0x027F
>> -;
>> -; Multimedia-extensions control word:
>> -; all exceptions masked, round-to-nearest, flush to zero for masked
>> underflow -;
>> -ASM_PFX(mMmxControlWord):
>> - dd 0x01F80
>> -
>> -SECTION .text
>> -
>> -;
>> -; Initializes floating point units for requirement of UEFI specification.
>> -;
>> -; This function initializes floating-point control word to 0x027F (all
>> exceptions -; masked,double-precision, round-to-nearest) and
>> multimedia-extensions control word -; (if supported) to 0x1F80 (all
>> exceptions masked, round-to-nearest, flush to zero -; for masked underflow).
>> -;
>> -
>> -global ASM_PFX(InitializeFloatingPointUnits)
>> -ASM_PFX(InitializeFloatingPointUnits):
>> -
>> -
>> -pushebx
>> -
>> -;
>> -; Initialize floating point units
>> -;
>> -finit
>> -fldcw[ASM_PFX(mFpuControlWord)]
>> -
>> -;
>> -; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
>> -; whether the processor supports SSE instruction.
>> -;
>> -mov eax, 1
>> -cpuid
>> -bt  edx, 25
>> -jnc Done
>> -
>> -;
>> -; Set OSFXSR bit 9 in CR4
>> -;
>> -mov eax, cr4
>> -or  eax, BIT9
>> -mov cr4, eax
>> -
>> -;
>> -; The processor should support SSE instruction and we can use
>> -; ldmxcsr instruction
>> -;
>> -ldmxcsr [ASM_PFX(mMmxControlWord)]
>> -Done:
>> -pop ebx
>> -
>> -ret
>> diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h
>> b/IntelFsp2Pkg/FspSecCore/SecMain.h
>> index af7f387960..f6333b0ffb 100644
>> --- a/IntelFsp2Pkg/FspSecCore/SecMain.h
>> +++ b/IntelFsp2Pkg/FspSecCore/SecMain.h
>> @@ -21,6 +21,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>
>>  typedef VOID (*PEI_CORE_ENTRY) ( \
>> 

Re: [edk2-devel] warning: Empty loadable segment detected

[Ard Biesheuvel]

On 7/6/20 11:39 AM, Laszlo Ersek via groups.io wrote:

Hi,

I've just noticed the following warning in the build log:


objcopy: [...]: warning: Empty loadable segment detected, is this
intentional ?


The modules this is logged for are:

- CapsuleRuntimeDxe
- CpuS3DataDxe
- EnrollDefaultKeys
- FaultTolerantWriteSmm
- IncompatiblePciDeviceSupport
- MonotonicCounterRuntimeDxe
- RealTimeClockRuntimeDxe
- XenIoPvhDxe

I can't tell if this is a new symptom, or the only "new" thing is my
noticing of it.

The warning is familiar, from commit 26ecc55c027d ("BaseTools IA32/X64:
prevent .eh_frame sections from being generated", 2015-08-13).

I get the warnings in NOOPT_GCC48 builds of OVMF (Ia32X64, X64, and Xen
-- not in Ia32).

Does someone have an idea what the warnings could be due to?



Could you share the output of 'readelf -a' for such a module?

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[edk2-devel] warning: Empty loadable segment detected

[Laszlo Ersek]

Hi,

I've just noticed the following warning in the build log:

> objcopy: [...]: warning: Empty loadable segment detected, is this
> intentional ?

The modules this is logged for are:

- CapsuleRuntimeDxe
- CpuS3DataDxe
- EnrollDefaultKeys
- FaultTolerantWriteSmm
- IncompatiblePciDeviceSupport
- MonotonicCounterRuntimeDxe
- RealTimeClockRuntimeDxe
- XenIoPvhDxe

I can't tell if this is a new symptom, or the only "new" thing is my
noticing of it.

The warning is familiar, from commit 26ecc55c027d ("BaseTools IA32/X64:
prevent .eh_frame sections from being generated", 2015-08-13).

I get the warnings in NOOPT_GCC48 builds of OVMF (Ia32X64, X64, and Xen
-- not in Ia32).

Does someone have an idea what the warnings could be due to?

Thanks!
Laszlo


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Re: [edk2-devel] [PATCH V3 3/4] UefiCpuPkg: Update EFI_MEMORY_CACHETYPE_MASK definition

[Laszlo Ersek]

On 07/02/20 22:50, Oleksiy Yakovlev wrote:
> Add EFI_MEMORY_WP attribute to
> EFI_MEMORY_CACHETYPE_MASK definition.
> 
> Signed-off-by: Oleksiy Yakovlev 
> ---
>  UefiCpuPkg/CpuDxe/CpuDxe.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.h b/UefiCpuPkg/CpuDxe/CpuDxe.h
> index 9299eaa..b30a896 100644
> --- a/UefiCpuPkg/CpuDxe/CpuDxe.h
> +++ b/UefiCpuPkg/CpuDxe/CpuDxe.h
> @@ -43,7 +43,8 @@
> EFI_MEMORY_WC  | \
> EFI_MEMORY_WT  | \
> EFI_MEMORY_WB  | \
> -   EFI_MEMORY_UCE   \
> +   EFI_MEMORY_UCE | \
> +   EFI_MEMORY_WP\
> )
>  
>  #define EFI_MEMORY_PAGETYPE_MASK  (EFI_MEMORY_RP  | \
> 

Reviewed-by: Laszlo Ersek 


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Re: [edk2-devel] [PATCH V3 2/4] MdeModulePkg: Add New Memory Attributes

[Laszlo Ersek]

On 07/02/20 22:50, Oleksiy Yakovlev wrote:
> Add usage of EFI_MEMORY_SP and EFI_MEMORY_CPU_CRYPTO
> attributes introduced in UEFI 2.8
> (UEFI 2.8, mantis 1919 and 1872)
> Use attributes bitmasks, defined in MdePkg.
> 
> Signed-off-by: Oleksiy Yakovlev 
> Reviewed-by: Laszlo Ersek 
> ---
>  MdeModulePkg/Core/Dxe/Gcd/Gcd.c   | 11 ++-
>  MdeModulePkg/Core/Dxe/Mem/Page.c  |  9 +++--
>  MdeModulePkg/Core/Dxe/Misc/MemoryProtection.c |  7 ++-
>  MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c| 10 ++
>  4 files changed, 9 insertions(+), 28 deletions(-)

This is missing Dandan's R-b from
. (To be picked up by the
maintainer that merges the series, if no more versions of the set are
needed.)

Thanks
Laszlo

> 
> diff --git a/MdeModulePkg/Core/Dxe/Gcd/Gcd.c b/MdeModulePkg/Core/Dxe/Gcd/Gcd.c
> index 74f3b1b..2d8c076 100644
> --- a/MdeModulePkg/Core/Dxe/Gcd/Gcd.c
> +++ b/MdeModulePkg/Core/Dxe/Gcd/Gcd.c
> @@ -35,13 +35,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>  
>  #define PRESENT_MEMORY_ATTRIBUTES (EFI_RESOURCE_ATTRIBUTE_PRESENT)
>  
> -#define EXCLUSIVE_MEMORY_ATTRIBUTES   (EFI_MEMORY_UC | EFI_MEMORY_WC | \
> -   EFI_MEMORY_WT | EFI_MEMORY_WB | \
> -   EFI_MEMORY_WP | EFI_MEMORY_UCE)
> -
> -#define NONEXCLUSIVE_MEMORY_ATTRIBUTES (EFI_MEMORY_XP | EFI_MEMORY_RP | \
> -EFI_MEMORY_RO)
> -
>  //
>  // Module Variables
>  //
> @@ -665,7 +658,7 @@ ConverToCpuArchAttributes (
>  {
>UINT64  CpuArchAttributes;
>  
> -  CpuArchAttributes = Attributes & NONEXCLUSIVE_MEMORY_ATTRIBUTES;
> +  CpuArchAttributes = Attributes & EFI_MEMORY_ATTRIBUTE_MASK;
>  
>if ( (Attributes & EFI_MEMORY_UC) == EFI_MEMORY_UC) {
>  CpuArchAttributes |= EFI_MEMORY_UC;
> @@ -951,7 +944,7 @@ CoreConvertSpace (
>  // Keep original CPU arch attributes when caller just calls
>  // SetMemorySpaceAttributes() with none CPU arch attributes (for 
> example, RUNTIME).
>  //
> -Attributes |= (Entry->Attributes & (EXCLUSIVE_MEMORY_ATTRIBUTES | 
> NONEXCLUSIVE_MEMORY_ATTRIBUTES));
> +Attributes |= (Entry->Attributes & (EFI_CACHE_ATTRIBUTE_MASK | 
> EFI_MEMORY_ATTRIBUTE_MASK));
>}
>Entry->Attributes = Attributes;
>break;
> diff --git a/MdeModulePkg/Core/Dxe/Mem/Page.c 
> b/MdeModulePkg/Core/Dxe/Mem/Page.c
> index 1f0e3d9..2c2c9cd 100644
> --- a/MdeModulePkg/Core/Dxe/Mem/Page.c
> +++ b/MdeModulePkg/Core/Dxe/Mem/Page.c
> @@ -1857,8 +1857,7 @@ CoreGetMemoryMap (
>MemoryMap->VirtualStart  = 0;
>MemoryMap->NumberOfPages = RShiftU64 ((MergeGcdMapEntry.EndAddress - 
> MergeGcdMapEntry.BaseAddress + 1), EFI_PAGE_SHIFT);
>MemoryMap->Attribute = (MergeGcdMapEntry.Attributes & 
> ~EFI_MEMORY_PORT_IO) |
> -(MergeGcdMapEntry.Capabilities & 
> (EFI_MEMORY_RP | EFI_MEMORY_WP | EFI_MEMORY_XP | EFI_MEMORY_RO |
> -EFI_MEMORY_UC | EFI_MEMORY_UCE | 
> EFI_MEMORY_WC | EFI_MEMORY_WT | EFI_MEMORY_WB));
> +(MergeGcdMapEntry.Capabilities & 
> (EFI_CACHE_ATTRIBUTE_MASK | EFI_MEMORY_ATTRIBUTE_MASK));
>  
>if (MergeGcdMapEntry.GcdMemoryType == EfiGcdMemoryTypeReserved) {
>  MemoryMap->Type = EfiReservedMemoryType;
> @@ -1892,8 +1891,7 @@ CoreGetMemoryMap (
>MemoryMap->VirtualStart  = 0;
>MemoryMap->NumberOfPages = RShiftU64 ((MergeGcdMapEntry.EndAddress - 
> MergeGcdMapEntry.BaseAddress + 1), EFI_PAGE_SHIFT);
>MemoryMap->Attribute = MergeGcdMapEntry.Attributes | EFI_MEMORY_NV 
> |
> -(MergeGcdMapEntry.Capabilities & 
> (EFI_MEMORY_RP | EFI_MEMORY_WP | EFI_MEMORY_XP | EFI_MEMORY_RO |
> -EFI_MEMORY_UC | EFI_MEMORY_UCE | 
> EFI_MEMORY_WC | EFI_MEMORY_WT | EFI_MEMORY_WB));
> +(MergeGcdMapEntry.Capabilities & 
> (EFI_CACHE_ATTRIBUTE_MASK | EFI_MEMORY_ATTRIBUTE_MASK));
>MemoryMap->Type  = EfiPersistentMemory;
>  
>//
> @@ -1935,8 +1933,7 @@ CoreGetMemoryMap (
>MemoryMapEnd = MemoryMap;
>MemoryMap = MemoryMapStart;
>while (MemoryMap < MemoryMapEnd) {
> -MemoryMap->Attribute &= ~(UINT64)(EFI_MEMORY_RP | EFI_MEMORY_RO |
> -  EFI_MEMORY_XP);
> +MemoryMap->Attribute &= ~(UINT64)EFI_MEMORY_ATTRIBUTE_MASK;
>  MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, Size);
>}
>MergeMemoryMap (MemoryMapStart, &BufferSize, Size);
> diff --git a/MdeModulePkg/Core/Dxe/Misc/MemoryProtection.c 
> b/MdeModulePkg/Core/Dxe/Misc/MemoryProtection.c
> index 92a442f..7d1daf0 100644
> --- a/MdeModulePkg/Core/Dxe/Misc/MemoryProtection.c
> +++ b/MdeModulePkg/Core/Dxe/Misc/MemoryProtection.c
> @@ -42,9 +42,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>  #include "DxeMain.h"
>  #include "

Re: [edk2-devel] [PATCH V3 1/4] MdePkg: Add New Memory Attributes

[Laszlo Ersek]

Hi Oleksiy,

On 07/02/20 22:50, Oleksiy Yakovlev wrote:
> Add usage of EFI_MEMORY_SP and EFI_MEMORY_CPU_CRYPTO
> attributes introduced in UEFI 2.8
> (UEFI 2.8, mantis 1919 and 1872)
> Fix typos in EFI_MEMORY_CPU_CRYPTO description.
> Add attributes bitmasks, grouped by type.
> 
> Signed-off-by: Oleksiy Yakovlev 
> Reviewed-by: Laszlo Ersek 
> Reviewed-by: Liming Gao 
> ---
>  MdePkg/Include/Uefi/UefiSpec.h | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)

I think you forgot to pick up Zhiguang Liu's "Reviewed-by" from
 (i.e., under the v2 thread).

Of course I think that can be remedied by the maintainer that merges
this series in the end. (I can help with that too, but the series isn't
fully reviewed yet -- patches v3 #2 through #4 still need maintainer
approval.)

Thanks,
Laszlo

> 
> diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h
> index 558e1bc..05b82e0 100644
> --- a/MdePkg/Include/Uefi/UefiSpec.h
> +++ b/MdePkg/Include/Uefi/UefiSpec.h
> @@ -96,9 +96,9 @@ typedef enum {
>  #define EFI_MEMORY_SP   0x0004ULL
>  //
>  // If this flag is set, the memory region is capable of being
> -// protected with the CPU?s memory cryptographic
> +// protected with the CPU's memory cryptographic
>  // capabilities. If this flag is clear, the memory region is not
> -// capable of being protected with the CPU?s memory
> +// capable of being protected with the CPU's memory
>  // cryptographic capabilities or the CPU does not support CPU
>  // memory cryptographic capabilities.
>  //
> @@ -109,6 +109,12 @@ typedef enum {
>  //
>  #define EFI_MEMORY_RUNTIME  0x8000ULL
>  
> +//
> +// Attributes bitmasks, grouped by type
> +//
> +#define EFI_CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | 
> EFI_MEMORY_WT | EFI_MEMORY_WB | EFI_MEMORY_UCE | EFI_MEMORY_WP)
> +#define EFI_MEMORY_ATTRIBUTE_MASK (EFI_MEMORY_RP | EFI_MEMORY_XP | 
> EFI_MEMORY_RO | EFI_MEMORY_SP | EFI_MEMORY_CPU_CRYPTO)
> +
>  ///
>  /// Memory descriptor version number.
>  ///
> 


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Re: [edk2-devel] [PATCH v7 00/16] Add a plugin to check Ecc issues for edk2 on open ci

[Leif Lindholm]

On Mon, Jul 06, 2020 at 16:48:30 +0800, Zhang, Shenglei wrote:
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2606
> As planed we will enable Ecc check for edk2 on open ci. And they are
> ready now. I appreciate receiving feedback and comments if someone
> find errors or false positive issues.
> 
> I created a pipline of EccCheck for my forked edk2. Welcome everyone to
> create pull request to test the quality of this plugin.
> My forked tree: https://github.com/shenglei10/edk2
> 
> And I also created some test cases for ECC plugin. Below are test cases.
> https://github.com/shenglei10/edk2/tree/ECC
> Results can be view in below azure server.
> https://dev.azure.com/shengleizhang/shengleizhang/_build?definitionId=12&_a=summary
> 
> Patches
> 1/16: It's a lib necessary for py3 to run Ecc on azure servers.
> 
> 2/16: EccCheck.py is a plugin to report Ecc issues for commits. It can be run
>  on azure servers for open ci, or a local virtual environment.
> 
> 3/16~16/16: We consider some cases that will report out Ecc issues but they 
> won't
>  be fixed, like submodule and industry standard related things. So we
>  add two configuration fields "Exception" and "IgnoreFiles" for people
>  to use. These patches add configuration in yaml files for Ecc check.
> 
> Cc: Bob Feng 
> Cc: Bret Barkelew 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Sean Brogan 
> 
> v2: Update 1/17, fix the bug that the script can't hanlde multiple commits.
> 
> v3: Update 1/17, set the only workalbe workspace is edk2 root directory.
> Update 2/17, designate the version of antlr4 is 4.7.1.
> Add 4/17~17/17.
> 
> v4. Update 1/17, remove the function EdksetupRebuild(), instead add
> function SetupEnvironment(). Update variables' format and type hints
> to pass flake8 and mypy.
> 
> v5. Conver the former method to plugin solution, to align with
> other check points on open ci.
> 
> v6. The 1/16 patch is missed in v5 series. Now add it in v6.
> 
> v7. Fix a bug that Ecc plugin can not be run correctly under Linux OS.

What is the bug? Where is it fixed?

/
Leif

> Shenglei Zhang (16):
>   pip-requirements.txt: Add Ecc required lib
>   .pytool/Plugin: Add a plugin EccCheck
>   MdeModulePkg/MdeModulePkg.ci.yaml: Add configuration for Ecc check
>   ArmVirtPkg/ArmVirtPkg.ci.yaml: Add configuration for Ecc check
>   CryptoPkg/CryptoPkg.ci.yaml: Add configuration for Ecc check
>   EmulatorPkg/EmulatorPkg.ci.yaml: Add configuration for Ecc check
>   FatPkg/FatPkg.ci.yaml: Add configuration for Ecc check
>   FmpDevicePkg/FmpDevicePkg.ci.yaml: Add configuration for Ecc check
>   MdePkg/MdePkg.ci.yaml: Add configuration for Ecc check
>   NetworkPkg/NetworkPkg.ci.yaml: Add configuration for Ecc check
>   OvmfPkg/OvmfPkg.ci.yaml: Add configuration for Ecc check
>   PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml: Add configuration for Ecc check
>   SecurityPkg/SecurityPkg.ci.yaml: Add configuration for Ecc check
>   ShellPkg/ShellPkg.ci.yaml: Add configuration for Ecc check
>   UefiCpuPkg/UefiCpuPkg.ci.yaml: Add configuration for Ecc check
>   UnitTestFrameworkPkg: Add configuration for Ecc check in yaml file
> 
>  .pytool/Plugin/EccCheck/EccCheck.py   | 267 ++
>  .pytool/Plugin/EccCheck/EccCheck_plug_in.yaml |  11 +
>  .pytool/Plugin/EccCheck/Readme.md |  15 +
>  ArmVirtPkg/ArmVirtPkg.ci.yaml |  11 +
>  CryptoPkg/CryptoPkg.ci.yaml   |  11 +
>  EmulatorPkg/EmulatorPkg.ci.yaml   |  11 +
>  FatPkg/FatPkg.ci.yaml |  11 +
>  FmpDevicePkg/FmpDevicePkg.ci.yaml |  11 +
>  MdeModulePkg/MdeModulePkg.ci.yaml |  11 +
>  MdePkg/MdePkg.ci.yaml |  11 +
>  NetworkPkg/NetworkPkg.ci.yaml |  11 +
>  OvmfPkg/OvmfPkg.ci.yaml   |  11 +
>  PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml |  11 +
>  SecurityPkg/SecurityPkg.ci.yaml   |  11 +
>  ShellPkg/ShellPkg.ci.yaml |  11 +
>  UefiCpuPkg/UefiCpuPkg.ci.yaml |  11 +
>  .../UnitTestFrameworkPkg.ci.yaml  |  10 +
>  pip-requirements.txt  |   1 +
>  18 files changed, 447 insertions(+)
>  create mode 100644 .pytool/Plugin/EccCheck/EccCheck.py
>  create mode 100644 .pytool/Plugin/EccCheck/EccCheck_plug_in.yaml
>  create mode 100644 .pytool/Plugin/EccCheck/Readme.md
> 
> -- 
> 2.18.0.windows.1
> 
> 
> 
> 

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[edk2-devel] [PATCH v7 16/16] UnitTestFrameworkPkg: Add configuration for Ecc check in yaml file

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Michael D Kinney 
Cc: Sean Brogan 
Cc: Bret Barkelew 
Signed-off-by: Shenglei Zhang 
Acked-by: Ray Ni 
---
 UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml 
b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml
index 51e172537f8a..7e9fc5d005fb 100644
--- a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml
+++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml
@@ -5,6 +5,16 @@
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 ## options defined .pytool/Plugin/CompilerPlugin
 "CompilerPlugin": {
 "DscPath": "UnitTestFrameworkPkg.dsc"
-- 
2.18.0.windows.1


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[edk2-devel] [PATCH v7 11/16] OvmfPkg/OvmfPkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Cc: Ard Biesheuvel 
Signed-off-by: Shenglei Zhang 
Acked-by: Laszlo Ersek 
---
 OvmfPkg/OvmfPkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/OvmfPkg/OvmfPkg.ci.yaml b/OvmfPkg/OvmfPkg.ci.yaml
index 98992f0429ff..e151cebf7020 100644
--- a/OvmfPkg/OvmfPkg.ci.yaml
+++ b/OvmfPkg/OvmfPkg.ci.yaml
@@ -5,9 +5,20 @@
 # used for code analysis.
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 ## options defined .pytool/Plugin/CompilerPlugin
 "CompilerPlugin": {
 "DscPath": "" # Don't support this test
-- 
2.18.0.windows.1


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[edk2-devel] [PATCH v7 15/16] UefiCpuPkg/UefiCpuPkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Signed-off-by: Shenglei Zhang 
Acked-by: Ray Ni 
Reviewed-by: Eric Dong 
Acked-by: Laszlo Ersek 
---
 UefiCpuPkg/UefiCpuPkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml b/UefiCpuPkg/UefiCpuPkg.ci.yaml
index 99e460a8b090..0e216344cd53 100644
--- a/UefiCpuPkg/UefiCpuPkg.ci.yaml
+++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml
@@ -2,9 +2,20 @@
 # CI configuration for UefiCpuPkg
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 "CompilerPlugin": {
 "DscPath": "UefiCpuPkg.dsc"
 },
-- 
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[edk2-devel] [PATCH v7 12/16] PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Ray Ni 
Signed-off-by: Shenglei Zhang 
Acked-by: Ray Ni 
---
 PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml 
b/PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml
index be470807bd9e..c59287064d65 100644
--- a/PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml
+++ b/PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml
@@ -2,9 +2,20 @@
 # CI configuration for PcAtChipsetPkg
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 "CompilerPlugin": {
 "DscPath": "PcAtChipsetPkg.dsc"
 },
-- 
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[edk2-devel] [PATCH v7 13/16] SecurityPkg/SecurityPkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Jiewen Yao 
Cc: Jian J Wang 
Cc: Chao Zhang 
Signed-off-by: Shenglei Zhang 
Reviewed-by: Jian J Wang 
---
 SecurityPkg/SecurityPkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/SecurityPkg/SecurityPkg.ci.yaml b/SecurityPkg/SecurityPkg.ci.yaml
index 953219053318..a0e143140875 100644
--- a/SecurityPkg/SecurityPkg.ci.yaml
+++ b/SecurityPkg/SecurityPkg.ci.yaml
@@ -2,9 +2,20 @@
 # CI configuration for SecurityPkg
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 "CompilerPlugin": {
 "DscPath": "SecurityPkg.dsc"
 },
-- 
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[edk2-devel] [PATCH v7 14/16] ShellPkg/ShellPkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Ray Ni 
Cc: Zhichao Gao 
Signed-off-by: Shenglei Zhang 
Acked-by: Ray Ni 
---
 ShellPkg/ShellPkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/ShellPkg/ShellPkg.ci.yaml b/ShellPkg/ShellPkg.ci.yaml
index 67de34a2556e..eedc173738dc 100644
--- a/ShellPkg/ShellPkg.ci.yaml
+++ b/ShellPkg/ShellPkg.ci.yaml
@@ -2,9 +2,20 @@
 # CI configuration for ShellPkg
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 "CompilerPlugin": {
 "DscPath": "ShellPkg.dsc"
 },
-- 
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[edk2-devel] [PATCH v7 10/16] NetworkPkg/NetworkPkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Maciej Rabeda 
Cc: Jiaxin Wu 
Cc: Siyuan Fu 
Signed-off-by: Shenglei Zhang 
Reviewed-by: Maciej Rabeda 
---
 NetworkPkg/NetworkPkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/NetworkPkg/NetworkPkg.ci.yaml b/NetworkPkg/NetworkPkg.ci.yaml
index 70f2e1014748..d45faf0ac967 100644
--- a/NetworkPkg/NetworkPkg.ci.yaml
+++ b/NetworkPkg/NetworkPkg.ci.yaml
@@ -2,9 +2,20 @@
 # CI configuration for NetworkPkg
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 "CompilerPlugin": {
 "DscPath": "NetworkPkg.dsc"
 },
-- 
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[edk2-devel] [PATCH v7 01/16] pip-requirements.txt: Add Ecc required lib

[Zhang, Shenglei]

antlr4-python3-runtime is a lib to support Ecc run with Py3.x.

Cc: Sean Brogan 
Cc: Bret Barkelew 
Cc: Michael D Kinney 
Cc: Liming Gao 
Signed-off-by: Shenglei Zhang 
Reviewed-by: Liming Gao 
---
 pip-requirements.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/pip-requirements.txt b/pip-requirements.txt
index 574dac43b1a6..0fecd37f2a83 100644
--- a/pip-requirements.txt
+++ b/pip-requirements.txt
@@ -14,3 +14,4 @@
 
 edk2-pytool-library==0.10.*
 edk2-pytool-extensions~=0.13.3
+antlr4-python3-runtime==4.7.1
-- 
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[edk2-devel] [PATCH v7 05/16] CryptoPkg/CryptoPkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Jian J Wang 
Cc: Xiaoyu Lu 
Signed-off-by: Shenglei Zhang 
Reviewed-by: Guomin Jiang 
Reviewed-by: Jian J Wang 
---
 CryptoPkg/CryptoPkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/CryptoPkg/CryptoPkg.ci.yaml b/CryptoPkg/CryptoPkg.ci.yaml
index f54ebfb22e70..c60d8bac6dee 100644
--- a/CryptoPkg/CryptoPkg.ci.yaml
+++ b/CryptoPkg/CryptoPkg.ci.yaml
@@ -2,9 +2,20 @@
 # CI configuration for CryptoPkg
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 "CompilerPlugin": {
 "DscPath": "CryptoPkg.dsc"
 },
-- 
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[edk2-devel] [PATCH v7 03/16] MdeModulePkg/MdeModulePkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Jian J Wang 
Cc: Hao A Wu 
Signed-off-by: Shenglei Zhang 
---
 MdeModulePkg/MdeModulePkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/MdeModulePkg/MdeModulePkg.ci.yaml 
b/MdeModulePkg/MdeModulePkg.ci.yaml
index 1cfc1328390e..0ed929855417 100644
--- a/MdeModulePkg/MdeModulePkg.ci.yaml
+++ b/MdeModulePkg/MdeModulePkg.ci.yaml
@@ -2,9 +2,20 @@
 # CI configuration for MdeModulePkg
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 ## options defined ci/Plugin/CompilerPlugin
 "CompilerPlugin": {
 "DscPath": "MdeModulePkg.dsc"
-- 
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[edk2-devel] [PATCH v7 08/16] FmpDevicePkg/FmpDevicePkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Liming Gao 
Cc: Michael D Kinney 
Signed-off-by: Shenglei Zhang 
Reviewed-by: Guomin Jiang 
---
 FmpDevicePkg/FmpDevicePkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/FmpDevicePkg/FmpDevicePkg.ci.yaml 
b/FmpDevicePkg/FmpDevicePkg.ci.yaml
index 74a0aefe8e49..b84400f06ffd 100644
--- a/FmpDevicePkg/FmpDevicePkg.ci.yaml
+++ b/FmpDevicePkg/FmpDevicePkg.ci.yaml
@@ -2,9 +2,20 @@
 # CI configuration for FmpDevicePkg
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 "CompilerPlugin": {
 "DscPath": "FmpDevicePkg.dsc"
 },
-- 
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[edk2-devel] [PATCH v7 00/16] Add a plugin to check Ecc issues for edk2 on open ci

[Zhang, Shenglei]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2606
As planed we will enable Ecc check for edk2 on open ci. And they are
ready now. I appreciate receiving feedback and comments if someone
find errors or false positive issues.

I created a pipline of EccCheck for my forked edk2. Welcome everyone to
create pull request to test the quality of this plugin.
My forked tree: https://github.com/shenglei10/edk2

And I also created some test cases for ECC plugin. Below are test cases.
https://github.com/shenglei10/edk2/tree/ECC
Results can be view in below azure server.
https://dev.azure.com/shengleizhang/shengleizhang/_build?definitionId=12&_a=summary

Patches
1/16: It's a lib necessary for py3 to run Ecc on azure servers.

2/16: EccCheck.py is a plugin to report Ecc issues for commits. It can be run
 on azure servers for open ci, or a local virtual environment.

3/16~16/16: We consider some cases that will report out Ecc issues but they 
won't
 be fixed, like submodule and industry standard related things. So we
 add two configuration fields "Exception" and "IgnoreFiles" for people
 to use. These patches add configuration in yaml files for Ecc check.

Cc: Bob Feng 
Cc: Bret Barkelew 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Sean Brogan 

v2: Update 1/17, fix the bug that the script can't hanlde multiple commits.

v3: Update 1/17, set the only workalbe workspace is edk2 root directory.
Update 2/17, designate the version of antlr4 is 4.7.1.
Add 4/17~17/17.

v4. Update 1/17, remove the function EdksetupRebuild(), instead add
function SetupEnvironment(). Update variables' format and type hints
to pass flake8 and mypy.

v5. Conver the former method to plugin solution, to align with
other check points on open ci.

v6. The 1/16 patch is missed in v5 series. Now add it in v6.

v7. Fix a bug that Ecc plugin can not be run correctly under Linux OS.

Shenglei Zhang (16):
  pip-requirements.txt: Add Ecc required lib
  .pytool/Plugin: Add a plugin EccCheck
  MdeModulePkg/MdeModulePkg.ci.yaml: Add configuration for Ecc check
  ArmVirtPkg/ArmVirtPkg.ci.yaml: Add configuration for Ecc check
  CryptoPkg/CryptoPkg.ci.yaml: Add configuration for Ecc check
  EmulatorPkg/EmulatorPkg.ci.yaml: Add configuration for Ecc check
  FatPkg/FatPkg.ci.yaml: Add configuration for Ecc check
  FmpDevicePkg/FmpDevicePkg.ci.yaml: Add configuration for Ecc check
  MdePkg/MdePkg.ci.yaml: Add configuration for Ecc check
  NetworkPkg/NetworkPkg.ci.yaml: Add configuration for Ecc check
  OvmfPkg/OvmfPkg.ci.yaml: Add configuration for Ecc check
  PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml: Add configuration for Ecc check
  SecurityPkg/SecurityPkg.ci.yaml: Add configuration for Ecc check
  ShellPkg/ShellPkg.ci.yaml: Add configuration for Ecc check
  UefiCpuPkg/UefiCpuPkg.ci.yaml: Add configuration for Ecc check
  UnitTestFrameworkPkg: Add configuration for Ecc check in yaml file

 .pytool/Plugin/EccCheck/EccCheck.py   | 267 ++
 .pytool/Plugin/EccCheck/EccCheck_plug_in.yaml |  11 +
 .pytool/Plugin/EccCheck/Readme.md |  15 +
 ArmVirtPkg/ArmVirtPkg.ci.yaml |  11 +
 CryptoPkg/CryptoPkg.ci.yaml   |  11 +
 EmulatorPkg/EmulatorPkg.ci.yaml   |  11 +
 FatPkg/FatPkg.ci.yaml |  11 +
 FmpDevicePkg/FmpDevicePkg.ci.yaml |  11 +
 MdeModulePkg/MdeModulePkg.ci.yaml |  11 +
 MdePkg/MdePkg.ci.yaml |  11 +
 NetworkPkg/NetworkPkg.ci.yaml |  11 +
 OvmfPkg/OvmfPkg.ci.yaml   |  11 +
 PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml |  11 +
 SecurityPkg/SecurityPkg.ci.yaml   |  11 +
 ShellPkg/ShellPkg.ci.yaml |  11 +
 UefiCpuPkg/UefiCpuPkg.ci.yaml |  11 +
 .../UnitTestFrameworkPkg.ci.yaml  |  10 +
 pip-requirements.txt  |   1 +
 18 files changed, 447 insertions(+)
 create mode 100644 .pytool/Plugin/EccCheck/EccCheck.py
 create mode 100644 .pytool/Plugin/EccCheck/EccCheck_plug_in.yaml
 create mode 100644 .pytool/Plugin/EccCheck/Readme.md

-- 
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[edk2-devel] [PATCH v7 04/16] ArmVirtPkg/ArmVirtPkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Laszlo Ersek 
Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Signed-off-by: Shenglei Zhang 
Acked-by: Laszlo Ersek 
---
 ArmVirtPkg/ArmVirtPkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/ArmVirtPkg/ArmVirtPkg.ci.yaml b/ArmVirtPkg/ArmVirtPkg.ci.yaml
index 4553725ee528..3b321c806a62 100644
--- a/ArmVirtPkg/ArmVirtPkg.ci.yaml
+++ b/ArmVirtPkg/ArmVirtPkg.ci.yaml
@@ -5,9 +5,20 @@
 # used for code analysis.
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 ## options defined .pytool/Plugin/CompilerPlugin
 "CompilerPlugin": {
 "DscPath": "" # Don't support this test
-- 
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[edk2-devel] [PATCH v7 02/16] .pytool/Plugin: Add a plugin EccCheck

[Zhang, Shenglei]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2606
EccCheck is a plugin to report Ecc issues for code in pull request
, which will be run on open ci.
But note not each kind of issue could be reported out.
It can only handle the issues, whose line number in CSV report
accurately map with their code in source code files. And Ecc issues
about comments can also be handled.

Cc: Sean Brogan 
Cc: Bret Barkelew 
Cc: Michael D Kinney 
Cc: Liming Gao 
Signed-off-by: Shenglei Zhang 
---
 .pytool/Plugin/EccCheck/EccCheck.py   | 267 ++
 .pytool/Plugin/EccCheck/EccCheck_plug_in.yaml |  11 +
 .pytool/Plugin/EccCheck/Readme.md |  15 +
 3 files changed, 293 insertions(+)
 create mode 100644 .pytool/Plugin/EccCheck/EccCheck.py
 create mode 100644 .pytool/Plugin/EccCheck/EccCheck_plug_in.yaml
 create mode 100644 .pytool/Plugin/EccCheck/Readme.md

diff --git a/.pytool/Plugin/EccCheck/EccCheck.py 
b/.pytool/Plugin/EccCheck/EccCheck.py
new file mode 100644
index ..3857f472eda2
--- /dev/null
+++ b/.pytool/Plugin/EccCheck/EccCheck.py
@@ -0,0 +1,267 @@
+# @file EccCheck.py
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+import os
+import re
+import csv
+import xml.dom.minidom
+from typing import List, Dict, Tuple
+import logging
+from io import StringIO
+from edk2toolext.environment import shell_environment
+from edk2toolext.environment.plugintypes.ci_build_plugin import ICiBuildPlugin
+from edk2toolext.environment.var_dict import VarDict
+from edk2toollib.utility_functions import RunCmd
+
+
+class EccCheck(ICiBuildPlugin):
+"""
+A CiBuildPlugin that finds the Ecc issues of newly added code in pull 
request.
+
+Configuration options:
+"EccCheck": {
+"ExceptionList": [],
+"IgnoreFiles": []
+},
+"""
+
+ReModifyFile = re.compile(r'[B-Q,S-Z]+[\d]*\t(.*)')
+FindModifyFile = re.compile(r'\+\+\+ b\/(.*)')
+LineScopePattern = (r'@@ -\d*\,*\d* \+\d*\,*\d* @@.*')
+LineNumRange = re.compile(r'@@ -\d*\,*\d* \+(\d*)\,*(\d*) @@.*')
+
+def GetTestName(self, packagename: str, environment: VarDict) -> tuple:
+""" Provide the testcase name and classname for use in reporting
+testclassname: a descriptive string for the testcase can include 
whitespace
+classname: should be patterned ..
+
+Args:
+  packagename: string containing name of package to build
+  environment: The VarDict for the test to run in
+Returns:
+a tuple containing the testcase name and the classname
+(testcasename, classname)
+"""
+return ("Check for efi coding style for " + packagename, packagename + 
".EccCheck")
+
+##
+# External function of plugin.  This function is used to perform the task 
of the ci_build_plugin Plugin
+#
+#   - package is the edk2 path to package.  This means 
workspace/packagepath relative.
+#   - edk2path object configured with workspace and packages path
+#   - PkgConfig Object (dict) for the pkg
+#   - EnvConfig Object
+#   - Plugin Manager Instance
+#   - Plugin Helper Obj Instance
+#   - Junit Logger
+#   - output_stream the StringIO output stream from this plugin via logging
+def RunBuildPlugin(self, packagename, Edk2pathObj, pkgconfig, environment, 
PLM, PLMHelper, tc, output_stream=None):
+edk2_path = Edk2pathObj.WorkspacePath
+python_path = os.path.join(edk2_path, "BaseTools", "Source", "Python")
+env = shell_environment.GetEnvironment()
+env.set_shell_var('PYTHONPATH', python_path)
+env.set_shell_var('WORKSPACE', edk2_path)
+self.ECC_PASS = True
+self.ApplyConfig(pkgconfig, edk2_path, packagename)
+modify_dir_list = self.GetModifyDir(packagename)
+patch = self.GetDiff(packagename)
+ecc_diff_range = self.GetDiffRange(patch, packagename, edk2_path)
+self.GenerateEccReport(modify_dir_list, ecc_diff_range, edk2_path)
+ecc_log = os.path.join(edk2_path, "Ecc.log")
+if self.ECC_PASS:
+tc.SetSuccess()
+self.RemoveFile(ecc_log)
+return 0
+else:
+with open(ecc_log, encoding='utf8') as output:
+ecc_output = output.readlines()
+for line in ecc_output:
+logging.error(line)
+self.RemoveFile(ecc_log)
+tc.SetFailed("EccCheck failed for {0}".format(packagename), "Ecc 
detected issues")
+return 1
+
+def GetDiff(self, pkg: str) -> List[str]:
+return_buffer = StringIO()
+params = "diff --unified=0 origin/master HEAD"
+RunCmd("git", params, outstream=return_buffer)
+p = return_buffer.getvalue().strip()
+patch = p.split("\n")
+return_buffer.close()
+
+return patch
+
+def RemoveFile(self, file: str) -> None

[edk2-devel] [PATCH v7 07/16] FatPkg/FatPkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Ray Ni 
Signed-off-by: Shenglei Zhang 
Reviewed-by: Guomin Jiang 
---
 FatPkg/FatPkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/FatPkg/FatPkg.ci.yaml b/FatPkg/FatPkg.ci.yaml
index 8b0fb1d4fcd5..e6a4c810976f 100644
--- a/FatPkg/FatPkg.ci.yaml
+++ b/FatPkg/FatPkg.ci.yaml
@@ -2,9 +2,20 @@
 # CI configuration for FatPkg
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 "CompilerPlugin": {
 "DscPath": "FatPkg.dsc"
 },
-- 
2.18.0.windows.1


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[edk2-devel] [PATCH v7 09/16] MdePkg/MdePkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Michael D Kinney 
Cc: Liming Gao 
Signed-off-by: Shenglei Zhang 
Reviewed-by: Liming Gao 
---
 MdePkg/MdePkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index 3268f1535499..b6d7c57de83c 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -2,9 +2,20 @@
 # CI configuration for MdePkg
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 ## options defined ci/Plugin/CompilerPlugin
 "CompilerPlugin": {
 "DscPath": "MdePkg.dsc"
-- 
2.18.0.windows.1


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[edk2-devel] [PATCH v7 06/16] EmulatorPkg/EmulatorPkg.ci.yaml: Add configuration for Ecc check

[Zhang, Shenglei]

Add configuration ExceptionList and IgnoreFiles for package config
files. So users can rely on this to ignore some Ecc issues.

Cc: Jordan Justen 
Cc: Andrew Fish 
Cc: Ray Ni 
Signed-off-by: Shenglei Zhang 
Acked-by: Ray Ni 
---
 EmulatorPkg/EmulatorPkg.ci.yaml | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/EmulatorPkg/EmulatorPkg.ci.yaml b/EmulatorPkg/EmulatorPkg.ci.yaml
index 81f81780ec76..a664f4462e5d 100644
--- a/EmulatorPkg/EmulatorPkg.ci.yaml
+++ b/EmulatorPkg/EmulatorPkg.ci.yaml
@@ -5,9 +5,20 @@
 # used for code analysis.
 #
 # Copyright (c) Microsoft Corporation
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
+"EccCheck": {
+## Exception sample looks like below:
+## "ExceptionList": [
+## "", ""
+## ]
+"ExceptionList": [
+],
+"IgnoreFiles": [
+]
+},
 ## options defined .pytool/Plugin/CompilerPlugin
 "CompilerPlugin": {
 "DscPath": "" # Don't support this test
-- 
2.18.0.windows.1


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[edk2-devel] [PATCH edk2-platforms v2 1/6] Silicon/NXP: Add comments explaining RCW bits' parsing

[Pankaj Bansal]

From: Pankaj Bansal 

RCW bits parsing and their interpretation varies between various SOCs.
Add the comments that explain this parsing scheme.

Based on this explanation, fix the comments for SYS_PLL_RAT parsing
in LX2160A.

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/LS1043A/Include/Soc.h | 27 +++
 Silicon/NXP/LX2160A/Include/Soc.h | 28 +++-
 2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/Silicon/NXP/LS1043A/Include/Soc.h 
b/Silicon/NXP/LS1043A/Include/Soc.h
index 21b0dafffe91..c694576ed18d 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -50,6 +50,33 @@
 
 /**
   Reset Control Word (RCW) Bits
+
+  RCWSR contains the Reset Configuration Word (RCW) information written with
+  values read from flash memory by the device at power-on reset and read-only
+  upon exiting reset.
+
+  RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 
26 27 28 29 30 31
+
+LE   | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 
8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+  Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name  | Description  | Notes/comments
+--
+ 2-6   | SYS_PLL_RAT | System PLL Multiplier/Ratio  | This field selects the 
platform
+   | |  | clock:SYSCLK ratio.
+   | |  | 0_0011 3:1
+   | |  | 0_0100 4:1
+   | |  | 0_1101 13:1
+   | |  | 0_ 15:1
+   | |  | 1_ 16:1
+
+  which is why the RCW bits in RCWSR registers are parsed this way
 **/
 #define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
 
diff --git a/Silicon/NXP/LX2160A/Include/Soc.h 
b/Silicon/NXP/LX2160A/Include/Soc.h
index d62b8adcdbe7..e8198addc966 100644
--- a/Silicon/NXP/LX2160A/Include/Soc.h
+++ b/Silicon/NXP/LX2160A/Include/Soc.h
@@ -36,8 +36,34 @@
 
 /**
   Reset Control Word (RCW) Bits
+
+  RCWSR contains the Reset Configuration Word (RCW) information written with
+  values read from flash memory by the device at power-on reset and read-only
+  upon exiting reset.
+
+  RCW bits in RCWSR registers are same as bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(LSBit 0)| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 
8 7 6 5 4 3 2 1 0
+
+LE   | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 
8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+  Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name  | Description  | Notes/comments
+--
+ 6-2   | SYS_PLL_RAT | System PLL Multiplier/Ratio  | This field selects the 
platform
+   | |  | clock:SYSCLK ratio.
+   | |  | 0_0100 4:1
+   | |  | 0_0110 6:1
+   | |  | 0_1000 8:1
+   | |  | 0_1101 13:1
+   | |  | 0_ 15:1
+
 **/
-#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 6-2
 
 typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v2 5/6] Platform/NXP: Add LS1046AFRWY Platform

[Pankaj Bansal]

From: Pankaj Bansal 

LS1046A Freeway (FRWY) is a high-performance development
platform that supports the QorIQ LS1046A Layerscape Architecture SOCs.

Co-authored-by: Pramod Kumar 
Co-authored-by: Pankaj Bansal 
Signed-off-by: Pankaj Bansal 
---
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec |  23 
+++
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc |  46 
++
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 168 

 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  |   4 +
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c|  53 
+-
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c |  49 
+-
 6 files changed, 341 insertions(+), 2 deletions(-)

diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
new file mode 100644
index ..a693d8262444
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
@@ -0,0 +1,23 @@
+#  LS1046aFrwyPkg.dec
+#  LS1046a board package.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  PACKAGE_NAME   = LS1046aFrwyPkg
+  PACKAGE_GUID   = 3547d88c-62c2-4fb2-a11b-80245f80928f
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
new file mode 100644
index ..3f29dadd5d1d
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -0,0 +1,46 @@
+#  LS1046aFrwyPkg.dsc
+#
+#  LS1046AFRWY Board package.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_NAME  = LS1046aFrwyPkg
+  PLATFORM_GUID  = 79adaa48-5f50-49f0-aa9a-544ac9260ef8
+  OUTPUT_DIRECTORY   = Build/LS1046aFrwyPkg
+  FLASH_DEFINITION   = 
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
+
+[LibraryClasses.common]
+  
ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+  
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  #
+  # Architectural Protocols
+  #
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+
+gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+  }
+
+##
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
new file mode 100644
index ..8da5b57cb49e
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -0,0 +1,168 @@
+#  LS1046aFrwyPkg.fdf
+#
+#  FLASH layout file for LS1046a board.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+
+
+[FD.LS1046AFRWY_EFI]
+BaseAddress   = 0x8200|gArmTokenSpaceGuid.PcdFdBaseAddress  #The base 
address of the FLASH Device.
+Size  = 0x0014|gArmTokenSpaceGuid.PcdFdSize #The size

[edk2-devel] [PATCH edk2-platforms v2 4/6] Platform/NXP/LS1046AFRWY: Add ArmPlatformLib

[Pankaj Bansal]

From: Pankaj Bansal 

Add ArmPlatformLib for LS1046AFRWY platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.

Signed-off-by: Pankaj Bansal 
---
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  
| 38 
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
| 96 
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c 
| 28 ++
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S 
| 45 +
 4 files changed, 207 insertions(+)

diff --git 
a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
new file mode 100644
index ..de93681708e3
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,38 @@
+# @file
+# Copyright 2019-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PlatformLib
+  FILE_GUID  = c61c8a13-36a0-46f4-a3bc-7bab5a55db81
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+
+[Sources.common]
+  ArmPlatformLib.c
+  ArmPlatformLibMem.c
+
+[Sources.AArch64]
+  AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
diff --git 
a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c 
b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
new file mode 100644
index ..f59e7aa556a3
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -0,0 +1,96 @@
+/** @file
+*
+*  Copyright 2019-2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+#include 
+
+ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
+  {
+// Cluster 0, Core 0
+0x0, 0x0,
+
+// MP Core MailBox Set/Get/Clear Addresses and Clear Value
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(UINT64)0x
+  }
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/PrePi or 
ArmPlatformPkg/PlatformPei
+  in the PEI phase.
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+  IN  UINTN MpId
+  )
+{
+  //TODO: Implement me
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN   *CoreCount,
+  OUT ARM_CORE_INFO   **ArmCoreTable
+  )
+{
+  if (ArmIsMpCore()) {
+*CoreCount= sizeof(mLS1046aMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
+*ArmCoreTable = mLS1046aMpCoreInfoTable;
+return EFI_SUCCESS;
+  } else {
+return EFI_UNSUPPORTED;
+  }
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR  gPlatformPpiTable[] = {
+  {
+EFI_PEI_PPI_DESCRIPTOR_PPI,
+&gArmMpCoreInfoPpiGuid,
+&mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  if (ArmIsMpCore()) {
+*PpiListSize = sizeof(gPlatformPpiTable);
+*PpiList = gPlatformPpiTable;
+  } else {
+*PpiListSize = 0;
+*PpiList = NULL;
+  }
+}
diff --git 
a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c 
b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
new file mode 100644
index ..24d949369b98
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -0,0 +1,28 @@
+/** @file
+*
+*  Copyright 2019-2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the 
MMU on your platform.
+
+  @param[out]   VirtualMemoryMapArray of ARM_MEMORY_REGION_DESCRIPTOR 
describing a Physical-to-
+Virtual Memory mapping. This array must be 
ended by a zero-filled
+entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ASSERT(0);
+}
diff --git 
a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
 
b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatf

[edk2-devel] [PATCH edk2-platforms v2 2/6] Silicon/NXP/LS1043A: Fix the RCW bits' parsing

[Pankaj Bansal]

From: Pankaj Bansal 

For LS1043A SOC the DCFG registers are read in big endian format.
After Reading the registers in code we have the registers in Little
Endian Bit format i.e. LSBit 0.

However, the RCW bits in RCWSR registers in LS1043A SOC are in MSBit 0
format.

Currently, we are parsing the RCW bits in LE bit format i.e. LSBit 0.
Therefore, Fix the RCW bits' parsing as per MSBit 0.

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/NXP/LS1043A/Include/Soc.h 
b/Silicon/NXP/LS1043A/Include/Soc.h
index c694576ed18d..40619536c6fe 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -78,7 +78,7 @@ Bit(s) | Field Name  | Description  | 
Notes/comments
 
   which is why the RCW bits in RCWSR registers are parsed this way
 **/
-#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
 
 typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v2 3/6] Silicon/NXP: Add LS1046A Soc package

[Pankaj Bansal]

From: Pankaj Bansal 

LS1046A is QorIq Layerscape multicore communications processor with
four Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v2.

Co-authored-by: Vabhav Sharma 
Co-authored-by: Pankaj Bansal 
Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/LS1046A/LS1046A.dec   |  13 +++
 Silicon/NXP/LS1046A/LS1046A.dsc.inc   |  42 +++
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf |  27 +
 Silicon/NXP/LS1046A/Include/Soc.h |  63 +++
 Silicon/NXP/LS1046A/Include/SocSerDes.h   |  33 ++
 Silicon/NXP/LS1046A/Library/SocLib/SerDes.c   | 119 
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c   |  78 +
 7 files changed, 375 insertions(+)

diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
new file mode 100644
index ..bf4863c6d89e
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dec
@@ -0,0 +1,13 @@
+# LS1046A.dec
+#
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 0x0001001A
+
+[Includes]
+  Include
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc 
b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
new file mode 100644
index ..dbe7f408fce9
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -0,0 +1,42 @@
+#  LS1046A.dsc
+#  LS1046A Soc package.
+#
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+
+[LibraryClasses.common]
+  SocLib|Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+  SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+
+
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+
+[PcdsDynamicDefault.common]
+
+  #
+  # ARM General Interrupt Controller
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x0141
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0142
+
+[PcdsFixedAtBuild.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+
+[PcdsFeatureFlag]
+  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+##
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf 
b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
new file mode 100644
index ..01ed0f6592d2
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -0,0 +1,27 @@
+#  @file
+#
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = SocLib
+  FILE_GUID  = ddd5f950-8816-4d38-8f98-f42b07333f78
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = SocLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis2/Chassis2.dec
+  Silicon/NXP/LS1046A/LS1046A.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ChassisLib
+  DebugLib
+
+[Sources.common]
+  SocLib.c
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h 
b/Silicon/NXP/LS1046A/Include/Soc.h
new file mode 100644
index ..84f433d5cb94
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -0,0 +1,63 @@
+/** @file
+
+  Copyright 2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+#include 
+
+/**
+  Soc Memory Map
+**/
+#define LS1046A_DRAM0_PHYS_ADDRESS   (BASE_2GB)
+#define LS1046A_DRAM0_SIZE   (SIZE_2GB)
+#define LS1046A_DRAM1_PHYS_ADDRESS   (BASE_32GB + BASE_2GB)
+#define LS1046A_DRAM1_SIZE   (SIZE_32GB - SIZE_2GB)  // 30 GB
+
+#define LS1046A_CCSR_PHYS_ADDRESS(BASE_16MB)
+#define LS1046A_CCSR_SIZE(SIZE_256MB - SIZE_16MB) // 240MB
+
+#define LS1046A_QSPI0_PHYS_ADDRESS   (BASE_1GB)
+#define LS1046A_QSPI0_SIZE   (SIZE_512MB)
+
+#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+
+/**
+  Reset Control Word (RCW) Bits
+
+  RCWSR contains the Reset Configuration Word (RCW) information written with
+  values read from flash memory by the device at power-on reset and read-only
+  upon exiting reset.
+
+  RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 
26 27 28 29 30 31
+
+LE   | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 
8 7 6 5 4 3 

[edk2-devel] [PATCH edk2-platforms v2 6/6] Platform/NXP/LS1046aFrwyPkg: Add VarStore

[Pankaj Bansal]

From: Pankaj Bansal 

Add VarStore Fd. This Fd is used to store non volatile variables in
flash.

Signed-off-by: Pankaj Bansal 
---
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf |  1 +
 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc   | 91 
 2 files changed, 92 insertions(+)

diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
index 8da5b57cb49e..24af547729c7 100644
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -48,6 +48,7 @@ [FD.LS1046AFRWY_EFI]
 FV = FVMAIN_COMPACT
 
 !include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
 

 #
 # FV Section
diff --git a/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc 
b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
new file mode 100644
index ..727705feaea1
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+#  FDF include file with FD definition that defines an empty variable store.
+#
+#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+#  Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LS1046aFrwyNv_EFI]
+BaseAddress   = 0x4050  #The base address of the FLASH device
+Size  = 0x000C  #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1000
+NumBlocks = 0xC0
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE= 0x
+DEFINE NVRAM_AREA_VARIABLE_SIZE= 0x0004
+DEFINE FTW_WORKING_BASE= $(NVRAM_AREA_VARIABLE_BASE) + 
$(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE= 0x0004
+DEFINE FTW_SPARE_BASE  = $(FTW_WORKING_BASE) + 
$(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE  = 0x0004
+
+#
+# LS1046AFRWY NVRAM Area
+# LS1046AFRWY NVRAM Area contains: Variable + FTW Working + FTW Spare
+#
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid =
+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
+  # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: Flash Size : 0x400
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+  # Signature "_FVH"   # Attributes
+  0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+  # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+  0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+  # Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+  # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+  # Signature: gEfiVariableGuid =
+  #   { 0xddcf3616, 0x3275, 0x4164,
+  # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  # Size: 0x4 
(gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+  # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xFF, 0x03, 0x00,
+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = 
gEdkiiWorkingBlockSignatureGuid =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 
0x95 }}
+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
+  # Crc:UINT32#WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64
+  0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeMod

[edk2-devel] [PATCH edk2-platforms v2 0/6] Add LS1046AFRWY Platform

[Pankaj Bansal]

From: Pankaj Bansal 

The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance
development platform that supports the QorIQ LS1046A architecture
processor.

The LS1046A SOC is based on Layerscape Chassis2.

The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.

V1 can be referred here:
https://edk2.groups.io/g/devel/message/60577

Changes in V2 w.r.t V1:
- No functional changes
- Explaination Added for PATCH 2/6 Silicon/NXP/LS1043A: Fix the RCW bits' 
parsing
- Refer PATCH 1/6 Silicon/NXP: Add comments explaining RCW bits' parsing
  for expalaination for PATCH 2/6 Silicon/NXP/LS1043A: Fix the RCW bits' parsing

Pankaj Bansal (6):
  Silicon/NXP: Add comments explaining RCW bits' parsing
  Silicon/NXP/LS1043A: Fix the RCW bits' parsing
  Silicon/NXP: Add LS1046A Soc package
  Platform/NXP/LS1046AFRWY: Add ArmPlatformLib
  Platform/NXP: Add LS1046AFRWY Platform
  Platform/NXP/LS1046aFrwyPkg: Add VarStore

 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec |  23 +++
 Silicon/NXP/LS1046A/LS1046A.dec   |  13 ++
 Silicon/NXP/LS1046A/LS1046A.dsc.inc   |  42 +
 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc |  46 +
 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 169 ++
 .../Library/ArmPlatformLib/ArmPlatformLib.inf |  42 +
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf |  27 +++
 Silicon/NXP/LS1043A/Include/Soc.h |  29 ++-
 Silicon/NXP/LS1046A/Include/Soc.h |  63 +++
 Silicon/NXP/LS1046A/Include/SocSerDes.h   |  33 
 Silicon/NXP/LX2160A/Include/Soc.h |  28 ++-
 .../Library/ArmPlatformLib/ArmPlatformLib.c   | 147 +++
 .../ArmPlatformLib/ArmPlatformLibMem.c|  75 
 Silicon/NXP/LS1046A/Library/SocLib/SerDes.c   | 119 
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c   |  78 
 .../AArch64/ArmPlatformHelper.S   |  45 +
 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc  |  91 ++
 17 files changed, 1068 insertions(+), 2 deletions(-)
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
 create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
 create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc.inc
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
 create mode 100644 Silicon/NXP/LS1046A/Include/Soc.h
 create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SerDes.c
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc

-- 
2.17.1


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