date:20210206

[edk2-devel] [Patch 1/1] BaseTools/ECC: Add antlr version check

2021-02-06 Thread Bob Feng

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3201

ECC requires a specific version of Antlr installed.
This patch is to add a checker in the Ecc command wrapper
to check if the ECC required version of antlr is installed.

Signed-off-by: Bob Feng 
Cc: Liming Gao 
Cc: Yuwei Chen 
---
 BaseTools/BinWrappers/PosixLike/Ecc   | 22 +-
 BaseTools/BinWrappers/WindowsLike/Ecc.bat | 14 +-
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/BaseTools/BinWrappers/PosixLike/Ecc 
b/BaseTools/BinWrappers/PosixLike/Ecc
index 15edf52106bd..8a3539b8a604 100755
--- a/BaseTools/BinWrappers/PosixLike/Ecc
+++ b/BaseTools/BinWrappers/PosixLike/Ecc
@@ -9,6 +9,26 @@ fi
 full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a 
discussion of why $0 is not a good choice here
 dir=$(dirname "$full_cmd")
 cmd=${full_cmd##*/}
 
 export PYTHONPATH="$dir/../../Source/Python${PYTHONPATH:+:"$PYTHONPATH"}"
-exec "${python_exe:-python}" -m $cmd.EccMain "$@"
+pyver=`${python_exe} -c "import sys; print(sys.version_info.major)"`
+if [ $pyver == 3 ]; then
+echo "Checking the antlr4-python3-runtime version..."
+antlrver=`pip3 list | grep antlr4-python3-runtime`
+echo "Installed antlr4-python3-runtime version $antlrver"
+if [ "$antlrver"="antlr4-python3-runtime (4.7.1)" ]; then
+exec "${python_exe:-python}" -m $cmd.EccMain "$@"
+else
+echo "Please install antlr4-python3-runtime=4.7.1 for ECC usage"
+fi
+else
+echo "Checking the antlr-python-runtime version..."
+antlrver=`pip list | grep antlr-python-runtime`
+echo "Installed antlr-python-runtime version $antlrver"
+if [ "$antlrver"="antlr-python-runtime (3.0.1)" ]; then
+exec "${python_exe:-python}" -m $cmd.EccMain "$@"
+else
+echo "Please install antlr-python-runtime=3.0.1 for ECC usage"
+fi
+fi
+
diff --git a/BaseTools/BinWrappers/WindowsLike/Ecc.bat 
b/BaseTools/BinWrappers/WindowsLike/Ecc.bat
index ba1a15b3b8b0..bd739ef8e2b9 100644
--- a/BaseTools/BinWrappers/WindowsLike/Ecc.bat
+++ b/BaseTools/BinWrappers/WindowsLike/Ecc.bat
@@ -1,4 +1,16 @@
 @setlocal
 @set ToolName=%~n0%
 @set PYTHONPATH=%PYTHONPATH%;%BASE_TOOLS_PATH%\Source\Python
-@%PYTHON_COMMAND% -m %ToolName%.EccMain %*
+@for /f ' %%i in ('%PYTHON_COMMAND% -c "import sys; 
print(sys.version_info.major)"') do @set pyver=%%i
+@IF %pyver%==3 (
+@echo Checking the antlr4-python3-runtime version...
+@for /f "tokens=2" %%i in ('%PYTHON_COMMAND% -m pip list -l ^| findstr 
antlr4-python3-runtime') do @set antlr4version=%%i
+@echo Installed antlr4-python3-runtime version %antlr4version%
+@IF "%antlr4version%"=="4.7.1" (@%PYTHON_COMMAND% -m %ToolName%.EccMain %*) 
ELSE (Echo Please install antlr4-python3-runtime=4.7.1 for ECC usage)
+) ELSE (
+@echo Checking the antlr-python-runtime version...
+@for /f "tokens=2" %%i in ('%PYTHON_COMMAND% -m pip list -l ^| findstr 
antlr-python-runtime') do set antlr3version=%%i
+@echo Installed antlr-python-runtime version %antlr3version%
+@IF "%antlr3version%"=="3.0.1" (@%PYTHON_COMMAND% -m %ToolName%.EccMain %*) 
ELSE (Echo Please install antlr-python-runtime=3.0.1 for ECC usage)
+)
+
-- 
2.29.1.windows.1



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Re: [edk2-devel] [PATCH v2 1/1] UefiCpuPkg/CpuExceptionHandlerLib: Clear CET shadow stack token busy bit

2021-02-06 Thread Sheng Wei

HI JieWen,
Thank you for the comment. I have updated the patch to v3
Hi All,
The different between patch v2 and patch v3 is add more comment.
Could you help to continue the review .
Thank you.
BR
Sheng Wei 

> -Original Message-
> From: Yao, Jiewen 
> Sent: 2021年2月5日 17:59
> To: Sheng, W ; devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Laszlo
> Ersek ; Kumar, Rahul1 ;
> Feng, Roger 
> Subject: RE: [PATCH v2 1/1] UefiCpuPkg/CpuExceptionHandlerLib: Clear CET
> shadow stack token busy bit
> 
> Would you please add comment on why we need reserve and program the 8
> bytes here?
> Something like:
> 
> //
> // The highest address on the stack (0xFF8) is a save-previous-ssp token
> pointing to a location that is 40 bytes away �C 0xFD0.
> // The supervisor shadow stack token is just above it at address 0xFF0. This 
> is
> where the interrupt SSP table points.
> // So when an interrupt of exception occurs, we can use
> SAVESSP/RESTORESSP/CLEARSSBUSY for the supervisor shadow stack, // due
> to the reason the RETF in SMM exception handler cannot clear the BUSY flag
> with same CPL.
> // (only IRET or RETF with different CPL can clear BUSY flag) // Please refer 
> to
> UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for the full stack frame at
> runtime.
> //
> 
> -  mCetInterruptSsp = (UINT32)((UINTN)ShadowStack +
> EFI_PAGES_TO_SIZE(1) - sizeof(UINT64));
> +  InterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1)
> - sizeof(UINT64));
> +  *(UINT32 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) |
> 0x2;
> +  mCetInterruptSsp = InterruptSsp - sizeof(UINT64);
> 
> > -Original Message-
> > From: Sheng, W 
> > Sent: Friday, February 5, 2021 5:28 PM
> > To: devel@edk2.groups.io
> > Cc: Dong, Eric ; Ni, Ray ;
> > Laszlo Ersek ; Kumar, Rahul1
> > ; Yao, Jiewen ; Feng,
> > Roger 
> > Subject: [PATCH v2 1/1] UefiCpuPkg/CpuExceptionHandlerLib: Clear CET
> > shadow stack token busy bit
> >
> > If CET shadows stack feature enabled in SMM and stack switch is enabled.
> > When code execute from SMM handler to SMM exception, CPU will check
> > SMM exception shadow stack token busy bit if it is cleared or not.
> > If it is set, it will trigger #DF exception.
> > If it is not set, CPU will set the busy bit when enter SMM exception.
> > So, the busy bit should be cleared when return back form SMM exception
> > to SMM handler. Otherwise, keeping busy bit 1 will cause to trigger
> > #DF exception when enter SMM exception next time.
> > So, we use instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP to clear the
> > shadow stack token busy bit before RETF instruction in SMM exception.
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192
> >
> > Signed-off-by: Sheng Wei 
> > Cc: Eric Dong 
> > Cc: Ray Ni 
> > Cc: Laszlo Ersek 
> > Cc: Rahul Kumar 
> > Cc: Jiewen Yao 
> > Cc: Roger Feng 
> > ---
> >  .../DxeCpuExceptionHandlerLib.inf  |  3 ++
> >  .../PeiCpuExceptionHandlerLib.inf  |  3 ++
> >  .../SecPeiCpuExceptionHandlerLib.inf   |  4 ++
> >  .../SmmCpuExceptionHandlerLib.inf  |  3 ++
> >  .../X64/Xcode5ExceptionHandlerAsm.nasm | 48
> > --
> >  .../Xcode5SecPeiCpuExceptionHandlerLib.inf |  4 ++
> >  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c   |  5 ++-
> >  7 files changed, 66 insertions(+), 4 deletions(-)
> >
> > diff --git
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.
> > inf
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.
> > inf
> > index 07b34c92a8..e7a81bebdb 100644
> > ---
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.
> > inf
> > +++
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.
> > inf
> > @@ -43,6 +43,9 @@
> >gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> >gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> >
> > +[FeaturePcd]
> > +  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard##
> > CONSUMES
> > +
> >  [Packages]
> >MdePkg/MdePkg.dec
> >MdeModulePkg/MdeModulePkg.dec
> > diff --git
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.
> > inf
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.
> > inf
> > index feae7b3e06..cf5bfe4083 100644
> > ---
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.
> > inf
> > +++
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.
> > inf
> > @@ -57,3 +57,6 @@
> >  [Pcd]
> >gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard# CONSUMES
> >
> > +[FeaturePcd]
> > +  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard##
> > CONSUMES
> > +
> > diff --git
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandler
> L
> > ib.i
> > nf
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandler
> L
> > ib.i
> > nf
> >

[edk2-devel] [PATCH v3 0/1] Fix CET shadow stack token busy bit clear issue

2021-02-06 Thread Sheng Wei

If CET shadows stack feature enabled in SMM and stack switch is enabled.
When code execute from SMM handler to SMM exception, CPU will check SMM
exception shadow stack token busy bit if it is cleared or not.
If it is set, it will trigger #DF exception.
If it is not set, CPU will set the busy bit when enter SMM exception.
So, the busy bit should be cleared when return back form SMM exception to
SMM handler. Otherwise, keeping busy bit 1 will cause to trigger #DF
exception when enter SMM exception next time.
So, we use instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP to clear the
shadow stack token busy bit before RETF instruction in SMM exception.
Since open CI is using NASM 2.14.02, it has not supported CET instructions
yet. Use DB xx xx xx xx to replace the assembly instruction before NASM
2.15.01 is used.

Change from patch v1 to patch v2:
1 Add behavior description in source code comment.
2 Structure interrupt shadow stack memory in InitShadowStack().
3 Update commit comment.

Change from patch v2 to patch v3:
1 Add comment /UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192

Signed-off-by: Sheng Wei 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Cc: Rahul Kumar 
Cc: Jiewen Yao 
Cc: Roger Feng 

Sheng Wei (1):
  UefiCpuPkg/CpuExceptionHandlerLib: Clear CET shadow stack token busy
bit

 .../DxeCpuExceptionHandlerLib.inf  |  3 ++
 .../PeiCpuExceptionHandlerLib.inf  |  3 ++
 .../SecPeiCpuExceptionHandlerLib.inf   |  4 ++
 .../SmmCpuExceptionHandlerLib.inf  |  3 ++
 .../X64/Xcode5ExceptionHandlerAsm.nasm | 48 --
 .../Xcode5SecPeiCpuExceptionHandlerLib.inf |  4 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c   | 15 ++-
 7 files changed, 76 insertions(+), 4 deletions(-)

-- 
2.16.2.windows.1



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[edk2-devel] [PATCH v3 1/1] UefiCpuPkg/CpuExceptionHandlerLib: Clear CET shadow stack token busy bit

2021-02-06 Thread Sheng Wei

If CET shadows stack feature enabled in SMM and stack switch is enabled.
When code execute from SMM handler to SMM exception, CPU will check SMM
exception shadow stack token busy bit if it is cleared or not.
If it is set, it will trigger #DF exception.
If it is not set, CPU will set the busy bit when enter SMM exception.
So, the busy bit should be cleared when return back form SMM exception to
SMM handler. Otherwise, keeping busy bit 1 will cause to trigger #DF
exception when enter SMM exception next time.
So, we use instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP to clear the
shadow stack token busy bit before RETF instruction in SMM exception.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192

Signed-off-by: Sheng Wei 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Cc: Rahul Kumar 
Cc: Jiewen Yao 
Cc: Roger Feng 
---
 .../DxeCpuExceptionHandlerLib.inf  |  3 ++
 .../PeiCpuExceptionHandlerLib.inf  |  3 ++
 .../SecPeiCpuExceptionHandlerLib.inf   |  4 ++
 .../SmmCpuExceptionHandlerLib.inf  |  3 ++
 .../X64/Xcode5ExceptionHandlerAsm.nasm | 48 --
 .../Xcode5SecPeiCpuExceptionHandlerLib.inf |  4 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c   | 15 ++-
 7 files changed, 76 insertions(+), 4 deletions(-)

diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index 07b34c92a8..e7a81bebdb 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -43,6 +43,9 @@
   gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
   gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
 
+[FeaturePcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard## CONSUMES
+
 [Packages]
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
index feae7b3e06..cf5bfe4083 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
@@ -57,3 +57,6 @@
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard# CONSUMES
 
+[FeaturePcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard## CONSUMES
+
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
index 967cb61ba6..8ae4feae62 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
@@ -49,3 +49,7 @@
   LocalApicLib
   PeCoffGetEntryPointLib
   VmgExitLib
+
+[FeaturePcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard## CONSUMES
+
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
index 4cdb11c04e..5c3d1f7cfd 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
@@ -53,3 +53,6 @@
   DebugLib
   VmgExitLib
 
+[FeaturePcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard## CONSUMES
+
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
index 26cae56cc5..05a802a633 100644
--- 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
+++ 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
@@ -1,5 +1,5 @@
 
;-- 
;
-; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+; Copyright (c) 2012 - 2021, Intel Corporation. All rights reserved.
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Module Name:
@@ -13,6 +13,7 @@
 ; Notes:
 ;
 ;--
+%include "Nasm.inc"
 
 ;
 ; CommonExceptionHandler()
@@ -23,6 +24,7 @@
 extern ASM_PFX(mErrorCodeFlag); Error code flags for exceptions
 extern ASM_PFX(mDoFarReturnFlag)  ; Do far return flag
 extern ASM_PFX(CommonExceptionHandler)
+extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
 
 SECTION .data
 
@@ -371,8 +373,48 @@ DoReturn:
 pushqword [rax + 0x18]   ; save EFLAGS in new location
 mov rax, [rax]; restore rax
 popfq ; restore EFLAGS
-DB  0x48   ; prefix to composite "retq" with next "retf"
-retf  ; far return
+
+; The follow

[edk2-devel] [PATCH 8/8] Update Maintainers.txt for TigerlakeOpenBoardPkg

2021-02-06 Thread Heng Luo

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3175

This change adds owners to the the Maintainers.txt for TigerlakeOpenBoardPkg

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Signed-off-by: Heng Luo 
---
 Maintainers.txt | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index 34f0b58581..b2f1b67cf9 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -195,6 +195,12 @@ M: Rangasai V Chaganty 
 R: Deepika Kethi Reddy 
 R: Kathappan Esakkithevar 
 
+Platform/Intel/TigerlakeOpenBoardPkg
+F: Platform/Intel/TigerlakeOpenBoardPkg/
+M: Sai Chaganty 
+M: Nate DeSimone 
+R: Heng Luo 
+
 Platform/Intel/SimicsOpenBoardPkg
 F: Platform/Intel/SimicsOpenBoardPkg/
 M: Agyeman Prince 
-- 
2.24.0.windows.2



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[edk2-devel] [PATCH 7/8] Enable build for TigerlakeOpenBoardPkg

2021-02-06 Thread Heng Luo

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3175

This change adds the configuration to enable build for TigerlakeURvp.
Also it updates Tigerlake U Rvp details to the Readme.md.

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Signed-off-by: Heng Luo 
---
 Platform/Intel/Readme.md | 11 +++
 Platform/Intel/build.cfg |  1 +
 2 files changed, 12 insertions(+)

diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md
index f7bfc7aad2..b3b15405af 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -57,6 +57,7 @@ A UEFI firmware implementation using MinPlatformPkg is 
constructed using the fol
 * The `SimicsOpenBoardPkg` contains board implementations for the Simics 
hardware simulator.
 * The `WhiskeylakeOpenBoardPkg` contains board implementations for WhiskeyLake 
systems.
 * The `CometlakeOpenBoardPkg` contains board implementations for CometLake 
systems.
+* The `TigerlakeOpenBoardPkg` contains board implementations for TigerLake 
systems.
 
 ### **Supported Hardware**
 
@@ -75,6 +76,7 @@ A UEFI firmware implementation using MinPlatformPkg is 
constructed using the fol
 | RVP 3 | SkyLake, KabyLake, KabyLake Refresh  
  | KabylakeOpenBoardPkg | KabylakeRvp3   |
 | WHL-U DDR4 RVP| WhiskeyLake  
  | WhiskeylakeOpenBoardPkg  | WhiskeylakeURvp|
 | CML-U LPDDR3 RVP  | CometLake V1 
  | CometlakeOpenBoardPkg| CometlakeURvp  |
+| TGL-U LPDDR4 RVP  | TigerLake
  | TigerlakeOpenBoardPkg| TigerlakeURvp  |
 
 *Note: RVP = Reference and Validation Platform*
 
@@ -253,6 +255,11 @@ return back to the minimum platform caller.
   |   ||   |---build_config.cfg: CometlakeURvp 
specific build
   |   || settings 
environment variables.
   |   ||
+  |   ||--TigerlakeOpenBoardPkg
+  |   ||   |--TigerlakeURvp
+  |   ||   |---build_config.cfg: TigerlakeURvp 
specific build
+  |   || settings 
environment variables.
+  |   ||
   |--FSP
   
 
@@ -283,6 +290,10 @@ return back to the minimum platform caller.
 1. This firmware project has been tested booting to Microsoft Windows 10 x64 
with AHCI mode and External Graphic Device.
 2. This firmware project has been also tested booting to Ubuntu 17.10 with 
AHCI mode and Integrated Graphic Device.
 
+**TigerlakeOpenBoardPkg**
+1. This firmware project has been tested booting to Microsoft Windows 10 x64 
with AHCI mode and Integrated Graphic Device.
+2. This firmware project has been also tested booting to Puppy Linux 
BionicPup64 8.0 with AHCI mode and Integrated Graphic Device.
+
 ### **Package Builds**
 
 In some cases, such as BoardModulePkg, a package may provide a set of 
functionality that is included in other
diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg
index 8aa6b22956..97c5c9a290 100644
--- a/Platform/Intel/build.cfg
+++ b/Platform/Intel/build.cfg
@@ -60,3 +60,4 @@ KabylakeRvp3 = 
KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg
 UpXtreme = WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg
 WhiskeylakeURvp = WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg
 CometlakeURvp = CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg
+TigerlakeURvp = TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg
-- 
2.24.0.windows.2



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[edk2-devel] [PATCH 4/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add library instances

2021-02-06 Thread Heng Luo

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3175

Adds the following library instances:
  * TigerlakeURvp/Library/BoardAcpiLib
  * TigerlakeURvp/Library/BoardInitLib
  * TigerlakeURvp/Library/PeiPlatformHookLib

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Signed-off-by: Heng Luo 
---
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
  |  88 

 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
|  43 +++
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
  | 160 

 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmTigerlakeURvpAcpiEnableLib.c
|  51 +++
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
| 160 

 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
 |  96 

 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/GpioTableTigerlakeUDdr4Rvp.h
   |  93 
+
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/GpioTableTigerlakeUDdr4RvpPreMem.h
 |  33 +
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
  |  41 +
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
|  49 +
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
   |  88 

 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
 | 115 
+++
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpDetect.c
   |  39 +++
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPostMemLib.c
   | 153 
+
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPreMemLib.c
| 445 
+
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/TigerlakeURvpInit.h
|  23 +++
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c
 | 212 

 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
   |  58 ++
 18 files changed, 1947 insertions(+)

diff --git 
a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
 
b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 00..1436d9b79a
--- /dev/null
+++ 
b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,88 @@
+/** @file
+  Tiger Lake U RVP SMM Multi-Board ACPI Support library
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include

[edk2-devel] [PATCH 6/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add DSC and build files

2021-02-06 Thread Heng Luo

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3175

Adds the DSC and build files necessary to build the
TigerlakeURvp board instance.

Key files:
  * build_config.cfg - Board-specific build configuration file.
  * OpenBoardPkg.dsc - The TigerlakeURvp board description file.
  * OpenBoardPkgPcd.dsc - Used for other PCD customization.
  * OpenBoardPkg.fdf - The TigerlakeURvp board flash file.
  * OpenBoardPkgBuildOption.dsc - Sets build options Based on PCD values.

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Signed-off-by: Heng Luo 
---
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
| 347 
+++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
| 702 
++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgBuildOption.dsc 
| 141 
+
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc 
| 392 

 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg
|  34 ++
 5 files changed, 1616 insertions(+)

diff --git 
a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc 
b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
new file mode 100644
index 00..a4265a839c
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
@@ -0,0 +1,347 @@
+## @file
+#  The main build description file for the TigerlakeURvp board.
+#
+#  Copyright (c) 2021, Intel Corporation. All rights reserved.
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  DEFINE  PLATFORM_PACKAGE  = MinPlatformPkg
+  DEFINE  PLATFORM_SI_PACKAGE   = TigerlakeSiliconPkg
+  DEFINE  PLATFORM_SI_BIN_PACKAGE   = TigerlakeSiliconBinPkg
+  DEFINE  PLATFORM_FSP_BIN_PACKAGE  = TigerLakeFspBinPkg/Client
+  DEFINE  PLATFORM_BOARD_PACKAGE= TigerlakeOpenBoardPkg
+  DEFINE  BOARD = TigerlakeURvp
+  DEFINE  PROJECT   = $(PLATFORM_BOARD_PACKAGE)/$(BOARD)
+  DEFINE  PEI_ARCH  = IA32
+  DEFINE  DXE_ARCH  = X64
+  DEFINE  TOP_MEMORY_ADDRESS= 0x0
+
+  #
+  # Default value for OpenBoardPkg.fdf use
+  #
+  DEFINE BIOS_SIZE_OPTION = SIZE_120
+
+[Defines]
+  PLATFORM_NAME = $(PLATFORM_BOARD_PACKAGE)
+  PLATFORM_GUID = 465B0A0B-7AC1-443b-8F67-7B8DEC145F90
+  PLATFORM_VERSION  = 0.1
+  DSC_SPECIFICATION = 0x00010005
+  OUTPUT_DIRECTORY  = Build/$(PROJECT)
+  SUPPORTED_ARCHITECTURES   = IA32|X64
+  BUILD_TARGETS = DEBUG|RELEASE
+  SKUID_IDENTIFIER  = ALL
+
+  FLASH_DEFINITION  = $(PROJECT)/OpenBoardPkg.fdf
+  FIX_LOAD_TOP_MEMORY_ADDRESS   = 0x0
+
+  #
+  # Include PCD configuration for this board.
+  #
+  !include OpenBoardPkgPcd.dsc
+
+
+#
+# SKU Identification section - list of all SKU IDs supported by this board.
+#
+
+[SkuIds]
+  0|DEFAULT  # 0|DEFAULT is reserved and always required.
+  0x01|SkuIdTglU
+
+
+
+#
+# Includes section

[edk2-devel] [PATCH 5/8] TigerlakeOpenBoardPkg: Add modules

2021-02-06 Thread Heng Luo

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3175

Adds the following modules:
  * BiosInfo

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Signed-off-by: Heng Luo 
---
 Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.c   | 200 

 Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.inf |  83 
+++
 2 files changed, 283 insertions(+)

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.c 
b/Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.c
new file mode 100644
index 00..46c3d439c2
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.c
@@ -0,0 +1,200 @@
+/** @file
+  Driver for BIOS Info support.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define BASE_FV_SIZE 10
+
+#define FSP_WRAPPER_FV_SIZE 3
+
+#define TSN_MAC_ADDRESS_FV_SIZE 0
+
+#define BIOS_INFO_STRUCT_SIZE (BASE_FV_SIZE + FSP_WRAPPER_FV_SIZE + 
TSN_MAC_ADDRESS_FV_SIZE)
+
+
+/*
+  BIOS_INFO structure is the base of the firmware volume layout for Intel 
platform BIOS implementation
+  so security checker module can run based on the structure and throw 
warnings, error or deadloop
+  when any unexpected firmware volumes are detected.
+
+  BIOS_INFO is recommended to support full entries of firmware volumes present 
in a flash
+  with right type, attribute, version, flash map base address and size,
+  all associated information which is defined by BIOS_INFO_STRUCT structure.
+  - IBB firmware volumes, which are expected to be measured or/and verified
+by hardware base security solution to meet SecureBoot chain of trust
+(Intel BootGuard for example), have attribute 0x0.
+  - Post IBB firmware volumes, which are expected to be measured or/and 
verified
+by BIOS (TCG code for measurement, RSA2048SHA256Sign algorithm for 
verification for example),
+have attribute BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB.
+  - Else, follows Firmware Interface Table specification.
+*/
+#pragma pack (1)
+typedef struct {
+  BIOS_INFO_HEADER  Header;
+  BIOS_INFO_STRUCT  Entry[BIOS_INFO_STRUCT_SIZE];
+} BIOS_INFO;
+#pragma pack ()
+
+GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO  mBiosInfo = {
+  {
+BIOS_INFO_SIGNATURE,
+BIOS_INFO_STRUCT_SIZE,
+0,
+  },
+  {
+{
+  FIT_TYPE_07_BIOS_STARTUP_MODULE,
+  BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+  0x0100,
+  FixedPcdGet32 (PcdFlashNvStorageVariableSize) + FixedPcdGet32 
(PcdFlashNvStorageFtwWorkingSize) + FixedPcdGet32 
(PcdFlashNvStorageFtwSpareSize),
+  FixedPcdGet32 (PcdFlashNvStorageVariableBase)
+},
+{
+  FIT_TYPE_07_BIOS_STARTUP_MODULE,
+  BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+  0x0100,
+  FixedPcdGet32 (PcdFlashFvAdvancedSize),
+  FixedPcdGet32 (PcdFlashFvAdvancedBase)
+},
+{
+  FIT_TYPE_07_BIOS_STARTUP_MODULE,
+  BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+  0x0100,
+  FixedPcdGet32 (PcdFlashFvOptionalSize),
+  FixedPcdGet32 (PcdFlashFvOptionalBase)
+},
+{
+  FIT_TYPE_07_BIOS_STARTUP_MODULE,
+  BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+  0x0100,
+  FixedPcdGet32 (PcdFlashFvOsBootSize),
+  FixedPcdGet32 (PcdFlashFvOsBootBase)
+},
+{
+  FIT_TYPE_07_BIOS_STARTUP_MODULE,
+  BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+  0x0100,
+  FixedPcdGet32 (PcdFlashFvUefiBootSize),
+  FixedPcdGet32 (PcdFlashFvUefiBootBase)
+},
+{
+  FIT_TYPE_07_BIOS_STARTUP_MODULE,
+  BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+  0x0100,
+  FixedPcdGet32 (PcdFlashFvPostMemorySize),
+  FixedPcdGet32 (PcdFlashFvPostMemoryBase)
+},
+{
+  /*
+Note :
+Startup ACM is one of the binaries in FvFirmwareBinaries,
+so put type 07 but not type 02.
+FIT table will contain a type 02 entry with actual address
+of ACM binary (it is passed as an input to FitGen tool).
+  */
+  FIT_TYPE_07_BIOS_STARTUP_MODULE,
+  BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+  0x0100,
+  FixedPcdGet32 (PcdFlashFvFirmwareBinariesSize),
+  FixedPcdGet32 (PcdFlashFvFirmwareBinariesBase)
+},
+{
+  FIT_TYPE_07_BIOS_STARTUP_MODULE,
+  BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+  0x0100,
+  FixedPcdGet32 (PcdFlashFvFspSSize),
+  FixedPcdGet32 (PcdFlashFvFspSBase)
+},
+{
+  FIT_TYPE_07_BIOS_STARTUP_MODULE,
+  0x00,// IBB FV
+  0x0100,
+  FixedPcdGet32 (PcdFlashFvFspMSize),
+  FixedPcdGet32 (PcdFlashFvFspMBase)
+},
+{
+

[edk2-devel] [PATCH 2/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add fdf and header file

2021-02-06 Thread Heng Luo

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3175

Adds the following files:
  * TigerlakeURvp/Include/Fdf/FlashMapInclude.fdf
  * TigerlakeURvp/Include/PeiPlatformHookLib.h

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Signed-off-by: Heng Luo 
---
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapInclude.fdf
 |  54 ++
 
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/PeiPlatformHookLib.h 
   | 130 
++
 2 files changed, 184 insertions(+)

diff --git 
a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapInclude.fdf
 
b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapInclude.fdf
new file mode 100644
index 00..b21ae6401f
--- /dev/null
+++ 
b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapInclude.fdf
@@ -0,0 +1,54 @@
+## @file
+#  FDF file of Platform.
+#
+#  Copyright (c) 2021, Intel Corporation. All rights reserved.
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+#=#
+# 12 M BIOS - for FSP wrapper
+#=#
+DEFINE FLASH_BASE   = 
0xFF40  #
+DEFINE FLASH_SIZE   = 
0x00C0  #
+DEFINE FLASH_BLOCK_SIZE = 
0x0001  #
+DEFINE FLASH_NUM_BLOCKS = 
0x00C0  #
+#=#
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 
0x  # Flash addr (0xFF40)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize   = 
0x0006  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 
0x  # Flash addr (0xFF40)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize  = 
0x0002E000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset   = 
0x0002E000  # Flash addr (0xFF42E000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize= 
0x2000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 
0x0003  # Flash addr (0xFF43)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize  = 
0x0003  #
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset= 
0x000E  # Flash addr (0xFF4E)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize  = 
0x001A  #
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset   = 
0x0028  # Flash addr (0xFF68)
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize = 
0x0030  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset  = 
0x0058  # Flash addr (0xFF98)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize= 
0x000A  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset= 
0x0062  # Flash addr (0xFFA2)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize  = 
0x001D  #
+
+## Firmware binaries FV absolute address requires 256kB alignment
+## Build script checks the requirement.
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset   = 
0x0080  # Flash addr (0xFFC0)
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize = 
0x0008  # Keep 0x8 or larger
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset= 
0x0088  # Flash addr (0xFFC8)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize  = 
0x0007  # Keep 0x7 or larger, change MicrocodeFv.fdf in case that this 
value change
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset  = 
0x008F  # Flash addr (0xFFC0)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize= 
0x0008  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset= 
0x0097  # Flash addr (0xFFD7)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize  = 
0x000A  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset= 
0x00A1  # Flash addr (0xFFE1)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize  = 
0x0011  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset= 
0x00B2  # Flash addr (0xFFF2)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize  = 
0x0001  #
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset= 
0x00B3  # Flash addr (0xFFF3)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize

[edk2-devel] [PATCH 1/8] TigerlakeOpenBoardPkg: Add package and headers

2021-02-06 Thread Heng Luo

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3175

Create the TigerlakeOpenBoardPkg to provide board support code. The
package may support Tigerlake boards. The package serves as a board
support package in the EDK II Minimum Platform design. Silicon support
for this package is provided in TigerLakeFspBinPkg in the FSP repository
and TigerlakeSiliconPkg in the edk2-platforms repository.

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Signed-off-by: Heng Luo 
---
 Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardConfig.h |  61 
+
 Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardId.h |  17 
+
 Platform/Intel/TigerlakeOpenBoardPkg/Include/PolicyUpdateMacro.h   |  49 
+
 Platform/Intel/TigerlakeOpenBoardPkg/OpenBoardPkg.dec  | 153 
+
 4 files changed, 280 insertions(+)

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardConfig.h 
b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardConfig.h
new file mode 100644
index 00..148abcce74
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardConfig.h
@@ -0,0 +1,61 @@
+/** @file
+  Header file for Platform Boards Configurations.
+
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_BOARD_CONFIG_H
+#define _PLATFORM_BOARD_CONFIG_H
+
+#include 
+#include 
+
+
+#pragma pack(1)
+
+typedef struct {
+  UINT8 ClkReqNumber : 4;
+  UINT8 ClkReqSupported : 1;
+  UINT8 DeviceResetPadActiveHigh : 1;
+  UINT32 DeviceResetPad;
+} ROOT_PORT_CLK_INFO;
+
+typedef struct {
+  UINT8 Section;
+  UINT8 Pin;
+} EXPANDER_GPIO_CONFIG;
+
+typedef struct {
+  UINT8 Type;
+  UINT8 Reserved[3];  // alignment for COMMON_GPIO_CONFIG
+  union {
+UINT32 Pin;
+EXPANDER_GPIO_CONFIG Expander;
+  } u;
+} BOARD_GPIO_CONFIG;
+
+// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAGE 
from PCH RC.
+#define NOT_USED 0xFF
+#define FREE_RUNNING 0x80
+#define LAN_CLOCK0x70
+#define PCIE_PEG 0x40
+#define PCIE_PCH 0x00
+
+typedef struct {
+  UINT32 ClockUsage;
+  UINT32 ClkReqSupported;
+} PCIE_CLOCK_CONFIG;
+
+typedef union {
+  UINT64 Blob;
+  BOARD_GPIO_CONFIG  BoardGpioConfig;
+  ROOT_PORT_CLK_INFO Info;
+  PCIE_CLOCK_CONFIG  PcieClock;
+} PCD64_BLOB;
+
+#pragma pack()
+
+#endif // _PLATFORM_BOARD_CONFIG_H
+
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardId.h 
b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardId.h
new file mode 100644
index 00..2e1ee9eca4
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardId.h
@@ -0,0 +1,17 @@
+/** @file
+  Defines Platform BoardIds
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_BOARD_ID_H_
+#define _PLATFORM_BOARD_ID_H_
+
+// TigerLake Sku IDs
+#define SkuIdTglU 0x1
+
+// TigerLake Board Id 0x01
+#define BoardIdTglUDdr4   0x01
+
+#endif // _PLATFORM_BOARD_ID_H_
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Include/PolicyUpdateMacro.h 
b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
new file mode 100644
index 00..0848efe5b6
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
@@ -0,0 +1,49 @@
+
+/** @file
+  Macros for platform to update different types of policy.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _POLICY_UPDATE_MACRO_H_
+#define _POLICY_UPDATE_MACRO_H_
+
+#ifdef UPDATE_POLICY
+#undef UPDATE_POLICY
+#endif
+
+#ifdef COPY_POLICY
+#undef COPY_POLICY
+#endif
+
+#ifdef GET_POLICY
+#undef GET_POLICY
+#endif
+
+#ifdef AND_POLICY
+#undef AND_POLICY
+#endif
+
+#ifdef OR_POLICY
+#undef OR_POLICY
+#endif
+
+#if FixedPcdGetBool(PcdFspModeSelection) == 1
+//
+// MACROS for platform code use
+//
+#define UPDATE_POLICY(UpdField, ConfigField, Value)  UpdField = Value;
+#define COPY_POLICY(UpdField, ConfigField, Value, Size)  CopyMem (UpdField, 
Value, Size);
+#define GET_POLICY(UpdField, ConfigField, Value)  Value = UpdField;
+#define AND_POLICY(UpdField, ConfigField, Value)  UpdField &= Value;
+#define OR_POLICY(UpdField, ConfigField, Value)  UpdField |= Value;
+#else
+#define UPDATE_POLICY(UpdField, ConfigField, Value)  ConfigField = Value;
+#define COPY_POLICY(UpdField, ConfigField, Value, Size)  CopyMem (ConfigField, 
Value, Size);
+#define GET_POLICY(UpdField, ConfigField, Value)  Value = ConfigField;
+#define AND_POLICY(UpdField, ConfigField, Value)  ConfigField &= Value;
+#define OR_POLICY(UpdField, ConfigField, Value)  ConfigField |= Value;

[edk2-devel] [PATCH 3/8] TigerlakeOpenBoardPkg: Add library instances

2021-02-06 Thread Heng Luo

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3175

Adds the following library instances:
  * FspWrapper/Library/PeiFspPolicyInitLib
  * FspWrapper/Library/PeiSiDefaultPolicyInitLib
  * FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib
  * Library/BasePlatformHookLib
  * Library/SmmSpiFlashCommonLib
  * Policy/Library/DxeSiliconPolicyUpdateLib

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Signed-off-by: Heng Luo 
---
 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
|  79 
+++
 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c
 |  51 
+++
 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c
  |  27 +++
 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c
| 372 

 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c
   | 308 

 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h
   | 187 
+++
 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
 | 184 

 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c
 | 240 

 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSecurityPolicyInitLib.c
   |  49 +
 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c
 |  10 ++
 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPolicyInitLib.c
   |  39 +++
 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPolicyInitLib.inf
 |  38 ++
 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c
   |  40 
 
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf
 |  38 ++
 
Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
  | 460 

 
Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
|  51 
+++
 
Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
  |  49 
+

Re: [edk2-devel] [PATCH v1 0/1] Introduce DxeMmUnblockMemoryLib Interface

2021-02-06 Thread Wu, Hao A

Hello Kun,

Could you help to send the library interface together with its usage in modules 
in the series?
Thanks in advance.

Also, one more question is that are Tcg2Smm and VariableSmmRuntimeDxe the only 
modules need to be updated?
Or an investigation in the code base should be done to address all the 
potential modules affected?

Best Regards,
Hao Wu

From: devel@edk2.groups.io  On Behalf Of Kun Qin
Sent: Saturday, February 6, 2021 10:48 AM
To: Wu; Wu, Hao A ; devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH v1 0/1] Introduce DxeMmUnblockMemoryLib 
Interface

Hi Hao,

My plan was to follow up with the driver changes regarding Tcg2Smm and 
VariableSmmRuntimeDxe once this interface is officially checked in. But if it 
is preferred to submit the patch for Tcg2Smm and VariableSmmRuntimeDxe to make 
better sense on how this interface will be consumed, I can send them out in v2. 
Please let me know how you would like to proceed.

Thanks,
Kun



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[edk2-devel] [PATCH 8/8] Update Maintainers.txt for TigerlakeOpenBoardPkg

[edk2-devel] [PATCH 7/8] Enable build for TigerlakeOpenBoardPkg

[edk2-devel] [PATCH 4/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add library instances

[edk2-devel] [PATCH 6/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add DSC and build files

[edk2-devel] [PATCH 5/8] TigerlakeOpenBoardPkg: Add modules

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Re: [edk2-devel] [PATCH v1 0/1] Introduce DxeMmUnblockMemoryLib Interface

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