Re: [edk2-devel] [PATCH v6 18/36] UefiCpuPkg: Add a new CPU IO 2 driver named CpuMmio2Dxe

[Ni, Ray]

Reviewed-by: Ray Ni 

Thanks,
Ray
> -Original Message-
> From: Chao Li 
> Sent: Friday, January 5, 2024 5:44 PM
> To: devel@edk2.groups.io
> Cc: Ni, Ray ; Kumar, Rahul R ;
> Gerd Hoffmann ; Leif Lindholm
> ; Ard Biesheuvel ;
> Sami Mujawar 
> Subject: [PATCH v6 18/36] UefiCpuPkg: Add a new CPU IO 2 driver named
> CpuMmio2Dxe
> 
> CpuIo2Dxe only supports IO to access to CPU IO. Some ARCHs that do not
> implement ports for CPU IO require MMIO to access PCI IO, and they
> pretty much put the IO devices under the LPC bus, which is usually under
> the PCIe/PCI bus. CpuMmio2Dxe was added to meet these needs.
> 
> CpuMmio2Dxe depends on PcdPciIoTranslation. The code is copied from
> ArmPkg.
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
> 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> Cc: Leif Lindholm 
> Cc: Ard Biesheuvel 
> Cc: Sami Mujawar 
> Signed-off-by: Chao Li 
> ---
>  UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c   | 557
> +
>  UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf |  48 +++
>  UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni |  18 +
>  UefiCpuPkg/UefiCpuPkg.dsc  |   2 +
>  4 files changed, 625 insertions(+)
>  create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
>  create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
>  create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni
> 
> diff --git a/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
> b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
> new file mode 100644
> index 00..32ccac1cc6
> --- /dev/null
> +++ b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
> @@ -0,0 +1,557 @@
> +/** @file
> +  Produces the CPU I/O 2 Protocol.
> +
> +Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
> +Copyright (c) 2016, Linaro Ltd. All rights reserved.
> +Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
> reserved.
> +
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include 
> +
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define MAX_IO_PORT_ADDRESS  0x
> +
> +//
> +// Handle for the CPU I/O 2 Protocol
> +//
> +STATIC EFI_HANDLE  mHandle = NULL;
> +
> +//
> +// Lookup table for increment values based on transfer widths
> +//
> +STATIC CONST UINT8  mInStride[] = {
> +  1, // EfiCpuIoWidthUint8
> +  2, // EfiCpuIoWidthUint16
> +  4, // EfiCpuIoWidthUint32
> +  8, // EfiCpuIoWidthUint64
> +  0, // EfiCpuIoWidthFifoUint8
> +  0, // EfiCpuIoWidthFifoUint16
> +  0, // EfiCpuIoWidthFifoUint32
> +  0, // EfiCpuIoWidthFifoUint64
> +  1, // EfiCpuIoWidthFillUint8
> +  2, // EfiCpuIoWidthFillUint16
> +  4, // EfiCpuIoWidthFillUint32
> +  8  // EfiCpuIoWidthFillUint64
> +};
> +
> +//
> +// Lookup table for increment values based on transfer widths
> +//
> +STATIC CONST UINT8  mOutStride[] = {
> +  1, // EfiCpuIoWidthUint8
> +  2, // EfiCpuIoWidthUint16
> +  4, // EfiCpuIoWidthUint32
> +  8, // EfiCpuIoWidthUint64
> +  1, // EfiCpuIoWidthFifoUint8
> +  2, // EfiCpuIoWidthFifoUint16
> +  4, // EfiCpuIoWidthFifoUint32
> +  8, // EfiCpuIoWidthFifoUint64
> +  0, // EfiCpuIoWidthFillUint8
> +  0, // EfiCpuIoWidthFillUint16
> +  0, // EfiCpuIoWidthFillUint32
> +  0  // EfiCpuIoWidthFillUint64
> +};
> +
> +/**
> +  Check parameters to a CPU I/O 2 Protocol service request.
> +
> +  The I/O operations are carried out exactly as requested. The caller is
> responsible
> +  for satisfying any alignment and I/O width restrictions that a PI System 
> on a
> +  platform might require. For example on some platforms, width requests of
> +  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand,
> will
> +  be handled by the driver.
> +
> +  @param[in] MmioOperation  TRUE for an MMIO operation, FALSE for I/O
> Port operation.
> +  @param[in] Width  Signifies the width of the I/O or Memory 
> operation.
> +  @param[in] AddressThe base address of the I/O operation.
> +  @param[in] Count  The number of I/O operations to perform. The
> number of
> +bytes moved is Width size * Count, starting at 
> Address.
> +  @param[in] Buffer For read operations, the destination buffer to 
> store
> the results.
> +For write operations, the source buffer from 
> which to write
> data.
> +
> +  @retval EFI_SUCCESSThe parameters for this request pass the 
> checks.
> +  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
> +  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
> +  @retval EFI_UNSUPPORTEDThe Buffer is not aligned for the given
> Width.
> +  @retval EFI_UNSUPPORTEDThe address range specified by Address,
> Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +CpuIoCheckParameter (
> +  IN BOOLEANMmioOperation,
> +  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
> +  IN UINT64 Address,
> +  IN UINTN  

Re: [edk2-devel] [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default

[Ashish Singhal via groups.io]

Thanks Saloni. PR for getting this merged is available at 
https://github.com/tianocore/edk2/pull/5150

Thanks
Ashish


From: Kasbekar, Saloni 
Sent: Saturday, January 6, 2024 1:31 AM
To: Ashish Singhal ; devel@edk2.groups.io 
; Clark-williams, Zachary 
; Jeff Brasen 
Subject: RE: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default

External email: Use caution opening links or attachments


Yes, SetData does reset the previous configuration.



Reviewed-by: Saloni Kasbekar 



Thanks,

Saloni



From: Ashish Singhal 
Sent: Friday, January 5, 2024 2:34 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io; 
Clark-williams, Zachary ; Jeff Brasen 

Subject: Re: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



I do not recommend doing that. Setting policy via SetData does enough to wipe 
out any previous manual configuration and that is the goal for reset to default.



From: Kasbekar, Saloni 
mailto:saloni.kasbe...@intel.com>>
Sent: Friday, January 5, 2024 2:30 AM
To: Ashish Singhal mailto:ashishsin...@nvidia.com>>; 
devel@edk2.groups.io 
mailto:devel@edk2.groups.io>>; Clark-williams, Zachary 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Subject: RE: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



External email: Use caution opening links or attachments



Makes sense. Should we also set IfrNvData->DhcpEnable = TRUE when updating the 
Policy then?



From: Ashish Singhal mailto:ashishsin...@nvidia.com>>
Sent: Wednesday, January 3, 2024 8:52 AM
To: Kasbekar, Saloni 
mailto:saloni.kasbe...@intel.com>>; 
devel@edk2.groups.io; Clark-williams, Zachary 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Subject: Re: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



Hello Saloni,



Thanks for the feedback. After the reset, or when we disable configure from 
menu, GetData returns policy to static as the enum value is 0. However, setting 
value as static does not have any benefit as it forces to reuse the old network 
settings. Using DHCP really mimics the reset behavior that we see without any 
configuration done manually.



Thanks

Ashish





From: Kasbekar, Saloni 
mailto:saloni.kasbe...@intel.com>>
Sent: Tuesday, January 2, 2024 1:47 PM
To: Ashish Singhal mailto:ashishsin...@nvidia.com>>; 
devel@edk2.groups.io 
mailto:devel@edk2.groups.io>>; Clark-williams, Zachary 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Subject: RE: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



External email: Use caution opening links or attachments



Hi Ashish,



+Ip4NvData->Policy = Ip4Config2PolicyDhcp;

+Status= Ip4Cfg2->SetData (

+   Ip4Cfg2,

+   Ip4Config2DataTypePolicy,

+   sizeof (EFI_IP4_CONFIG2_POLICY),

+   >Policy

+   );



Here we’re assuming IfrFormNvData->DhcpEnable is TRUE. Should we check it 
before setting the policy and calling SetData()?



Thanks,

Saloni





From: Ashish Singhal mailto:ashishsin...@nvidia.com>>
Sent: Monday, January 1, 2024 8:48 AM
To: devel@edk2.groups.io; Kasbekar, Saloni 
mailto:saloni.kasbe...@intel.com>>; Clark-williams, 
Zachary 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Subject: Re: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



Hello,



Checking again for some feedback on this.



Thanks

Ashish





From: Ashish Singhal mailto:ashishsin...@nvidia.com>>
Sent: Thursday, December 14, 2023 4:42 PM
To: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>>; 
saloni.kasbe...@intel.com 
mailto:saloni.kasbe...@intel.com>>; 
zachary.clark-willi...@intel.com 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Cc: Ashish Singhal mailto:ashishsin...@nvidia.com>>
Subject: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



Exercising reset to default does not reset the settings.
Add handler code for the case where configuration is
disabled.

Signed-off-by: Ashish Singhal 
mailto:ashishsin...@nvidia.com>>
---
 NetworkPkg/Ip4Dxe/Ip4Config2Nv.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/NetworkPkg/Ip4Dxe/Ip4Config2Nv.c b/NetworkPkg/Ip4Dxe/Ip4Config2Nv.c
index e0b6a4d4a9..dac5817b7c 100644
--- a/NetworkPkg/Ip4Dxe/Ip4Config2Nv.c
+++ b/NetworkPkg/Ip4Dxe/Ip4Config2Nv.c
@@ -586,6 +586,31 @@ Ip4Config2ConvertIfrNvDataToConfigNvData (
   }

   if (IfrFormNvData->Configure != TRUE) {
+if (Ip4NvData->DnsAddress != NULL) {
+  FreePool (Ip4NvData->DnsAddress);
+   

Re: [edk2-devel] [PATCH 1/5] NetwokrPkg/HttpDxe: Refactor TlsCreateChild

[Saloni Kasbekar]

 //
 // Check whether we need to create Tls child and open the TLS protocol.
 //
+if (HttpInstance->UseHttps && !HttpInstance->TlsAlreadyCreated) {
+  // Create TLS child for this HTTP instance.
+  Status = TlsCreateChild (HttpInstance);
+  if (EFI_ERROR (Status)) {
 return EFI_DEVICE_ERROR;
   }

Considering we're not creating TlsChildHandle anymore, we should probably 
rename TlsCreateChild() to TlsCreateHandle(). Also update the comments 
accordingly.

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Michael Brown
Sent: Friday, January 5, 2024 9:12 AM
To: abner.ch...@amd.com; devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Clark-williams, Zachary 
; Nickle Wang ; Igor 
Kulchytskyy 
Subject: Re: [edk2-devel] [PATCH 1/5] NetwokrPkg/HttpDxe: Refactor 
TlsCreateChild

On 05/01/2024 08:37, abner.ch...@amd.com wrote:
> From: Abner Chang 
> 
> - Use HTTP instance as the parameter for TlsCreateChild function.
> - Install TLS protocol on the HTTP instance thats create TLS child.

Logic looks good to me, just some minor cosmetic comments.

Commit title has "NetwokrPkg" typo, should be "NetworkPkg".

> -  @return  The child handle with opened EFI_TLS_PROTOCOL and 
> EFI_TLS_CONFIGURATION_PROTOCOL.
> +  @return  EFI_SUCCESSTLS child handle is returned in 
> HttpInstance->TlsChildHandle
> +  with opened EFI_TLS_PROTOCOL and 
> EFI_TLS_CONFIGURATION_PROTOCOL.

Comment refers to TlsChildHandle, which no longer exists after this patch.

> -  @return  The child handle with opened EFI_TLS_PROTOCOL and 
> EFI_TLS_CONFIGURATION_PROTOCOL.
> +  @return  EFI_SUCCESSTLS child handle is returned in 
> HttpInstance->TlsChildHandle
> +  with opened EFI_TLS_PROTOCOL and 
> EFI_TLS_CONFIGURATION_PROTOCOL.

As above.

Reviewed-by: Michael Brown 

Michael








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Re: [edk2-devel] [PATCH v2] EmulatorPkg: Add EFI_STATUS return to EMU_THUNK_PROTOCOL.SetTime()

[Nate DeSimone]

Pushed as 9cf1d03

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Nate
> DeSimone
> Sent: Friday, September 29, 2023 3:12 PM
> To: devel@edk2.groups.io
> Cc: Andrew Fish ; Ni, Ray ; Kinney,
> Michael D ; Chiu, Chasel
> 
> Subject: [edk2-devel] [PATCH v2] EmulatorPkg: Add EFI_STATUS return to
> EMU_THUNK_PROTOCOL.SetTime()
> 
> There is an inconsistency between the UNIX and Windows implementations of
> EMU_THUNK_PROTOCOL.SetTime(). The Windows version returns an
> EFI_STATUS value whereas the the UNIX implementation is VOID. However,
> the UNIX implementation is an unimplemented stub whereas the Windows
> version is implementated.
> 
> The current EMU_THUNK_PROTOCOL function pointer definition specifies a
> VOID return type. However, EMU_THUNK_PROTOCOL.SetTime() is close to the
> spec defined gRT->SetTime() except for missing the EFI_STATUS return type.
> 
> Therefore, I conclude that the most sensible reconciliation is to add the
> EFI_STATUS return type to the protocol definition.
> 
> Cc: Andrew Fish 
> Cc: Ray Ni 
> Cc: Michael D Kinney 
> Cc: Chasel Chiu 
> Signed-off-by: Nate DeSimone 
> ---
>  EmulatorPkg/Include/Protocol/EmuThunk.h | 5 +++--
>  EmulatorPkg/Unix/Host/EmuThunk.c| 4 ++--
>  2 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/EmulatorPkg/Include/Protocol/EmuThunk.h
> b/EmulatorPkg/Include/Protocol/EmuThunk.h
> index c419d0a677..bdd57f410b 100644
> --- a/EmulatorPkg/Include/Protocol/EmuThunk.h
> +++ b/EmulatorPkg/Include/Protocol/EmuThunk.h
> @@ -2,6 +2,7 @@
>Emulator Thunk to abstract OS services from pure EFI code
> 
>Copyright (c) 2008 - 2011, Apple Inc. All rights reserved.
> +  Copyright (c) 2023, Intel Corporation. All rights reserved.
> 
>SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> @@ -148,12 +149,12 @@ VOID
>  typedef
>  VOID
>  (EFIAPI *EMU_GET_TIME)(
> -  OUT  EFI_TIME   *Time,
> +  OUT EFI_TIME*Time,
>OUT EFI_TIME_CAPABILITIES   *Capabilities OPTIONAL
>);
> 
>  typedef
> -VOID
> +EFI_STATUS
>  (EFIAPI *EMU_SET_TIME)(
>IN   EFI_TIME   *Time
>);
> diff --git a/EmulatorPkg/Unix/Host/EmuThunk.c
> b/EmulatorPkg/Unix/Host/EmuThunk.c
> index ee0843eebf..c57c105a53 100644
> --- a/EmulatorPkg/Unix/Host/EmuThunk.c
> +++ b/EmulatorPkg/Unix/Host/EmuThunk.c
> @@ -387,14 +387,14 @@ SecGetTime (
>}
>  }
> 
> -VOID
> +EFI_STATUS
>  SecSetTime (
>IN  EFI_TIME  *Time
>)
>  {
>// Don't change the time on the system
>// We could save delta to localtime() and have SecGetTime adjust return
> values?
> -  return;
> +  return EFI_UNSUPPORTED;
>  }
> 
>  EFI_STATUS
> --
> 2.39.2.windows.1
> 
> 
> 
> 
> 



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Re: [edk2-devel] [PATCH 2/5] NetwokrPkg/HttpDxe: Consider TLS certificate not found as a success case

[Saloni Kasbekar]

Reviewed-by: Saloni Kasbekar 

-Original Message-
From: abner.ch...@amd.com  
Sent: Friday, January 5, 2024 12:37 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Clark-williams, Zachary 
; Michael Brown ; Nickle Wang 
; Igor Kulchytskyy 
Subject: [PATCH 2/5] NetwokrPkg/HttpDxe: Consider TLS certificate not found as 
a success case

From: Abner Chang 

We still return EFI_SUCCESS to the caller when TlsConfigCertificate returns 
error, for the use case the platform doesn't require certificate for the 
specific HTTP session. This ensures HttpInitSession function still initiated 
and returns EFI_SUCCESS to the caller. The failure is pushed back to TLS DXE 
driver if the HTTP communication actually requires certificate.

Signed-off-by: Abner Chang 
Cc: Saloni Kasbekar 
Cc: Zachary Clark-williams 
Cc: Michael Brown 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
---
 NetworkPkg/HttpDxe/HttpsSupport.c | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/NetworkPkg/HttpDxe/HttpsSupport.c 
b/NetworkPkg/HttpDxe/HttpsSupport.c
index a07323ff0bd..04a830f7152 100644
--- a/NetworkPkg/HttpDxe/HttpsSupport.c
+++ b/NetworkPkg/HttpDxe/HttpsSupport.c
@@ -722,8 +722,21 @@ TlsConfigureSession (
   //
   Status = TlsConfigCertificate (HttpInstance);
   if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "TLS Certificate Config Error!\n"));
-return Status;
+if (Status == EFI_NOT_FOUND) {
+  DEBUG((DEBUG_WARN, "TLS Certificate is not found on the system!\n"));
+  //
+  // We still return EFI_SUCCESS to the caller when TlsConfigCertificate
+  // returns error, for the use case the platform doesn't require
+  // certificate for the specific HTTP session. This ensures
+  // HttpInitSession function still initiated and returns EFI_SUCCESS to
+  // the caller. The failure is pushed back to TLS DXE driver if the
+  // HTTP communication actually requires certificate.
+  //
+  Status = EFI_SUCCESS;
+} else {
+  DEBUG((DEBUG_ERROR, "TLS Certificate Config Error!\n"));
+  return Status;
+}
   }
 
   //
--
2.37.1.windows.1



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Re: [edk2-devel] [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default

[Saloni Kasbekar]

Yes, SetData does reset the previous configuration.

Reviewed-by: Saloni Kasbekar 

Thanks,
Saloni

From: Ashish Singhal 
Sent: Friday, January 5, 2024 2:34 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io; 
Clark-williams, Zachary ; Jeff Brasen 

Subject: Re: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default

I do not recommend doing that. Setting policy via SetData does enough to wipe 
out any previous manual configuration and that is the goal for reset to default.

From: Kasbekar, Saloni 
mailto:saloni.kasbe...@intel.com>>
Sent: Friday, January 5, 2024 2:30 AM
To: Ashish Singhal mailto:ashishsin...@nvidia.com>>; 
devel@edk2.groups.io 
mailto:devel@edk2.groups.io>>; Clark-williams, Zachary 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Subject: RE: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default

External email: Use caution opening links or attachments


Makes sense. Should we also set IfrNvData->DhcpEnable = TRUE when updating the 
Policy then?



From: Ashish Singhal mailto:ashishsin...@nvidia.com>>
Sent: Wednesday, January 3, 2024 8:52 AM
To: Kasbekar, Saloni 
mailto:saloni.kasbe...@intel.com>>; 
devel@edk2.groups.io; Clark-williams, Zachary 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Subject: Re: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



Hello Saloni,



Thanks for the feedback. After the reset, or when we disable configure from 
menu, GetData returns policy to static as the enum value is 0. However, setting 
value as static does not have any benefit as it forces to reuse the old network 
settings. Using DHCP really mimics the reset behavior that we see without any 
configuration done manually.



Thanks

Ashish





From: Kasbekar, Saloni 
mailto:saloni.kasbe...@intel.com>>
Sent: Tuesday, January 2, 2024 1:47 PM
To: Ashish Singhal mailto:ashishsin...@nvidia.com>>; 
devel@edk2.groups.io 
mailto:devel@edk2.groups.io>>; Clark-williams, Zachary 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Subject: RE: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



External email: Use caution opening links or attachments



Hi Ashish,



+Ip4NvData->Policy = Ip4Config2PolicyDhcp;

+Status= Ip4Cfg2->SetData (

+   Ip4Cfg2,

+   Ip4Config2DataTypePolicy,

+   sizeof (EFI_IP4_CONFIG2_POLICY),

+   >Policy

+   );



Here we're assuming IfrFormNvData->DhcpEnable is TRUE. Should we check it 
before setting the policy and calling SetData()?



Thanks,

Saloni





From: Ashish Singhal mailto:ashishsin...@nvidia.com>>
Sent: Monday, January 1, 2024 8:48 AM
To: devel@edk2.groups.io; Kasbekar, Saloni 
mailto:saloni.kasbe...@intel.com>>; Clark-williams, 
Zachary 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Subject: Re: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



Hello,



Checking again for some feedback on this.



Thanks

Ashish





From: Ashish Singhal mailto:ashishsin...@nvidia.com>>
Sent: Thursday, December 14, 2023 4:42 PM
To: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>>; 
saloni.kasbe...@intel.com 
mailto:saloni.kasbe...@intel.com>>; 
zachary.clark-willi...@intel.com 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Cc: Ashish Singhal mailto:ashishsin...@nvidia.com>>
Subject: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



Exercising reset to default does not reset the settings.
Add handler code for the case where configuration is
disabled.

Signed-off-by: Ashish Singhal 
mailto:ashishsin...@nvidia.com>>
---
 NetworkPkg/Ip4Dxe/Ip4Config2Nv.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/NetworkPkg/Ip4Dxe/Ip4Config2Nv.c b/NetworkPkg/Ip4Dxe/Ip4Config2Nv.c
index e0b6a4d4a9..dac5817b7c 100644
--- a/NetworkPkg/Ip4Dxe/Ip4Config2Nv.c
+++ b/NetworkPkg/Ip4Dxe/Ip4Config2Nv.c
@@ -586,6 +586,31 @@ Ip4Config2ConvertIfrNvDataToConfigNvData (
   }

   if (IfrFormNvData->Configure != TRUE) {
+if (Ip4NvData->DnsAddress != NULL) {
+  FreePool (Ip4NvData->DnsAddress);
+  Ip4NvData->DnsAddress  = NULL;
+  Ip4NvData->DnsAddressCount = 0;
+}
+
+if (Ip4NvData->GatewayAddress != NULL) {
+  FreePool (Ip4NvData->GatewayAddress);
+  Ip4NvData->GatewayAddress  = NULL;
+  Ip4NvData->GatewayAddressCount = 0;
+}
+
+if (Ip4NvData->ManualAddress != NULL) {
+  FreePool (Ip4NvData->ManualAddress);
+  Ip4NvData->ManualAddress  = NULL;
+  

Re: [edk2-devel] [PATCH v1 1/1] BoardModulePkg\Library\BiosIdLib: Support Standalone MM

[Nate DeSimone]

Pushed as b46ecad

> -Original Message-
> From: Huang, Li-Xia 
> Sent: Monday, December 25, 2023 11:56 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Desimone, Nathaniel L
> 
> Subject: [PATCH v1 1/1] BoardModulePkg\Library\BiosIdLib: Support
> Standalone MM
> 
> Add Standalone Mm BiosIdLib and format code with Uncrustify.
> 
> Cc: Eric Dong 
> Cc: Nate DeSimone 
> 
> Signed-off-by: Lixia Huang 
> ---
>  Platform/Intel/BoardModulePkg/Library/BiosIdLib/BiosIdCommon.c|
> 96 
>  Platform/Intel/BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.c| 
> 111
> +++---
>  Platform/Intel/BoardModulePkg/Library/BiosIdLib/PeiBiosIdLib.c| 
> 118
> +++-
>  Platform/Intel/BoardModulePkg/Library/BiosIdLib/StandaloneMmBiosIdLib.c
> |  65 +++
>  Platform/Intel/BoardModulePkg/BoardModulePkg.dsc  |  
>  1 +
>  Platform/Intel/BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.inf  |  
>  1
> +
>  Platform/Intel/BoardModulePkg/Library/BiosIdLib/PeiBiosIdLib.inf  |  
>  6
> +-
> 
> Platform/Intel/BoardModulePkg/Library/BiosIdLib/StandaloneMmBiosIdLib.i
> nf |  42 +++
>  8 files changed, 241 insertions(+), 199 deletions(-)
> 
> diff --git
> a/Platform/Intel/BoardModulePkg/Library/BiosIdLib/BiosIdCommon.c
> b/Platform/Intel/BoardModulePkg/Library/BiosIdLib/BiosIdCommon.c
> new file mode 100644
> index ..5735566bfe3a
> --- /dev/null
> +++ b/Platform/Intel/BoardModulePkg/Library/BiosIdLib/BiosIdCommon.c
> @@ -0,0 +1,96 @@
> +/** @file
> +  Boot service common BIOS ID library implementation.
> +
> +  These functions in this file can be called during DXE and cannot be
> + called during runtime  or in SMM which should use a RT or SMM library.
> +
> +
> +Copyright (c) 2023, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/**
> +  This function returns the BIOS Version & Release Date and Time by getting
> and converting BIOS ID.
> +
> +  @param[out] BiosVersion   The Bios Version out of the conversion.
> +  @param[out] BiosReleaseDate   The Bios Release Date out of the
> conversion.
> +  @param[out] BiosReleaseTime   The Bios Release Time out of the
> conversion.
> +
> +  @retval EFI_SUCCESS   BIOS Version & Release Date and Time have
> been got successfully.
> +  @retval EFI_NOT_FOUND BIOS ID image is not found, and no
> parameter will be modified.
> +  @retval EFI_INVALID_PARAMETER All the parameters are NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +GetBiosVersionDateTime (
> +  OUT CHAR16  *BiosVersion OPTIONAL,
> +  OUT CHAR16  *BiosReleaseDate OPTIONAL,
> +  OUT CHAR16  *BiosReleaseTime OPTIONAL
> +  )
> +{
> +  EFI_STATUS Status;
> +  BIOS_ID_IMAGE  BiosIdImage;
> +
> +  if ((BiosVersion == NULL) && (BiosReleaseDate == NULL) &&
> (BiosReleaseTime == NULL)) {
> +return EFI_INVALID_PARAMETER;
> +  }
> +
> +  Status = GetBiosId ();
> +  if (EFI_ERROR (Status)) {
> +return EFI_NOT_FOUND;
> +  }
> +
> +  if (BiosVersion != NULL) {
> +//
> +// Fill the BiosVersion data from the BIOS ID.
> +//
> +CopyMem (BiosVersion, &(BiosIdImage.BiosIdString), sizeof
> + (BIOS_ID_STRING));  }
> +
> +  if (BiosReleaseDate != NULL) {
> +//
> +// Fill the build timestamp date from the BIOS ID in the "MM/DD/YY"
> format.
> +//
> +BiosReleaseDate[0] = BiosIdImage.BiosIdString.TimeStamp[2];
> +BiosReleaseDate[1] = BiosIdImage.BiosIdString.TimeStamp[3];
> +BiosReleaseDate[2] = (CHAR16)((UINT8)('/'));
> +
> +BiosReleaseDate[3] = BiosIdImage.BiosIdString.TimeStamp[4];
> +BiosReleaseDate[4] = BiosIdImage.BiosIdString.TimeStamp[5];
> +BiosReleaseDate[5] = (CHAR16)((UINT8)('/'));
> +
> +//
> +// Add 20 for SMBIOS table
> +// Current Linux kernel will misjudge 09 as year 0, so using 2009 for
> SMBIOS table
> +//
> +BiosReleaseDate[6] = '2';
> +BiosReleaseDate[7] = '0';
> +BiosReleaseDate[8] = BiosIdImage.BiosIdString.TimeStamp[0];
> +BiosReleaseDate[9] = BiosIdImage.BiosIdString.TimeStamp[1];
> +
> +BiosReleaseDate[10] = (CHAR16)((UINT8)('\0'));  }
> +
> +  if (BiosReleaseTime != NULL) {
> +//
> +// Fill the build timestamp time from the BIOS ID in the "HH:MM" format.
> +//
> +BiosReleaseTime[0] = BiosIdImage.BiosIdString.TimeStamp[6];
> +BiosReleaseTime[1] = BiosIdImage.BiosIdString.TimeStamp[7];
> +BiosReleaseTime[2] = (CHAR16)((UINT8)(':'));
> +
> +BiosReleaseTime[3] = BiosIdImage.BiosIdString.TimeStamp[8];
> +BiosReleaseTime[4] = BiosIdImage.BiosIdString.TimeStamp[9];
> +
> +BiosReleaseTime[5] = (CHAR16)((UINT8)('\0'));  }
> +
> +  return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.c
> b/Platform/Intel/BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.c
> index 3e614d9efc3e..6535bb36f6c9 100644
> --- 

Re: [edk2-devel] [PATCH v1 1/1] BoardModulePkg\Library\BiosIdLib: Support Standalone MM

[Nate DeSimone]

Hi Li,

It looks like the standalone MM version of this library is missing the search 
for the BiosId file. I suspect the issue you ran into is that standalone MM 
only has support for 1 FV, and it is highly likely that the BiosId file is not 
in the standalone MM FV. This is understandable; however, it does highlight yet 
another deficiency in the architecture of standalone MM. Again, that is not 
your fault and is beyond the scope of this patch.

Reviewed-by: Nate DeSimone 

> -Original Message-
> From: Huang, Li-Xia 
> Sent: Monday, December 25, 2023 11:56 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Desimone, Nathaniel L
> 
> Subject: [PATCH v1 1/1] BoardModulePkg\Library\BiosIdLib: Support
> Standalone MM
> 
> Add Standalone Mm BiosIdLib and format code with Uncrustify.
> 
> Cc: Eric Dong 
> Cc: Nate DeSimone 
> 
> Signed-off-by: Lixia Huang 
> ---
>  Platform/Intel/BoardModulePkg/Library/BiosIdLib/BiosIdCommon.c|
> 96 
>  Platform/Intel/BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.c| 
> 111
> +++---
>  Platform/Intel/BoardModulePkg/Library/BiosIdLib/PeiBiosIdLib.c| 
> 118
> +++-
>  Platform/Intel/BoardModulePkg/Library/BiosIdLib/StandaloneMmBiosIdLib.c
> |  65 +++
>  Platform/Intel/BoardModulePkg/BoardModulePkg.dsc  |  
>  1 +
>  Platform/Intel/BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.inf  |  
>  1
> +
>  Platform/Intel/BoardModulePkg/Library/BiosIdLib/PeiBiosIdLib.inf  |  
>  6
> +-
> 
> Platform/Intel/BoardModulePkg/Library/BiosIdLib/StandaloneMmBiosIdLib.i
> nf |  42 +++
>  8 files changed, 241 insertions(+), 199 deletions(-)
> 
> diff --git
> a/Platform/Intel/BoardModulePkg/Library/BiosIdLib/BiosIdCommon.c
> b/Platform/Intel/BoardModulePkg/Library/BiosIdLib/BiosIdCommon.c
> new file mode 100644
> index ..5735566bfe3a
> --- /dev/null
> +++ b/Platform/Intel/BoardModulePkg/Library/BiosIdLib/BiosIdCommon.c
> @@ -0,0 +1,96 @@
> +/** @file
> +  Boot service common BIOS ID library implementation.
> +
> +  These functions in this file can be called during DXE and cannot be
> + called during runtime  or in SMM which should use a RT or SMM library.
> +
> +
> +Copyright (c) 2023, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/**
> +  This function returns the BIOS Version & Release Date and Time by getting
> and converting BIOS ID.
> +
> +  @param[out] BiosVersion   The Bios Version out of the conversion.
> +  @param[out] BiosReleaseDate   The Bios Release Date out of the
> conversion.
> +  @param[out] BiosReleaseTime   The Bios Release Time out of the
> conversion.
> +
> +  @retval EFI_SUCCESS   BIOS Version & Release Date and Time have
> been got successfully.
> +  @retval EFI_NOT_FOUND BIOS ID image is not found, and no
> parameter will be modified.
> +  @retval EFI_INVALID_PARAMETER All the parameters are NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +GetBiosVersionDateTime (
> +  OUT CHAR16  *BiosVersion OPTIONAL,
> +  OUT CHAR16  *BiosReleaseDate OPTIONAL,
> +  OUT CHAR16  *BiosReleaseTime OPTIONAL
> +  )
> +{
> +  EFI_STATUS Status;
> +  BIOS_ID_IMAGE  BiosIdImage;
> +
> +  if ((BiosVersion == NULL) && (BiosReleaseDate == NULL) &&
> (BiosReleaseTime == NULL)) {
> +return EFI_INVALID_PARAMETER;
> +  }
> +
> +  Status = GetBiosId ();
> +  if (EFI_ERROR (Status)) {
> +return EFI_NOT_FOUND;
> +  }
> +
> +  if (BiosVersion != NULL) {
> +//
> +// Fill the BiosVersion data from the BIOS ID.
> +//
> +CopyMem (BiosVersion, &(BiosIdImage.BiosIdString), sizeof
> + (BIOS_ID_STRING));  }
> +
> +  if (BiosReleaseDate != NULL) {
> +//
> +// Fill the build timestamp date from the BIOS ID in the "MM/DD/YY"
> format.
> +//
> +BiosReleaseDate[0] = BiosIdImage.BiosIdString.TimeStamp[2];
> +BiosReleaseDate[1] = BiosIdImage.BiosIdString.TimeStamp[3];
> +BiosReleaseDate[2] = (CHAR16)((UINT8)('/'));
> +
> +BiosReleaseDate[3] = BiosIdImage.BiosIdString.TimeStamp[4];
> +BiosReleaseDate[4] = BiosIdImage.BiosIdString.TimeStamp[5];
> +BiosReleaseDate[5] = (CHAR16)((UINT8)('/'));
> +
> +//
> +// Add 20 for SMBIOS table
> +// Current Linux kernel will misjudge 09 as year 0, so using 2009 for
> SMBIOS table
> +//
> +BiosReleaseDate[6] = '2';
> +BiosReleaseDate[7] = '0';
> +BiosReleaseDate[8] = BiosIdImage.BiosIdString.TimeStamp[0];
> +BiosReleaseDate[9] = BiosIdImage.BiosIdString.TimeStamp[1];
> +
> +BiosReleaseDate[10] = (CHAR16)((UINT8)('\0'));  }
> +
> +  if (BiosReleaseTime != NULL) {
> +//
> +// Fill the build timestamp time from the BIOS ID in the "HH:MM" format.
> +//
> +BiosReleaseTime[0] = BiosIdImage.BiosIdString.TimeStamp[6];
> +BiosReleaseTime[1] = BiosIdImage.BiosIdString.TimeStamp[7];
> +

Re: [edk2-devel] [PATCH 0/4] RISC-V: Add support for Sstc extension

[Pedro Falcato]

On Wed, Jan 3, 2024 at 1:59 PM Sunil V L  wrote:
>
> This series adds the support for RISV-V Sstc extension in EDK2 timer

nit: RISC-V
> implementation. Sstc extension allows S-mode software to program the
> timer directly without using SBI calls.
>
> Currently, PCD variable is used to detect whether feature is enabled. By
> default the feature is enabled and platforms need to set the PCD to
> disable the feature if Sstc is not supported.
>
> For RiscVVirtQemu, it is disabled by default (until extension discovery
> feature is enabled).

I'm curious, what do you want Sstc for? Is the performance difference
measurable (if so, please post numbers, and add them to the commit)?
Does it have any other advantages?

-- 
Pedro


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Re: [edk2-devel] [PATCH v1 1/1] StandaloneMmPkg: Initialise serial port early in StandaloneMmEntryPoint

[Oliver Smith-Denny]

On 1/5/2024 9:22 AM, levi.yun wrote:


Hi Ard :)


So now we will always initialize the serial port in the entrypoint
only because DebugLib might use it later with doing the
initialization.

That doesn't sound quite correct to me.

Could you explain why we cannot rely on DebugLib to call the
initializer / constructor at the right time?

Because, DebugLib constructor which use serial port is called in
StandAloneMmMain function.
But, this constrcutor is in _ModuleEntryPoint in StandAloneMmCoreEntry.

That means all DEBUG used in _ModuleEntryPoint can use uninitialized
serial port.
one of typical example is GetSpmVersion function.

     _ModuleEntryPoint (in StandAloneMmCoreEntry)

  // Hazard Area start
     GetSpmVersion
     DEBUG (DEBUG_INFO, xxx)  // It could be use uninitalized
Serial port.

     ...
     //  Hazard Area end
     ProcessModuleEntryPointList (StandAloneMmMain)
     ProcessLibraryConstructorList // Here. call DebugLib
constructor with SerialPortIntialize

When you see above, I would be clear. between Hazard Area Start to
Hazard Area End.
DEBUG macro would use uninitailized Serial port if that's not
initialized by TF-A.

So, It should be call SerialPortInitialized at the _ModuleEntryPoint.


+ Laszlo

This sounds very similar to our DxeCore early serial logging discussion
a couple months ago :).

Laszlo wrote up a good summary here: 
https://edk2.groups.io/g/devel/topic/101203427#109235.


If I am understanding correctly, this would be the "lower left" in
Laszlo's diagram.

Standalone MM is likely smaller missing window than in DxeCore, but
some important information could be lost there (like the SPM version
called out, which could be very important for debugging early crashes).

So this goes back to should be we have a more generic solution for the
cores to use early logging, by fixing the SerialPortLibs? I'll parse
this more and reread the old thread further, still paging the info back
in.

Oliver


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Re: [edk2-devel] [PATCH v1 1/1] StandaloneMmPkg: Initialise serial port early in StandaloneMmEntryPoint

[levi.yun]

Hi Ard :)


So now we will always initialize the serial port in the entrypoint
only because DebugLib might use it later with doing the
initialization.

That doesn't sound quite correct to me.

Could you explain why we cannot rely on DebugLib to call the
initializer / constructor at the right time?

Because, DebugLib constructor which use serial port is called in
StandAloneMmMain function.
But, this constrcutor is in _ModuleEntryPoint in StandAloneMmCoreEntry.

That means all DEBUG used in _ModuleEntryPoint can use uninitialized
serial port.
one of typical example is GetSpmVersion function.

_ModuleEntryPoint (in StandAloneMmCoreEntry)

 // Hazard Area start
GetSpmVersion
DEBUG (DEBUG_INFO, xxx)  // It could be use uninitalized
Serial port.

...
//  Hazard Area end
ProcessModuleEntryPointList (StandAloneMmMain)
ProcessLibraryConstructorList // Here. call DebugLib
constructor with SerialPortIntialize

When you see above, I would be clear. between Hazard Area Start to
Hazard Area End.
DEBUG macro would use uninitailized Serial port if that's not
initialized by TF-A.

So, It should be call SerialPortInitialized at the _ModuleEntryPoint.








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Re: [edk2-devel] [RFC][PATCH 0/2] Introduce HTTPS Platform TLS policy

[Michael Brown]

On 05/01/2024 08:41, Chang, Abner wrote:

We are not aware there is a TlsConnectSession() for TLS handshake using the 
default TLS configuration data and it returns a failure as expected because the 
default TLS configuration is TLS_VERIFY_HOST without certificate installed on 
system.
This happens in HttpInitSession before notifying HttpEventInitSession event,  
so we have to reconfigure TLS config data before TlsConnectSession() function.
As there is an existing HttpEventTlsConnectSession event notified after 
TlsConnectSession(), that makes sense to me to introduce a new HTTP event 
HttpEventTlsConfigured as I mentioned in previous conversation and notify 
callback functions after TlsConfigureSession().
Upper layer HTTP application then listen to HttpEventTlsConfigured event and 
reconfigure TLS configuration data in the callback function.


Sounds good to me.  Thank you for the improvements.  I think this design 
is now ready.


Thanks,

Michael



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Re: [edk2-devel] [PATCH 3/5] NetwokrPkg/HttpDxe: Add HttpEventTlsConfigured HTTP callback event

[Michael Brown]

On 05/01/2024 08:37, abner.ch...@amd.com wrote:

+  ///
+  /// The Status of Event to configure TLS configuration data.
+  /// EventStatus:
+  /// EFI_SUCCESSThe TLS is configured successfully with the 
default value.
+  /// EFI_INVALID_PARAMETER  One or more input parameters to SetSessionData() 
is invalid.
+  /// EFI_NOT_READY  Current TLS session state is NOT 
EfiTlsSessionStateNotStarted.
+  /// EFI_NOT_FOUND  Fail to get 'HttpTlsCipherList' variable.
+  /// Others Other error as indicated.
+  ///
+  HttpEventTlsConfigured,
+


Since this changes the ABI, you may want to also update the protocol 
GUID to prevent strange errors if old and new binaries are used on the 
same system.


Reviewed-by: Michael Brown 

Thanks,

Michael



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Re: [edk2-devel] [PATCH 2/5] NetwokrPkg/HttpDxe: Consider TLS certificate not found as a success case

[Michael Brown]

On 05/01/2024 08:37, abner.ch...@amd.com wrote:

We still return EFI_SUCCESS to the caller when TlsConfigCertificate
returns error, for the use case the platform doesn't require
certificate for the specific HTTP session. This ensures
HttpInitSession function still initiated and returns EFI_SUCCESS to
the caller. The failure is pushed back to TLS DXE driver if the
HTTP communication actually requires certificate.


Reviewed-by: Michael Brown 

Thanks,

Michael



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Re: [edk2-devel] [PATCH 1/5] NetwokrPkg/HttpDxe: Refactor TlsCreateChild

[Michael Brown]

On 05/01/2024 08:37, abner.ch...@amd.com wrote:

From: Abner Chang 

- Use HTTP instance as the parameter for TlsCreateChild function.
- Install TLS protocol on the HTTP instance thats create TLS child.


Logic looks good to me, just some minor cosmetic comments.

Commit title has "NetwokrPkg" typo, should be "NetworkPkg".


-  @return  The child handle with opened EFI_TLS_PROTOCOL and 
EFI_TLS_CONFIGURATION_PROTOCOL.
+  @return  EFI_SUCCESSTLS child handle is returned in 
HttpInstance->TlsChildHandle
+  with opened EFI_TLS_PROTOCOL and 
EFI_TLS_CONFIGURATION_PROTOCOL.


Comment refers to TlsChildHandle, which no longer exists after this patch.


-  @return  The child handle with opened EFI_TLS_PROTOCOL and 
EFI_TLS_CONFIGURATION_PROTOCOL.
+  @return  EFI_SUCCESSTLS child handle is returned in 
HttpInstance->TlsChildHandle
+  with opened EFI_TLS_PROTOCOL and 
EFI_TLS_CONFIGURATION_PROTOCOL.


As above.

Reviewed-by: Michael Brown 

Michael



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[edk2-devel] [PATCH 7/8] Platform/Sgi: Low Power Idle States for RD-Fremont

[Prabin CA]

RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf |   1 +
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl  | 154 

 2 files changed, 155 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
index 9d07001dec96..7556c1239116 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
@@ -48,6 +48,7 @@ [FixedPcd]
   gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
   gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
   gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+  gArmSgiTokenSpaceGuid.PcdOscLpiEnable
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
index 8812ea877f7a..f921eeb2d99e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
@@ -8,6 +8,9 @@
 * @par Specification Reference:
 *   - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Description
 * Table (DSDT)
+*   - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States
+*   - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.1,
+* Idle management and Low Power Idle states
 *
 **/
 
@@ -17,6 +20,93 @@
 DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
  EFI_ACPI_ARM_OEM_REVISION) {
   Scope (_SB) {
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+  CreateDWordField (Arg3, 0x00, STS0)
+  CreateDWordField (Arg3, 0x04, CAP0)
+
+  /* Platform-wide Capabilities */
+  If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+
+  If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+
+  If (And (CAP0, OSC_CAP_PLAT_COORDINATED_LPI)) {
+if (LEqual (FixedPcdGet32 (PcdOscLpiEnable), Zero)) {
+  And (CAP0, Not (OSC_CAP_PLAT_COORDINATED_LPI), CAP0)
+  Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+}
+  }
+} Else {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+  Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+}
+  } Else {
+And (STS0, Not (OSC_STS_MASK), STS0)
+Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+  }
+
+  Return (Arg3)
+}
+
+Name (PLPI, Package () {  /* LPI for Processor, support 2 LPI states */
+  0,  // Version
+  0,  // Level Index
+  2,  // Count
+  Package () {// WFI for CPU
+1,// Min residency (uS)
+1,// Wake latency (uS)
+1,// Flags
+0,// Arch Context lost Flags (no loss)
+0,// Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x,   // Address
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI1-Core"
+  },
+  Package () {// Power Gating state for CPU
+150,  // Min residency (uS)
+350,  // Wake latency (uS)
+1,// Flags
+1,// Arch Context lost Flags (Core context lost)
+0,// Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x4002,   // Address (PwrLvl:core, StateTyp:PwrDn)
+3,// Access Size
+  )
+},
+

[edk2-devel] [PATCH 8/8] Platform/Sgi: Add CPPC support for RD-Fremont platform

[Prabin CA]

Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with LCP to set
the desired performance. RD-Fremont platform does not support CPPC
revision 1 and below. So update the _OSC method to let OSPM know about
this fact.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf |   1 +
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl  | 162 

 2 files changed, 163 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
index 7556c1239116..fcaa3299c4ea 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
@@ -48,6 +48,7 @@ [FixedPcd]
   gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
   gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
   gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+  gArmSgiTokenSpaceGuid.PcdOscCppcEnable
   gArmSgiTokenSpaceGuid.PcdOscLpiEnable
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
index f921eeb2d99e..0d3ba3debd53 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
@@ -11,6 +11,10 @@
 *   - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States
 *   - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.1,
 * Idle management and Low Power Idle states
+*   - ACPI 6.5, Chapter 8, Section 8.4.6, Collaborative Processor Performance
+* Control
+*   - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.2,
+* Performance management and Collaborative Processor Performance Control
 *
 **/
 
@@ -43,6 +47,20 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
   Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
 }
   }
+
+  If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+/* CPPC revision 1 and below not supported */
+And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+
+  If (And (CAP0, OSC_CAP_CPPC2_SUPPORT)) {
+if (LEqual (FixedPcdGet32 (PcdOscCppcEnable), Zero)) {
+  And (CAP0, Not (OSC_CAP_CPPC2_SUPPORT), CAP0)
+  Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+}
+  }
+
 } Else {
   And (STS0, Not (OSC_STS_MASK), STS0)
   Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -116,6 +134,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 0)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200093000, 0x200093004, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (0)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -131,6 +158,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 1)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200293000, 0x200293004, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (1)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -146,6 +182,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 2)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200493000, 0x200493004, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (2)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -161,6 +206,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 3)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200693000, 0x200063004, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (3)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -176,6 +230,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 4)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200893000, 0x200893004, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (4)
+})
+
 Method (_LPI, 0, 

[edk2-devel] [PATCH 6/8] Platform/Sgi: Extend SMBIOS support for RD-Fremont

[Prabin CA]

Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/Include/SgiPlatform.h | 5 
+
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c| 5 
-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 5 
-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 1 +
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 6 
++
 5 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h 
b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index 6fa39d407bc9..acfa45910aed 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -51,6 +51,10 @@
 #define RD_V2_PART_NUM0x7F2
 #define RD_V2_CONF_ID 0x1
 
+// RD-Fremont Platform Identification values
+#define RD_Fremont_PART_NUM   0x7EE
+#define RD_Fremont_CONF_ID0x1
+
 #define SGI_CONFIG_MASK   0x0F
 #define SGI_CONFIG_SHIFT  0x1C
 #define SGI_PART_NUM_MASK 0xFFF
@@ -90,6 +94,7 @@ typedef enum {
   RdN2Cfg1,
   RdN2Cfg2,
   RdV2,
+  RdFremont,
 } ARM_RD_PRODUCT_ID;
 
 // Arm ProductId look-up table
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index edf2a5f63c63..9c28b051ebc2 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -34,7 +34,8 @@
   "RdN2\0"  \
   "RdN2Cfg1\0"  \
   "RdN2Cfg2\0"  \
-  "RdV2\0"
+  "RdV2\0"  \
+  "RdFremont\0"
 
 typedef enum {
   ManufacturerName = 1,
@@ -74,6 +75,8 @@ STATIC GUID mSmbiosUid[] = {
   {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, 
0x60}},
   /* Rd-V2 */
   {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43, 
0x45}},
+  /* Rd-Fremont*/
+  {0x904b28d6, 0x0662, 0x11ed, {0xb9, 0x39, 0x02, 0x42, 0xac, 0x12, 0x00, 
0x02}},
 };
 
 /* System information */
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index ee269f707714..c39c1553f6aa 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -44,6 +44,7 @@
   "Neoverse-N2\0"   \
   "Neoverse-N2\0"   \
   "Neoverse-V2\0"   \
+  "Neoverse-Poseidon\0" \
   "000-0\0" /* Serial number */ \
   "783-3\0" \
   "786-1\0" \
@@ -54,7 +55,8 @@
   "7B7-1\0" \
   "7B6-1\0" \
   "7B7-1\0" \
-  "7F2-1\0"
+  "7F2-1\0" \
+  "7EE-1\0"
 
 typedef enum {
   PartNumber = 1,
@@ -181,6 +183,7 @@ InstallType4ProcessorInformation (
   case RdN2:
   case RdN2Cfg1:
   case RdV2:
+  case RdFremont:
 mArmRdSmbiosType4.Base.CoreCount = CoreCount;
 mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
 mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index 4af72919a3f1..4cdea5b3b763 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -335,6 +335,7 @@ InstallType7CacheInformation (
 mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
 break;
   case RdV2:
+  case RdFremont:
 /* L1 instruction cache */
 mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64;// 64KB
 mArmRdSmbiosType7[0].Base.InstalledSize2 = 64;   // 64KB
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c 
b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index 14b06796ae9c..ae31be142d12 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++ 

[edk2-devel] [PATCH 5/8] Platform/Sgi: Add initial support for RD-Fremont platform

[Prabin CA]

The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM.
Add initial support for this platform by adding the required platform
build configuration files. This platform has considerable differences in
its memory map compared to its predecessors. So add a corresponding
memory map file as well to define the PCDs for its generation of
platforms.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc   | 71 
 Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc | 55 +++
 Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc | 10 +++
 3 files changed, 136 insertions(+)

diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc 
b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc
new file mode 100644
index ..06c3b37388c1
--- /dev/null
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc
@@ -0,0 +1,71 @@
+#
+#  Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[PcdsFixedAtBuild.common]
+  # System Peripherals
+  gArmSgiTokenSpaceGuid.PcdSmcCs0Base|0x0800
+  gArmSgiTokenSpaceGuid.PcdSmcCs1Base|0x06
+  gArmSgiTokenSpaceGuid.PcdSysPeriphBase|0x0C00
+  gArmSgiTokenSpaceGuid.PcdSysPeriphSysRegBase|0x0C01
+
+  # SP804 dual timer
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0x0C11
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0x0001
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|216
+
+  # Virtio Disk
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x0C13
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkSize|0x1
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt|184
+
+  # GPIO controller
+  gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D
+  gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x0001
+  gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|168
+
+   # Ethernet
+  gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress|0x0C15
+  gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|186
+
+  # PL031 RealTimeClock
+  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0C17
+
+  # Virtio P9
+  gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress|0x0C19
+  gArmSgiTokenSpaceGuid.PcdVirtioP9Size|0x1
+  gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt|185
+
+  # PL370 - HDLCD1
+  gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0EF6
+
+  # PL011 - Serial Debug UART
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0EF7
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt|179
+
+  # PL011 - Serial Terminal
+  gArmPlatformTokenSpaceGuid.PL011UartInterrupt|112
+
+  # System Memory (2GB - 128MB of Trusted DRAM at the top of the 32bit address 
space)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7800
+
+  # SMMU
+  gArmSgiTokenSpaceGuid.PcdSmmuBase|0x28000
+  gArmSgiTokenSpaceGuid.PcdSmmuSize|0x400
+
+  # Non-Volatile variable storage
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x06
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x060140
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x060280
+
+  # Address bus width - 64TB address space
+  gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|46
+
+  # Timer & Watchdog interrupts
+  gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv|109
+  gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv|108
+  gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv|110
+  gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|111
diff --git a/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc 
b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc
new file mode 100644
index ..b52d2f59e15d
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc
@@ -0,0 +1,55 @@
+#
+#  Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  PLATFORM_NAME  = RdFremont
+  PLATFORM_GUID  = fd140b0f-4467-4314-aa69-cd0bd712e08e
+  PLATFORM_VERSION   = 0.1
+  DSC_SPECIFICATION  = 0x0001001B
+  OUTPUT_DIRECTORY   = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES= AARCH64
+  BUILD_TARGETS  = NOOPT|DEBUG|RELEASE
+  SKUID_IDENTIFIER   = DEFAULT
+  FLASH_DEFINITION   = Platform/ARM/SgiPkg/SgiPlatform.fdf
+  BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc
+  BUILD_NUMBER   = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc
+
+# include common/basic libraries from MdePkg.
+!include MdePkg/MdeLibs.dsc.inc
+
+
+#
+# Pcd Section - list of 

[edk2-devel] [PATCH 3/8] Platform/Sgi: Introduce a flag to enable PCIe support for RD Platforms

[Prabin CA]

Introducing a flag called PCIE_ENABLE, which can be set to TRUE or
FALSE from the respective .dsc files to enable or disable the
PCIe support. As not all reference design platforms have PCIe support
enabled, this flag is introduced.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiPlatform.dec  |  1 +
 Platform/ARM/SgiPkg/SgiPlatform.dsc.inc  |  6 ++
 Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc|  4 +++-
 Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc|  4 +++-
 Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc|  4 +++-
 Platform/ARM/SgiPkg/RdV1/RdV1.dsc|  4 +++-
 Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc|  4 +++-
 Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc|  4 +++-
 Platform/ARM/SgiPkg/SgiPlatform.fdf  |  4 +++-
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf  |  5 -
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 19 
+++
 11 files changed, 43 insertions(+), 16 deletions(-)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec 
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 4087ff6cad2e..af7887e54126 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -31,6 +31,7 @@ [Guids.common]
 [PcdsFeatureFlag.common]
   gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x0001
   gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|FALSE|BOOLEAN|0x0010
+  gArmSgiTokenSpaceGuid.PcdPcieEnable|FALSE|BOOLEAN|0x002E
 
 [PcdsFixedAtBuild]
   gArmSgiTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x0002
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc 
b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
index 1cfe07c7e4ed..1bf489ffeb39 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -103,6 +103,10 @@ [PcdsFeatureFlag.common]
   gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache|FALSE
 
+!if $(PCIE_ENABLE) == TRUE
+  gArmSgiTokenSpaceGuid.PcdPcieEnable|TRUE
+!endif
+
 [PcdsFixedAtBuild.common]
   gArmTokenSpaceGuid.PcdVFPEnabled|1
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
@@ -330,6 +334,7 @@ [Components.common]
   # Virtio Network
   OvmfPkg/VirtioNetDxe/VirtioNet.inf
 
+!if $(PCIE_ENABLE) == TRUE
   #
   # Required by PCI
   #
@@ -343,6 +348,7 @@ [Components.common]
 
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
   }
+!endif
 
   #
   # AHCI Support
diff --git a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc 
b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc
index 32d67d380814..c7463da5203e 100644
--- a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc
+++ b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020-2022, ARM Limited. All rights reserved.
+#  Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -22,6 +22,8 @@ [Defines]
   BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.fdf.inc
   BUILD_NUMBER   = 1
 
+  DEFINE PCIE_ENABLE = TRUE
+
 # include common definitions from SgiPlatform.dsc
 !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
 !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
diff --git a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc 
b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc
index 6c9a64df054f..77efec9d9533 100644
--- a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc
+++ b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020-2022, ARM Limited. All rights reserved.
+#  Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -22,6 +22,8 @@ [Defines]
   BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.fdf.inc
   BUILD_NUMBER   = 1
 
+  DEFINE PCIE_ENABLE = TRUE
+
 # include common definitions from SgiPlatform.dsc
 !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
 !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
diff --git a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc 
b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
index 10e5bfa29b46..521d88925059 100644
--- a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
+++ b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020-2022, ARM Limited. All rights reserved.
+#  Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -22,6 +22,8 @@ [Defines]
   BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.fdf.inc
   BUILD_NUMBER   = 1
 
+  DEFINE PCIE_ENABLE = TRUE
+
 # include common definitions from SgiPlatform.dsc
 !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
 !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
diff --git a/Platform/ARM/SgiPkg/RdV1/RdV1.dsc 

[edk2-devel] [PATCH 4/8] Platform/Sgi: Add ACPI tables for RD-Fremont platform

[Prabin CA]

From: Shriram K 

RD-Fremont is the next platform in the Arm's reference design platform
series. This platform includes 32 CPUs but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. In preparation for
adding support for this platform, add the initial set of ACPI tables and
reuse existing ACPI tables as applicable to boot a operating system on
this platform.

Signed-off-by: Shriram K 
Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf |  73 
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl  | 196 

 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc | 138 ++
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc | 167 +
 4 files changed, 574 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
new file mode 100644
index ..9d07001dec96
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
@@ -0,0 +1,73 @@
+## @file
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2024, Arm Ltd. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = RdFremontAcpiTables
+  FILE_GUID  = c712719a-0aaf-438c-9cdd-35ab4d60207d  # 
gArmSgiAcpiTablesGuid
+  MODULE_TYPE= USER_DEFINED
+  VERSION_STRING = 1.0
+
+[Sources]
+  Dbg2.aslc
+  Fadt.aslc
+  Gtdt.aslc
+  RdFremont/Dsdt.asl
+  RdFremont/Madt.aslc
+  RdFremont/Pptt.aslc
+  Spcr.aslc
+  SsdtEvents.asl
+  SsdtRos.asl
+  SsdtRosVirtioP9.asl
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+  gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmPlatformTokenSpaceGuid.PcdClusterCount
+
+  gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress
+  gArmSgiTokenSpaceGuid.PcdGpioController0Size
+  gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
+  gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
+  gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+  gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+  gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+  gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+  gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress
+  gArmSgiTokenSpaceGuid.PcdVirtioP9Size
+  gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt
+  gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
+  gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
+
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
new file mode 100644
index ..8812ea877f7a
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
@@ -0,0 +1,196 @@
+/** @file
+*  Differentiated System Description Table Fields (DSDT)
+*
+*  Copyright (c) 2024, Arm Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+*   - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Description
+* Table (DSDT)
+*
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+  Scope (_SB) {
+Device (CL00) {   // Cluster 0
+  Name (_HID, "ACPI0010")
+  Name (_UID, 0)
+
+  Device (CP00) { // Neoverse Poseidon core 0
+Name (_HID, "ACPI0007")
+Name (_UID, 0)
+Name (_STA, 0xF)
+  }
+}
+
+Device (CL01) {   // Cluster 1
+  Name (_HID, "ACPI0010")
+  Name (_UID, 1)
+
+  Device (CP01) { // Neoverse Poseidon core 1
+Name (_HID, "ACPI0007")
+Name (_UID, 1)
+Name (_STA, 0xF)
+  }
+}
+
+Device (CL02) {   // Cluster 2
+  Name (_HID, "ACPI0010")
+  Name (_UID, 2)
+
+  Device (CP02) { // Neoverse 

[edk2-devel] [PATCH 2/8] Platform/Sgi: Refactor system memory base and size definitions

[Prabin CA]

In preparation of adding the next generation of reference design
platform that have different memory map, refactor the
PcdSystemMemoryBase and PcdSystemMemorySize PCD definitions from the
common PCD definitions file into the various platform generation
specific memory map PCD definitions file.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc  | 8 +++-
 Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 8 +++-
 Platform/ARM/SgiPkg/SgiPlatform.dsc.inc   | 6 +-
 3 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc 
b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
index 0c577c42..eab43b23ec6d 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+#  Copyright (c) 2020 - 2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -67,3 +67,9 @@ [PcdsFixedAtBuild.common]
   gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x1C1D
   gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x0001
   gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|136
+
+  # System Memory (1GB - 16MB of Trusted DRAM at the top of the
+  # 32bit address space)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F00
+
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc 
b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
index de1d8ea24b89..35e27d42d5a2 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020 - 2023, Arm Limited. All rights reserved.
+#  Copyright (c) 2020 - 2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -75,3 +75,9 @@ [PcdsFixedAtBuild.common]
 
   # IO virtualization block
   gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base|0x108000
+
+  # System Memory (1GB - 16MB of Trusted DRAM at the top of the
+  # 32bit address space)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F00
+
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc 
b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
index 26ecd9ed59a7..1cfe07c7e4ed 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
+#  Copyright (c) 2018 - 2024, Arm Limited. All rights reserved.
 #  (C) Copyright 2021 Hewlett Packard Enterprise Development LP
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -131,10 +131,6 @@ [PcdsFixedAtBuild.common]
   gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4
   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0
 
-  # System Memory (1GB - 16MB of Trusted DRAM at the top of the 32bit address 
space)
-  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
-  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F00
-
   # ACPI Table Version
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
 
-- 
2.34.1



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[edk2-devel] [PATCH 1/8] Platform/Sgi: Update the datatype of PcdSmmuBase from u32 to u64

[Prabin CA]

From: Vivek Gautam 

On RD-N2 and previous generation platforms, the base address was within
32-bit region. However, on upcoming platforms, the SMMUv3 base address
is beyond 32-bit address region. So, update the datatype of SMMUv3 base
PCD.

Signed-off-by: Vivek Gautam 
Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiPlatform.dec  | 2 +-
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec 
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 103dff8471a7..4087ff6cad2e 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -79,7 +79,7 @@ [PcdsFixedAtBuild]
   gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|0|UINT32|0x0014
 
   # SMMU
-  gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT32|0x001D
+  gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT64|0x001D
   gArmSgiTokenSpaceGuid.PcdSmmuSize|0|UINT32|0x001E
 
   # GPIO Controller
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c 
b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
index fa3cfbc730f6..62c212f3c5b0 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2018-2023, ARM Limited. All rights reserved.
+*  Copyright (c) 2018-2024, Arm Limited. All rights reserved.
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -167,8 +167,8 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Attributes  = 
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
   // Sub System Peripherals - SMMU
-  VirtualMemoryTable[++Index].PhysicalBase  = FixedPcdGet32 (PcdSmmuBase);
-  VirtualMemoryTable[Index].VirtualBase = FixedPcdGet32 (PcdSmmuBase);
+  VirtualMemoryTable[++Index].PhysicalBase  = FixedPcdGet64 (PcdSmmuBase);
+  VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSmmuBase);
   VirtualMemoryTable[Index].Length  = FixedPcdGet32 (PcdSmmuSize);
   VirtualMemoryTable[Index].Attributes  = 
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
-- 
2.34.1



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[edk2-devel] [PATCH 0/8] Platform/Sgi: Add support for RD-Fremont platform

[Prabin CA]

This patch series introduce support for RD-Fremont reference design
platform. This platform includes 32 CPUs, but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. Each of the CPUs
include 64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.
Also, this patch series adding the extended SMBIO support for RD-Fremont
platform.

In addition to patches that introduce RD-Fremont platform, there are
three patches that update support for existing platforms. The first
patch in this series changes the data type of PcdSmmuBase from u32 to
u64. The second patch refactor the system memory map base and size
values. The third patch add a flag to enable PCIE support for existing
and future platforms.

Link to github branch with the patches in this series -
https://gitlab.arm.com/infra-solutions/reference-design/platsw/edk2-platforms/-/commits/topics/rdfremont/

Prabin CA (6):
  Platform/Sgi: Refactor system memory base and size definitions
  Platform/Sgi: Introduce a flag to enable PCIe support for RD Platforms
  Platform/Sgi: Add initial support for RD-Fremont platform
  Platform/Sgi: Extend SMBIOS support for RD-Fremont
  Platform/Sgi: Low Power Idle States for RD-Fremont
  Platform/Sgi: Add CPPC support for RD-Fremont platform

Shriram K (1):
  Platform/Sgi: Add ACPI tables for RD-Fremont platform

Vivek Gautam (1):
  Platform/Sgi: Update the datatype of PcdSmmuBase from u32 to u64

 Platform/ARM/SgiPkg/SgiPlatform.dec   |   3 +-
 Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc  |   7 +-
 Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc |   7 +-
 ...moryMap2.dsc.inc => SgiMemoryMap3.dsc.inc} |  88 ++-
 Platform/ARM/SgiPkg/SgiPlatform.dsc.inc   |  12 +-
 Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc |   4 +-
 .../RdN2.dsc => RdFremont/RdFremont.dsc}  |  14 +-
 Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc |   4 +-
 Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc |   4 +-
 Platform/ARM/SgiPkg/RdN2/RdN2.dsc |   4 +-
 Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc |   4 +-
 Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.dsc |   4 +-
 Platform/ARM/SgiPkg/RdV1/RdV1.dsc |   4 +-
 Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc |   4 +-
 Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc |   4 +-
 Platform/ARM/SgiPkg/SgiPlatform.fdf   |   4 +-
 .../SgiPkg/AcpiTables/RdFremontAcpiTables.inf |  75 +++
 .../Library/PlatformLib/PlatformLib.inf   |   5 +-
 Platform/ARM/SgiPkg/Include/SgiPlatform.h |   5 +
 .../Type1SystemInformation.c  |   5 +-
 .../Type4ProcessorInformation.c   |   5 +-
 .../SmbiosPlatformDxe/Type7CacheInformation.c |   1 +
 .../SgiPkg/Library/PlatformLib/PlatformLib.c  |   6 +
 .../Library/PlatformLib/PlatformLibMem.c  |  25 +-
 .../ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl  | 512 ++
 .../ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc | 138 +
 .../ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc | 167 ++
 .../ARM/SgiPkg/RdFremont/RdFremont.fdf.inc|  10 +
 28 files changed, 1040 insertions(+), 85 deletions(-)
 copy Platform/ARM/SgiPkg/{SgiMemoryMap2.dsc.inc => SgiMemoryMap3.dsc.inc} (62%)
 copy Platform/ARM/SgiPkg/{RdN2/RdN2.dsc => RdFremont/RdFremont.dsc} (78%)
 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc
 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc
 create mode 100644 Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc

-- 
2.34.1



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Re: [edk2-devel] [PATCH v1 1/1] StandaloneMmPkg: Initialise serial port early in StandaloneMmEntryPoint

[Ard Biesheuvel]

On Fri, 5 Jan 2024 at 12:49, levi.yun  wrote:
>
> Serial port used by the DEBUG macro is initialised in StandaloneMmMain
> by the DebugLib constructor.
>
> When we use a serial port initialised by TF-A it is not a problem.
> However, if we use a serial port that is not initialised by TF-A,
> the debug log prints hangs.
>
> Therefore, initialise the serial port early on in the entry point.
>
> Signed-off-by: levi.yun 
> ---
> These changes can be seen at
> https://github.com/LeviYeoReum/edk2/tree/levi/2956_init_serial too.
>

So now we will always initialize the serial port in the entrypoint
only because DebugLib might use it later with doing the
initialization.

That doesn't sound quite correct to me.

Could you explain why we cannot rely on DebugLib to call the
initializer / constructor at the right time?



>  StandaloneMmPkg/StandaloneMmPkg.dsc  
>| 1 +
>  
> StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
>| 1 +
>  
> StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
>  | 3 +++
>  3 files changed, 5 insertions(+)
>
> diff --git a/StandaloneMmPkg/StandaloneMmPkg.dsc 
> b/StandaloneMmPkg/StandaloneMmPkg.dsc
> index 
> 8012f93b7dcc38ea8fdd2de98912bbc09157ec53..040a4aa5b3d268fdfaaec9a975cfc6ff31aa37b4
>  100644
> --- a/StandaloneMmPkg/StandaloneMmPkg.dsc
> +++ b/StandaloneMmPkg/StandaloneMmPkg.dsc
> @@ -66,6 +66,7 @@ [LibraryClasses.AARCH64, LibraryClasses.ARM]
>ArmSvcLib|ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
>
> CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
>
> PeCoffExtraActionLib|StandaloneMmPkg/Library/StandaloneMmPeCoffExtraActionLib/StandaloneMmPeCoffExtraActionLib.inf
> +  
> SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
>
>NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
>NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
> diff --git 
> a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
>  
> b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
> index 
> 75cfb98c0e75cd7cee2a59723035679612da4528..086639ecfbc983627aed73817815e2485104375e
>  100644
> --- 
> a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
> +++ 
> b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
> @@ -42,6 +42,7 @@ [LibraryClasses]
>DebugLib
>
>  [LibraryClasses.ARM, LibraryClasses.AARCH64]
> +  SerialPortLib
>StandaloneMmMmuLib
>ArmSvcLib
>
> diff --git 
> a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
>  
> b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
> index 
> 96de10405af829c66e3f43ed4692f785d8df113e..66b56bdfe4959d5ab6152ff024caa6e900e7a948
>  100644
> --- 
> a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
> +++ 
> b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
> @@ -335,6 +335,9 @@ _ModuleEntryPoint (
>UINTN   TeDataSize;
>EFI_PHYSICAL_ADDRESSImageBase;
>
> +  // Initialize the Serial Port early to print debug log before 
> StandaloneMmMain.
> +  SerialPortInitialize ();
> +
>// Get Secure Partition Manager Version Information
>Status = GetSpmVersion ();
>if (EFI_ERROR (Status)) {
> --
> Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")
>
> IMPORTANT NOTICE: The contents of this email and any attachments are 
> confidential and may also be privileged. If you are not the intended 
> recipient, please notify the sender immediately and do not disclose the 
> contents to any other person, use it for any purpose, or store or copy the 
> information in any medium. Thank you.
>
>
> 
>
>


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Re: [edk2-devel] [PATCH v3 0/3] ArmPkg: GenericWatchdogDxe fixes and improvements

[Rebecca Cran via groups.io]

On 1/5/2024 1:26 AM, Ard Biesheuvel via groups.io wrote:

On Fri, 5 Jan 2024 at 06:15, Rebecca Cran
 wrote:


Fixes and improvements to GenericWatchdogDxe.



What is the difference between v2 and v3?


Sorry, I should have said that. I forgot to build v2 and it had a bug in 
the exit boot services handler where I'd forgotten to update a line.


--
Rebecca Cran


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Re: [edk2-devel] [PATCH v2] MdePkg/BaseLib:Fix boot DxeCore hang on riscv platform

[Andrei Warkentin]

Looks reasonable to me.

Reviewed-by: Andrei Warkentin 

> -Original Message-
> From: Yang Wang 
> Sent: Wednesday, December 27, 2023 8:57 PM
> To: Warkentin, Andrei ; devel@edk2.groups.io
> Cc: Yang Wang ; Ran Wang ;
> Bamvor Jian ZHANG ; Gao, Liming
> ; Kinney, Michael D
> ; Sunil V L ; Liu,
> Zhiguang 
> Subject: [PATCH v2] MdePkg/BaseLib:Fix boot DxeCore hang on riscv platform
> 
> For scene of
> HandOffToDxeCore()->SwitchStack(DxeCoreEntryPoint)->
> InternalSwitchStack()->LongJump(),Variable HobList.Raw
> will be passed (from *Context1 to register a0) to
> DxeMain() in parameter *HobStart.
> 
> However, meanwhile the function LongJump() overrides
> register a0 with a1 (-1)  due to commit (ea628f28e5 "RISCV: Fix
> InternalLongJump to return correct value"), then cause hang.
> 
> Replacing calling LongJump() with new InternalSwitchStackAsm() to pass
> addres data in register s0 to register a0 could fix this issue (just
> like the solution in MdePkg/Library/BaseLib/AArch64/SwitchStack.S)
> 
> Signed-off-by: Yang Wang 
> Reviewed-by: Ran Wang 
> Cc: Bamvor Jian ZHANG 
> Cc: Andrei Warkentin 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Sunil V L 
> Cc: Zhiguang Liu 
> ---
> Change in v2:
> - Remove JumpBuffer variable parameter
> - Take these in the order of Context1, Context2, EntryPoint, NewStack
> - Fix BaseLib.inf, add Compilation SwitchStack.S
> - Drop REG_S/REG_L
> 
>  MdePkg/Library/BaseLib/BaseLib.inf|  1 +
>  .../BaseLib/RiscV64/InternalSwitchStack.c | 31 
>  MdePkg/Library/BaseLib/RiscV64/SwitchStack.S  | 37
> +++
>  3 files changed, 62 insertions(+), 7 deletions(-)
>  create mode 100644 MdePkg/Library/BaseLib/RiscV64/SwitchStack.S
> 
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> b/MdePkg/Library/BaseLib/BaseLib.inf
> index 5338938944..6b46949be3 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -397,6 +397,7 @@
>RiscV64/CpuPause.c
> 
>RiscV64/MemoryFence.S | GCC
> 
>RiscV64/RiscVSetJumpLongJump.S| GCC
> 
> +  RiscV64/SwitchStack.S | GCC
> 
>RiscV64/RiscVCpuBreakpoint.S  | GCC
> 
>RiscV64/RiscVCpuPause.S   | GCC
> 
>RiscV64/RiscVInterrupt.S  | GCC
> 
> diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> index b78424c163..3216d241ad 100644
> --- a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> +++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> @@ -8,6 +8,29 @@
> 
> 
>  #include "BaseLibInternals.h"
> 
> 
> 
> +/**
> 
> +  Transfers control to a function starting with a new stack.
> 
> +
> 
> +  This internal worker function transfers control to the function
> 
> +  specified by EntryPoint using the new stack specified by NewStack,
> 
> +  and passes in the parameters specified by Context1 and Context2.
> 
> +  Context1 and Context2 are optional and may be NULL.
> 
> +  The function EntryPoint must never return.
> 
> +
> 
> +  @param Context1 The first parameter to pass in.
> 
> +  @param Context2 The second Parameter to pass in
> 
> +  @param EntryPoint   The pointer to the function to enter.
> 
> +  @param NewStack The new Location of the stack
> 
> +
> 
> +**/
> 
> +VOID
> 
> +EFIAPI
> 
> +InternalSwitchStackAsm (
> 
> +  IN  VOID  *Context1OPTIONAL,
> 
> +  IN  VOID  *Context2OPTIONAL,
> 
> +  IN  SWITCH_STACK_ENTRY_POINT  EntryPoint,
> 
> +  IN  VOID  *NewStack
> 
> +  );
> 
>  /**
> 
>Transfers control to a function starting with a new stack.
> 
> 
> 
> @@ -42,12 +65,6 @@ InternalSwitchStack (
>IN  VA_LIST   Marker
> 
>)
> 
>  {
> 
> -  BASE_LIBRARY_JUMP_BUFFER  JumpBuffer;
> 
> -
> 
> -  JumpBuffer.RA = (UINTN)EntryPoint;
> 
> -  JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);
> 
> -  JumpBuffer.S0 = (UINT64)(UINTN)Context1;
> 
> -  JumpBuffer.S1 = (UINT64)(UINTN)Context2;
> 
> -  LongJump (, (UINTN)-1);
> 
> +  InternalSwitchStackAsm (Context1, Context2, EntryPoint, (VOID
> *)((UINTN)NewStack - sizeof (VOID *)));
> 
>ASSERT (FALSE);
> 
>  }
> 
> diff --git a/MdePkg/Library/BaseLib/RiscV64/SwitchStack.S
> b/MdePkg/Library/BaseLib/RiscV64/SwitchStack.S
> new file mode 100644
> index 00..db535c1aab
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/SwitchStack.S
> @@ -0,0 +1,37 @@
> +//--
> 
> +//
> 
> +// InternalSwitchStackAsm for RISC-V
> 
> +//
> 
> +// Copyright (c) 2023, Bosc Corporation. All rights reserved.
> 
> +//
> 
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +//
> 
> +//--
> 
> +.align 3
> 
> +
> 
> +#/**
> 
> +#
> 
> +# This allows the caller to switch the stack and goes 

[edk2-devel] [edk2-platforms][PATCH v2 7/7] Platform/Sgi: Extend SMBIOS support for RD-V2 platform

[Prabin CA]

From: Pranav Madhu 

The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB
of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level
cache. Extend the SMBIOS support for RD-V2 platform with this
configuration and reuse rest of the RD-N2 SMBIOS configuration for the
RD-V2 platform.

Signed-off-by: Pranav Madhu 
Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c|  7 
+--
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c |  9 
++---
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 20 
+++-
 3 files changed, 30 insertions(+), 6 deletions(-)

diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index b7e2238fb39c..edf2a5f63c63 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -5,7 +5,7 @@
   Reference Design platforms. Type 1 table defines attributes of the
   overall system such as manufacturer, product name, UUID etc.
 
-  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+  Copyright (c) 2021 - 2024, Arm Limited. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Specification Reference:
@@ -33,7 +33,8 @@
   "RdV1Mc\0"\
   "RdN2\0"  \
   "RdN2Cfg1\0"  \
-  "RdN2Cfg2\0"
+  "RdN2Cfg2\0"  \
+  "RdV2\0"
 
 typedef enum {
   ManufacturerName = 1,
@@ -71,6 +72,8 @@ STATIC GUID mSmbiosUid[] = {
   {0xa4941d3d, 0xfac3, 0x4ace, {0x9a, 0x7e, 0xce, 0x26, 0x76, 0x64, 0x5e, 
0xda}},
   /* Rd-N2-Cfg2*/
   {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, 
0x60}},
+  /* Rd-V2 */
+  {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43, 
0x45}},
 };
 
 /* System information */
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index b59172cf1cb9..ee269f707714 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -6,7 +6,7 @@
   family, processor id, maximum operating frequency, and other information
   related to the processor.
 
-  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+  Copyright (c) 2021 - 2024, Arm Limited. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Specification Reference:
@@ -27,7 +27,7 @@
 #define SOCKET_TYPE_BASE3
 #define SOCKET_TYPE_NUM 1
 #define PROCESSOR_VERSION_BASE  (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM)
-#define PROCESSOR_VERSION_NUM   10
+#define PROCESSOR_VERSION_NUM   11
 #define SERIAL_NUMBER_BASE  (PROCESSOR_VERSION_BASE + 
PROCESSOR_VERSION_NUM)
 #define TYPE4_STRINGS   \
   "0x000\0" /* Part Number */   \
@@ -43,6 +43,7 @@
   "Neoverse-N2\0"   \
   "Neoverse-N2\0"   \
   "Neoverse-N2\0"   \
+  "Neoverse-V2\0"   \
   "000-0\0" /* Serial number */ \
   "783-3\0" \
   "786-1\0" \
@@ -52,7 +53,8 @@
   "78A-2\0" \
   "7B7-1\0" \
   "7B6-1\0" \
-  "7B7-1\0"
+  "7B7-1\0" \
+  "7F2-1\0"
 
 typedef enum {
   PartNumber = 1,
@@ -178,6 +180,7 @@ InstallType4ProcessorInformation (
 break;
   case RdN2:
   case RdN2Cfg1:
+  case RdV2:
 mArmRdSmbiosType4.Base.CoreCount = CoreCount;
 mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
 mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index b71ce721e2e8..4af72919a3f1 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -6,7 +6,7 @@
   implemented, cache configuration, ways of associativity and other
   information related to cache memory installed.
 
-  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+  Copyright (c) 2021 - 2024, Arm Limited. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Specification Reference:
@@ -334,6 +334,24 @@ 

[edk2-devel] [edk2-platforms][PATCH v2 6/7] Platform/Sgi: Define RD-V2 platform id values

[Prabin CA]

From: Pranav Madhu 

Add RD-V2 platform identification values including the part number
and configuration number. This information will be used in populating
the SMBIOS tables.

Signed-off-by: Pranav Madhu 
Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 ++-
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 8 +++-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h 
b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index e83853664c4c..6fa39d407bc9 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+*  Copyright (c) 2018 - 2024, Arm Limited. All rights reserved.
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -47,6 +47,10 @@
 #define RD_N2_PART_NUM0x7B7
 #define RD_N2_CONF_ID 0x1
 
+// RD-V2 Platform Identification values
+#define RD_V2_PART_NUM0x7F2
+#define RD_V2_CONF_ID 0x1
+
 #define SGI_CONFIG_MASK   0x0F
 #define SGI_CONFIG_SHIFT  0x1C
 #define SGI_PART_NUM_MASK 0xFFF
@@ -85,6 +89,7 @@ typedef enum {
   RdN2,
   RdN2Cfg1,
   RdN2Cfg2,
+  RdV2,
 } ARM_RD_PRODUCT_ID;
 
 // Arm ProductId look-up table
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c 
b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index fa006320025b..14b06796ae9c 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+*  Copyright (c) 2018 - 2024, Arm Limited. All rights reserved.
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -79,6 +79,12 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = {
 RD_N2_CONF_ID,
 1
   },
+  {
+RdV2,
+RD_V2_PART_NUM,
+RD_V2_CONF_ID,
+0
+  },
 };
 
 EFI_BOOT_MODE
-- 
2.34.1



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[edk2-devel] [edk2-platforms][PATCH v2 5/7] Platform/Sgi: Add support for RD-N2-Cfg3 platform

[Prabin CA]

The Neoverse RD-N2-Cfg3 platform is a variant of RD-N2 platform with a
different mesh size and GIC ITS count. As part of the initial platform
support, add the corresponding platform and flash description files.
Use PcdPlatformVariant for the RD-N2-Cfg3 platform to specify the
platform variant. RD-N2-Cfg3 has 12 GIC ITS blocks when compared to the
other RD-N2 variants that have 6 GIC ITS blocks.

Signed-off-by: Vijayenthiran Subramaniam 
Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.dsc 
| 58 
 Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf 
|  3 +-
 Platform/ARM/SgiPkg/AcpiTables/{RdN2AcpiTables.inf => RdN2Cfg3AcpiTables.inf} 
| 15 ++---
 Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc 
| 14 -
 Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.fdf.inc 
| 10 
 5 files changed, 88 insertions(+), 12 deletions(-)

diff --git a/Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.dsc 
b/Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.dsc
new file mode 100644
index ..88293b236a32
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.dsc
@@ -0,0 +1,58 @@
+#
+#  Copyright (c) 2024, ARM Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  PLATFORM_NAME  = RdN2Cfg3
+  PLATFORM_GUID  = b890ba7d-a256-4820-9d3a-655acbb737c9
+  PLATFORM_VERSION   = 0.1
+  DSC_SPECIFICATION  = 0x0001001B
+  OUTPUT_DIRECTORY   = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES= AARCH64
+  BUILD_TARGETS  = NOOPT|DEBUG|RELEASE
+  SKUID_IDENTIFIER   = DEFAULT
+  FLASH_DEFINITION   = Platform/ARM/SgiPkg/SgiPlatform.fdf
+  BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.fdf.inc
+  BUILD_NUMBER   = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+
+# include common/basic libraries from MdePkg.
+!include MdePkg/MdeLibs.dsc.inc
+
+
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+
+
+[PcdsFixedAtBuild.common]
+  # GIC configurations
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x3000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x3030
+  gArmSgiTokenSpaceGuid.PcdGicSize|0x40
+
+  # ARM Cores and Clusters
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|1
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|16
+
+  # RdN2Cfg3 is the third variant from RdN2 Platform
+  gArmSgiTokenSpaceGuid.PcdPlatformVariant|3
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+
+[Components.common]
+  Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg3AcpiTables.inf
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index 8025ef58171b..afc38385c051 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
@@ -1,7 +1,7 @@
 ## @file
 #  ACPI table data and ASL sources required to boot the platform.
 #
-#  Copyright (c) 2020 - 2023, Arm Ltd. All rights reserved.
+#  Copyright (c) 2020 - 2024, Arm Ltd. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -67,6 +67,7 @@ [FixedPcd]
   gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip
   gArmSgiTokenSpaceGuid.PcdOscLpiEnable
   gArmSgiTokenSpaceGuid.PcdOscCppcEnable
+  gArmSgiTokenSpaceGuid.PcdPlatformVariant
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg3AcpiTables.inf
similarity index 90%
copy from Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
copy to Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg3AcpiTables.inf
index 8025ef58171b..a703d5a994f7 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg3AcpiTables.inf
@@ -1,7 +1,7 @@
 ## @file
 #  ACPI table data and ASL sources required to boot the platform.
 #
-#  Copyright (c) 2020 - 2023, Arm Ltd. All rights reserved.
+#  Copyright (c) 2024, Arm Ltd. All rights reserved.
 #
 #  

[edk2-devel] [edk2-platforms][PATCH v2 4/7] Platform/Sgi: Add a PCD to specify platform variant

[Prabin CA]

A new PCD named PcdPlatformVariant is introduced to specify the variant
number of a platform. This PCD can be used to select platform variant
specific configurations. The default value of this PCD is 0 which
selects the base variant.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiPlatform.dec | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec 
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 1613cc01981e..103dff8471a7 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2018 - 2023, Arm Limited. All rights reserved.
+#  Copyright (c) 2018 - 2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -51,8 +51,9 @@ [PcdsFixedAtBuild]
   gArmSgiTokenSpaceGuid.PcdVirtioP9Size|0x|UINT32|0x0029
   gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt|0x|UINT32|0x002A
 
-  # Chip count on the platform
+  # Chip count on the platform and platform variant
   gArmSgiTokenSpaceGuid.PcdChipCount|1|UINT32|0x000B
+  gArmSgiTokenSpaceGuid.PcdPlatformVariant|0|UINT32|0x002D
 
   # GIC
   gArmSgiTokenSpaceGuid.PcdGicSize|0|UINT64|0x000A
-- 
2.34.1



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[edk2-devel] [edk2-platforms][PATCH v2 3/7] Platform/Sgi: Add VariableFlashInfoLib to fix missing dependency

[Prabin CA]

From: Vijayenthiran Subramaniam 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3479

A recent change in MdeModulePkg [1] introduced VariableFlashInfoLib as a
dependency to support dynamic variable flash information. Add an
instance for the library class VariableFlashInfoLib in
SgiPlatformMm.dsc.inc to resolve this dependency.

[1]: 
https://github.com/tianocore/edk2/commit/8db39c60cdf35e0a53ccdbccf7e152ab41f54f4c

Signed-off-by: Vijayenthiran Subramaniam 
Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc 
b/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc
index 2a8c678c0816..5cc33e9f4af8 100644
--- a/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc
@@ -70,6 +70,7 @@ [LibraryClasses.common.MM_STANDALONE]
   
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
   TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
   VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+  
VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf
   SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
 !endif
 
-- 
2.34.1



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[edk2-devel] [edk2-platforms][PATCH v2 2/7] Platform/Sgi: add no-stack-protector flag for StMM builds

[Prabin CA]

Add the no-stack-protector compiler flag to allow StandaloneMM builds
on both AArch64 and x86 host. Without this flag, the link stage fails
with the following errors on multiple files when built with gcc
(Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0:

undefined reference to `__stack_chk_guard'
undefined reference to `__stack_chk_fail'

Signed-off-by: Vijayenthiran Subramaniam 
Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc 
b/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc
index ab54b3b25f4c..2a8c678c0816 100644
--- a/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc
@@ -145,5 +145,5 @@ [Components.AARCH64]
 #
 
###
 [BuildOptions.AARCH64]
-  GCC:*_*_*_CC_FLAGS = -mstrict-align -march=armv8-a -D 
DISABLE_NEW_DEPRECATED_INTERFACES
+  GCC:*_*_*_CC_FLAGS = -mstrict-align -march=armv8-a -fno-stack-protector -D 
DISABLE_NEW_DEPRECATED_INTERFACES
   GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
-- 
2.34.1



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[edk2-devel] [edk2-platforms][PATCH v2 1/7] Platform/Sgi: remove +nofp gcc option flag

[Prabin CA]

From: Omkar Anand Kulkarni 

The software executing at a higher privileged level on the reference
design platforms have been updated to allow software executing at EL1
and EL0 to access the Advanced SIMD and floating-point registers (FPEN
field of CPACR_EL1 system register is programmed to allow access). So,
remove the use of +nofp gcc build option flag.

Signed-off-by: Omkar Anand Kulkarni 
Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc 
b/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc
index ae0ff7247a6a..ab54b3b25f4c 100644
--- a/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc
@@ -145,5 +145,5 @@ [Components.AARCH64]
 #
 
###
 [BuildOptions.AARCH64]
-  GCC:*_*_*_CC_FLAGS = -mstrict-align -march=armv8-a+nofp -D 
DISABLE_NEW_DEPRECATED_INTERFACES
+  GCC:*_*_*_CC_FLAGS = -mstrict-align -march=armv8-a -D 
DISABLE_NEW_DEPRECATED_INTERFACES
   GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
-- 
2.34.1



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[edk2-devel] [edk2-platforms][PATCH v2 0/7] Platform/Sgi: Add support for RD-N2-Cfg3 and RD-V2 platform

[Prabin CA]

Changes since V1:
- Addressed comments from Sami

This patch series introduces support for two reference design platforms-
RD-N2-Cfg3 and RD-V2. The RD-N2-Cfg3 FVP platform is a variant of RD-N2
platform with a different mesh size and GIC ITS count. It is based on
the Neoverse N2 CPUs and includes 16xMP1 CPUs. RD-N2-Cfg3 has 12 GIC ITS
blocks, 6 more than the other RD-N2 variants.

The Neoverse RD-V2 FVP platform includes 16xMP1 Neoverse V2 CPUs and
each CPU has 64KB of L1 instruction/data cache, 2MB of L2 cache and 32MB
of system level cache. The system architecture of the RD-V2 platform is
similar to the RD-N2 platform, except for the CPU and L2 cache size. So
existing RD-N2 SMBIOS support is extended for RD-V2 platform to reuse
rest of the RD-N2 SMBIOS configuration for the RD-V2 platform.

In addition to patches that introduce support for these two platforms,
there are three patches that update support for existing platforms. The
first patch in this series removes +nofp gcc option flag. The second
patch adds no-stack-protector flag to the gcc build option for the StMM
builds. The third patch adds VariableFlashInfoLib to the common dsc
file.

Link to github branch with the patches in this series -
https://gitlab.arm.com/infra-solutions/reference-design/platsw/edk2-platforms/-/tree/topics/rdn2cfg3_rdv2_updates

Omkar Anand Kulkarni (1):
  Platform/Sgi: remove +nofp gcc option flag

Prabin CA (3):
  Platform/Sgi: add no-stack-protector flag for StMM builds
  Platform/Sgi: Add a PCD to specify platform variant
  Platform/Sgi: Add support for RD-N2-Cfg3 platform

Pranav Madhu (2):
  Platform/Sgi: Define RD-V2 platform id values
  Platform/Sgi: Extend SMBIOS support for RD-V2 platform

Vijayenthiran Subramaniam (1):
  Platform/Sgi: Add VariableFlashInfoLib to fix missing dependency

 Platform/ARM/SgiPkg/SgiPlatform.dec   
|  5 +-
 Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc 
|  3 +-
 Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.dsc 
| 58 
 Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf 
|  3 +-
 Platform/ARM/SgiPkg/AcpiTables/{RdN2AcpiTables.inf => RdN2Cfg3AcpiTables.inf} 
| 15 ++---
 Platform/ARM/SgiPkg/Include/SgiPlatform.h 
|  7 ++-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
|  7 ++-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c 
|  9 ++-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c 
| 20 ++-
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c 
|  8 ++-
 Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc 
| 14 -
 Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.fdf.inc 
| 10 
 12 files changed, 136 insertions(+), 23 deletions(-)
 create mode 100644 Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.dsc
 copy Platform/ARM/SgiPkg/AcpiTables/{RdN2AcpiTables.inf => 
RdN2Cfg3AcpiTables.inf} (90%)
 create mode 100644 Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.fdf.inc

-- 
2.34.1



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Re: [edk2-devel] [PATCH 1/2] UefiCpuPkg: Retrive EXTENDED_PROCESSOR_INFORMATION

[Laszlo Ersek]

On 1/5/24 13:56, Ni, Ray wrote:
> Laszlo,
> Good suggestion.
> 
> Your solution will not work if in future some extra fields might require to 
> be set to non-zero.
> But future is not coming yet. I agree with your approach.

Well, if we need to set some fields to nonzero, manual assignments will
become necessary either way, with or without the ZeroMem(). With the
ZeroMem(), we just overwrite the zero values later.

I certainly agree that there is a tipping point. Like, if we have 5
fields, and we need to set 4 of them to nonzero values, then an initial
ZeroMem is wasteful. Right now the ZeroMem() looks much more frugal, and
a bit more future-proof too.

Thanks!
Laszlo

> 
> Thanks,
> Ray
>> -Original Message-
>> From: Tan, Dun 
>> Sent: Friday, January 5, 2024 5:25 PM
>> To: Laszlo Ersek ; devel@edk2.groups.io
>> Cc: Ni, Ray ; Kumar, Rahul R ;
>> Gerd Hoffmann ; Xu, Min M 
>> Subject: RE: [edk2-devel] [PATCH 1/2] UefiCpuPkg: Retrive
>> EXTENDED_PROCESSOR_INFORMATION
>>
>> Hi Laszlo,
>>
>> Thanks for your comments. I agree with your solution. It seems simpler and
>> clearer. Will change the code and keep the additional function comments in
>> next version patch set.
>>
>> Thanks,
>> Dun
>>
>> -Original Message-
>> From: Laszlo Ersek 
>> Sent: Thursday, January 4, 2024 10:53 PM
>> To: devel@edk2.groups.io; Tan, Dun 
>> Cc: Ni, Ray ; Kumar, Rahul R ;
>> Gerd Hoffmann ; Xu, Min M 
>> Subject: Re: [edk2-devel] [PATCH 1/2] UefiCpuPkg: Retrive
>> EXTENDED_PROCESSOR_INFORMATION
>>
>> On 1/4/24 08:32, duntan wrote:
>>> Retrive EXTENDED_PROCESSOR_INFORMATION in the API
>>> MpInitLibGetProcessorInfo() of MpInitLibUp instance when the BIT24 of
>>> input ProcessorNumber is set.
>>> It's to align with the behavior in PEI/DXE MpInitLib
>>>
>>> Signed-off-by: Dun Tan 
>>> Cc: Ray Ni 
>>> Cc: Laszlo Ersek 
>>> Cc: Rahul Kumar 
>>> Cc: Gerd Hoffmann 
>>> Cc: Min Xu 
>>> ---
>>>  UefiCpuPkg/Include/Library/MpInitLib.h   |  2 ++
>>>  UefiCpuPkg/Library/MpInitLib/MpLib.c |  2 ++
>>>  UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c | 12 
>>>  3 files changed, 16 insertions(+)
>>>
>>> diff --git a/UefiCpuPkg/Include/Library/MpInitLib.h
>>> b/UefiCpuPkg/Include/Library/MpInitLib.h
>>> index 1853c46415..842c6f7ff9 100644
>>> --- a/UefiCpuPkg/Include/Library/MpInitLib.h
>>> +++ b/UefiCpuPkg/Include/Library/MpInitLib.h
>>> @@ -63,6 +63,8 @@ MpInitLibGetNumberOfProcessors (
>>>instant this call is made. This service may only be called from the BSP.
>>>
>>>@param[in]  ProcessorNumber   The handle number of processor.
>>> +Lower 24 bits contains the actual 
>>> processor number.
>>> +BIT24 indicates if the
>> EXTENDED_PROCESSOR_INFORMATION will be retrived.
>>>@param[out] ProcessorInfoBuffer   A pointer to the buffer where
>> information for
>>>  the requested processor is deposited.
>>>@param[out] HealthDataReturn processor health data.
>>> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
>>> b/UefiCpuPkg/Library/MpInitLib/MpLib.c
>>> index a359906923..cdfb570e61 100644
>>> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
>>> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
>>> @@ -2333,6 +2333,8 @@ MpInitLibInitialize (
>>>instant this call is made. This service may only be called from the BSP.
>>>
>>>@param[in]  ProcessorNumber   The handle number of processor.
>>> +Lower 24 bits contains the actual 
>>> processor number.
>>> +BIT24 indicates if the
>> EXTENDED_PROCESSOR_INFORMATION will be retrived.
>>>@param[out] ProcessorInfoBuffer   A pointer to the buffer where
>> information for
>>>  the requested processor is deposited.
>>>@param[out]  HealthDataReturn processor health data.
>>> diff --git a/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
>>> b/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
>>> index 86f9fbf903..3af4911d4b 100644
>>> --- a/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
>>> +++ b/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
>>> @@ -77,6 +77,8 @@ MpInitLibGetNumberOfProcessors (
>>>instant this call is made. This service may only be called from the BSP.
>>>
>>>@param[in]  ProcessorNumber   The handle number of processor.
>>> +Lower 24 bits contains the actual 
>>> processor number.
>>> +BIT24 indicates if the
>> EXTENDED_PROCESSOR_INFORMATION will be retrived.
>>>@param[out] ProcessorInfoBuffer   A pointer to the buffer where
>> information for
>>>  the requested processor is deposited.
>>>@param[out] HealthDataReturn processor health data.
>>> @@ -115,6 +117,16 @@ MpInitLibGetProcessorInfo (
>>>ProcessorInfoBuffer->Location.Package = 0;
>>>

Re: [edk2-devel] [PATCH 2/2] UefiCpuPkg: Check lower 24 bits of ProcessorNumber

[Laszlo Ersek]

On 1/5/24 13:55, Ni, Ray wrote:
>>> -  if (ProcessorNumber != 0) {
>>> +  //
>>> +  // Lower 24 bits contains the actual processor number.
>>> +  //
>>> +  if ((ProcessorNumber & (CPU_V2_EXTENDED_TOPOLOGY - 1)) != 0) {
> I suggest we explicitly use BIT24 instead of CPU_V2_EXTENDED_TOPOLOGY.
> Using BIT24 clearly tells that processor number only occupies the lower 24 
> bits.

Yes, I've noticed this discrepancy too; I agree BIT24 is clearer here!

> 
> 
>>>  return EFI_NOT_FOUND;
>>>}
>>>
>>
>> Reviewed-by: Laszlo Ersek 
> 



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Re: [edk2-devel] [PATCH v2 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize PatchSmmSaveStateMap and FlushTlbForAll

[Laszlo Ersek]

On 1/5/24 13:52, Ni, Ray wrote:
> Reviewed-by: Ray Ni 

Thanks, please feel free to merge this!
Laszlo

> 
> 
> Thanks,
> Ray
>> -Original Message-
>> From: Jin, Zhi 
>> Sent: Friday, January 5, 2024 10:54 AM
>> To: devel@edk2.groups.io
>> Cc: Jin, Zhi ; Ni, Ray ; Laszlo Ersek
>> ; Kumar, Rahul R ; Gerd
>> Hoffmann ; Wu, Jiaxin 
>> Subject: [PATCH v2 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize
>> PatchSmmSaveStateMap and FlushTlbForAll
>>
>> PatchSmmSaveStateMap patches the SMM entry (code) and SmmSaveState
>> region (data) for each core, which can be improved to flush TLB once
>> after all the memory entries have been patched.
>> FlushTlbForAll flushes TLB for each core in serial, which can be
>> improved to flush TLB in parrallel.
>>
>> v2:
>>Add the missing FlushTlbForAll() back in PatchSmmSaveStateMap().
>>
>> Cc: Ray Ni 
>> Cc: Laszlo Ersek 
>> Cc: Rahul Kumar 
>> Cc: Gerd Hoffmann 
>> Cc: Jiaxin Wu 
>> Signed-off-by: Zhi Jin 
>> ---
>>  .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c   | 97
>> +--
>>  1 file changed, 65 insertions(+), 32 deletions(-)
>>
>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
>> b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
>> index 15f998e501..12f3c0b8e8 100644
>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
>> @@ -547,17 +547,14 @@ FlushTlbForAll (
>>VOID
>>)
>>  {
>> -  UINTN  Index;
>> -
>>FlushTlbOnCurrentProcessor (NULL);
>> -
>> -  for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>> -if (Index != gSmst->CurrentlyExecutingCpu) {
>> -  // Force to start up AP in blocking mode,
>> -  SmmBlockingStartupThisAp (FlushTlbOnCurrentProcessor, Index, NULL);
>> -  // Do not check return status, because AP might not be present in some
>> corner cases.
>> -}
>> -  }
>> +  InternalSmmStartupAllAPs (
>> +(EFI_AP_PROCEDURE2)FlushTlbOnCurrentProcessor,
>> +0,
>> +NULL,
>> +NULL,
>> +NULL
>> +);
>>  }
>>
>>  /**
>> @@ -799,72 +796,108 @@ PatchSmmSaveStateMap (
>>UINTN  TileCodeSize;
>>UINTN  TileDataSize;
>>UINTN  TileSize;
>> +  UINTN  PageTableBase;
>>
>> -  TileCodeSize = GetSmiHandlerSize ();
>> -  TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB);
>> -  TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) +
>> sizeof (SMRAM_SAVE_STATE_MAP);
>> -  TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB);
>> -  TileSize = TileDataSize + TileCodeSize - 1;
>> -  TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
>> +  TileCodeSize  = GetSmiHandlerSize ();
>> +  TileCodeSize  = ALIGN_VALUE (TileCodeSize, SIZE_4KB);
>> +  TileDataSize  = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) +
>> sizeof (SMRAM_SAVE_STATE_MAP);
>> +  TileDataSize  = ALIGN_VALUE (TileDataSize, SIZE_4KB);
>> +  TileSize  = TileDataSize + TileCodeSize - 1;
>> +  TileSize  = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
>> +  PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
>>
>>DEBUG ((DEBUG_INFO, "PatchSmmSaveStateMap:\n"));
>>for (Index = 0; Index < mMaxNumberOfCpus - 1; Index++) {
>>  //
>>  // Code
>>  //
>> -SmmSetMemoryAttributes (
>> +ConvertMemoryPageAttributes (
>> +  PageTableBase,
>> +  mPagingMode,
>>mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET,
>>TileCodeSize,
>> -  EFI_MEMORY_RO
>> +  EFI_MEMORY_RO,
>> +  TRUE,
>> +  NULL
>>);
>> -SmmClearMemoryAttributes (
>> +ConvertMemoryPageAttributes (
>> +  PageTableBase,
>> +  mPagingMode,
>>mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET,
>>TileCodeSize,
>> -  EFI_MEMORY_XP
>> +  EFI_MEMORY_XP,
>> +  FALSE,
>> +  NULL
>>);
>>
>>  //
>>  // Data
>>  //
>> -SmmClearMemoryAttributes (
>> +ConvertMemoryPageAttributes (
>> +  PageTableBase,
>> +  mPagingMode,
>>mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET +
>> TileCodeSize,
>>TileSize - TileCodeSize,
>> -  EFI_MEMORY_RO
>> +  EFI_MEMORY_RO,
>> +  FALSE,
>> +  NULL
>>);
>> -SmmSetMemoryAttributes (
>> +ConvertMemoryPageAttributes (
>> +  PageTableBase,
>> +  mPagingMode,
>>mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET +
>> TileCodeSize,
>>TileSize - TileCodeSize,
>> -  EFI_MEMORY_XP
>> +  EFI_MEMORY_XP,
>> +  TRUE,
>> +  NULL
>>);
>>}
>>
>>//
>>// Code
>>//
>> -  SmmSetMemoryAttributes (
>> +  ConvertMemoryPageAttributes (
>> +PageTableBase,
>> +mPagingMode,
>>  mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] +
>> SMM_HANDLER_OFFSET,
>>  TileCodeSize,
>> -EFI_MEMORY_RO
>> +EFI_MEMORY_RO,
>> +TRUE,
>> +NULL
>>  );
>> -  SmmClearMemoryAttributes (
>> +  ConvertMemoryPageAttributes (
>> +PageTableBase,
>> +mPagingMode,
>>  mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] +
>> 

Re: [edk2-devel] [PATCH 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc

[Laszlo Ersek]

On 1/4/24 16:46, Sunil V L wrote:
> On Thu, Jan 04, 2024 at 03:38:17PM +0100, Laszlo Ersek wrote:
>> On 1/3/24 14:58, Sunil V L wrote:
>>> Sstc extension allows to program the timer and receive the interrupt
>>> without using an SBI call. This reduces the latency to generate the timer
>>> interrupt. So, detect whether Sstc extension is supported and use the
>>> stimecmp register directly to program the timer interrupt.
>>>
>>> Cc: Gerd Hoffmann 
>>> Cc: Rahul Kumar 
>>> Cc: Laszlo Ersek 
>>> Cc: Ray Ni 
>>> Cc: Andrei Warkentin 
>>> Signed-off-by: Sunil V L 
>>> ---
>>>  .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf |  1 +
>>>  UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h |  2 ++
>>>  UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 30 +--
>>>  3 files changed, 31 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf 
>>> b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
>>> index aba660186dc0..f2a2cf12caef 100644
>>> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
>>> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
>>> @@ -41,6 +41,7 @@ [Sources.RISCV64]
>>>Timer.c
>>>  
>>>  [Pcd]
>>> +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride   ## CONSUMES
>>>gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency  ## CONSUMES
>>>  
>>>  [Protocols]
>>> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h 
>>> b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
>>> index 9b3542230cb5..5e5071b3f0b2 100644
>>> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
>>> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
>>> @@ -26,6 +26,8 @@
>>>  //
>>>  #define DEFAULT_TIMER_TICK_DURATION  10
>>>  
>>> +#define RISCV_CPU_FEATURE_SSTC_BITMASK  0x2
>>
>> (1) Not a bug by any means, but BIT1 might read more idiomatic.
>>
> I misunderstood your comment. Will use BIT1 instead of 0x2.

OK then :)



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Re: [edk2-devel] [PATCH 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc

[Laszlo Ersek]

On 1/4/24 16:01, Sunil V L wrote:
> Hi Laszlo,
> 
> Thank you very much for the review!.
> 
> On Thu, Jan 04, 2024 at 03:38:17PM +0100, Laszlo Ersek wrote:
>> On 1/3/24 14:58, Sunil V L wrote:
>>> Sstc extension allows to program the timer and receive the interrupt
>>> without using an SBI call. This reduces the latency to generate the timer
>>> interrupt. So, detect whether Sstc extension is supported and use the
>>> stimecmp register directly to program the timer interrupt.
>>>
>>> Cc: Gerd Hoffmann 
>>> Cc: Rahul Kumar 
>>> Cc: Laszlo Ersek 
>>> Cc: Ray Ni 
>>> Cc: Andrei Warkentin 
>>> Signed-off-by: Sunil V L 
>>> ---
>>>  .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf |  1 +
>>>  UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h |  2 ++
>>>  UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 30 +--
>>>  3 files changed, 31 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf 
>>> b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
>>> index aba660186dc0..f2a2cf12caef 100644
>>> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
>>> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
>>> @@ -41,6 +41,7 @@ [Sources.RISCV64]
>>>Timer.c
>>>  
>>>  [Pcd]
>>> +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride   ## CONSUMES
>>>gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency  ## CONSUMES
>>>  
>>>  [Protocols]
>>> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h 
>>> b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
>>> index 9b3542230cb5..5e5071b3f0b2 100644
>>> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
>>> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
>>> @@ -26,6 +26,8 @@
>>>  //
>>>  #define DEFAULT_TIMER_TICK_DURATION  10
>>>  
>>> +#define RISCV_CPU_FEATURE_SSTC_BITMASK  0x2
>>
>> (1) Not a bug by any means, but BIT1 might read more idiomatic.
>>
> Agree. Would RISCV_CPU_FEATURE_BIT1_SSTC be better?

Sorry, I was unclear: the macro *name* was fine, IMO; my proposal was to
change the *replacement text* from 0x2 to BIT1. (Because BIT1 is another
macro, from "MdePkg/Include/Base.h"; those are frequently used all over
edk2.)

Thanks!
Laszlo

> 
>>> +
>>>  extern VOID
>>>  RiscvSetTimerPeriod (
>>>UINT32  TimerPeriod
>>> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c 
>>> b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
>>> index 30e48061cd06..4babfb4bfc60 100644
>>> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
>>> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
>>> @@ -44,6 +44,19 @@ STATIC EFI_TIMER_NOTIFY  mTimerNotifyFunction;
>>>  STATIC UINT64  mTimerPeriod = 0;
>>>  STATIC UINT64  mLastPeriodStart = 0;
>>>  
>>> +/**
>>> +  Check whether Sstc is enabled in PCD.
>>> +
>>> +**/
>>> +STATIC
>>> +BOOLEAN
>>> +RiscVIsSstcEnabled (
>>> +  VOID
>>> +  )
>>> +{
>>> +  return ((PcdGet64 (PcdRiscVFeatureOverride) & 
>>> RISCV_CPU_FEATURE_SSTC_BITMASK) != 0);
>>> +}
>>> +
>>>  /**
>>>Timer Interrupt Handler.
>>>  
>>> @@ -94,7 +107,12 @@ TimerInterruptHandler (
>>>   ),
>>> 100u
>>> );  // convert to tick
>>> -  SbiSetTimer (PeriodStart);
>>> +  if (RiscVIsSstcEnabled ()) {
>>
>> (2) Even though the PCD is currently declared as fixed or
>> patchable-in-module, seeing a PcdGet64() call on the call stack of the
>> timer interrupt handler (and at a high TPL) makes me uncomfortable. It
>> carries a risk that later on we relax the PCD decl to dynamic, and then
>> this code would become brittle.
>>
>> I propose: either replace the PcdGet64 call above with FixedPcdGet64 (so
>> it can never land in the runtime / dynamic PCD protocol), or perform the
>> PCD check in the entry point function of the driver, and store the
>> result in a STATIC BOOLEAN variable. Then further PCD accesses (dynamic
>> or otherwise) will not be needed.
>>
> Ahh yes. Good point. Let me use a static variable as you suggested.
> 
>>> +RiscVSetSupervisorTimeCompareRegister (PeriodStart);
>>> +  } else {
>>> +SbiSetTimer (PeriodStart);
>>> +  }
>>> +
>>>RiscVEnableTimerInterrupt (); // enable SMode timer int
>>>gBS->RestoreTPL (OriginalTPL);
>>>  }
>>> @@ -197,7 +215,11 @@ TimerDriverSetTimerPeriod (
>>>   ),
>>> 100u
>>> ); // convert to tick
>>> -  SbiSetTimer (PeriodStart);
>>> +  if (RiscVIsSstcEnabled ()) {
>>> +RiscVSetSupervisorTimeCompareRegister (PeriodStart);
>>> +  } else {
>>> +SbiSetTimer (PeriodStart);
>>> +  }
>>>  
>>>mCpu->EnableInterrupt (mCpu);
>>>RiscVEnableTimerInterrupt (); // enable SMode timer int
>>
>> (3) This seems like duplicated code. How about replacing the
>> RiscVIsSstcEnabled() function with a more substantive function that
>> incorporates both the feature check *and* the "PeriodStart" setting?
>> Then you can easily call that function from both TimerInterruptHandler()
>> and TimerDriverSetTimerPeriod().
>>
> I agree. Let me update in 

Re: [edk2-devel] [PATCH v3 1/1] OvmfPkg/VirtNorFlashDxe: sanity-check variables

[Laszlo Ersek]

On 1/4/24 16:06, Gerd Hoffmann wrote:
>   Hi,
> 
 - if the StartId is 0x55aa, then we need to look further, beause we
 can't decide yet. For example, if State is VAR_HEADER_VALID_ONLY (0x7f),
 then it might be fine for the variable header (at the very end of the
 varstore) *not* to be followed by payload bytes (name, data).
>>>
>>> Not sure this makes sense.  VAR_HEADER_VALID_ONLY is a temporary state,
>>> while the variable driver writes name and data just after the header,
>>> to be updated to VAR_ADDED when the write completed successfully.  So
>>> I'd expect to never find a header without space for name + data.
>>
>> - Do we know for sure that VAR_HEADER_VALID_ONLY is never expected to be
>> seen?
> 
> Writing goes like this:
> 
>   (1) find free space
>   (2) write header, with VAR_HEADER_VALID_ONLY.
>   (3) write name + data
>   (4) update header, set state = VAR_ADDED.
> 
>> What if the variable update design defines VAR_HEADER_VALID_ONLY
>> specifically so that the variable driver can recover from a power loss
>> "in the middle"?
> 
> Power loss in step (3) can surely lead to variables in
> VAR_HEADER_VALID_ONLY state, and I'd expect the variable driver can
> actually recover from that.
> 
> [ side note:  The (2) write should be small enough that it fits into the
>   flash block write buffer (128 bytes).  Which could be
>   important to maintain variable store consistency. ]
> 
> Nevertheless we should never find a header at the end of the variable
> store, without space allocated for name + date.  Minimal space for the
> name is 4 bytes (one char16 + '\0'), for the data 1 byte, alignment
> rounds the latter to 4 bytes too, so this should be true:
> 
> VarOffset + sizeof(*VarHeader) + 8 <= VariableStoreHeader->Size
> 
>> So I figure, if we accept VAR_HEADER_VALID_ONLY in that logic, then we
>> should also accept VAR_HEADER_VALID_ONLY if it's at the very end of
>> the varstore.
> 
> Disagree, see above.  Storing the header at a place which leaves no room
> for name + data doesn't make sense to me.

OK, that sounds convincing, thanks!
Laszlo

> We could go the extra mile and look at the next StartId location, verify
> StartId != 0x55aa, in the no-space-left-for-header case.
> 
> take care,
>   Gerd
> 



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Re: [edk2-devel] [PATCH 1/2] UefiCpuPkg: Retrive EXTENDED_PROCESSOR_INFORMATION

[Ni, Ray]

Laszlo,
Good suggestion.

Your solution will not work if in future some extra fields might require to be 
set to non-zero.
But future is not coming yet. I agree with your approach.

Thanks,
Ray
> -Original Message-
> From: Tan, Dun 
> Sent: Friday, January 5, 2024 5:25 PM
> To: Laszlo Ersek ; devel@edk2.groups.io
> Cc: Ni, Ray ; Kumar, Rahul R ;
> Gerd Hoffmann ; Xu, Min M 
> Subject: RE: [edk2-devel] [PATCH 1/2] UefiCpuPkg: Retrive
> EXTENDED_PROCESSOR_INFORMATION
> 
> Hi Laszlo,
> 
> Thanks for your comments. I agree with your solution. It seems simpler and
> clearer. Will change the code and keep the additional function comments in
> next version patch set.
> 
> Thanks,
> Dun
> 
> -Original Message-
> From: Laszlo Ersek 
> Sent: Thursday, January 4, 2024 10:53 PM
> To: devel@edk2.groups.io; Tan, Dun 
> Cc: Ni, Ray ; Kumar, Rahul R ;
> Gerd Hoffmann ; Xu, Min M 
> Subject: Re: [edk2-devel] [PATCH 1/2] UefiCpuPkg: Retrive
> EXTENDED_PROCESSOR_INFORMATION
> 
> On 1/4/24 08:32, duntan wrote:
> > Retrive EXTENDED_PROCESSOR_INFORMATION in the API
> > MpInitLibGetProcessorInfo() of MpInitLibUp instance when the BIT24 of
> > input ProcessorNumber is set.
> > It's to align with the behavior in PEI/DXE MpInitLib
> >
> > Signed-off-by: Dun Tan 
> > Cc: Ray Ni 
> > Cc: Laszlo Ersek 
> > Cc: Rahul Kumar 
> > Cc: Gerd Hoffmann 
> > Cc: Min Xu 
> > ---
> >  UefiCpuPkg/Include/Library/MpInitLib.h   |  2 ++
> >  UefiCpuPkg/Library/MpInitLib/MpLib.c |  2 ++
> >  UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c | 12 
> >  3 files changed, 16 insertions(+)
> >
> > diff --git a/UefiCpuPkg/Include/Library/MpInitLib.h
> > b/UefiCpuPkg/Include/Library/MpInitLib.h
> > index 1853c46415..842c6f7ff9 100644
> > --- a/UefiCpuPkg/Include/Library/MpInitLib.h
> > +++ b/UefiCpuPkg/Include/Library/MpInitLib.h
> > @@ -63,6 +63,8 @@ MpInitLibGetNumberOfProcessors (
> >instant this call is made. This service may only be called from the BSP.
> >
> >@param[in]  ProcessorNumber   The handle number of processor.
> > +Lower 24 bits contains the actual 
> > processor number.
> > +BIT24 indicates if the
> EXTENDED_PROCESSOR_INFORMATION will be retrived.
> >@param[out] ProcessorInfoBuffer   A pointer to the buffer where
> information for
> >  the requested processor is deposited.
> >@param[out] HealthDataReturn processor health data.
> > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > index a359906923..cdfb570e61 100644
> > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > @@ -2333,6 +2333,8 @@ MpInitLibInitialize (
> >instant this call is made. This service may only be called from the BSP.
> >
> >@param[in]  ProcessorNumber   The handle number of processor.
> > +Lower 24 bits contains the actual 
> > processor number.
> > +BIT24 indicates if the
> EXTENDED_PROCESSOR_INFORMATION will be retrived.
> >@param[out] ProcessorInfoBuffer   A pointer to the buffer where
> information for
> >  the requested processor is deposited.
> >@param[out]  HealthDataReturn processor health data.
> > diff --git a/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
> > b/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
> > index 86f9fbf903..3af4911d4b 100644
> > --- a/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
> > +++ b/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
> > @@ -77,6 +77,8 @@ MpInitLibGetNumberOfProcessors (
> >instant this call is made. This service may only be called from the BSP.
> >
> >@param[in]  ProcessorNumber   The handle number of processor.
> > +Lower 24 bits contains the actual 
> > processor number.
> > +BIT24 indicates if the
> EXTENDED_PROCESSOR_INFORMATION will be retrived.
> >@param[out] ProcessorInfoBuffer   A pointer to the buffer where
> information for
> >  the requested processor is deposited.
> >@param[out] HealthDataReturn processor health data.
> > @@ -115,6 +117,16 @@ MpInitLibGetProcessorInfo (
> >ProcessorInfoBuffer->Location.Package = 0;
> >ProcessorInfoBuffer->Location.Core= 0;
> >ProcessorInfoBuffer->Location.Thread  = 0;
> > +
> > +  if ((ProcessorNumber & CPU_V2_EXTENDED_TOPOLOGY) != 0) {
> > +ProcessorInfoBuffer->ExtendedInformation.Location2.Package = 0;
> > +ProcessorInfoBuffer->ExtendedInformation.Location2.Die = 0;
> > +ProcessorInfoBuffer->ExtendedInformation.Location2.Tile= 0;
> > +ProcessorInfoBuffer->ExtendedInformation.Location2.Module  = 0;
> > +ProcessorInfoBuffer->ExtendedInformation.Location2.Core= 0;
> > +

Re: [edk2-devel] [PATCH 2/2] UefiCpuPkg: Check lower 24 bits of ProcessorNumber

[Ni, Ray]

> > -  if (ProcessorNumber != 0) {
> > +  //
> > +  // Lower 24 bits contains the actual processor number.
> > +  //
> > +  if ((ProcessorNumber & (CPU_V2_EXTENDED_TOPOLOGY - 1)) != 0) {
I suggest we explicitly use BIT24 instead of CPU_V2_EXTENDED_TOPOLOGY.
Using BIT24 clearly tells that processor number only occupies the lower 24 bits.


> >  return EFI_NOT_FOUND;
> >}
> >
> 
> Reviewed-by: Laszlo Ersek 



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Re: [edk2-devel] [PATCH v6 13/36] UefiCpuPkg: Add LoongArch64CpuMmuLib to UefiCpuPkg

[Ni, Ray]

Acked-by: Ray Ni 

Thanks,
Ray
> -Original Message-
> From: Chao Li 
> Sent: Friday, January 5, 2024 5:44 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann ;
> Baoqi Zhang ; Dongyan Qian
> ; Xianglai Li ; Bibo Mao
> 
> Subject: [PATCH v6 13/36] UefiCpuPkg: Add LoongArch64CpuMmuLib to
> UefiCpuPkg
> 
> Add a new library LoongArch64CpuMmuLib. It provides two-stage MMU
> library
> instances, PEI and DXE.
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
> 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> Signed-off-by: Chao Li 
> Co-authored-by: Baoqi Zhang 
> Co-authored-by: Dongyan Qian 
> Co-authored-by: Xianglai Li 
> Co-authored-by: Bibo Mao 
> ---
>  .../LoongArch64CpuMmuLib/CommonMmuLib.c   | 986
> ++
>  .../LoongArch64CpuMmuLib/CommonMmuLib.h   |  43 +
>  .../LoongArch64CpuMmuLib/DxeCpuMmuLib.inf |  36 +
>  .../LoongArch64CpuMmuLib/DxeCpuMmuLib.uni |  14 +
>  .../Library/LoongArch64CpuMmuLib/Page.h   | 279 +
>  .../LoongArch64CpuMmuLib/PeiCpuMmuLib.c   | 178 
>  .../LoongArch64CpuMmuLib/PeiCpuMmuLib.inf |  44 +
>  .../LoongArch64CpuMmuLib/PeiCpuMmuLib.uni |  14 +
>  UefiCpuPkg/Library/LoongArch64CpuMmuLib/Tlb.h |  48 +
>  .../LoongArch64CpuMmuLib/TlbOperation.S   |  44 +
>  UefiCpuPkg/UefiCpuPkg.dsc |   2 +
>  11 files changed, 1688 insertions(+)
>  create mode 100644
> UefiCpuPkg/Library/LoongArch64CpuMmuLib/CommonMmuLib.c
>  create mode 100644
> UefiCpuPkg/Library/LoongArch64CpuMmuLib/CommonMmuLib.h
>  create mode 100644
> UefiCpuPkg/Library/LoongArch64CpuMmuLib/DxeCpuMmuLib.inf
>  create mode 100644
> UefiCpuPkg/Library/LoongArch64CpuMmuLib/DxeCpuMmuLib.uni
>  create mode 100644 UefiCpuPkg/Library/LoongArch64CpuMmuLib/Page.h
>  create mode 100644
> UefiCpuPkg/Library/LoongArch64CpuMmuLib/PeiCpuMmuLib.c
>  create mode 100644
> UefiCpuPkg/Library/LoongArch64CpuMmuLib/PeiCpuMmuLib.inf
>  create mode 100644
> UefiCpuPkg/Library/LoongArch64CpuMmuLib/PeiCpuMmuLib.uni
>  create mode 100644 UefiCpuPkg/Library/LoongArch64CpuMmuLib/Tlb.h
>  create mode 100644
> UefiCpuPkg/Library/LoongArch64CpuMmuLib/TlbOperation.S
> 
> diff --git a/UefiCpuPkg/Library/LoongArch64CpuMmuLib/CommonMmuLib.c
> b/UefiCpuPkg/Library/LoongArch64CpuMmuLib/CommonMmuLib.c
> new file mode 100644
> index 00..c92f678f3e
> --- /dev/null
> +++ b/UefiCpuPkg/Library/LoongArch64CpuMmuLib/CommonMmuLib.c
> @@ -0,0 +1,986 @@
> +/** @file
> +
> +  CPU Memory Map Unit Handler Library common functions.
> +
> +  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
> reserved.
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +  @par Glossary:
> +- Pgd or Pgd or PGD- Page Global Directory
> +- Pud or Pud or PUD- Page Upper Directory
> +- Pmd or Pmd or PMD- Page Middle Directory
> +- Pte or pte or PTE- Page Table Entry
> +- Val or VAL or val- Value
> +- Dir- Directory
> +**/
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "Tlb.h"
> +#include "Page.h"
> +
> +#define SWAP_PAGE_DIR  CsrRead(LOONGARCH_CSR_PGDL)
> +#define EFI_MEMORY_CACHETYPE_MASK  (EFI_MEMORY_UC  | \
> +EFI_MEMORY_WC  | \
> +EFI_MEMORY_WT  | \
> +EFI_MEMORY_WB  | \
> +EFI_MEMORY_UCE   \
> +)
> +
> +BOOLEAN  mMmuInited = FALSE;
> +
> +/**
> +  Check to see if mmu successfully initializes.
> +
> +  @param  VOID.
> +
> +  @retval  TRUE  Initialization has been completed.
> +   FALSE Initialization did not complete.
> +**/
> +STATIC
> +BOOLEAN
> +MmuIsInit (
> +  VOID
> +  )
> +{
> +  if (mMmuInited || (SWAP_PAGE_DIR != 0)) {
> +return TRUE;
> +  }
> +
> +  return FALSE;
> +}
> +
> +/**
> +  Iterates through the page directory to initialize it.
> +
> +  @param  Dst  A pointer to the directory of the page to initialize.
> +  @param  Num  The number of page directories to initialize.
> +  @param  Src  A pointer to the data used to initialize the page directory.
> +
> +  @return VOID.
> +**/
> +STATIC
> +VOID
> +PageDirInit (
> +  IN VOID   *Dst,
> +  IN UINTN  Num,
> +  IN VOID   *Src
> +  )
> +{
> +  UINTN  *Ptr;
> +  UINTN  *End;
> +  UINTN  Entry;
> +
> +  Entry = (UINTN)Src;
> +  Ptr   = (UINTN *)Dst;
> +  End   = Ptr + Num;
> +
> +  for ( ; Ptr < End; Ptr++) {
> +*Ptr = Entry;
> +  }
> +
> +  return;
> +}
> +
> +/**
> +  Gets the virtual address corresponding to the page global directory table
> entry.
> +
> +  @param  Address  the virtual address for the table entry.
> +
> +  @retval PGD A pointer to get the table item.
> +**/
> +STATIC
> +PGD *
> +PgdOffset (
> +  IN UINTN  Address
> +  )
> +{
> +  return (PGD *)(SWAP_PAGE_DIR) + PGD_INDEX (Address);
> +}
> +
> +/**
> +  Gets the 

Re: [edk2-devel] [PATCH v2 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize PatchSmmSaveStateMap and FlushTlbForAll

[Ni, Ray]

Reviewed-by: Ray Ni 


Thanks,
Ray
> -Original Message-
> From: Jin, Zhi 
> Sent: Friday, January 5, 2024 10:54 AM
> To: devel@edk2.groups.io
> Cc: Jin, Zhi ; Ni, Ray ; Laszlo Ersek
> ; Kumar, Rahul R ; Gerd
> Hoffmann ; Wu, Jiaxin 
> Subject: [PATCH v2 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize
> PatchSmmSaveStateMap and FlushTlbForAll
> 
> PatchSmmSaveStateMap patches the SMM entry (code) and SmmSaveState
> region (data) for each core, which can be improved to flush TLB once
> after all the memory entries have been patched.
> FlushTlbForAll flushes TLB for each core in serial, which can be
> improved to flush TLB in parrallel.
> 
> v2:
>Add the missing FlushTlbForAll() back in PatchSmmSaveStateMap().
> 
> Cc: Ray Ni 
> Cc: Laszlo Ersek 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> Cc: Jiaxin Wu 
> Signed-off-by: Zhi Jin 
> ---
>  .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c   | 97
> +--
>  1 file changed, 65 insertions(+), 32 deletions(-)
> 
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> index 15f998e501..12f3c0b8e8 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> @@ -547,17 +547,14 @@ FlushTlbForAll (
>VOID
>)
>  {
> -  UINTN  Index;
> -
>FlushTlbOnCurrentProcessor (NULL);
> -
> -  for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
> -if (Index != gSmst->CurrentlyExecutingCpu) {
> -  // Force to start up AP in blocking mode,
> -  SmmBlockingStartupThisAp (FlushTlbOnCurrentProcessor, Index, NULL);
> -  // Do not check return status, because AP might not be present in some
> corner cases.
> -}
> -  }
> +  InternalSmmStartupAllAPs (
> +(EFI_AP_PROCEDURE2)FlushTlbOnCurrentProcessor,
> +0,
> +NULL,
> +NULL,
> +NULL
> +);
>  }
> 
>  /**
> @@ -799,72 +796,108 @@ PatchSmmSaveStateMap (
>UINTN  TileCodeSize;
>UINTN  TileDataSize;
>UINTN  TileSize;
> +  UINTN  PageTableBase;
> 
> -  TileCodeSize = GetSmiHandlerSize ();
> -  TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB);
> -  TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) +
> sizeof (SMRAM_SAVE_STATE_MAP);
> -  TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB);
> -  TileSize = TileDataSize + TileCodeSize - 1;
> -  TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
> +  TileCodeSize  = GetSmiHandlerSize ();
> +  TileCodeSize  = ALIGN_VALUE (TileCodeSize, SIZE_4KB);
> +  TileDataSize  = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) +
> sizeof (SMRAM_SAVE_STATE_MAP);
> +  TileDataSize  = ALIGN_VALUE (TileDataSize, SIZE_4KB);
> +  TileSize  = TileDataSize + TileCodeSize - 1;
> +  TileSize  = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
> +  PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
> 
>DEBUG ((DEBUG_INFO, "PatchSmmSaveStateMap:\n"));
>for (Index = 0; Index < mMaxNumberOfCpus - 1; Index++) {
>  //
>  // Code
>  //
> -SmmSetMemoryAttributes (
> +ConvertMemoryPageAttributes (
> +  PageTableBase,
> +  mPagingMode,
>mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET,
>TileCodeSize,
> -  EFI_MEMORY_RO
> +  EFI_MEMORY_RO,
> +  TRUE,
> +  NULL
>);
> -SmmClearMemoryAttributes (
> +ConvertMemoryPageAttributes (
> +  PageTableBase,
> +  mPagingMode,
>mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET,
>TileCodeSize,
> -  EFI_MEMORY_XP
> +  EFI_MEMORY_XP,
> +  FALSE,
> +  NULL
>);
> 
>  //
>  // Data
>  //
> -SmmClearMemoryAttributes (
> +ConvertMemoryPageAttributes (
> +  PageTableBase,
> +  mPagingMode,
>mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET +
> TileCodeSize,
>TileSize - TileCodeSize,
> -  EFI_MEMORY_RO
> +  EFI_MEMORY_RO,
> +  FALSE,
> +  NULL
>);
> -SmmSetMemoryAttributes (
> +ConvertMemoryPageAttributes (
> +  PageTableBase,
> +  mPagingMode,
>mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET +
> TileCodeSize,
>TileSize - TileCodeSize,
> -  EFI_MEMORY_XP
> +  EFI_MEMORY_XP,
> +  TRUE,
> +  NULL
>);
>}
> 
>//
>// Code
>//
> -  SmmSetMemoryAttributes (
> +  ConvertMemoryPageAttributes (
> +PageTableBase,
> +mPagingMode,
>  mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] +
> SMM_HANDLER_OFFSET,
>  TileCodeSize,
> -EFI_MEMORY_RO
> +EFI_MEMORY_RO,
> +TRUE,
> +NULL
>  );
> -  SmmClearMemoryAttributes (
> +  ConvertMemoryPageAttributes (
> +PageTableBase,
> +mPagingMode,
>  mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] +
> SMM_HANDLER_OFFSET,
>  TileCodeSize,
> -EFI_MEMORY_XP
> +EFI_MEMORY_XP,
> +FALSE,
> +NULL
>  );
> 
>//
>// Data
>//
> -  SmmClearMemoryAttributes (
> +  ConvertMemoryPageAttributes (
> +PageTableBase,
> 

Re: [edk2-devel] [PATCH v6 12/36] UefiCpuPkg: Add CpuMmuLib.h to UefiCpuPkg

[Ni, Ray]

Reviewed-by: Ray Ni 

Thanks,
Ray
> -Original Message-
> From: Chao Li 
> Sent: Friday, January 5, 2024 5:44 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann ;
> Leif Lindholm ; Ard Biesheuvel
> ; Sami Mujawar ;
> Sunil V L ; Warkentin, Andrei
> 
> Subject: [PATCH v6 12/36] UefiCpuPkg: Add CpuMmuLib.h to UefiCpuPkg
> 
> Add a new header file CpuMmuLib.h, whitch is referenced from
> ArmPkg/Include/Library/ArmMmuLib.h. Currently, only support for
> LoongArch64 is added, and more architectures can be accommodated in the
> future.
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
> 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> Cc: Leif Lindholm 
> Cc: Ard Biesheuvel 
> Cc: Sami Mujawar 
> Cc: Sunil V L 
> Cc: Andrei Warkentin 
> Signed-off-by: Chao Li 
> Reviewed-by: Andrei Warkentin 
> ---
>  UefiCpuPkg/Include/Library/CpuMmuLib.h | 62
> ++
>  UefiCpuPkg/UefiCpuPkg.dec  |  4 ++
>  2 files changed, 66 insertions(+)
>  create mode 100644 UefiCpuPkg/Include/Library/CpuMmuLib.h
> 
> diff --git a/UefiCpuPkg/Include/Library/CpuMmuLib.h
> b/UefiCpuPkg/Include/Library/CpuMmuLib.h
> new file mode 100644
> index 00..f88ec4eb2e
> --- /dev/null
> +++ b/UefiCpuPkg/Include/Library/CpuMmuLib.h
> @@ -0,0 +1,62 @@
> +/** @file
> +
> +  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
> reserved.
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef CPU_MMU_LIB_H_
> +#define CPU_MMU_LIB_H_
> +
> +#include 
> +
> +typedef struct {
> +  EFI_PHYSICAL_ADDRESSPhysicalBase;
> +  EFI_VIRTUAL_ADDRESS VirtualBase;
> +  UINTN   Length;
> +  UINTN   Attributes;
> +} MEMORY_REGION_DESCRIPTOR;
> +
> +/**
> +  Finds the first of the length and memory properties of the memory region
> corresponding
> +  to the specified base address.
> +
> +  @param[in]   BaseAddress   To find the base address of the memory
> region.
> +  @param[in, out]  RegionLength  Pointer holding:
> +  - At entry, the length of the memory 
> region
> +expected to be found.
> +  - At exit, the length of the memory 
> region found.
> +  @param[out]  RegionAttributes  Properties of the memory region found.
> +
> +  @retval  EFI_SUCCESSThe corresponding memory area was successfully
> found
> +   EFI_NOT_FOUNDNo memory area found
> +**/
> +EFI_STATUS
> +EFIAPI
> +GetMemoryRegionAttributes (
> +  IN UINTN  BaseAddress,
> +  IN OUT UINTN  *RegionLength,
> +  OUTUINTN  *RegionAttributes
> +  );
> +
> +/**
> +  Sets the Attributes  of the specified memory region.
> +
> +  @param[in]  BaseAddressThe base address of the memory region to set
> the Attributes.
> +  @param[in]  Length The length of the memory region to set the
> Attributes.
> +  @param[in]  Attributes The Attributes to be set.
> +  @param[in]  AttributeMask  Mask of memory attributes to take into
> account.
> +
> +  @retval  EFI_SUCCESSThe Attributes was set successfully
> +**/
> +EFI_STATUS
> +EFIAPI
> +SetMemoryRegionAttributes (
> +  IN EFI_PHYSICAL_ADDRESS  BaseAddress,
> +  IN UINTN Length,
> +  IN UINTN Attributes,
> +  IN UINT64AttributeMask
> +  );
> +
> +#endif // CPU_MMU_LIB_H_
> diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
> index 84f61254bb..9b11a3da72 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -62,6 +62,10 @@
>##  @libraryclass  Provides function for manipulating x86 paging 
> structures.
>CpuPageTableLib|Include/Library/CpuPageTableLib.h
> 
> +[LibraryClasses.LoongArch64]
> +  ##  @libraryclass  Provides macros and functions for the memory
> management unit.
> +  CpuMmuLib|Include/Library/CpuMmuLib.h
> +
>## @libraryclass   Provides functions for manipulating smram savestate
> registers.
>MmSaveStateLib|Include/Library/MmSaveStateLib.h
> 
> --
> 2.27.0



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Re: [edk2-devel] [PATCH v1 1/1] StandaloneMmPkg: Initialise serial port early in StandaloneMmEntryPoint

[levi.yun]

+ ardb+tianoc...@kernel.org


From: levi.yun 
Sent: 05 January 2024 11:49
To: devel@edk2.groups.io
Cc: Yeo Reum Yun; ard.biesheu...@linaro.org; Sami Mujawar; ray...@intel.com; 
Pierre Gondois; nd
Subject: [PATCH v1 1/1] StandaloneMmPkg: Initialise serial port early in 
StandaloneMmEntryPoint

Serial port used by the DEBUG macro is initialised in StandaloneMmMain
by the DebugLib constructor.

When we use a serial port initialised by TF-A it is not a problem.
However, if we use a serial port that is not initialised by TF-A,
the debug log prints hangs.

Therefore, initialise the serial port early on in the entry point.

Signed-off-by: levi.yun 
---
These changes can be seen at
https://github.com/LeviYeoReum/edk2/tree/levi/2956_init_serial too.

 StandaloneMmPkg/StandaloneMmPkg.dsc
 | 1 +
 
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
   | 1 +
 
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
 | 3 +++
 3 files changed, 5 insertions(+)

diff --git a/StandaloneMmPkg/StandaloneMmPkg.dsc 
b/StandaloneMmPkg/StandaloneMmPkg.dsc
index 
8012f93b7dcc38ea8fdd2de98912bbc09157ec53..040a4aa5b3d268fdfaaec9a975cfc6ff31aa37b4
 100644
--- a/StandaloneMmPkg/StandaloneMmPkg.dsc
+++ b/StandaloneMmPkg/StandaloneMmPkg.dsc
@@ -66,6 +66,7 @@ [LibraryClasses.AARCH64, LibraryClasses.ARM]
   ArmSvcLib|ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
   
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
   
PeCoffExtraActionLib|StandaloneMmPkg/Library/StandaloneMmPeCoffExtraActionLib/StandaloneMmPeCoffExtraActionLib.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf

   NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
   NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
diff --git 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
index 
75cfb98c0e75cd7cee2a59723035679612da4528..086639ecfbc983627aed73817815e2485104375e
 100644
--- 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
+++ 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
@@ -42,6 +42,7 @@ [LibraryClasses]
   DebugLib

 [LibraryClasses.ARM, LibraryClasses.AARCH64]
+  SerialPortLib
   StandaloneMmMmuLib
   ArmSvcLib

diff --git 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
index 
96de10405af829c66e3f43ed4692f785d8df113e..66b56bdfe4959d5ab6152ff024caa6e900e7a948
 100644
--- 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
+++ 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
@@ -335,6 +335,9 @@ _ModuleEntryPoint (
   UINTN   TeDataSize;
   EFI_PHYSICAL_ADDRESSImageBase;

+  // Initialize the Serial Port early to print debug log before 
StandaloneMmMain.
+  SerialPortInitialize ();
+
   // Get Secure Partition Manager Version Information
   Status = GetSpmVersion ();
   if (EFI_ERROR (Status)) {
--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")

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[edk2-devel] [PATCH v1 1/1] StandaloneMmPkg: Initialise serial port early in StandaloneMmEntryPoint

[levi.yun]

Serial port used by the DEBUG macro is initialised in StandaloneMmMain
by the DebugLib constructor.

When we use a serial port initialised by TF-A it is not a problem.
However, if we use a serial port that is not initialised by TF-A,
the debug log prints hangs.

Therefore, initialise the serial port early on in the entry point.

Signed-off-by: levi.yun 
---
These changes can be seen at
https://github.com/LeviYeoReum/edk2/tree/levi/2956_init_serial too.

 StandaloneMmPkg/StandaloneMmPkg.dsc
 | 1 +
 
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
   | 1 +
 
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
 | 3 +++
 3 files changed, 5 insertions(+)

diff --git a/StandaloneMmPkg/StandaloneMmPkg.dsc 
b/StandaloneMmPkg/StandaloneMmPkg.dsc
index 
8012f93b7dcc38ea8fdd2de98912bbc09157ec53..040a4aa5b3d268fdfaaec9a975cfc6ff31aa37b4
 100644
--- a/StandaloneMmPkg/StandaloneMmPkg.dsc
+++ b/StandaloneMmPkg/StandaloneMmPkg.dsc
@@ -66,6 +66,7 @@ [LibraryClasses.AARCH64, LibraryClasses.ARM]
   ArmSvcLib|ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
   
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
   
PeCoffExtraActionLib|StandaloneMmPkg/Library/StandaloneMmPeCoffExtraActionLib/StandaloneMmPeCoffExtraActionLib.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf

   NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
   NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
diff --git 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
index 
75cfb98c0e75cd7cee2a59723035679612da4528..086639ecfbc983627aed73817815e2485104375e
 100644
--- 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
+++ 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
@@ -42,6 +42,7 @@ [LibraryClasses]
   DebugLib

 [LibraryClasses.ARM, LibraryClasses.AARCH64]
+  SerialPortLib
   StandaloneMmMmuLib
   ArmSvcLib

diff --git 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
index 
96de10405af829c66e3f43ed4692f785d8df113e..66b56bdfe4959d5ab6152ff024caa6e900e7a948
 100644
--- 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
+++ 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
@@ -335,6 +335,9 @@ _ModuleEntryPoint (
   UINTN   TeDataSize;
   EFI_PHYSICAL_ADDRESSImageBase;

+  // Initialize the Serial Port early to print debug log before 
StandaloneMmMain.
+  SerialPortInitialize ();
+
   // Get Secure Partition Manager Version Information
   Status = GetSpmVersion ();
   if (EFI_ERROR (Status)) {
--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")

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confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
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Re: [edk2-devel] [edk2-redfish-client][PATCH V2] RedfishClientPkg: Add ETag PCD and revise Redfish ETag functions

[Mike Maslenkin]

Hi Abner,

Thank you for the clarification.

Regards,
Mike.

On Fri, Jan 5, 2024 at 12:03 PM Chang, Abner  wrote:
>
> [AMD Official Use Only - General]
>
> Hi Mike,
> This PCD is introduced for the platform that connects to the Redfish service 
> which doesn't support ETag.
> We disable the client code that handles ETag with setting this PCD to FALSE. 
> So client will just consume any Redfish property from service even there is 
> nothing changed. This knob doesn't control Redfish service behavior on BMC.
> Yes, there is no method to detect if Redfish service supports ETag or not. So 
> we introduce a client side knob to disable ETag checking although it mentions 
> the service "should" support ETag in Redfish spec. However, a simple Redfish 
> services may not implementing ETag HTTP header.
> Does above clarify the question?
>
> Thanks
> Abner
>
> > -Original Message-
> > From: Mike Maslenkin 
> > Sent: Friday, January 5, 2024 8:20 AM
> > To: devel@edk2.groups.io; Chang, Abner 
> > Cc: Nickle Wang ; Igor Kulchytskyy 
> > Subject: Re: [edk2-devel] [edk2-redfish-client][PATCH V2] RedfishClientPkg:
> > Add ETag PCD and revise Redfish ETag functions
> >
> > Caution: This message originated from an External Source. Use proper caution
> > when opening attachments, clicking links, or responding.
> >
> >
> > Looks good to me.
> >
> > But could it be possible to rephrase "ETAG is not supported on Redfish
> > service." ?
> > May be I misunderstand, but I assume "Redfish service" is a service at
> > BMC side, while we are disabling ETAG functionality at Redfish client
> > side.
> > README.md says "Redfish service hosted by Board Management Controller
> > (BMC) in server".
> > Currently there is no method to get server features (AFAIR), so we
> > disable a work with those explicitly on the client side.
> >
> > Regards,
> > Mike.
> >
> > On Thu, Jan 4, 2024 at 11:57 AM Chang, Abner via groups.io
> >  wrote:
> > >
> > > From: Abner Chang 
> > >
> > > Add PCD to disable ETag capability for the case Redfish
> > > service doesn't support ETag.
> > >
> > > Signed-off-by: Abner Chang 
> > > Cc: Nickle Wang 
> > > Cc: Igor Kulchytskyy 
> > > Cc: Mike Maslenkin 
> > > ---
> > >  RedfishClientPkg/RedfishClientPkg.dec |   2 +
> > >  .../RedfishFeatureUtilityLib.inf  |   1 +
> > >  .../Library/RedfishFeatureUtilityLib.h|  46 +++-
> > >  .../Features/Bios/v1_0_9/Dxe/BiosDxe.c|  18 +-
> > >  .../v1_0_4/Common/BootOptionCommon.c  |   4 +-
> > >  .../BootOption/v1_0_4/Dxe/BootOptionDxe.c |  16 +-
> > >  .../v1_5_0/Dxe/ComputerSystemDxe.c|  16 +-
> > >  .../Features/Memory/V1_7_1/Dxe/MemoryDxe.c|  16 +-
> > >  .../RedfishFeatureUtilityLib.c| 208 --
> > >  9 files changed, 197 insertions(+), 130 deletions(-)
> > >
> > > diff --git a/RedfishClientPkg/RedfishClientPkg.dec
> > b/RedfishClientPkg/RedfishClientPkg.dec
> > > index b350facae0..8adef327fb 100644
> > > --- a/RedfishClientPkg/RedfishClientPkg.dec
> > > +++ b/RedfishClientPkg/RedfishClientPkg.dec
> > > @@ -76,6 +76,8 @@
> > >
> > gEfiRedfishClientPkgTokenSpaceGuid.PcdDefaultRedfishVersion|L"v1"|VOID*
> > |0x1004
> > >## The number of seconds that the firmware will wait before system 
> > > reboot
> > >
> > gEfiRedfishClientPkgTokenSpaceGuid.PcdRedfishSystemRebootTimeout|5|UI
> > NT16|0x2002
> > > +  ## Default capability of Redfish service side ETAG support
> > > +
> > gEfiRedfishClientPkgTokenSpaceGuid.PcdRedfishServiceEtagSupported|TRUE|
> > BOOLEAN|0x1005
> > >
> > >  [PcdsDynamicEx]
> > >## The flag used to indicate that system reboot is required due to 
> > > system
> > configuration change
> > > diff --git
> > a/RedfishClientPkg/Library/RedfishFeatureUtilityLib/RedfishFeatureUtilityLib.i
> > nf
> > b/RedfishClientPkg/Library/RedfishFeatureUtilityLib/RedfishFeatureUtilityLib.i
> > nf
> > > index 718273b248..fde6a176d0 100644
> > > ---
> > a/RedfishClientPkg/Library/RedfishFeatureUtilityLib/RedfishFeatureUtilityLib.i
> > nf
> > > +++
> > b/RedfishClientPkg/Library/RedfishFeatureUtilityLib/RedfishFeatureUtilityLib.i
> > nf
> > > @@ -54,6 +54,7 @@
> > >
> > >  [Pcd]
> > >gEfiRedfishClientPkgTokenSpaceGuid.PcdRedfishSystemRebootRequired
> > > +  gEfiRedfishClientPkgTokenSpaceGuid.PcdRedfishServiceEtagSupported
> > >
> > >  [Guids]
> > >
> > > diff --git a/RedfishClientPkg/Include/Library/RedfishFeatureUtilityLib.h
> > b/RedfishClientPkg/Include/Library/RedfishFeatureUtilityLib.h
> > > index 9513a65617..834ea0fcfe 100644
> > > --- a/RedfishClientPkg/Include/Library/RedfishFeatureUtilityLib.h
> > > +++ b/RedfishClientPkg/Include/Library/RedfishFeatureUtilityLib.h
> > > @@ -81,7 +81,7 @@ CopyConfiglanguageList (
> > >
> > >  /**
> > >
> > > -  Get number of node from the string. Node is seperated by '/'.
> > > +  Get number of node from the string. Node is separated by '/'.
> > >
> > >@param[in]  NodeString The node string to parse.
> > 

Re: [edk2-devel] [PATCH v3 3/3] ArmPkg: Disable watchdog interaction after exiting boot services

[Sami Mujawar]

Hi Rebecca,

Thank you for this patch. 
Please see my feedback inline marked [SAMI].

Regards,

Sami Mujawar

On 05/01/2024, 05:15, "Rebecca Cran" mailto:rebe...@os.amperecomputing.com>> wrote:


Update GenericWatchdogDxe to disable watchdog interaction after exiting
boot services. Also, move the mEfiExitBootServicesEvent event to the top
of the file with the other static variables.


Signed-off-by: Rebecca Cran mailto:rebe...@os.amperecomputing.com>>
---
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)


diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c 
b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
index 78cee62a19d6..ddf131660f9d 100644
--- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
+++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
@@ -33,10 +33,14 @@
It is therefore stored here. 0 means the timer is not running. */
STATIC UINT64 mTimerPeriod = 0;


+/* disables watchdog interaction after Exit Boot Services */
+STATIC BOOLEAN mExitedBootServices = FALSE;
+
#define MAX_UINT48 0xULL


STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol;
STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;
+STATIC EFI_EVENT mEfiExitBootServicesEvent;


STATIC
VOID
@@ -200,7 +204,13 @@ WatchdogSetTimerPeriod (
UINT64 TimerFrequencyHz;
UINT64 NumTimerTicks;


- // if TimerPeriod is 0, this is a request to stop the watchdog.
+ // If we've exited Boot Services but TimerPeriod isn't zero, this
+ // indicates that the caller is doing something wrong.
+ if (mExitedBootServices && (TimerPeriod != 0)) {
[SAMI] Thanks for updating the code to return the error code. 
However, I see you are not stopping the watchdog timer. Is this because you 
expect the watchdog period to expire and reset the system? 
Also, did you see an issue that motivated this patch, or this was just a case 
of hardening the code?
Can you provide more information, please?
[/SAMI]
+ return EFI_DEVICE_ERROR;
+ }
+
+ // If TimerPeriod is 0 this is a request to stop the watchdog.
if (TimerPeriod == 0) {
mTimerPeriod = 0;
WatchdogDisable ();
@@ -304,8 +314,6 @@ STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = {
WatchdogGetTimerPeriod
};


-STATIC EFI_EVENT mEfiExitBootServicesEvent;
-
EFI_STATUS
EFIAPI
GenericWatchdogEntry (
-- 
2.34.1







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Re: [edk2-devel] [PATCH v3 2/3] ArmPkg: Introduce global mTimerPeriod and remove calculation

[Sami Mujawar]

Hi Rebecca,

I have a minor suggestion marked inline as [SAMI], otherwise this patch looks 
good to me.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar

On 05/01/2024, 05:15, "Rebecca Cran" mailto:rebe...@os.amperecomputing.com>> wrote:


The calculation of the timer period was broken. Introduce a global
mTimerPeriod so the calculation can be removed. Since mTimerFrequencyHz
is only used in one place, remove the global and make it a local
variable. Do the same with mNumTimerTicks.


Signed-off-by: Rebecca Cran mailto:rebe...@os.amperecomputing.com>>
---
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 36 
++
1 file changed, 17 insertions(+), 19 deletions(-)


diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c 
b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
index f8c39458a53a..78cee62a19d6 100644
--- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
+++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
@@ -28,13 +28,10 @@
in a second */
#define TIME_UNITS_PER_SECOND 1000


-// Tick frequency of the generic timer basis of the generic watchdog.
-STATIC UINTN mTimerFrequencyHz = 0;
-
/* In cases where the compare register was set manually, information about
how long the watchdog was asked to wait cannot be retrieved from hardware.
It is therefore stored here. 0 means the timer is not running. */
-STATIC UINT64 mNumTimerTicks = 0;
+STATIC UINT64 mTimerPeriod = 0;


#define MAX_UINT48 0xULL


@@ -91,7 +88,8 @@ WatchdogExitBootServicesEvent (
)
{
WatchdogDisable ();
- mNumTimerTicks = 0;
+ mTimerPeriod = 0;
+ mExitedBootServices = TRUE;
}


/* This function is called when the watchdog's first signal (WS0) goes high.
@@ -106,7 +104,6 @@ WatchdogInterruptHandler (
)
{
STATIC CONST CHAR16 ResetString[] = L"The generic watchdog timer ran out.";
- UINT64 TimerPeriod;


WatchdogDisable ();


@@ -119,8 +116,7 @@ WatchdogInterruptHandler (
// the timer period plus 1.
//
if (mWatchdogNotify != NULL) {
- TimerPeriod = ((TIME_UNITS_PER_SECOND / mTimerFrequencyHz) * mNumTimerTicks);
- mWatchdogNotify (TimerPeriod + 1);
+ mWatchdogNotify (mTimerPeriod + 1);
}


gRT->ResetSystem (
@@ -200,22 +196,27 @@ WatchdogSetTimerPeriod (
IN UINT64 TimerPeriod // In 100ns units
)
{
- UINTN SystemCount;
+ UINTN SystemCount;
+ UINT64 TimerFrequencyHz;
+ UINT64 NumTimerTicks;


// if TimerPeriod is 0, this is a request to stop the watchdog.
if (TimerPeriod == 0) {
- mNumTimerTicks = 0;
+ mTimerPeriod = 0;
WatchdogDisable ();
return EFI_SUCCESS;
}


// Work out how many timer ticks will equate to TimerPeriod
- mNumTimerTicks = (mTimerFrequencyHz * TimerPeriod) / TIME_UNITS_PER_SECOND;
+ TimerFrequencyHz = ArmGenericTimerGetTimerFreq ();
+ ASSERT (TimerFrequencyHz != 0);
+ mTimerPeriod = TimerPeriod;
+ NumTimerTicks = (TimerFrequencyHz * TimerPeriod) / TIME_UNITS_PER_SECOND;


/* If the number of required ticks is greater than the max the watchdog's
offset register (WOR) can hold, we need to manually compute and set
the compare register (WCV) */
- if (mNumTimerTicks > MAX_UINT48) {
+ if (NumTimerTicks > MAX_UINT48) {
/* We need to enable the watchdog *before* writing to the compare register,
because enabling the watchdog causes an "explicit refresh", which
clobbers the compare register (WCV). In order to make sure this doesn't
@@ -223,9 +224,9 @@ WatchdogSetTimerPeriod (
WatchdogWriteOffsetRegister (MAX_UINT48);
WatchdogEnable ();
SystemCount = ArmGenericTimerGetSystemCount ();
- WatchdogWriteCompareRegister (SystemCount + mNumTimerTicks);
+ WatchdogWriteCompareRegister (SystemCount + NumTimerTicks);
} else {
- WatchdogWriteOffsetRegister (mNumTimerTicks);
+ WatchdogWriteOffsetRegister (NumTimerTicks);
WatchdogEnable ();
}


@@ -260,7 +261,7 @@ WatchdogGetTimerPeriod (
return EFI_INVALID_PARAMETER;
}


- *TimerPeriod = ((TIME_UNITS_PER_SECOND / mTimerFrequencyHz) * mNumTimerTicks);
+ *TimerPeriod = mTimerPeriod;


return EFI_SUCCESS;
}
@@ -327,9 +328,6 @@ GenericWatchdogEntry (
This will avoid conflicts with the universal watchdog */
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, );


- mTimerFrequencyHz = ArmGenericTimerGetTimerFreq ();
- ASSERT (mTimerFrequencyHz != 0);
-
// Install interrupt handler
Status = mInterruptProtocol->RegisterInterruptSource (
mInterruptProtocol,
@@ -371,7 +369,7 @@ GenericWatchdogEntry (
);
ASSERT_EFI_ERROR (Status);


- mNumTimerTicks = 0;
+ mTimerPeriod = 0;
[SAMI] I think we do not need to initialise mTimerPeriod to 0 here as it would 
already be 0, right?
WatchdogDisable ();


return EFI_SUCCESS;
-- 
2.34.1







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Re: [edk2-devel] [PATCH v3 1/3] ArmPkg: Update GenericWatchdogDxe to allow setting full 48-bit offset

[Sami Mujawar]

Hi Rebecca,

Thank you for the updated patch.

Please find my feedback inline marked [SAMI].

Regards,

Sami Mujawar

On 05/01/2024, 05:15, "Rebecca Cran" mailto:rebe...@os.amperecomputing.com>> wrote:


The generic watchdog offset register is 48 bits wide, and can be set by
performing two 32-bit writes.


Add support for writing the high 16 bits of the offset register and
update the signature of the WatchdogWriteOffsetRegister function to take
a UINT64 value.


Signed-off-by: Rebecca Cran mailto:rebe...@os.amperecomputing.com>>
---
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h | 6 +-
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 14 +-
2 files changed, 14 insertions(+), 6 deletions(-)


diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h 
b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h
index 9bc3bf47047c..2a0634e7e9f1 100644
--- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h
+++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h
@@ -1,9 +1,12 @@
/** @file
*
+* Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
* Copyright (c) 2013-2017, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
+* See Generic Watchdog specification in Arm Base System Architecture 1.0C:
+* https://developer.arm.com/documentation/den0094/c/ 

[SAMI] Minor. I think this should be changed to use the @par Reference(s):
e.g.
* @par Reference(s):
*  - Generic Watchdog specification in Arm Base System Architecture 1.0C:
*  https://developer.arm.com/documentation/den0094/c/
[/SAMI]
**/


#ifndef GENERIC_WATCHDOG_H_
@@ -14,7 +17,8 @@


// Control Frame:
#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 
(PcdGenericWatchdogControlBase) + 0x000)
-#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 
(PcdGenericWatchdogControlBase) + 0x008)
+#define GENERIC_WDOG_OFFSET_REG_LOW ((UINTN)FixedPcdGet64 
(PcdGenericWatchdogControlBase) + 0x008)
+#define GENERIC_WDOG_OFFSET_REG_HIGH ((UINTN)FixedPcdGet64 
(PcdGenericWatchdogControlBase) + 0x00C)
#define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 
(PcdGenericWatchdogControlBase) + 0x010)
#define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 
(PcdGenericWatchdogControlBase) + 0x014)


diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c 
b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
index 66c6c37c08b0..f8c39458a53a 100644
--- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
+++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
@@ -1,5 +1,6 @@
/** @file
*
+* Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
* Copyright (c) 2013-2018, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -35,16 +36,19 @@ STATIC UINTN mTimerFrequencyHz = 0;
It is therefore stored here. 0 means the timer is not running. */
STATIC UINT64 mNumTimerTicks = 0;


+#define MAX_UINT48 0xULL
+
STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol;
STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;


STATIC
VOID
WatchdogWriteOffsetRegister (
- UINT32 Value
+ UINT64 Value
)
{
- MmioWrite32 (GENERIC_WDOG_OFFSET_REG, Value);
+ MmioWrite32 (GENERIC_WDOG_OFFSET_REG_LOW, Value & MAX_UINT32);
+ MmioWrite32 (GENERIC_WDOG_OFFSET_REG_HIGH, (Value >> 32) & MAX_UINT16);
[SAMI] Apologies for not catching this in my earlier review, but I think you 
need to read W_IIDR and only write to the GENERIC_WDOG_OFFSET_REG_HIGH register 
if the watchdog revision is == 1. Otherwise, this may cause undesirable results 
on systems that implement watchdog timer revision 0.
}


STATIC
@@ -211,17 +215,17 @@ WatchdogSetTimerPeriod (
/* If the number of required ticks is greater than the max the watchdog's
offset register (WOR) can hold, we need to manually compute and set
the compare register (WCV) */
- if (mNumTimerTicks > MAX_UINT32) {
+ if (mNumTimerTicks > MAX_UINT48) {
/* We need to enable the watchdog *before* writing to the compare register,
because enabling the watchdog causes an "explicit refresh", which
clobbers the compare register (WCV). In order to make sure this doesn't
trigger an interrupt, set the offset to max. */
- WatchdogWriteOffsetRegister (MAX_UINT32);
+ WatchdogWriteOffsetRegister (MAX_UINT48);
WatchdogEnable ();
SystemCount = ArmGenericTimerGetSystemCount ();
WatchdogWriteCompareRegister (SystemCount + mNumTimerTicks);
} else {
- WatchdogWriteOffsetRegister ((UINT32)mNumTimerTicks);
+ WatchdogWriteOffsetRegister (mNumTimerTicks);
WatchdogEnable ();
}


-- 
2.34.1







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Re: [edk2-devel] [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default

[Ashish Singhal via groups.io]

I do not recommend doing that. Setting policy via SetData does enough to wipe 
out any previous manual configuration and that is the goal for reset to default.

From: Kasbekar, Saloni 
Sent: Friday, January 5, 2024 2:30 AM
To: Ashish Singhal ; devel@edk2.groups.io 
; Clark-williams, Zachary 
; Jeff Brasen 
Subject: RE: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default

External email: Use caution opening links or attachments


Makes sense. Should we also set IfrNvData->DhcpEnable = TRUE when updating the 
Policy then?



From: Ashish Singhal 
Sent: Wednesday, January 3, 2024 8:52 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io; 
Clark-williams, Zachary ; Jeff Brasen 

Subject: Re: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



Hello Saloni,



Thanks for the feedback. After the reset, or when we disable configure from 
menu, GetData returns policy to static as the enum value is 0. However, setting 
value as static does not have any benefit as it forces to reuse the old network 
settings. Using DHCP really mimics the reset behavior that we see without any 
configuration done manually.



Thanks

Ashish





From: Kasbekar, Saloni 
mailto:saloni.kasbe...@intel.com>>
Sent: Tuesday, January 2, 2024 1:47 PM
To: Ashish Singhal mailto:ashishsin...@nvidia.com>>; 
devel@edk2.groups.io 
mailto:devel@edk2.groups.io>>; Clark-williams, Zachary 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Subject: RE: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



External email: Use caution opening links or attachments



Hi Ashish,



+Ip4NvData->Policy = Ip4Config2PolicyDhcp;

+Status= Ip4Cfg2->SetData (

+   Ip4Cfg2,

+   Ip4Config2DataTypePolicy,

+   sizeof (EFI_IP4_CONFIG2_POLICY),

+   >Policy

+   );



Here we’re assuming IfrFormNvData->DhcpEnable is TRUE. Should we check it 
before setting the policy and calling SetData()?



Thanks,

Saloni





From: Ashish Singhal mailto:ashishsin...@nvidia.com>>
Sent: Monday, January 1, 2024 8:48 AM
To: devel@edk2.groups.io; Kasbekar, Saloni 
mailto:saloni.kasbe...@intel.com>>; Clark-williams, 
Zachary 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Subject: Re: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



Hello,



Checking again for some feedback on this.



Thanks

Ashish





From: Ashish Singhal mailto:ashishsin...@nvidia.com>>
Sent: Thursday, December 14, 2023 4:42 PM
To: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>>; 
saloni.kasbe...@intel.com 
mailto:saloni.kasbe...@intel.com>>; 
zachary.clark-willi...@intel.com 
mailto:zachary.clark-willi...@intel.com>>; 
Jeff Brasen mailto:jbra...@nvidia.com>>
Cc: Ashish Singhal mailto:ashishsin...@nvidia.com>>
Subject: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To Default



Exercising reset to default does not reset the settings.
Add handler code for the case where configuration is
disabled.

Signed-off-by: Ashish Singhal 
mailto:ashishsin...@nvidia.com>>
---
 NetworkPkg/Ip4Dxe/Ip4Config2Nv.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/NetworkPkg/Ip4Dxe/Ip4Config2Nv.c b/NetworkPkg/Ip4Dxe/Ip4Config2Nv.c
index e0b6a4d4a9..dac5817b7c 100644
--- a/NetworkPkg/Ip4Dxe/Ip4Config2Nv.c
+++ b/NetworkPkg/Ip4Dxe/Ip4Config2Nv.c
@@ -586,6 +586,31 @@ Ip4Config2ConvertIfrNvDataToConfigNvData (
   }

   if (IfrFormNvData->Configure != TRUE) {
+if (Ip4NvData->DnsAddress != NULL) {
+  FreePool (Ip4NvData->DnsAddress);
+  Ip4NvData->DnsAddress  = NULL;
+  Ip4NvData->DnsAddressCount = 0;
+}
+
+if (Ip4NvData->GatewayAddress != NULL) {
+  FreePool (Ip4NvData->GatewayAddress);
+  Ip4NvData->GatewayAddress  = NULL;
+  Ip4NvData->GatewayAddressCount = 0;
+}
+
+if (Ip4NvData->ManualAddress != NULL) {
+  FreePool (Ip4NvData->ManualAddress);
+  Ip4NvData->ManualAddress  = NULL;
+  Ip4NvData->ManualAddressCount = 0;
+}
+
+Ip4NvData->Policy = Ip4Config2PolicyDhcp;
+Status= Ip4Cfg2->SetData (
+   Ip4Cfg2,
+   Ip4Config2DataTypePolicy,
+   sizeof (EFI_IP4_CONFIG2_POLICY),
+   >Policy
+   );
 return EFI_SUCCESS;
   }

--
2.17.1

Hello,

Hello Saloni,


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[edk2-devel] [PATCH v6 36/36] OvmfPkg/LoongArchVirt: Add self introduction file

[Chao Li]

Add self introduction file for LoongArch virtual machine.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
---
 OvmfPkg/LoongArchVirt/Readme.md | 67 +
 1 file changed, 67 insertions(+)
 create mode 100644 OvmfPkg/LoongArchVirt/Readme.md

diff --git a/OvmfPkg/LoongArchVirt/Readme.md b/OvmfPkg/LoongArchVirt/Readme.md
new file mode 100644
index 00..57fc74c296
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Readme.md
@@ -0,0 +1,67 @@
+# LoongArch QEMU virt platform
+
+## Overview
+
+  LoongArch QEMU virt is a generic platform that dose not require any actual 
hardware.
+  The minimum required QEMU version is 
[8.1](https://gitlab.com/qemu-project/qemu/-/tags), the minimum required GCC 
version is [GCC13](https://gcc.gnu.org/gcc-13/), the minimum required Binutils 
version is [2.40](https://ftp.gnu.org/gnu/binutils/).
+
+## Prepare (X86 Linux Environment)
+
+### Fedora39
+Install LoongArch64 cross compiler, LoongArch system QEMU.
+
+yum install gcc-loongarch64-linux-gnu
+yum install qemu-system-loongarch64
+
+### Others X86 OS ENV
+ Configure cross-tools
+
+**Download:**
+
+wget 
https://github.com/loongson/build-tools/releases/download/2023.08.08/x86_64-cross-tools-loongarch64-binutils_2.41-gcc_13.2.0.tar.xz
+
+**Configure the cross-tools environment:**
+
+mkdir /opt/loongarch64_cross-toolchain/
+tar -vxf x86_64-cross-tools-loongarch64-binutils_2.41-gcc_13.2.0.tar.xz -C 
/opt/loongarch64_cross-toolchain/
+export PATH=/opt/loongarch64_cross-toolchain/cross-tools/bin:$PATH
+
+Note: Please obtain [the latest 
cross-compilation](https://github.com/loongson/build-tools) toolchains.
+
+ Build QEMU
+
+git clone https://gitlab.com/qemu-project/qemu.git
+
+Note: Please refer to QEMU compilation rules, located in 
qemu/doc/system/loongarch/virt.rst.
+
+
+## Build LoongArch QEMU virtual machine firmware
+ Get edk2 resouces
+
+git clone --recurse-submodule https://github.com/tianocore/edk2.git
+
+ Building LoongArch QEMU virt FW with GCC
+
+export WORKSPACE=`pwd`
+export GCC5_LOONGARCH64_PREFIX=loongarch64-unknown-linux-gnu-
+export PACKAGES_PATH=$WORKSPACE/edk2
+export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools
+source edk2/edksetup.sh --reconfig
+make -C edk2/BaseTools
+source edk2/edksetup.sh BaseTools
+build -b RELEASE -t GCC5 -a LOONGARCH64 -p 
OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc
+
+## Test LoongArch QEMU virtual machine firmware
+qemu-system-loongarch64 \
+-m 4G \
+-M virt \
+-smp 2 \
+-cpu la464 \
+-bios Build/LoongArchVirtQemu/RELEASE_GCC5/FV/QEMU_EFI.fd \
+-serial stdio
+
+## Test LoongArch QEMU virtual machine OS
+
+* Download ArchLinux QCOW 
[images](https://mirrors.pku.edu.cn/loongarch/archlinux/images) for LoongArch.
+
+* [Running LoongArch ArchLinux on virtual 
machine](https://mirrors.pku.edu.cn/loongarch/archlinux/images/README.html).
-- 
2.27.0



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[edk2-devel] [PATCH v6 35/36] OvmfPkg/LoongArchVirt: Add build file

[Chao Li]

Add infrastructure files to build edk2 for LoongArch QEMU virtual
machine.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
---
 OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc |  34 +
 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc | 679 
 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.fdf | 313 +
 OvmfPkg/LoongArchVirt/VarStore.fdf.inc  |  67 ++
 4 files changed, 1093 insertions(+)
 create mode 100644 OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc
 create mode 100644 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc
 create mode 100644 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.fdf
 create mode 100644 OvmfPkg/LoongArchVirt/VarStore.fdf.inc

diff --git a/OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc 
b/OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc
new file mode 100644
index 00..22373bec6a
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc
@@ -0,0 +1,34 @@
+## @file
+#
+#  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+DEFINE BLOCK_SIZE = 0x1000
+
+
+# FW total
+DEFINE FW_BASE_ADDRESS= 0x1c00
+DEFINE FW_BLOCKS  = 0x400
+DEFINE FW_SIZE= 0x40
+
+
+#Flash code layout
+#Set Sec size in flash
+DEFINE SECFV_SIZE = 0x0001
+
+#Set Pei size in flash
+DEFINE PEIFV_SIZE = 0x0004
+
+#Set Dxe size in flash
+DEFINE DXEFV_SIZE = 0x0035
+
+#Set FVMAIN size
+DEFINE FVMAIN_SIZE= $(SECFV_SIZE) + $(PEIFV_SIZE) 
+$(DXEFV_SIZE)
+
+#Set Memory layout
+DEFINE SEC_PEI_TEMP_RAM_BASE  = 0x1
+DEFINE SEC_PEI_TEMP_RAM_SIZE  = 0x8
+DEFINE DEVICE_TREE_RAM_BASE   = 0x10
diff --git a/OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc 
b/OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc
new file mode 100644
index 00..0a6b5f830b
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc
@@ -0,0 +1,679 @@
+## @file
+#
+#  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+###
+[Defines]
+  PLATFORM_NAME  = LoongArchVirtQemu
+  PLATFORMPKG_NAME   = LoongArchVirtQemu
+  PLATFORM_GUID  = 7926ea52-b0dc-4ee8-ac63-341eebd84ed4
+  PLATFORM_VERSION   = 0.1
+  DSC_SPECIFICATION  = 0x00010005
+  OUTPUT_DIRECTORY   = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES= LOONGARCH64
+  BUILD_TARGETS  = DEBUG|RELEASE
+  SKUID_IDENTIFIER   = DEFAULT
+  FLASH_DEFINITION   = OvmfPkg/LoongArchVirt/LoongArchVirtQemu.fdf
+  TTY_TERMINAL   = FALSE
+
+!include LoongArchVirt.fdf.inc
+
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  DEFINE TTY_TERMINAL= FALSE
+  DEFINE SECURE_BOOT_ENABLE  = FALSE
+  DEFINE TPM2_ENABLE = FALSE
+  DEFINE TPM2_CONFIG_ENABLE  = FALSE
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_IP6_ENABLE  = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE= FALSE
+  DEFINE NETWORK_SNP_ENABLE  = FALSE
+  DEFINE NETWORK_TLS_ENABLE  = FALSE
+  DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS  = TRUE
+  DEFINE NETWORK_ISCSI_ENABLE= FALSE
+
+!include NetworkPkg/NetworkDefines.dsc.inc
+
+#
+# Defines for default states.  These can be changed on the command line.
+# -D FLAG=VALUE
+
+[BuildOptions]
+  GCC:RELEASE_*_*_CC_FLAGS   = -DSPEEDUP
+
+  #
+  # Disable deprecated APIs.
+  #
+  GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
+
+!include NetworkPkg/NetworkBuildOptions.dsc.inc
+
+[BuildOptions.LOONGARCH64.EDKII.SEC]
+  *_*_*_CC_FLAGS =
+
+#
+# Default page size is 16K for loongarch qemu tcg
+# code section separated with data section with 16K page alignment, else data
+# write operation in the same page with code section will cause qemu TB flush.
+#
+[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x4000

[edk2-devel] [PATCH v6 34/36] OvmfPkg/LoongArchVirt: Support PEI phase

[Chao Li]

Platfrom PEI module for LoongArch platfrom initialization.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
Reviewed-by: Bibo Mao 
---
 OvmfPkg/LoongArchVirt/PlatformPei/Fv.c|  39 ++
 OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c | 201 +
 OvmfPkg/LoongArchVirt/PlatformPei/Platform.c  | 393 ++
 OvmfPkg/LoongArchVirt/PlatformPei/Platform.h  | 146 +++
 .../LoongArchVirt/PlatformPei/PlatformPei.inf |  72 
 5 files changed, 851 insertions(+)
 create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/Fv.c
 create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c
 create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/Platform.c
 create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/Platform.h
 create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/PlatformPei.inf

diff --git a/OvmfPkg/LoongArchVirt/PlatformPei/Fv.c 
b/OvmfPkg/LoongArchVirt/PlatformPei/Fv.c
new file mode 100644
index 00..d46326f135
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/PlatformPei/Fv.c
@@ -0,0 +1,39 @@
+/** @file
+  Build FV related hobs for platform.
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include "Platform.h"
+
+/**
+  Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+  and DXE know about them.
+
+  @retval EFI_SUCCESS   Platform PEI FVs were initialized successfully.
+**/
+EFI_STATUS
+PeiFvInitialization (
+  VOID
+  )
+{
+  DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
+
+  //
+  // Create a memory allocation HOB for the PEI FV.
+  //
+  BuildMemoryAllocationHob (
+FixedPcdGet64 (PcdOvmfSecPeiTempRamBase),
+FixedPcdGet32 (PcdOvmfSecPeiTempRamSize),
+EfiBootServicesData
+);
+
+  return EFI_SUCCESS;
+}
diff --git a/OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c 
b/OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c
new file mode 100644
index 00..9c90413524
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c
@@ -0,0 +1,201 @@
+/** @file
+  Memory Detection for Virtual Machines.
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "Platform.h"
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS  (128)
+#define LOONGARCH_FW_RAM_TOPBASE_256MB
+
+/**
+  Publish PEI core memory
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+**/
+EFI_STATUS
+PublishPeiMemory (
+  VOID
+  )
+{
+  EFI_STATUS  Status;
+  UINT64  Base;
+  UINT64  Size;
+  UINT64  RamTop;
+
+  //
+  // Determine the range of memory to use during PEI
+  //
+  Base   = FixedPcdGet64 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 
(PcdOvmfSecPeiTempRamSize);
+  RamTop = LOONGARCH_FW_RAM_TOP;
+  Size   = RamTop - Base;
+
+  //
+  // Publish this memory to the PEI Core
+  //
+  Status = PublishSystemMemory (Base, Size);
+  ASSERT_EFI_ERROR (Status);
+
+  DEBUG ((DEBUG_INFO, "Publish Memory Initialize done.\n"));
+  return Status;
+}
+
+/**
+  Peform Memory Detection
+  Publish system RAM and reserve memory regions
+**/
+VOID
+InitializeRamRegions (
+  VOID
+  )
+{
+  EFI_STATUSStatus;
+  FIRMWARE_CONFIG_ITEM  FwCfgItem;
+  UINTN FwCfgSize;
+  MEMMAP_ENTRY  MemoryMapEntry;
+  MEMMAP_ENTRY  *StartEntry;
+  MEMMAP_ENTRY  *pEntry;
+  UINTN Processed;
+
+  Status = QemuFwCfgFindFile ("etc/memmap", , );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/memmap error Status %d \n", __func__, 
__LINE__, Status));
+return;
+  }
+
+  if (FwCfgSize % sizeof MemoryMapEntry != 0) {
+DEBUG ((DEBUG_ERROR, "no MemoryMapEntry FwCfgSize:%d\n", FwCfgSize));
+return;
+  }
+
+  QemuFwCfgSelectItem (FwCfgItem);
+  StartEntry = AllocatePages (EFI_SIZE_TO_PAGES (FwCfgSize));
+  QemuFwCfgReadBytes (FwCfgSize, StartEntry);
+  for (Processed = 0; Processed < (FwCfgSize / sizeof MemoryMapEntry); 
Processed++) {
+pEntry = StartEntry + Processed;
+if (pEntry->Length == 0) {
+  continue;
+}
+
+DEBUG ((DEBUG_INFO, "MemmapEntry Base %p length %p  type %d\n", 
pEntry->BaseAddr, pEntry->Length, pEntry->Type));
+if (pEntry->Type != EfiAcpiAddressRangeMemory) {
+  continue;
+}
+
+AddMemoryRangeHob (pEntry->BaseAddr, pEntry->BaseAddr + pEntry->Length);
+  }
+
+  //
+  // When 0 address protection is enabled,
+  // 0-4k memory needs to be preallocated to prevent UEFI 

[edk2-devel] [PATCH v6 33/36] OvmfPkg/LoongArchVirt: Support SEC phase

[Chao Li]

Add SEC code for LoongArch virtual machine.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
---
 OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S | 180 +++
 OvmfPkg/LoongArchVirt/Sec/SecMain.c   | 507 ++
 OvmfPkg/LoongArchVirt/Sec/SecMain.inf |  53 ++
 3 files changed, 740 insertions(+)
 create mode 100644 OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S
 create mode 100644 OvmfPkg/LoongArchVirt/Sec/SecMain.c
 create mode 100644 OvmfPkg/LoongArchVirt/Sec/SecMain.inf

diff --git a/OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S 
b/OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S
new file mode 100644
index 00..ed099ba0fc
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S
@@ -0,0 +1,180 @@
+#--
+#
+# Start for Loongson LoongArch processor
+#
+# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#  @par Glossary:
+#- CSR - CPU Status Register
+#- EBASE - Exception Base Address
+#--
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include 
+#include 
+#include 
+
+#define BOOTCORE_ID  0
+//
+// For coding convenience, define the maximum valid
+// LoongArch exception.
+// Since UEFI V2.11, it will be present in DebugSupport.h.
+//
+#define MAX_LOONGARCH_EXCEPTION  64
+
+ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+  /* Disable interrupt */
+  li.d $t0, (1 << 2)
+  csrxchg  $zero, $t0, LOONGARCH_CSR_CRMD
+
+  /* Read physical cpu number id */
+  bl   GetApicId
+  li.d $t0, BOOTCORE_ID  //0
+  bne  $a0, $t0, SlaveMain
+
+  /* Set BSP stack */
+  li.d $t0, FixedPcdGet64(PcdOvmfSecPeiTempRamBase) + 
FixedPcdGet32(PcdOvmfSecPeiTempRamSize)  # stack base
+  move $sp, $t0
+  addi.d   $sp, $sp, -0x8
+
+  /* Load the exception vector base address */
+  li.d $s0, FixedPcdGet64(PcdCpuExceptionVectorBaseAddress)
+
+  /* Construct SEC and PEI step exception environment */
+  la.pcrel $a1, ExceptionEntryStart
+  la.pcrel $t0, ExceptionEntryEnd
+  sub.d$a2, $t0, $a1
+  li.w $t0, (MAX_LOONGARCH_EXCEPTION +  MAX_LOONGARCH_INTERRUPT) * 512
+  bgeu $a2, $t0, DeadLoop
+  move $a0, $s0
+  bl   CopyMem
+
+  /* Configure BSP reset ebase */
+  move $a0, $s0
+  bl   SetExceptionBaseAddress
+
+CallEntry:
+  /* Call C function make sure parameter true */
+  li.d $a0, FixedPcdGet64(PcdOvmfFdBaseAddress) # FW base
+  addi.d   $a1, $sp, 0x8
+  bl   SecCoreStartupWithStack
+# End of _ModuleEntryPoint
+
+ASM_PFX(ClearMailBox):
+  /* Clear mailbox */
+  li.d  $t1, LOONGARCH_IOCSR_MBUF3
+  iocsrwr.d $zero, $t1
+  li.d  $t1, LOONGARCH_IOCSR_MBUF2
+  iocsrwr.d $zero, $t1
+  li.d  $t1, LOONGARCH_IOCSR_MBUF1
+  iocsrwr.d $zero, $t1
+  li.d  $t1, LOONGARCH_IOCSR_MBUF0
+  iocsrwr.d $zero, $t1
+  jirl  $zero, $ra, 0
+# End of ClearMailBox
+
+ASM_PFX(EnableIPI):
+  /* Enable IPI interrupt */
+  li.d  $t1, (1 << 12)
+  csrxchg   $t1, $t1, LOONGARCH_CSR_ECFG
+
+  addi.d$t2, $zero, -1
+  li.d  $t1, LOONGARCH_IOCSR_IPI_EN
+  iocsrwr.w $t2, $t1
+  jirl  $zero, $ra, 0
+# End of EeableIPI
+
+#/**
+#   Get APIC ID for every CPU.
+#
+#   @param   NULL
+#   @return  APICID
+#
+#   UINTN
+#   EFI_API
+#   GetApicId (
+# VOID
+# )
+#**/
+ASM_PFX(GetApicId):
+  csrrd $a0, LOONGARCH_CSR_CPUNUM
+  andi  $a0, $a0, 0x3ff
+  jirl  $zero, $ra, 0
+# End of GetApicId
+
+ASM_PFX(ApInitStack):
+  li.d   $t1, SIZE_1KB
+  csrrd  $t0, LOONGARCH_CSR_TMID
+  mul.d  $t1, $t0, $t1
+  li.d   $t2, FixedPcdGet32(PcdCpuMaxLogicalProcessorNumber)
+  bgeu   $t0, $t2, DeadLoop
+  li.d   $t0, FixedPcdGet64(PcdOvmfSecPeiTempRamBase) + 
FixedPcdGet32(PcdOvmfSecPeiTempRamSize) - SIZE_64KB
+  sub.d  $sp, $t0, $t1
+  addi.d $sp, $sp, -0x8
+  jirl   $zero, $ra, 0
+# End of ApInitStack
+
+ASM_PFX(SlaveMain):
+  /* Set AP exception handle in flash */
+  la.pcrel  $a0, ApException
+  blSetExceptionBaseAddress
+
+  /* Clean up local mail box and open INT */
+  blClearMailBox
+  blEnableIPI
+  blEnableInterrupts
+
+WaitForWake:
+  /* Wait for wakeup */
+  blCpuSleep
+  b WaitForWake
+# End of SlaveMain
+
+.align 12
+ASM_PFX(ApException):
+  csrrd $t0, LOONGARCH_CSR_ESTAT
+  srli.d$t0, $t0, 12
+  beqz  $t0, DeadLoop
+
+  li.d  $t0, LOONGARCH_IOCSR_IPI_STATUS
+  iocsrrd.w $t1, $t0
+  li.d  $t0, LOONGARCH_IOCSR_IPI_CLEAR
+  iocsrwr.w $t1, $t0
+
+  /* Read mail buf and jump to specified entry */
+  li.d  $t1, LOONGARCH_IOCSR_MBUF0
+  iocsrrd.d $t0, $t1
+  beqz  $t0, OutOfException
+  csrwr $t0, 

[edk2-devel] [PATCH v6 32/36] OvmfPkg/LoongArchVirt: Add reset system library

[Chao Li]

This library provides interface related to restart and shudown the
LoongArch64 virtual machine.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
Reviewed-by: Bibo Mao 
---
 .../BaseResetSystemAcpiGed.c  | 148 ++
 .../BaseResetSystemAcpiGedLib.inf |  36 +++
 .../DxeResetSystemAcpiGed.c   | 259 ++
 .../DxeResetSystemAcpiGedLib.inf  |  41 +++
 .../ResetSystemAcpiLib/ResetSystemAcpiGed.c   | 125 +
 .../ResetSystemAcpiLib/ResetSystemAcpiGed.h   |  23 ++
 6 files changed, 632 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGedLib.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/DxeResetSystemAcpiGed.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/DxeResetSystemAcpiGedLib.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/ResetSystemAcpiGed.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/ResetSystemAcpiGed.h

diff --git 
a/OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c 
b/OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
new file mode 100644
index 00..0d94a62a38
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
@@ -0,0 +1,148 @@
+/** @file
+  Base ResetSystem library implementation.
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "ResetSystemAcpiGed.h"
+
+/**
+  Get configuration item data by the firmware configuration file name.
+
+  @param[in]  Name - Name of file to look up.
+
+  @returnVOID*   The Pointer of Value of Firmware Configuration item 
read.
+**/
+VOID *
+GetFwCfgData (
+  CONST CHAR8  *Name
+  )
+{
+  FIRMWARE_CONFIG_ITEM  FwCfgItem;
+  EFI_STATUSStatus;
+  UINTN FwCfgSize;
+  VOID  *Data;
+
+  Status = QemuFwCfgFindFile (Name, , );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "%a %d read  %s error Status %d \n", __func__, 
__LINE__, Name, Status));
+return NULL;
+  }
+
+  Data = AllocatePool (FwCfgSize);
+  if (Data == NULL) {
+return NULL;
+  }
+
+  QemuFwCfgSelectItem (FwCfgItem);
+  QemuFwCfgReadBytes (FwCfgSize, Data);
+
+  return Data;
+}
+
+/**
+  Find the power manager related info from ACPI table
+
+  @retval RETURN_SUCCESS Successfully find out all the required 
information.
+  @retval RETURN_NOT_FOUND   Failed to find the required info.
+**/
+STATIC EFI_STATUS
+GetPowerManagerByParseAcpiInfo (
+  VOID
+  )
+{
+  EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt   = NULL;
+  EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER  *Rsdp   = NULL;
+  EFI_ACPI_DESCRIPTION_HEADER   *Xsdt   = NULL;
+  EFI_ACPI_DESCRIPTION_HEADER   *Rsdt   = NULL;
+  VOID  *AcpiTables = NULL;
+  UINT32*Entry32= NULL;
+  UINTN Entry32Num;
+  UINT32*Signature = NULL;
+  UINTN Idx;
+
+  Rsdp = GetFwCfgData ("etc/acpi/rsdp");
+  if (Rsdp == NULL) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/acpi/rsdp error \n", __func__, 
__LINE__));
+return RETURN_NOT_FOUND;
+  }
+
+  AcpiTables = GetFwCfgData ("etc/acpi/tables");
+  if (AcpiTables == NULL) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/acpi/tables error \n", __func__, 
__LINE__));
+FreePool (Rsdp);
+return RETURN_NOT_FOUND;
+  }
+
+  Rsdt   = (EFI_ACPI_DESCRIPTION_HEADER *)((UINTN)AcpiTables +  
Rsdp->RsdtAddress);
+  Entry32= (UINT32 *)(Rsdt + 1);
+  Entry32Num = (Rsdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
+  for (Idx = 0; Idx < Entry32Num; Idx++) {
+Signature = (UINT32 *)((UINTN)Entry32[Idx] + (UINTN)AcpiTables);
+if (*Signature == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+  Fadt = (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
+  DEBUG ((DEBUG_INFO, "Found Fadt in Rsdt\n"));
+  goto Done;
+}
+  }
+
+  Xsdt   = (EFI_ACPI_DESCRIPTION_HEADER *)((UINTN)AcpiTables +  
Rsdp->XsdtAddress);
+  Entry32= (UINT32 *)(Xsdt + 1);
+  Entry32Num = (Xsdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
+  for (Idx = 0; Idx < Entry32Num; Idx++) {
+Signature = (UINT32 *)((UINTN)Entry32[Idx] + (UINTN)AcpiTables);
+if (*Signature == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+

[edk2-devel] [PATCH v6 31/36] OvmfPkg/LoongArchVirt: Add FdtQemuFwCfgLib

[Chao Li]

This library for PEI phase, and obtains the QemuFwCfg base address by
directly parsing the FDT, reads and writes the data in QemuFwCfg by
operating on the QemuFwCfg base address.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
---
 .../FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c  | 504 ++
 .../FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.inf|  42 ++
 .../FdtQemuFwCfgLib/QemuFwCfgLibInternal.h|  73 +++
 .../Library/FdtQemuFwCfgLib/QemuFwCfgPei.c| 117 
 4 files changed, 736 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/QemuFwCfgLibInternal.h
 create mode 100644 OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/QemuFwCfgPei.c

diff --git a/OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c 
b/OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c
new file mode 100644
index 00..a1f114b327
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c
@@ -0,0 +1,504 @@
+/** @file
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- FwCfg   - firmWare  Configure
+- CTL   - Control
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "QemuFwCfgLibInternal.h"
+
+EFI_GUID  mFwCfgSelectorAddressGuid = FW_CONFIG_SELECTOR_ADDRESS_HOB_GUID;
+EFI_GUID  mFwCfgDataAddressGuid = FW_CONFIG_DATA_ADDRESS_HOB_GUID;
+
+STATIC UINTN  mFwCfgSelectorAddress;
+STATIC UINTN  mFwCfgDataAddress;
+
+/**
+  To get firmware configure selector address.
+
+  @param VOID
+
+  @retval  firmware configure selector address
+**/
+UINTN
+EFIAPI
+QemuGetFwCfgSelectorAddress (
+  VOID
+  )
+{
+  UINTN  FwCfgSelectorAddress;
+  EFI_HOB_GUID_TYPE  *GuidHob;
+  VOID   *DataInHob;
+
+  FwCfgSelectorAddress = mFwCfgSelectorAddress;
+  GuidHob  = NULL;
+  DataInHob= NULL;
+
+  if (FwCfgSelectorAddress == 0) {
+GuidHob  = GetFirstGuidHob ();
+DataInHob= GET_GUID_HOB_DATA (GuidHob);
+FwCfgSelectorAddress = (UINT64)(*(UINTN *)DataInHob);
+  }
+
+  return FwCfgSelectorAddress;
+}
+
+/**
+  To get firmware configure Data address.
+
+  @param VOID
+
+  @retval  firmware configure data address
+**/
+UINTN
+EFIAPI
+QemuGetFwCfgDataAddress (
+  VOID
+  )
+{
+  UINTN  FwCfgDataAddress;
+  EFI_HOB_GUID_TYPE  *GuidHob;
+  VOID   *DataInHob;
+
+  FwCfgDataAddress = mFwCfgDataAddress;
+  GuidHob  = NULL;
+  DataInHob= NULL;
+
+  if (FwCfgDataAddress == 0) {
+GuidHob  = GetFirstGuidHob ();
+DataInHob= GET_GUID_HOB_DATA (GuidHob);
+FwCfgDataAddress = (UINT64)(*(UINTN *)DataInHob);
+  }
+
+  return FwCfgDataAddress;
+}
+
+/**
+  Selects a firmware configuration item for reading.
+
+  Following this call, any data read from this item will start from
+  the beginning of the configuration item's data.
+
+  @param[in] QemuFwCfgItem - Firmware Configuration item to read
+**/
+VOID
+EFIAPI
+QemuFwCfgSelectItem (
+  IN FIRMWARE_CONFIG_ITEM  QemuFwCfgItem
+  )
+{
+  UINTN  FwCfgSelectorAddress;
+
+  FwCfgSelectorAddress = QemuGetFwCfgSelectorAddress ();
+  MmioWrite16 (FwCfgSelectorAddress, SwapBytes16 
((UINT16)(UINTN)QemuFwCfgItem));
+}
+
+/**
+  Slow READ_BYTES_FUNCTION.
+
+  @param[in]  The size of the data to be read.
+  @param[in]  BufferThe buffer that stores the readout data.
+**/
+VOID
+EFIAPI
+MmioReadBytes (
+  IN UINTN  Size,
+  IN VOID   *Buffer OPTIONAL
+  )
+{
+  UINTN  Left;
+  UINT8  *Ptr;
+  UINT8  *End;
+  UINTN  FwCfgDataAddress;
+
+  Left = Size & 7;
+
+  Size -= Left;
+  Ptr   = Buffer;
+  End   = Ptr + Size;
+
+  FwCfgDataAddress = QemuGetFwCfgDataAddress ();
+  while (Ptr < End) {
+*(UINT64 *)Ptr = MmioRead64 (FwCfgDataAddress);
+Ptr   += 8;
+  }
+
+  if (Left & 4) {
+*(UINT32 *)Ptr = MmioRead32 (FwCfgDataAddress);
+Ptr   += 4;
+  }
+
+  if (Left & 2) {
+*(UINT16 *)Ptr = MmioRead16 (FwCfgDataAddress);
+Ptr   += 2;
+  }
+
+  if (Left & 1) {
+*Ptr = MmioRead8 (FwCfgDataAddress);
+  }
+}
+
+/**
+  Slow WRITE_BYTES_FUNCTION.
+
+  @param[in]  The size of the data to be write.
+  @param[in]  BufferThe buffer that stores the writein data.
+**/
+VOID
+EFIAPI
+MmioWriteBytes (
+  IN UINTN  Size,
+  IN VOID   *Buffer OPTIONAL
+  )
+{
+  UINTN  Idx;
+  UINTN  FwCfgDataAddress;
+
+  FwCfgDataAddress = QemuGetFwCfgDataAddress ();
+  for (Idx = 0; Idx < Size; ++Idx) {
+

[edk2-devel] [PATCH v6 30/36] OvmfPkg/LoongArchVirt: Add NorFlashQemuLib

[Chao Li]

Add NorFlashQemuLib for LoongArch, it is referenced from ArmVirtPkg.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
---
 .../Library/NorFlashQemuLib/NorFlashQemuLib.c | 140 ++
 .../NorFlashQemuLib/NorFlashQemuLib.inf   |  43 ++
 2 files changed, 183 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.inf

diff --git a/OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.c 
b/OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.c
new file mode 100644
index 00..ae9af09c4c
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.c
@@ -0,0 +1,140 @@
+/** @file
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define QEMU_NOR_BLOCK_SIZE  SIZE_128KB
+
+EFI_STATUS
+VirtNorFlashPlatformInitialization (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
+STATIC VIRT_NOR_FLASH_DESCRIPTION  mNorFlashDevices;
+
+EFI_STATUS
+VirtNorFlashPlatformGetDevices (
+  OUT VIRT_NOR_FLASH_DESCRIPTION  **NorFlashDescriptions,
+  OUT UINT32  *Count
+  )
+{
+  FDT_CLIENT_PROTOCOL  *FdtClient;
+  INT32Node;
+  EFI_STATUS   Status;
+  EFI_STATUS   FindNodeStatus;
+  CONST UINT32 *Reg;
+  UINT32   PropSize;
+  UINT64   Base;
+  UINT64   Size;
+
+  Status = gBS->LocateProtocol (
+  ,
+  NULL,
+  (VOID **)
+  );
+  ASSERT_EFI_ERROR (Status);
+
+  FindNodeStatus = FdtClient->FindCompatibleNode (
+FdtClient,
+"cfi-flash",
+
+);
+  ASSERT_EFI_ERROR (FindNodeStatus);
+
+  Status = FdtClient->GetNodeProperty (
+FdtClient,
+Node,
+"reg",
+(CONST VOID **),
+
+);
+  if (EFI_ERROR (Status)) {
+DEBUG ((
+  DEBUG_ERROR,
+  "%a: GetNodeProperty () failed (Status == %r)\n",
+  __func__,
+  Status
+  ));
+return Status;
+  }
+
+  ASSERT ((PropSize % (4 * sizeof (UINT32))) == 0);
+
+  if (PropSize < (4 * sizeof (UINT32))) {
+DEBUG ((
+  DEBUG_ERROR,
+  "%a: reg node size(%d) is too small \n",
+  __func__,
+  PropSize
+  ));
+return EFI_NOT_FOUND;
+  }
+
+  Base = SwapBytes64 (ReadUnaligned64 ((VOID *)[0]));
+  Size = SwapBytes64 (ReadUnaligned64 ((VOID *)[2]));
+
+  mNorFlashDevices.DeviceBaseAddress = (UINTN)Base;
+  mNorFlashDevices.RegionBaseAddress = (UINTN)Base;
+  mNorFlashDevices.Size  = (UINTN)Size;
+  mNorFlashDevices.BlockSize = QEMU_NOR_BLOCK_SIZE;
+
+  Status = PcdSet32S (PcdFlashNvStorageVariableBase, Base);
+  ASSERT_EFI_ERROR (Status);
+
+  /*
+   * Base is the value of PcdFlashNvStorageVariableBase,
+   * PcdFlashNvStorageFtwWorkingBase can be got by
+   *   PcdFlashNvStorageVariableBase + PcdFlashNvStorageVariableSize
+   */
+  Base  += PcdGet32 (PcdFlashNvStorageVariableSize);
+  Status = PcdSet32S (PcdFlashNvStorageFtwWorkingBase, Base);
+  ASSERT_EFI_ERROR (Status);
+
+  /*
+   * Now,Base is the value of PcdFlashNvStorageFtwWorkingBase,
+   * PcdFlashNvStorageFtwSpareBase can be got by
+   *   PcdFlashNvStorageFtwWorkingBase + PcdFlashNvStorageFtwWorkingSize.
+   */
+  Base  += PcdGet32 (PcdFlashNvStorageFtwWorkingSize);
+  Status = PcdSet32S (PcdFlashNvStorageFtwSpareBase, Base);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // UEFI takes ownership of the NOR flash, and exposes its functionality
+  // through the UEFI Runtime Services GetVariable, SetVariable, etc. This
+  // means we need to disable it in the device tree to prevent the OS from
+  // attaching its device driver as well.
+  // Note that this also hides other flash banks, but the only other flash
+  // bank we expect to encounter is the one that carries the UEFI executable
+  // code, which is not intended to be guest updatable, and is usually backed
+  // in a readonly manner by QEMU anyway.
+  //
+  Status = FdtClient->SetNodeProperty (
+FdtClient,
+Node,
+"status",
+"disabled",
+sizeof ("disabled")
+);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_WARN, "Failed to set NOR flash status to 'disabled'\n"));
+  }
+
+  *NorFlashDescriptions = 
+  *Count= 1;
+
+  return 

[edk2-devel] [PATCH v6 29/36] OvmfPkg/LoongArchVirt: Add real time clock library

[Chao Li]

This library is provides real time clock for LoongArch virtual machine.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Baoqi Zhang 
Co-authored-by: Xianglai Li 
Reviewed-by: Bibo Mao 
---
 .../DxeLsRealTimeClockLib.c   | 327 ++
 .../DxeLsRealTimeClockLib.inf |  41 +++
 .../LsRealTimeClockLib/LsRealTimeClock.h  |  47 +++
 .../PeiLsRealTimeClockLib.c   |  31 ++
 .../PeiLsRealTimeClockLib.inf |  29 ++
 5 files changed, 475 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/LsRealTimeClock.h
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/PeiLsRealTimeClockLib.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/PeiLsRealTimeClockLib.inf

diff --git 
a/OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.c 
b/OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.c
new file mode 100644
index 00..e990728069
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.c
@@ -0,0 +1,327 @@
+/** @file
+  Implement EFI RealTimeClock runtime services via RTC Lib.
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "LsRealTimeClock.h"
+
+STATIC BOOLEANmInitialized = FALSE;
+STATIC EFI_EVENT  mRtcVirtualAddrChangeEvent;
+STATIC UINTN  mRtcBase;
+
+/*
+  Enable Real-time clock.
+
+  @param VOID
+
+  @retval  VOID
+ */
+VOID
+InitRtc (
+  VOID
+  )
+{
+  UINTN  Val;
+  EFI_HOB_GUID_TYPE  *GuidHob   = NULL;
+  VOID   *DataInHob = NULL;
+
+  if (!mInitialized) {
+/* Enable rtc */
+GuidHob = GetFirstGuidHob ();
+if (GuidHob) {
+  DataInHob = GET_GUID_HOB_DATA (GuidHob);
+  mRtcBase  = (UINT64)(*(UINTN *)DataInHob);
+  Val   = MmioRead32 (mRtcBase + RTC_CTRL_REG);
+  Val  |= TOY_ENABLE_BIT | OSC_ENABLE_BIT;
+  MmioWrite32 (mRtcBase + RTC_CTRL_REG, Val);
+  mInitialized = TRUE;
+} else {
+  DebugPrint (EFI_D_INFO, "RTC register address not found!\n");
+  ASSERT (FALSE);
+}
+  }
+}
+
+/**
+  Returns the current time and date information, and the time-keeping 
capabilities
+  of the hardware platform.
+
+  @param  Time   A pointer to storage to receive a snapshot of 
the current time.
+  @param  Capabilities   An optional pointer to a buffer to receive 
the real time clock
+ device's capabilities.
+
+  @retval EFI_SUCCESSThe operation completed successfully.
+  @retval EFI_INVALID_PARAMETER  Time is NULL.
+  @retval EFI_DEVICE_ERROR   The time could not be retrieved due to 
hardware error.
+  @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an 
authentication failure.
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+  OUT EFI_TIME   *Time,
+  OUT EFI_TIME_CAPABILITIES  *Capabilities
+  )
+{
+  UINT32  Val;
+
+  // Ensure Time is a valid pointer
+  if (Time == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  Val= MmioRead32 (mRtcBase + TOY_READ1_REG);
+  Time->Year = Val + 1900;
+
+  Val  = MmioRead32 (mRtcBase + TOY_READ0_REG);
+  Time->Month  = (Val >> TOY_MON_SHIFT) & TOY_MON_MASK;
+  Time->Day= (Val >> TOY_DAY_SHIFT) & TOY_DAY_MASK;
+  Time->Hour   = (Val >> TOY_HOUR_SHIFT) & TOY_HOUR_MASK;
+  Time->Minute = (Val >> TOY_MIN_SHIFT) & TOY_MIN_MASK;
+  Time->Second = (Val >> TOY_SEC_SHIFT) & TOY_SEC_MASK;
+  Time->Nanosecond = 0;
+  return EFI_SUCCESS;
+}
+
+/**
+  Sets the current local time and date information.
+
+  @param  Time  A pointer to the current time.
+
+  @retval EFI_SUCCESS   The operation completed successfully.
+  @retval EFI_INVALID_PARAMETER A time field is out of range.
+  @retval EFI_DEVICE_ERROR  The time could not be set due due to hardware 
error.
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+  IN  EFI_TIME  *Time
+  )
+{
+  UINT32  Val;
+
+  // Initialize the hardware if not already done
+
+  Val  = 0;
+  Val |= (Time->Second << TOY_SEC_SHIFT);
+  Val |= (Time->Minute << TOY_MIN_SHIFT);
+  Val |= (Time->Hour   << TOY_HOUR_SHIFT);
+  Val |= (Time->Day<< TOY_DAY_SHIFT);
+  Val |= (Time->Month  << TOY_MON_SHIFT);
+  MmioWrite32 (mRtcBase + TOY_WRITE0_REG, Val);
+
+  Val = Time->Year - 1900;
+  MmioWrite32 (mRtcBase + TOY_WRITE1_REG, Val);
+  return EFI_SUCCESS;

[edk2-devel] [PATCH v6 28/36] OvmfPkg/LoongArchVirt: Add the early serial port output library

[Chao Li]

Add a early serial port output library into LoongArchVirt that named
EarlyFdtSerialPortLib16550, this library is referenced from
MdeModulePkg.

This library is used in the PEI phase. Since the serial port address can
not be saved in memory of the LoongArch QEMU virtual machine in the PEI
phase, the serial prot base address will be obtained from the FDT before
each output.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
---
 .../EarlyFdtSerialPortLib16550.c  | 815 ++
 .../EarlyFdtSerialPortLib16550.inf|  46 +
 2 files changed, 861 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.inf

diff --git 
a/OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.c
 
b/OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.c
new file mode 100644
index 00..8cc108501c
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.c
@@ -0,0 +1,815 @@
+/** @file
+  16550 UART Serial Port library functions
+
+  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+//
+// PCI Defintions.
+//
+#define PCI_BRIDGE_32_BIT_IO_SPACE  0x01
+
+//
+// 16550 UART register offsets and bitfields
+//
+#define R_UART_RXBUF   0// LCR_DLAB = 0
+#define R_UART_TXBUF   0// LCR_DLAB = 0
+#define R_UART_BAUD_LOW0// LCR_DLAB = 1
+#define R_UART_BAUD_HIGH   1// LCR_DLAB = 1
+#define R_UART_IER 1// LCR_DLAB = 0
+#define R_UART_FCR 2
+#define B_UART_FCR_FIFOE   BIT0
+#define B_UART_FCR_FIFO64  BIT5
+#define R_UART_LCR 3
+#define B_UART_LCR_DLABBIT7
+#define R_UART_MCR 4
+#define B_UART_MCR_DTRCBIT0
+#define B_UART_MCR_RTS BIT1
+#define R_UART_LSR 5
+#define B_UART_LSR_RXRDY   BIT0
+#define B_UART_LSR_TXRDY   BIT5
+#define B_UART_LSR_TEMTBIT6
+#define R_UART_MSR 6
+#define B_UART_MSR_CTS BIT4
+#define B_UART_MSR_DSR BIT5
+#define B_UART_MSR_RI  BIT6
+#define B_UART_MSR_DCD BIT7
+
+/**
+  Read an 8-bit 16550 register.  If PcdSerialUseMmio is TRUE, then the value 
is read from
+  MMIO space.  If PcdSerialUseMmio is FALSE, then the value is read from I/O 
space.  The
+  parameter Offset is added to the base address of the 16550 registers that is 
specified
+  by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO 
space access
+  width and defaults to 8 bit access, and supports 8 or 32 bit access.
+
+  @param  BaseThe base address register of UART device.
+  @param  Offset  The offset of the 16550 register to read.
+
+  @return The value read from the 16550 register.
+**/
+UINT8
+SerialPortReadRegister (
+  UINTN  Base,
+  UINTN  Offset
+  )
+{
+  if (PcdGetBool (PcdSerialUseMmio)) {
+if (PcdGet8 (PcdSerialRegisterAccessWidth) == 32) {
+  return (UINT8)MmioRead32 (Base + Offset * PcdGet32 
(PcdSerialRegisterStride));
+}
+
+return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
+  } else {
+return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
+  }
+}
+
+/**
+  Write an 8-bit 16550 register.  If PcdSerialUseMmio is TRUE, then the value 
is written to
+  MMIO space.  If PcdSerialUseMmio is FALSE, then the value is written to I/O 
space.  The
+  parameter Offset is added to the base address of the 16550 registers that is 
specified
+  by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO 
space access
+  width and defaults to 8 bit access, and supports 8 or 32 bit access.
+
+  @param  BaseThe base address register of UART device.
+  @param  Offset  The offset of the 16550 register to write.
+  @param  Value   The value to write to the 16550 register specified by Offset.
+
+  @return The value written to the 16550 register.
+**/
+UINT8
+SerialPortWriteRegister (
+  UINTN  Base,
+  UINTN  Offset,
+  UINT8  Value
+  )
+{
+  if (PcdGetBool (PcdSerialUseMmio)) {
+if (PcdGet8 (PcdSerialRegisterAccessWidth) == 32) {
+  return (UINT8)MmioWrite32 (Base + Offset * PcdGet32 
(PcdSerialRegisterStride), (UINT8)Value);
+}
+
+return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), 
Value);
+  } else {
+return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), 
Value);
+  }
+}
+
+/**
+  Retrieve the I/O or MMIO base address register for the PCI UART device.
+
+  This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in 
PCI UART
+  Device if they are not already 

[edk2-devel] [PATCH v6 27/36] OvmfPkg/LoongArchVirt: Add serial port hook library

[Chao Li]

Add a serial port hook library in LoongArchVirt named
Fdt16550SerialProtHookLib, this library is referenced from ArmVirtPkg.

LoongArch QEMU virtual machine uses register of LOONGARCH_CSR_KS1 to
transfer serial port base addres from the PEI phase to the DXE phase.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Reviewed-by: Bibo Mao 
---
 .../EarlyFdt16550SerialPortHookLib.c  | 52 +++
 .../EarlyFdt16550SerialPortHookLib.inf| 37 +
 .../Fdt16550SerialPortHookLib.c   | 39 ++
 .../Fdt16550SerialPortHookLib.inf | 33 
 .../Fdt16550SerialPortHookLib.uni | 14 +
 5 files changed, 175 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.uni

diff --git 
a/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.c
 
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.c
new file mode 100644
index 00..9f1fcc970a
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.c
@@ -0,0 +1,52 @@
+/** @file
+  PEI Phase Early Platform Hook Library instance for 16550 Uart.
+
+  Copyright (c) 2020 - 2023, Arm Ltd. All rights reserved.
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/** Platform hook to retrieve the 16550 UART base address from the platform
+Device tree and store it in the reigster LOONGARCH_CSR_KS1.
+
+  @retval RETURN_SUCCESSSuccess.
+  @retval RETURN_INVALID_PARAMETER  A parameter was invalid.
+  @retval RETURN_NOT_FOUND  Serial port information not found.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+  VOID
+  )
+{
+  RETURN_STATUS  Status;
+  VOID   *DeviceTreeBase;
+  UINT64 SerialConsoleAddress;
+
+  if (PcdGet64 (PcdSerialRegisterBase) != 0) {
+return RETURN_SUCCESS;
+  }
+
+  DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeInitialBaseAddress);
+  if (DeviceTreeBase == NULL) {
+return RETURN_NOT_FOUND;
+  }
+
+  Status = FdtSerialGetConsolePort (DeviceTreeBase, );
+  if (RETURN_ERROR (Status)) {
+return Status;
+  }
+
+  CsrWrite (LOONGARCH_CSR_KS1, (UINTN)SerialConsoleAddress);
+
+  return RETURN_SUCCESS;
+}
diff --git 
a/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
 
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
new file mode 100644
index 00..55b0c03a01
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
@@ -0,0 +1,37 @@
+## @file
+#  PEI Phase Early Platform Hook Library instance for 16550 Uart.
+#
+#  Copyright (c) 2020, ARM Ltd. All rights reserved.
+#  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 1.29
+  BASE_NAME  = EarlyFdt16550SerialPortHookLib
+  MODULE_UNI_FILE= Fdt16550SerialPortHookLib.uni
+  FILE_GUID  = 6A5FEBCB-C676-A7C1-A96C-B79D4860EEC5
+  MODULE_TYPE= PEIM
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = PlatformHookLib|SEC PEI_CORE PEIM
+
+[Sources]
+  EarlyFdt16550SerialPortHookLib.c
+
+[LibraryClasses]
+  BaseLib
+  PcdLib
+  FdtLib
+  FdtSerialPortAddressLib
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OvmfPkg/OvmfPkg.dec
+
+[Pcd]
+  gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git 
a/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.c
 
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.c
new file mode 100644
index 00..fd188f75b8
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.c
@@ -0,0 +1,39 @@
+/** @file
+  Platform Hook Library instance for 16550 Uart.
+
+  Copyright (c) 2020, ARM Ltd. All rights reserved.
+  Copyright (c) 2024 Loongson 

[edk2-devel] [PATCH v6 26/36] OvmfPkg/LoongArchVirt: Add a NULL library named CollectApResouceLibNull

[Chao Li]

This Library is used to collect APs resources, but is currently NULL
for OvmfPkg, because it is not used by the LoongArch virtual machine.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
---
 .../CollectApResourceLibNull.c| 38 +++
 .../CollectApResourceLibNull.inf  | 31 +++
 .../CollectApResourceLibNull.uni  |  9 +
 3 files changed, 78 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.uni

diff --git 
a/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.c
 
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.c
new file mode 100644
index 00..19995c1193
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.c
@@ -0,0 +1,38 @@
+/** @file
+  LoongArch64 CPU Collect AP resource NULL Library functions.
+
+  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "../../../UefiCpuPkg/Library/LoongArch64MpInitLib/MpLib.h"
+
+VOID
+SaveProcessorResourceData (
+  IN PROCESSOR_RESOURCE_DATA *
+  );
+
+VOID
+EFIAPI
+SaveProcessorResource (
+  PROCESSOR_RESOURCE_DATA  *mProcessorResource
+  )
+{
+  SaveProcessorResourceData (mProcessorResource);
+}
+
+VOID
+EFIAPI
+CollectAllProcessorResource (
+  VOID
+  )
+{
+  return;
+}
diff --git 
a/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.inf
 
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.inf
new file mode 100644
index 00..c166df6bbd
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.inf
@@ -0,0 +1,31 @@
+## @file
+#  LoongArch64 CPU Collect AP resource NULL Library.
+#
+#  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 1.29
+  BASE_NAME  = CollectApResourceLibNull
+  MODULE_UNI_FILE= CollectApResourceLibNull.uni
+  FILE_GUID  = 8C3B54BF-6A9F-E8B4-4D57-67B3AB578DD6
+  MODULE_TYPE= PEIM
+  VERSION_STRING = 1.1
+  LIBRARY_CLASS  = PEIM
+
+[Sources.common]
+  CollectApResourceLibNull.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  HobLib
+  MemoryAllocationLib
+
+[Pcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber
diff --git 
a/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.uni
 
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.uni
new file mode 100644
index 00..d1638ab11e
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.uni
@@ -0,0 +1,9 @@
+// @file
+//  LoongArch64 CPU Collect AP resource NULL Library.
+//
+//  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+//  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+#string STR_MODULE_ABSTRACT #language en-US "CPU Collect AP 
resource NULL Library."
+
+#string STR_MODULE_DESCRIPTION  #language en-US "CPU Collect AP 
resource NULL Library."
-- 
2.27.0



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[edk2-devel] [PATCH v6 25/36] OvmfPkg/LoongArchVirt: Add stable timer driver

[Chao Li]

Add a CPU timer driver named StableTimerDxe, which proviedes
EFI_TIMER_ARCH_PROTOCOL for LoongArch.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Baoqi Zhang 
---
 .../Drivers/StableTimerDxe/Timer.c| 381 ++
 .../Drivers/StableTimerDxe/Timer.h| 127 ++
 .../Drivers/StableTimerDxe/TimerDxe.inf   |  41 ++
 3 files changed, 549 insertions(+)
 create mode 100644 OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.c
 create mode 100644 OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.h
 create mode 100644 OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/TimerDxe.inf

diff --git a/OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.c 
b/OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.c
new file mode 100644
index 00..0e0f10970a
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.c
@@ -0,0 +1,381 @@
+/** @file
+  Timer Architectural Protocol as defined in the DXE CIS
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "Timer.h"
+
+//
+// The handle onto which the Timer Architectural Protocol will be installed
+//
+EFI_HANDLE  mTimerHandle = NULL;
+EFI_EVENT   EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+//
+// The Timer Architectural Protocol that this driver produces
+//
+EFI_TIMER_ARCH_PROTOCOL  mTimer = {
+  TimerDriverRegisterHandler,
+  TimerDriverSetTimerPeriod,
+  TimerDriverGetTimerPeriod,
+  TimerDriverGenerateSoftInterrupt
+};
+
+//
+// Pointer to the CPU Architectural Protocol instance
+//
+EFI_CPU_ARCH_PROTOCOL  *mCpu;
+
+//
+// The notification function to call on every timer interrupt.
+// A bug in the compiler prevents us from initializing this here.
+//
+EFI_TIMER_NOTIFY  mTimerNotifyFunction;
+
+/**
+  Sets the counter value for timer.
+
+  @param CountThe 16-bit counter value to program into stable timer.
+
+  @retval VOID
+**/
+VOID
+SetPitCount (
+  IN UINT64  Count
+  )
+{
+  if (Count <= 4) {
+return;
+  }
+
+  Count &= LOONGARCH_CSR_TMCFG_TIMEVAL;
+  Count |= LOONGARCH_CSR_TMCFG_EN | LOONGARCH_CSR_TMCFG_PERIOD;
+  CsrWrite (LOONGARCH_CSR_TMCFG, Count);
+}
+
+/**
+  Timer Interrupt Handler.
+
+  @param InterruptTypeThe type of interrupt that occurred
+  @param SystemContextA pointer to the system context when the interrupt 
occurred
+
+  @retval VOID
+**/
+VOID
+EFIAPI
+TimerInterruptHandler (
+  IN EFI_EXCEPTION_TYPE  InterruptType,
+  IN EFI_SYSTEM_CONTEXT  SystemContext
+  )
+{
+  EFI_TPL  OriginalTPL;
+
+  OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
+  //
+  // Clear interrupt.
+  //
+  CsrWrite (LOONGARCH_CSR_TINTCLR, 0x1);
+
+  if (mTimerNotifyFunction != NULL) {
+//
+// @bug : This does not handle missed timer interrupts
+//
+mTimerNotifyFunction (mTimerPeriod);
+  }
+
+  gBS->RestoreTPL (OriginalTPL);
+}
+
+/**
+  This function registers the handler NotifyFunction so it is called every time
+  the timer interrupt fires.  It also passes the amount of time since the last
+  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the
+  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is
+  returned.  If the CPU does not support registering a timer interrupt handler,
+  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a 
handler
+  when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not 
registered,
+  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to
+  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+  is returned.
+
+  @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+  @param NotifyFunction   The function to call when a timer interrupt fires.  
This
+  function executes at TPL_HIGH_LEVEL.  The DXE Core 
will
+  register a handler for the timer interrupt, so it 
can know
+  how much time has passed.  This information is used 
to
+  signal timer based events.  NULL will unregister the 
handler.
+
+  @retvalEFI_SUCCESSThe timer handler was registered.
+  @retvalEFI_UNSUPPORTEDThe platform does not support timer 
interrupts.
+  @retvalEFI_ALREADY_STARTEDNotifyFunction is not NULL, and a 
handler is already
+registered.
+  @retvalEFI_INVALID_PARAMETER  NotifyFunction is NULL, and a handler 
was not
+previously registered.
+  @retvalEFI_DEVICE_ERROR   The timer handler could not be 
registered.
+**/

[edk2-devel] [PATCH v6 24/36] ArmVirtPkg: Move PlatformBootManagerLib to OvmfPkg

[Chao Li]

Moved the PlatformBootManagerLib to OvmfPkg and renamed to
PlatformBootManagerLibLight for easy use by other ARCH.

Build-tested only (with "ArmVirtQemu.dsc").

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Cc: Jiewen Yao 
Cc: Lazlo Ersek 
Signed-off-by: Chao Li 
---
 ArmVirtPkg/ArmVirtPkg.ci.yaml  | 1 -
 ArmVirtPkg/ArmVirtPkg.dec  | 1 -
 ArmVirtPkg/ArmVirtQemu.dsc | 2 +-
 ArmVirtPkg/ArmVirtQemuKernel.dsc   | 2 +-
 .../Library/PlatformBootManagerLibLight}/PlatformBm.c  | 0
 .../Library/PlatformBootManagerLibLight}/PlatformBm.h  | 0
 .../PlatformBootManagerLib.inf | 7 +++
 .../Library/PlatformBootManagerLibLight}/QemuKernel.c  | 0
 OvmfPkg/OvmfPkg.dec| 4 
 9 files changed, 9 insertions(+), 8 deletions(-)
 rename {ArmVirtPkg/Library/PlatformBootManagerLib => 
OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBm.c (100%)
 rename {ArmVirtPkg/Library/PlatformBootManagerLib => 
OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBm.h (100%)
 rename {ArmVirtPkg/Library/PlatformBootManagerLib => 
OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBootManagerLib.inf (92%)
 rename {ArmVirtPkg/Library/PlatformBootManagerLib => 
OvmfPkg/Library/PlatformBootManagerLibLight}/QemuKernel.c (100%)

diff --git a/ArmVirtPkg/ArmVirtPkg.ci.yaml b/ArmVirtPkg/ArmVirtPkg.ci.yaml
index 506b0e72f0..b186d4eb42 100644
--- a/ArmVirtPkg/ArmVirtPkg.ci.yaml
+++ b/ArmVirtPkg/ArmVirtPkg.ci.yaml
@@ -24,7 +24,6 @@
 ],
 ## Both file path and directory path are accepted.
 "IgnoreFiles": [
-"Library/PlatformBootManagerLib/PlatformBm.c"
 ]
 },
 ## options defined .pytool/Plugin/CompilerPlugin
diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec
index 315db4e8ea..6aa5ea05f4 100644
--- a/ArmVirtPkg/ArmVirtPkg.dec
+++ b/ArmVirtPkg/ArmVirtPkg.dec
@@ -27,7 +27,6 @@
 
 [LibraryClasses]
   ArmVirtMemInfoLib|Include/Library/ArmVirtMemInfoLib.h
-  FdtSerialPortAddressLib|Include/Library/FdtSerialPortAddressLib.h
 
 [Guids.common]
   gArmVirtTokenSpaceGuid = { 0x0B6F5CA7, 0x4F53, 0x445A, { 0xB7, 0x6E, 0x2E, 
0x36, 0x5B, 0x80, 0x63, 0x66 } }
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 147180f645..e48c75b5e9 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -70,7 +70,7 @@
 
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
-  
PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  
PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
   
PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
   
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
   
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index c22a422353..668a65ba64 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -69,7 +69,7 @@
 
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
-  
PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  
PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
   
PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
   
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
   
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c 
b/OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.c
similarity index 100%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c
rename to OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.c
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.h 
b/OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.h
similarity index 100%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.h
rename to OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.h
diff --git 
a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf 
b/OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
similarity index 92%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
rename to OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
index 1ddcd107d2..f2fb69bd3c 100644
--- 

[edk2-devel] [PATCH v6 23/36] ArmVirtPkg: Move two PCD variables into OvmfPkg

[Chao Li]

Move the PcdTerminalTypeGuidBuffer and PcdUninstallMemAttrProtocol into
OvmfPkg so other ARCh can easily use it.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Cc: Jiewen Yao 
Signed-off-by: Chao Li 
---
 ArmVirtPkg/ArmVirtPkg.dec   | 13 -
 ArmVirtPkg/ArmVirtQemu.dsc  |  2 +-
 ArmVirtPkg/ArmVirtQemuKernel.dsc|  2 +-
 .../PlatformBootManagerLib.inf  |  4 ++--
 OvmfPkg/OvmfPkg.dec | 13 +
 5 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec
index 05d2d36c1d..315db4e8ea 100644
--- a/ArmVirtPkg/ArmVirtPkg.dec
+++ b/ArmVirtPkg/ArmVirtPkg.dec
@@ -42,21 +42,8 @@
   gArmVirtTokenSpaceGuid.PcdTpm2SupportEnabled|FALSE|BOOLEAN|0x0004
 
 [PcdsFixedAtBuild, PcdsPatchableInModule]
-  #
-  # Binary representation of the GUID that determines the terminal type. The
-  # size must be exactly 16 bytes. The default value corresponds to
-  # EFI_VT_100_GUID.
-  #
-  gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x65, 0x60, 0xA6, 0xDF, 
0x19, 0xB4, 0xD3, 0x11, 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 
0x4D}|VOID*|0x0007
-
   ##
   # This is the physical address of Rsdp which is the core struct of Acpi.
   # Cloud Hypervisor has no other way to pass Rsdp address to the guest except 
use a PCD.
   #
   gArmVirtTokenSpaceGuid.PcdCloudHvAcpiRsdpBaseAddress|0x0|UINT64|0x0005
-
-  ##
-  # Whether the EFI memory attributes protocol should be uninstalled before
-  # invoking the OS loader. This may be needed to work around problematic
-  # builds of shim that use the protocol incorrectly.
-  gArmVirtTokenSpaceGuid.PcdUninstallMemAttrProtocol|FALSE|BOOLEAN|0x0006
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index dbd2396c78..147180f645 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -182,7 +182,7 @@
 !if $(TTY_TERMINAL) == TRUE
   gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
   # Set terminal type to TtyTerm, the value encoded is EFI_TTY_TERM_GUID
-  gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 0x7d, 
0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
+  gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 
0x7d, 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
 !else
   gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1
 !endif
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index 6a6ecfc12a..c22a422353 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -147,7 +147,7 @@
 !if $(TTY_TERMINAL) == TRUE
   gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
   # Set terminal type to TtyTerm, the value encoded is EFI_TTY_TERM_GUID
-  gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 0x7d, 
0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
+  gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 
0x7d, 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
 !else
   gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1
 !endif
diff --git 
a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf 
b/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 70e4ebf94a..1ddcd107d2 100644
--- a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -56,14 +56,14 @@
   UefiRuntimeServicesTableLib
 
 [FixedPcd]
-  gArmVirtTokenSpaceGuid.PcdUninstallMemAttrProtocol
+  gUefiOvmfPkgTokenSpaceGuid.PcdUninstallMemAttrProtocol
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
 
 [Pcd]
-  gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer
+  gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer
   gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
 
 [Guids]
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index 7bc2bf1674..a03c30995b 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -401,6 +401,19 @@
   #
   gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeAllocationPadding|256|UINT32|0x6f
 
+  #
+  # Binary representation of the GUID that determines the terminal type. The
+  # size must be exactly 16 bytes. The default value corresponds to
+  # EFI_VT_100_GUID.
+  #
+  gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x65, 0x60, 0xA6, 
0xDF, 0x19, 0xB4, 0xD3, 0x11, 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 
0x4D}|VOID*|0x66
+
+  ##
+  # Whether the EFI memory attributes protocol should be uninstalled before
+  # invoking the OS loader. This may be needed to work around problematic
+  # 

[edk2-devel] [PATCH v6 22/36] ArmVirtPkg: Move the FdtSerialPortAddressLib to OvmfPkg

[Chao Li]

Move the FdtSerialPortAddressLib to Ovmfpkg so that other ARCH can
easily use it.

Build-tested only (with "ArmVirtQemu.dsc").

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Cc: Jiewen Yao 
Cc: Laszlo Ersek 
Signed-off-by: Chao Li 
---
 ArmVirtPkg/ArmVirt.dsc.inc  | 2 +-
 .../Include/Library/FdtSerialPortAddressLib.h   | 0
 .../Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c   | 0
 .../Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf | 2 +-
 4 files changed, 2 insertions(+), 2 deletions(-)
 rename {ArmVirtPkg => OvmfPkg}/Include/Library/FdtSerialPortAddressLib.h (100%)
 rename {ArmVirtPkg => 
OvmfPkg}/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c (100%)
 rename {ArmVirtPkg => 
OvmfPkg}/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf (90%)

diff --git a/ArmVirtPkg/ArmVirt.dsc.inc b/ArmVirtPkg/ArmVirt.dsc.inc
index 9b23ef97ec..2bc6a29eb1 100644
--- a/ArmVirtPkg/ArmVirt.dsc.inc
+++ b/ArmVirtPkg/ArmVirt.dsc.inc
@@ -122,7 +122,7 @@
   # ARM PL011 UART Driver
   PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
   
SerialPortLib|ArmVirtPkg/Library/FdtPL011SerialPortLib/FdtPL011SerialPortLib.inf
-  
FdtSerialPortAddressLib|ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
+  
FdtSerialPortAddressLib|OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
 
   
PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
   
#PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
diff --git a/ArmVirtPkg/Include/Library/FdtSerialPortAddressLib.h 
b/OvmfPkg/Include/Library/FdtSerialPortAddressLib.h
similarity index 100%
rename from ArmVirtPkg/Include/Library/FdtSerialPortAddressLib.h
rename to OvmfPkg/Include/Library/FdtSerialPortAddressLib.h
diff --git 
a/ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c 
b/OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c
similarity index 100%
rename from ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c
rename to OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c
diff --git 
a/ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf 
b/OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
similarity index 90%
rename from 
ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
rename to OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
index ae6d0d374b..e27742e9fa 100644
--- a/ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
+++ b/OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
@@ -18,9 +18,9 @@
   FdtSerialPortAddressLib.c
 
 [Packages]
-  ArmVirtPkg/ArmVirtPkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
   MdePkg/MdePkg.dec
+  OvmfPkg/OvmfPkg.dec
 
 [LibraryClasses]
   BaseLib
-- 
2.27.0



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[edk2-devel] [PATCH v6 21/36] OvmfPkg/RiscVVirt: Remove PciCpuIo2Dxe from RiscVVirt

[Chao Li]

CpuIo2Dxe is already used by RiscVVirt, so remove it.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Sunil V L 
Cc: Andrei Warkentin 
Signed-off-by: Chao Li 
Reviewed-by: Sunil V L 
---
 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 557 --
 .../RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf   |  48 --
 2 files changed, 605 deletions(-)
 delete mode 100644 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
 delete mode 100644 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf

diff --git a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c 
b/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
deleted file mode 100644
index f3bf07e631..00
--- a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
+++ /dev/null
@@ -1,557 +0,0 @@
-/** @file
-  Produces the CPU I/O 2 Protocol.
-
-Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
-Copyright (c) 2016, Linaro Ltd. All rights reserved.
-Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
-
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include 
-
-#include 
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define MAX_IO_PORT_ADDRESS  0x
-
-//
-// Handle for the CPU I/O 2 Protocol
-//
-STATIC EFI_HANDLE  mHandle = NULL;
-
-//
-// Lookup table for increment values based on transfer widths
-//
-STATIC CONST UINT8  mInStride[] = {
-  1, // EfiCpuIoWidthUint8
-  2, // EfiCpuIoWidthUint16
-  4, // EfiCpuIoWidthUint32
-  8, // EfiCpuIoWidthUint64
-  0, // EfiCpuIoWidthFifoUint8
-  0, // EfiCpuIoWidthFifoUint16
-  0, // EfiCpuIoWidthFifoUint32
-  0, // EfiCpuIoWidthFifoUint64
-  1, // EfiCpuIoWidthFillUint8
-  2, // EfiCpuIoWidthFillUint16
-  4, // EfiCpuIoWidthFillUint32
-  8  // EfiCpuIoWidthFillUint64
-};
-
-//
-// Lookup table for increment values based on transfer widths
-//
-STATIC CONST UINT8  mOutStride[] = {
-  1, // EfiCpuIoWidthUint8
-  2, // EfiCpuIoWidthUint16
-  4, // EfiCpuIoWidthUint32
-  8, // EfiCpuIoWidthUint64
-  1, // EfiCpuIoWidthFifoUint8
-  2, // EfiCpuIoWidthFifoUint16
-  4, // EfiCpuIoWidthFifoUint32
-  8, // EfiCpuIoWidthFifoUint64
-  0, // EfiCpuIoWidthFillUint8
-  0, // EfiCpuIoWidthFillUint16
-  0, // EfiCpuIoWidthFillUint32
-  0  // EfiCpuIoWidthFillUint64
-};
-
-/**
-  Check parameters to a CPU I/O 2 Protocol service request.
-
-  The I/O operations are carried out exactly as requested. The caller is 
responsible
-  for satisfying any alignment and I/O width restrictions that a PI System on a
-  platform might require. For example on some platforms, width requests of
-  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
-  be handled by the driver.
-
-  @param[in] MmioOperation  TRUE for an MMIO operation, FALSE for I/O Port 
operation.
-  @param[in] Width  Signifies the width of the I/O or Memory operation.
-  @param[in] AddressThe base address of the I/O operation.
-  @param[in] Count  The number of I/O operations to perform. The 
number of
-bytes moved is Width size * Count, starting at 
Address.
-  @param[in] Buffer For read operations, the destination buffer to 
store the results.
-For write operations, the source buffer from which 
to write data.
-
-  @retval EFI_SUCCESSThe parameters for this request pass the 
checks.
-  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
-  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
-  @retval EFI_UNSUPPORTEDThe Buffer is not aligned for the given Width.
-  @retval EFI_UNSUPPORTEDThe address range specified by Address, Width,
- and Count is not valid for this PI system.
-
-**/
-STATIC
-EFI_STATUS
-CpuIoCheckParameter (
-  IN BOOLEANMmioOperation,
-  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
-  IN UINT64 Address,
-  IN UINTN  Count,
-  IN VOID   *Buffer
-  )
-{
-  UINT64  MaxCount;
-  UINT64  Limit;
-
-  //
-  // Check to see if Buffer is NULL
-  //
-  if (Buffer == NULL) {
-return EFI_INVALID_PARAMETER;
-  }
-
-  //
-  // Check to see if Width is in the valid range
-  //
-  if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
-return EFI_INVALID_PARAMETER;
-  }
-
-  //
-  // For FIFO type, the target address won't increase during the access,
-  // so treat Count as 1
-  //
-  if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) 
{
-Count = 1;
-  }
-
-  //
-  // Check to see if Width is in the valid range for I/O Port operations
-  //
-  Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
-  if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
-return EFI_INVALID_PARAMETER;
-  }
-
-  //
-  // Check to see if Address is aligned
-  //
-  if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
-return EFI_UNSUPPORTED;
-  }
-
-  //
-  // Check to see if any address associated with this transfer exceeds the 
maximum
-  // allowed address.  

[edk2-devel] [PATCH v6 20/36] OvmfPkg/RiscVVirt: Enable CpuMmio2Dxe

[Chao Li]

CpuMmio2Dxe is supports MMIO, enable it.

Build-tested only (with "RiscVVirtQemu.dsc").

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Sunil V L 
Cc: Andrei Warkentin 
Signed-off-by: Chao Li 
Reviewed-by: Sunil V L 
---
 OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 2 +-
 OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc 
b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
index f8b9479345..0d4364780b 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
@@ -446,7 +446,7 @@
   #
   # PCI support
   #
-  OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf {
+  UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
 
   NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
   }
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf 
b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
index 8121b9e579..e579f5b9b7 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
@@ -184,7 +184,7 @@ INF  OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf
 #
 # PCI support
 #
-INF  OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+INF  UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
 INF  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
 INF  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
 INF  OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
-- 
2.27.0



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[edk2-devel] [PATCH v6 19/36] ArmVirtPkg: Enable CpuMmio2Dxe

[Chao Li]

CpuMmio2Dxe is supports MMIO, enable it.

Build-tested only (with "ArmVirtQemu.dsc").

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
---
 ArmVirtPkg/ArmVirtCloudHv.dsc| 2 +-
 ArmVirtPkg/ArmVirtCloudHv.fdf| 2 +-
 ArmVirtPkg/ArmVirtKvmTool.dsc| 2 +-
 ArmVirtPkg/ArmVirtKvmTool.fdf| 2 +-
 ArmVirtPkg/ArmVirtQemu.dsc   | 2 +-
 ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 2 +-
 ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/ArmVirtPkg/ArmVirtCloudHv.dsc b/ArmVirtPkg/ArmVirtCloudHv.dsc
index 76c0d28544..5cb2a609b1 100644
--- a/ArmVirtPkg/ArmVirtCloudHv.dsc
+++ b/ArmVirtPkg/ArmVirtCloudHv.dsc
@@ -341,7 +341,7 @@
   #
   # PCI support
   #
-  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+  UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
 
   NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
   }
diff --git a/ArmVirtPkg/ArmVirtCloudHv.fdf b/ArmVirtPkg/ArmVirtCloudHv.fdf
index 56d1ea6e8c..8554efc294 100644
--- a/ArmVirtPkg/ArmVirtCloudHv.fdf
+++ b/ArmVirtPkg/ArmVirtCloudHv.fdf
@@ -201,7 +201,7 @@ READ_LOCK_STATUS   = TRUE
   #
   # PCI support
   #
-  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+  INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
   INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
   INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
   INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/ArmVirtPkg/ArmVirtKvmTool.dsc b/ArmVirtPkg/ArmVirtKvmTool.dsc
index cac4fe06d3..20da331966 100644
--- a/ArmVirtPkg/ArmVirtKvmTool.dsc
+++ b/ArmVirtPkg/ArmVirtKvmTool.dsc
@@ -372,7 +372,7 @@
   #
   # PCI support
   #
-  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+  UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
 
   NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
   
NULL|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib.inf
diff --git a/ArmVirtPkg/ArmVirtKvmTool.fdf b/ArmVirtPkg/ArmVirtKvmTool.fdf
index 82aff47673..cdf756c112 100644
--- a/ArmVirtPkg/ArmVirtKvmTool.fdf
+++ b/ArmVirtPkg/ArmVirtKvmTool.fdf
@@ -195,7 +195,7 @@ READ_LOCK_STATUS   = TRUE
   #
   # PCI support
   #
-  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+  INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
   INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
   INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
   INF OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index cf306cac08..dbd2396c78 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -526,7 +526,7 @@
   #
   # PCI support
   #
-  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+  UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
 
   NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
   }
diff --git a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc 
b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
index 9b3e37d5c9..c5d097ffb9 100644
--- a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
+++ b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
@@ -153,7 +153,7 @@ READ_LOCK_STATUS   = TRUE
   #
   # PCI support
   #
-  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+  INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
   INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
   INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
   INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index c0d079e28d..6a6ecfc12a 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -431,7 +431,7 @@
   #
   # PCI support
   #
-  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+  UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
 
   NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
   }
-- 
2.27.0



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[edk2-devel] [PATCH v6 18/36] UefiCpuPkg: Add a new CPU IO 2 driver named CpuMmio2Dxe

[Chao Li]

CpuIo2Dxe only supports IO to access to CPU IO. Some ARCHs that do not
implement ports for CPU IO require MMIO to access PCI IO, and they
pretty much put the IO devices under the LPC bus, which is usually under
the PCIe/PCI bus. CpuMmio2Dxe was added to meet these needs.

CpuMmio2Dxe depends on PcdPciIoTranslation. The code is copied from
ArmPkg.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Sami Mujawar 
Signed-off-by: Chao Li 
---
 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c   | 557 +
 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf |  48 +++
 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni |  18 +
 UefiCpuPkg/UefiCpuPkg.dsc  |   2 +
 4 files changed, 625 insertions(+)
 create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
 create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
 create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni

diff --git a/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c 
b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
new file mode 100644
index 00..32ccac1cc6
--- /dev/null
+++ b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
@@ -0,0 +1,557 @@
+/** @file
+  Produces the CPU I/O 2 Protocol.
+
+Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2016, Linaro Ltd. All rights reserved.
+Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MAX_IO_PORT_ADDRESS  0x
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE  mHandle = NULL;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8  mInStride[] = {
+  1, // EfiCpuIoWidthUint8
+  2, // EfiCpuIoWidthUint16
+  4, // EfiCpuIoWidthUint32
+  8, // EfiCpuIoWidthUint64
+  0, // EfiCpuIoWidthFifoUint8
+  0, // EfiCpuIoWidthFifoUint16
+  0, // EfiCpuIoWidthFifoUint32
+  0, // EfiCpuIoWidthFifoUint64
+  1, // EfiCpuIoWidthFillUint8
+  2, // EfiCpuIoWidthFillUint16
+  4, // EfiCpuIoWidthFillUint32
+  8  // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8  mOutStride[] = {
+  1, // EfiCpuIoWidthUint8
+  2, // EfiCpuIoWidthUint16
+  4, // EfiCpuIoWidthUint32
+  8, // EfiCpuIoWidthUint64
+  1, // EfiCpuIoWidthFifoUint8
+  2, // EfiCpuIoWidthFifoUint16
+  4, // EfiCpuIoWidthFifoUint32
+  8, // EfiCpuIoWidthFifoUint64
+  0, // EfiCpuIoWidthFillUint8
+  0, // EfiCpuIoWidthFillUint16
+  0, // EfiCpuIoWidthFillUint32
+  0  // EfiCpuIoWidthFillUint64
+};
+
+/**
+  Check parameters to a CPU I/O 2 Protocol service request.
+
+  The I/O operations are carried out exactly as requested. The caller is 
responsible
+  for satisfying any alignment and I/O width restrictions that a PI System on a
+  platform might require. For example on some platforms, width requests of
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+  be handled by the driver.
+
+  @param[in] MmioOperation  TRUE for an MMIO operation, FALSE for I/O Port 
operation.
+  @param[in] Width  Signifies the width of the I/O or Memory operation.
+  @param[in] AddressThe base address of the I/O operation.
+  @param[in] Count  The number of I/O operations to perform. The 
number of
+bytes moved is Width size * Count, starting at 
Address.
+  @param[in] Buffer For read operations, the destination buffer to 
store the results.
+For write operations, the source buffer from which 
to write data.
+
+  @retval EFI_SUCCESSThe parameters for this request pass the 
checks.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTEDThe Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTEDThe address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+CpuIoCheckParameter (
+  IN BOOLEANMmioOperation,
+  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64 Address,
+  IN UINTN  Count,
+  IN VOID   *Buffer
+  )
+{
+  UINT64  MaxCount;
+  UINT64  Limit;
+
+  //
+  // Check to see if Buffer is NULL
+  //
+  if (Buffer == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Check to see if Width is in the valid range
+  //
+  if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // For FIFO type, the target address won't increase during the access,
+  // so treat Count as 1
+  //
+  if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) 
{
+Count = 1;
+  }
+
+  //
+  // Check to see if Width is in the 

[edk2-devel] [PATCH v6 17/36] ArmVirtPkg: Move PCD of FDT base address and FDT padding to OvmfPkg

[Chao Li]

Moved PcdDeviceTreeInitialBaseAddress and PcdDeviceTreeAllocationPadding
to OvmfPkg for easier use by other architectures.

Build-tested only (with "ArmVirtQemu.dsc").

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Signed-off-by: Chao Li 
Acked-by: Gerd Hoffmann 
Reviewed-by: Sami Mujawar 
---
 ArmVirtPkg/ArmVirtCloudHv.dsc |  2 +-
 ArmVirtPkg/ArmVirtKvmTool.dsc |  2 +-
 ArmVirtPkg/ArmVirtPkg.dec | 14 --
 ArmVirtPkg/ArmVirtQemu.dsc|  2 +-
 ArmVirtPkg/ArmVirtQemuKernel.dsc  |  2 +-
 ArmVirtPkg/ArmVirtXen.dsc |  2 +-
 .../ArmVirtPsciResetSystemPeiLib.inf  |  3 ++-
 .../CloudHvVirtMemInfoPeiLib.inf  |  3 ++-
 .../DebugLibFdtPL011UartFlash.inf |  3 ++-
 .../EarlyFdt16550SerialPortHookLib.inf|  3 ++-
 .../EarlyFdtPL011SerialPortLib.inf|  3 ++-
 .../KvmtoolPlatformPeiLib.inf |  5 +++--
 .../Library/PlatformPeiLib/PlatformPeiLib.inf | 10 +-
 .../QemuVirtMemInfoLib/QemuVirtMemInfoPeiLib.inf  |  3 ++-
 .../PrePi/ArmVirtPrePiUniCoreRelocatable.inf  |  3 ++-
 OvmfPkg/OvmfPkg.dec   | 15 +++
 16 files changed, 42 insertions(+), 33 deletions(-)

diff --git a/ArmVirtPkg/ArmVirtCloudHv.dsc b/ArmVirtPkg/ArmVirtCloudHv.dsc
index 2cb89ce10c..76c0d28544 100644
--- a/ArmVirtPkg/ArmVirtCloudHv.dsc
+++ b/ArmVirtPkg/ArmVirtCloudHv.dsc
@@ -129,7 +129,7 @@
   gArmTokenSpaceGuid.PcdSystemMemoryBase|0x4000
 
   # initial location of the device tree blob passed by Cloud Hypervisor -- 
base of DRAM
-  gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x4000
+  gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x4000
 
   gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
   gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 
0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
diff --git a/ArmVirtPkg/ArmVirtKvmTool.dsc b/ArmVirtPkg/ArmVirtKvmTool.dsc
index f50d53bf15..cac4fe06d3 100644
--- a/ArmVirtPkg/ArmVirtKvmTool.dsc
+++ b/ArmVirtPkg/ArmVirtKvmTool.dsc
@@ -179,7 +179,7 @@
   # We are booting from RAM using the Linux kernel boot protocol,
   # x0 will point to the DTB image in memory.
   #
-  gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0
+  gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0
 
   gArmTokenSpaceGuid.PcdFdBaseAddress|0x0
   gArmTokenSpaceGuid.PcdFvBaseAddress|0x0
diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec
index 313aebda90..05d2d36c1d 100644
--- a/ArmVirtPkg/ArmVirtPkg.dec
+++ b/ArmVirtPkg/ArmVirtPkg.dec
@@ -42,20 +42,6 @@
   gArmVirtTokenSpaceGuid.PcdTpm2SupportEnabled|FALSE|BOOLEAN|0x0004
 
 [PcdsFixedAtBuild, PcdsPatchableInModule]
-  #
-  # This is the physical address where the device tree is expected to be stored
-  # upon first entry into UEFI. This needs to be a FixedAtBuild PCD, so that we
-  # can do a first pass over the device tree in the SEC phase to discover the
-  # UART base address.
-  #
-  gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0|UINT64|0x0001
-
-  #
-  # Padding in bytes to add to the device tree allocation, so that the DTB can
-  # be modified in place (default: 256 bytes)
-  #
-  gArmVirtTokenSpaceGuid.PcdDeviceTreeAllocationPadding|256|UINT32|0x0002
-
   #
   # Binary representation of the GUID that determines the terminal type. The
   # size must be exactly 16 bytes. The default value corresponds to
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 30e3cfc8b9..cf306cac08 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -201,7 +201,7 @@
   gArmTokenSpaceGuid.PcdSystemMemoryBase|0x4000
 
   # initial location of the device tree blob passed by QEMU -- base of DRAM
-  gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x4000
+  gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x4000
 
   gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
   gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 
0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index b50f8e84a3..c0d079e28d 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -198,7 +198,7 @@
   # Define a default initial address for the device tree.
   # Ignored if x0 != 0 at entry.
   #
-  gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x4000
+  gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x4000
 
   gArmTokenSpaceGuid.PcdFdBaseAddress|0x0
   gArmTokenSpaceGuid.PcdFvBaseAddress|0x0

[edk2-devel] [PATCH v6 16/36] EmbeddedPkg: Add PcdPrePiCpuIoSize width for LOONGARCH64

[Chao Li]

Added LoongArch64 architecture CPU IO width.

https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Abner Chang 
Cc: Daniel Schaefer 
Signed-off-by: Chao Li 
Reviewed-by: Leif Lindholm 
---
 EmbeddedPkg/EmbeddedPkg.dec | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec
index b4834e8b4f..5dfbbc2933 100644
--- a/EmbeddedPkg/EmbeddedPkg.dec
+++ b/EmbeddedPkg/EmbeddedPkg.dec
@@ -166,6 +166,9 @@
 [PcdsFixedAtBuild.X64]
   gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16|UINT8|0x0011
 
+[PcdsFixedAtBuild.LOONGARCH64]
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16|UINT8|0x0011
+
 [PcdsFixedAtBuild.common, PcdsDynamic.common]
   #
   # Value to add to a host address to obtain a device address, using
-- 
2.27.0



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[edk2-devel] [PATCH v6 15/36] UefiCpuPkg: Add CpuDxe driver for LoongArch64

[Chao Li]

Added a new DXE driver named CpuDxeLoongArch64.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
Co-authored-by: Baoqi Zhang 
Co-authored-by: Dongyan Qian 
Acked-by: Ray Ni 
---
 UefiCpuPkg/CpuDxeLoongArch64/CpuDxe.c| 414 +
 UefiCpuPkg/CpuDxeLoongArch64/CpuDxe.h| 288 
 UefiCpuPkg/CpuDxeLoongArch64/CpuDxe.inf  |  60 +++
 UefiCpuPkg/CpuDxeLoongArch64/CpuDxe.uni  |  15 +
 UefiCpuPkg/CpuDxeLoongArch64/CpuMp.c | 544 +++
 UefiCpuPkg/CpuDxeLoongArch64/CpuMp.h | 469 +++
 UefiCpuPkg/CpuDxeLoongArch64/Exception.c | 159 +++
 UefiCpuPkg/UefiCpuPkg.dsc|   1 +
 8 files changed, 1950 insertions(+)
 create mode 100644 UefiCpuPkg/CpuDxeLoongArch64/CpuDxe.c
 create mode 100644 UefiCpuPkg/CpuDxeLoongArch64/CpuDxe.h
 create mode 100644 UefiCpuPkg/CpuDxeLoongArch64/CpuDxe.inf
 create mode 100644 UefiCpuPkg/CpuDxeLoongArch64/CpuDxe.uni
 create mode 100644 UefiCpuPkg/CpuDxeLoongArch64/CpuMp.c
 create mode 100644 UefiCpuPkg/CpuDxeLoongArch64/CpuMp.h
 create mode 100644 UefiCpuPkg/CpuDxeLoongArch64/Exception.c

diff --git a/UefiCpuPkg/CpuDxeLoongArch64/CpuDxe.c 
b/UefiCpuPkg/CpuDxeLoongArch64/CpuDxe.c
new file mode 100644
index 00..dd83df96ea
--- /dev/null
+++ b/UefiCpuPkg/CpuDxeLoongArch64/CpuDxe.c
@@ -0,0 +1,414 @@
+/** @file CpuDxe.c
+
+  CPU DXE Module to produce CPU ARCH Protocol.
+
+  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "CpuDxe.h"
+#include "CpuMp.h"
+#include 
+#include 
+#include 
+
+/**
+  IPI Interrupt Handler.
+
+  @param InterruptTypeThe type of interrupt that occurred
+  @param SystemContextA pointer to the system context when the interrupt 
occurred
+**/
+VOID
+EFIAPI
+IpiInterruptHandler (
+  IN EFI_EXCEPTION_TYPE  InterruptType,
+  IN EFI_SYSTEM_CONTEXT  SystemContext
+  );
+
+//
+// Globals used to initialize the protocol
+//
+EFI_HANDLE mCpuHandle = NULL;
+EFI_CPU_ARCH_PROTOCOL  gCpu   = {
+  CpuFlushCpuDataCache,
+  CpuEnableInterrupt,
+  CpuDisableInterrupt,
+  CpuGetInterruptState,
+  CpuInit,
+  CpuRegisterInterruptHandler,
+  CpuGetTimerValue,
+  CpuSetMemoryAttributes,
+  0,  // NumberOfTimers
+  4,  // DmaBufferAlignment
+};
+
+/**
+  This function flushes the range of addresses from Start to Start+Length
+  from the processor's data cache. If Start is not aligned to a cache line
+  boundary, then the bytes before Start to the preceding cache line boundary
+  are also flushed. If Start+Length is not aligned to a cache line boundary,
+  then the bytes past Start+Length to the end of the next cache line boundary
+  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
+  supported. If the data cache is fully coherent with all DMA operations, then
+  this function can just return EFI_SUCCESS. If the processor does not support
+  flushing a range of the data cache, then the entire data cache can be 
flushed.
+
+  @param  This The EFI_CPU_ARCH_PROTOCOL instance.
+  @param  StartThe beginning physical address to flush from the 
processor's data
+   cache.
+  @param  Length   The number of bytes to flush from the processor's 
data cache. This
+   function may flush more bytes than Length specifies 
depending upon
+   the granularity of the flush operation that the 
processor supports.
+  @param  FlushTypeSpecifies the type of flush operation to perform.
+
+  @retval EFI_SUCCESS   The address range from Start to Start+Length 
was flushed from
+the processor's data cache.
+  @retval EFI_INVALID_PARAMETER The processor does not support the cache flush 
type specified
+by FlushType.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+  IN EFI_CPU_ARCH_PROTOCOL  *This,
+  IN EFI_PHYSICAL_ADDRESS   Start,
+  IN UINT64 Length,
+  IN EFI_CPU_FLUSH_TYPE FlushType
+  )
+{
+  switch (FlushType) {
+case EfiCpuFlushTypeWriteBack:
+  WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
+  break;
+case EfiCpuFlushTypeInvalidate:
+  InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
+  break;
+case EfiCpuFlushTypeWriteBackInvalidate:
+  WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
+  break;
+default:
+  return EFI_INVALID_PARAMETER;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  This function enables interrupt processing by the processor.
+
+  @param  This The EFI_CPU_ARCH_PROTOCOL instance.
+
+  @retval EFI_SUCCESS   Interrupts are enabled on the processor.
+  @retval EFI_DEVICE_ERROR  Interrupts could not be enabled on the 
processor.
+

[edk2-devel] [PATCH v6 14/36] UefiCpuPkg: Add multiprocessor library for LoongArch64

[Chao Li]

Added a new library named LoongArch64MpInitLib.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
Acked-by: Ray Ni 
---
 .../LoongArch64MpInitLib/DxeMpInitLib.inf |   45 +
 .../LoongArch64MpInitLib/DxeMpInitLib.uni |   15 +
 .../Library/LoongArch64MpInitLib/DxeMpLib.c   |  480 +
 .../Library/LoongArch64MpInitLib/MpLib.c  | 1596 +
 .../Library/LoongArch64MpInitLib/MpLib.h  |  361 
 .../LoongArch64MpInitLib/PeiMpInitLib.inf |   37 +
 .../LoongArch64MpInitLib/PeiMpInitLib.uni |   15 +
 .../Library/LoongArch64MpInitLib/PeiMpLib.c   |  404 +
 UefiCpuPkg/UefiCpuPkg.dsc |2 +
 9 files changed, 2955 insertions(+)
 create mode 100644 UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpInitLib.inf
 create mode 100644 UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpInitLib.uni
 create mode 100644 UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpLib.c
 create mode 100644 UefiCpuPkg/Library/LoongArch64MpInitLib/MpLib.c
 create mode 100644 UefiCpuPkg/Library/LoongArch64MpInitLib/MpLib.h
 create mode 100644 UefiCpuPkg/Library/LoongArch64MpInitLib/PeiMpInitLib.inf
 create mode 100644 UefiCpuPkg/Library/LoongArch64MpInitLib/PeiMpInitLib.uni
 create mode 100644 UefiCpuPkg/Library/LoongArch64MpInitLib/PeiMpLib.c

diff --git a/UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpInitLib.inf 
b/UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpInitLib.inf
new file mode 100644
index 00..519af41209
--- /dev/null
+++ b/UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpInitLib.inf
@@ -0,0 +1,45 @@
+## @file
+#  LoongArch64 MP initialize support functions for DXE phase.
+#
+#  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[Defines]
+  INF_VERSION= 1.29
+  BASE_NAME  = DxeMpInitLib
+  MODULE_UNI_FILE= DxeMpInitLib.uni
+  FILE_GUID  = C3B9ACAA-B67C-D3E0-E70D-7982B6EA2931
+  MODULE_TYPE= DXE_DRIVER
+  VERSION_STRING = 1.1
+  LIBRARY_CLASS  = MpInitLib|DXE_DRIVER
+
+[Sources.common]
+  DxeMpLib.c
+  MpLib.c
+  MpLib.h
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  CpuLib
+  DebugAgentLib
+  HobLib
+  MemoryAllocationLib
+  SynchronizationLib
+  TimerLib
+  UefiLib
+
+[Protocols]
+  gEfiTimerArchProtocolGuid ## SOMETIMES_CONSUMES
+
+[Pcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber   ## 
CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds ## 
CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds ## 
CONSUMES
diff --git a/UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpInitLib.uni 
b/UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpInitLib.uni
new file mode 100644
index 00..c1c67291a6
--- /dev/null
+++ b/UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpInitLib.uni
@@ -0,0 +1,15 @@
+// /** @file
+// MP Initialize Library instance for DXE driver.
+//
+// MP Initialize Library instance for DXE driver.
+//
+// Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "MP Initialize Library 
instance for DXE driver."
+
+#string STR_MODULE_DESCRIPTION  #language en-US "MP Initialize Library 
instance for DXE driver."
diff --git a/UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpLib.c 
b/UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpLib.c
new file mode 100644
index 00..739da77e32
--- /dev/null
+++ b/UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpLib.c
@@ -0,0 +1,480 @@
+/** @file
+  LoongArch64 MP initialize support functions for DXE phase.
+
+  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "MpLib.h"
+
+#include 
+#include 
+#include 
+
+#include 
+
+CPU_MP_DATA   *mCpuMpData= NULL;
+EFI_EVENT mCheckAllApsEvent  = NULL;
+volatile BOOLEAN  mStopCheckAllApsStatus = TRUE;
+
+/**
+  Enable Debug Agent to support source debugging on AP function.
+
+**/
+VOID
+EnableDebugAgent (
+  VOID
+  )
+{
+  //
+  // Initialize Debug Agent to support source level debug in DXE phase
+  //
+  InitializeDebugAgent (DEBUG_AGENT_INIT_DXE_AP, NULL, NULL);
+}
+
+/**
+  Get the pointer to CPU MP Data structure.
+
+  @return  The pointer to CPU MP Data structure.
+**/
+CPU_MP_DATA *
+GetCpuMpData (
+  VOID
+  )
+{
+  ASSERT (mCpuMpData != NULL);
+  return mCpuMpData;
+}
+
+/**
+  Save the pointer to CPU MP Data structure.
+
+  @param[in] CpuMpData  The pointer to CPU MP Data structure will be saved.
+**/
+VOID
+SaveCpuMpData (
+  IN 

[edk2-devel] [PATCH v6 13/36] UefiCpuPkg: Add LoongArch64CpuMmuLib to UefiCpuPkg

[Chao Li]

Add a new library LoongArch64CpuMmuLib. It provides two-stage MMU library
instances, PEI and DXE.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
Co-authored-by: Baoqi Zhang 
Co-authored-by: Dongyan Qian 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
---
 .../LoongArch64CpuMmuLib/CommonMmuLib.c   | 986 ++
 .../LoongArch64CpuMmuLib/CommonMmuLib.h   |  43 +
 .../LoongArch64CpuMmuLib/DxeCpuMmuLib.inf |  36 +
 .../LoongArch64CpuMmuLib/DxeCpuMmuLib.uni |  14 +
 .../Library/LoongArch64CpuMmuLib/Page.h   | 279 +
 .../LoongArch64CpuMmuLib/PeiCpuMmuLib.c   | 178 
 .../LoongArch64CpuMmuLib/PeiCpuMmuLib.inf |  44 +
 .../LoongArch64CpuMmuLib/PeiCpuMmuLib.uni |  14 +
 UefiCpuPkg/Library/LoongArch64CpuMmuLib/Tlb.h |  48 +
 .../LoongArch64CpuMmuLib/TlbOperation.S   |  44 +
 UefiCpuPkg/UefiCpuPkg.dsc |   2 +
 11 files changed, 1688 insertions(+)
 create mode 100644 UefiCpuPkg/Library/LoongArch64CpuMmuLib/CommonMmuLib.c
 create mode 100644 UefiCpuPkg/Library/LoongArch64CpuMmuLib/CommonMmuLib.h
 create mode 100644 UefiCpuPkg/Library/LoongArch64CpuMmuLib/DxeCpuMmuLib.inf
 create mode 100644 UefiCpuPkg/Library/LoongArch64CpuMmuLib/DxeCpuMmuLib.uni
 create mode 100644 UefiCpuPkg/Library/LoongArch64CpuMmuLib/Page.h
 create mode 100644 UefiCpuPkg/Library/LoongArch64CpuMmuLib/PeiCpuMmuLib.c
 create mode 100644 UefiCpuPkg/Library/LoongArch64CpuMmuLib/PeiCpuMmuLib.inf
 create mode 100644 UefiCpuPkg/Library/LoongArch64CpuMmuLib/PeiCpuMmuLib.uni
 create mode 100644 UefiCpuPkg/Library/LoongArch64CpuMmuLib/Tlb.h
 create mode 100644 UefiCpuPkg/Library/LoongArch64CpuMmuLib/TlbOperation.S

diff --git a/UefiCpuPkg/Library/LoongArch64CpuMmuLib/CommonMmuLib.c 
b/UefiCpuPkg/Library/LoongArch64CpuMmuLib/CommonMmuLib.c
new file mode 100644
index 00..c92f678f3e
--- /dev/null
+++ b/UefiCpuPkg/Library/LoongArch64CpuMmuLib/CommonMmuLib.c
@@ -0,0 +1,986 @@
+/** @file
+
+  CPU Memory Map Unit Handler Library common functions.
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- Pgd or Pgd or PGD- Page Global Directory
+- Pud or Pud or PUD- Page Upper Directory
+- Pmd or Pmd or PMD- Page Middle Directory
+- Pte or pte or PTE- Page Table Entry
+- Val or VAL or val- Value
+- Dir- Directory
+**/
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "Tlb.h"
+#include "Page.h"
+
+#define SWAP_PAGE_DIR  CsrRead(LOONGARCH_CSR_PGDL)
+#define EFI_MEMORY_CACHETYPE_MASK  (EFI_MEMORY_UC  | \
+EFI_MEMORY_WC  | \
+EFI_MEMORY_WT  | \
+EFI_MEMORY_WB  | \
+EFI_MEMORY_UCE   \
+)
+
+BOOLEAN  mMmuInited = FALSE;
+
+/**
+  Check to see if mmu successfully initializes.
+
+  @param  VOID.
+
+  @retval  TRUE  Initialization has been completed.
+   FALSE Initialization did not complete.
+**/
+STATIC
+BOOLEAN
+MmuIsInit (
+  VOID
+  )
+{
+  if (mMmuInited || (SWAP_PAGE_DIR != 0)) {
+return TRUE;
+  }
+
+  return FALSE;
+}
+
+/**
+  Iterates through the page directory to initialize it.
+
+  @param  Dst  A pointer to the directory of the page to initialize.
+  @param  Num  The number of page directories to initialize.
+  @param  Src  A pointer to the data used to initialize the page directory.
+
+  @return VOID.
+**/
+STATIC
+VOID
+PageDirInit (
+  IN VOID   *Dst,
+  IN UINTN  Num,
+  IN VOID   *Src
+  )
+{
+  UINTN  *Ptr;
+  UINTN  *End;
+  UINTN  Entry;
+
+  Entry = (UINTN)Src;
+  Ptr   = (UINTN *)Dst;
+  End   = Ptr + Num;
+
+  for ( ; Ptr < End; Ptr++) {
+*Ptr = Entry;
+  }
+
+  return;
+}
+
+/**
+  Gets the virtual address corresponding to the page global directory table 
entry.
+
+  @param  Address  the virtual address for the table entry.
+
+  @retval PGD A pointer to get the table item.
+**/
+STATIC
+PGD *
+PgdOffset (
+  IN UINTN  Address
+  )
+{
+  return (PGD *)(SWAP_PAGE_DIR) + PGD_INDEX (Address);
+}
+
+/**
+  Gets the virtual address corresponding to the page upper directory table 
entry.
+
+  @param  Pgd  A pointer to a page global directory table entry.
+  @param  Address  the virtual address for the table entry.
+
+  @retval PUD A pointer to get the table item.
+**/
+STATIC
+PUD *
+PudOffset (
+  IN PGD*Pgd,
+  IN UINTN  Address
+  )
+{
+  UINTN  PgdVal;
+
+  PgdVal = (UINTN)PGD_VAL (*Pgd);
+
+  return (PUD *)PgdVal + PUD_INDEX (Address);
+}
+
+/**
+  Gets the virtual address corresponding to the page middle directory table 
entry.
+
+  @param  Pud  A pointer to a page upper directory table entry.
+  @param  Address  the virtual address for the table entry.
+
+  @retval PMD A 

[edk2-devel] [PATCH v6 12/36] UefiCpuPkg: Add CpuMmuLib.h to UefiCpuPkg

[Chao Li]

Add a new header file CpuMmuLib.h, whitch is referenced from
ArmPkg/Include/Library/ArmMmuLib.h. Currently, only support for
LoongArch64 is added, and more architectures can be accommodated in the
future.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Sami Mujawar 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Signed-off-by: Chao Li 
Reviewed-by: Andrei Warkentin 
---
 UefiCpuPkg/Include/Library/CpuMmuLib.h | 62 ++
 UefiCpuPkg/UefiCpuPkg.dec  |  4 ++
 2 files changed, 66 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Library/CpuMmuLib.h

diff --git a/UefiCpuPkg/Include/Library/CpuMmuLib.h 
b/UefiCpuPkg/Include/Library/CpuMmuLib.h
new file mode 100644
index 00..f88ec4eb2e
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/CpuMmuLib.h
@@ -0,0 +1,62 @@
+/** @file
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPU_MMU_LIB_H_
+#define CPU_MMU_LIB_H_
+
+#include 
+
+typedef struct {
+  EFI_PHYSICAL_ADDRESSPhysicalBase;
+  EFI_VIRTUAL_ADDRESS VirtualBase;
+  UINTN   Length;
+  UINTN   Attributes;
+} MEMORY_REGION_DESCRIPTOR;
+
+/**
+  Finds the first of the length and memory properties of the memory region 
corresponding
+  to the specified base address.
+
+  @param[in]   BaseAddress   To find the base address of the memory 
region.
+  @param[in, out]  RegionLength  Pointer holding:
+  - At entry, the length of the memory 
region
+expected to be found.
+  - At exit, the length of the memory 
region found.
+  @param[out]  RegionAttributes  Properties of the memory region found.
+
+  @retval  EFI_SUCCESSThe corresponding memory area was successfully found
+   EFI_NOT_FOUNDNo memory area found
+**/
+EFI_STATUS
+EFIAPI
+GetMemoryRegionAttributes (
+  IN UINTN  BaseAddress,
+  IN OUT UINTN  *RegionLength,
+  OUTUINTN  *RegionAttributes
+  );
+
+/**
+  Sets the Attributes  of the specified memory region.
+
+  @param[in]  BaseAddressThe base address of the memory region to set the 
Attributes.
+  @param[in]  Length The length of the memory region to set the 
Attributes.
+  @param[in]  Attributes The Attributes to be set.
+  @param[in]  AttributeMask  Mask of memory attributes to take into account.
+
+  @retval  EFI_SUCCESSThe Attributes was set successfully
+**/
+EFI_STATUS
+EFIAPI
+SetMemoryRegionAttributes (
+  IN EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN UINTN Length,
+  IN UINTN Attributes,
+  IN UINT64AttributeMask
+  );
+
+#endif // CPU_MMU_LIB_H_
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 84f61254bb..9b11a3da72 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -62,6 +62,10 @@
   ##  @libraryclass  Provides function for manipulating x86 paging structures.
   CpuPageTableLib|Include/Library/CpuPageTableLib.h
 
+[LibraryClasses.LoongArch64]
+  ##  @libraryclass  Provides macros and functions for the memory management 
unit.
+  CpuMmuLib|Include/Library/CpuMmuLib.h
+
   ## @libraryclass   Provides functions for manipulating smram savestate 
registers.
   MmSaveStateLib|Include/Library/MmSaveStateLib.h
 
-- 
2.27.0



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[edk2-devel] [PATCH v6 11/36] UefiCpuPkg: Add CPU exception library for LoongArch

[Chao Li]

Added a new library named LoongArch64CpuExceptionHandlerLib, and
modified the way LoongArch exceptions are expressed.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Signed-off-by: Chao Li 
Co-authored-by: Baoqi Zhang 
Acked-by: Ray Ni 
---
 MdePkg/Include/Protocol/DebugSupport.h|  14 +
 .../DxeCpuExceptionHandlerLib.inf |  45 +++
 .../DxeCpuExceptionHandlerLib.uni |  15 +
 .../DxeExceptionLib.c | 198 +++
 .../ExceptionCommon.c | 229 +
 .../ExceptionCommon.h | 131 +++
 .../LoongArch64/ArchExceptionHandler.c| 213 
 .../LoongArch64/ExceptionHandlerAsm.S | 320 ++
 .../SecPeiCpuExceptionHandlerLib.inf  |  45 +++
 .../SecPeiCpuExceptionHandlerLib.uni  |  15 +
 .../SecPeiExceptionLib.c  | 102 ++
 UefiCpuPkg/UefiCpuPkg.dec |   6 +
 UefiCpuPkg/UefiCpuPkg.dsc |   2 +
 13 files changed, 1335 insertions(+)
 create mode 100644 
UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
 create mode 100644 
UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.uni
 create mode 100644 
UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/DxeExceptionLib.c
 create mode 100644 
UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/ExceptionCommon.c
 create mode 100644 
UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/ExceptionCommon.h
 create mode 100644 
UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/LoongArch64/ArchExceptionHandler.c
 create mode 100644 
UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/LoongArch64/ExceptionHandlerAsm.S
 create mode 100644 
UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
 create mode 100644 
UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.uni
 create mode 100644 
UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/SecPeiExceptionLib.c

diff --git a/MdePkg/Include/Protocol/DebugSupport.h 
b/MdePkg/Include/Protocol/DebugSupport.h
index 9742663619..06f99ba7f7 100644
--- a/MdePkg/Include/Protocol/DebugSupport.h
+++ b/MdePkg/Include/Protocol/DebugSupport.h
@@ -683,6 +683,20 @@ typedef struct {
 //
 // LoongArch processor exception types.
 //
+// The exception types is located in the CSR ESTAT
+// register offset 16 bits, width 6 bits.
+//
+// If you want to register an exception hook, you can
+// shfit the number left by 16 bits, and the exception
+// handler will know the types.
+//
+// For example:
+// mCpu->CpuRegisterInterruptHandler (
+// mCpu,
+// (EXCEPT_LOONGARCH_PPI << CSR_ESTAT_EXC_SHIFT),
+// PpiExceptionHandler
+// );
+//
 #define EXCEPT_LOONGARCH_INT   0
 #define EXCEPT_LOONGARCH_PIL   1
 #define EXCEPT_LOONGARCH_PIS   2
diff --git 
a/UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
 
b/UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
new file mode 100644
index 00..0ce8abe98d
--- /dev/null
+++ 
b/UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -0,0 +1,45 @@
+## @file
+#  LoongArch exception library instance for DXE modules.
+#
+#  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 1.29
+  BASE_NAME  = DxeCpuExceptionHandlerLib
+  MODULE_UNI_FILE= DxeCpuExceptionHandlerLib.uni
+  FILE_GUID  = 23C5D29F-F54B-091B-BD94-027576ED09FA
+  MODULE_TYPE= DXE_DRIVER
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = CpuExceptionHandlerLib|DXE_CORE DXE_DRIVER 
UEFI_APPLICATION
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+#  VALID_ARCHITECTURES   = LOONGARCH64
+#
+
+[Sources.LoongArch64]
+  LoongArch64/ArchExceptionHandler.c
+  LoongArch64/ExceptionHandlerAsm.S | GCC
+
+[Sources]
+  DxeExceptionLib.c
+  ExceptionCommon.h
+  ExceptionCommon.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  CpuLib
+  PeCoffGetEntryPointLib
+  PrintLib
+  SerialPortLib
+  SynchronizationLib
diff --git 
a/UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.uni
 
b/UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.uni
new file mode 100644
index 00..25b1593666
--- /dev/null
+++ 
b/UefiCpuPkg/Library/LoongArch64CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.uni
@@ -0,0 +1,15 @@
+// /** @file
+// CPU Exception Handler library 

[edk2-devel] [PATCH v6 10/36] UefiCpuPkg: Add LoongArch64 CPU Timer library

[Chao Li]

Add the LoongArch64 CPU Timer library, using CPUCFG 0x4 and 0x5 for
Stable Counter frequency.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
Acked-by: Ray Ni 
---
 .../BaseLoongArch64CpuTimerLib.inf|  29 ++
 .../BaseLoongArch64CpuTimerLib.uni|  15 ++
 .../BaseLoongArch64CpuTimerLib/CpuTimerLib.c  | 251 ++
 UefiCpuPkg/UefiCpuPkg.dsc |   3 +
 4 files changed, 298 insertions(+)
 create mode 100644 
UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.inf
 create mode 100644 
UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.uni
 create mode 100644 UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c

diff --git 
a/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.inf 
b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.inf
new file mode 100644
index 00..8648cc2a57
--- /dev/null
+++ 
b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.inf
@@ -0,0 +1,29 @@
+## @file
+#  Base CPU Timer Library
+#
+#  Provides base timer support using CPUCFG 0x4 and 0x5 stable counter 
frequency.
+#
+#  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION   = 0x00010029
+  BASE_NAME = BaseLoongArch64CpuTimerLib
+  FILE_GUID = 740389C7-CC44-4A2F-88DC-89D97D312E7C
+  MODULE_TYPE   = BASE
+  VERSION_STRING= 1.0
+  LIBRARY_CLASS = TimerLib
+  MODULE_UNI_FILE   = BaseLoongArch64CpuTimerLib.uni
+
+[Sources]
+  CpuTimerLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  SafeIntLib
diff --git 
a/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.uni 
b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.uni
new file mode 100644
index 00..f66e96e972
--- /dev/null
+++ 
b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.uni
@@ -0,0 +1,15 @@
+// /** @file
+// Base CPU Timer Library
+//
+// Provides base timer support using CPUCFG 0x4 and 0x5 stable counter 
frequency.
+//
+// Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "LOONGARCH CPU Timer 
Library"
+
+#string STR_MODULE_DESCRIPTION  #language en-US "Provides basic timer 
support using CPUCFG 0x4 and 0x5 stable counter frequency."
diff --git a/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c 
b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c
new file mode 100644
index 00..a5ae8d0185
--- /dev/null
+++ b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c
@@ -0,0 +1,251 @@
+/** @file
+  CPUCFG 0x4 and 0x5 for Stable Counter frequency instance of Timer Library.
+
+  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Calculate clock frequency using CPUCFG 0x4 and 0x5 registers.
+
+  @param  VOID.
+
+  @return The frequency in Hz.
+
+**/
+STATIC
+UINT64
+CalcConstFreq (
+  VOID
+  )
+{
+  UINT32 BaseFreq;
+  UINT64 ClockMultiplier;
+  UINT32 ClockDivide;
+  CPUCFG_REG4_INFO_DATA  CcFreq;
+  CPUCFG_REG5_INFO_DATA  CpucfgReg5Data;
+  UINT64 StableTimerFreq;
+
+  //
+  // Get the the crystal frequency corresponding to the constant
+  // frequency timer and the clock used by the timer.
+  //
+  AsmCpucfg (CPUCFG_REG4_INFO, );
+
+  //
+  // Get the multiplication factor and frequency division factor
+  // corresponding to the constant frequency timer and the clock
+  // used by the timer.
+  //
+  AsmCpucfg (CPUCFG_REG5_INFO, );
+
+  BaseFreq= CcFreq.Bits.CC_FREQ;
+  ClockMultiplier = CpucfgReg5Data.Bits.CC_MUL & 0x;
+  ClockDivide = CpucfgReg5Data.Bits.CC_DIV & 0x;
+
+  if ((BaseFreq == 0x0) || (ClockMultiplier == 0x0) || (ClockDivide == 0x0)) {
+DEBUG ((
+  DEBUG_ERROR,
+  "LoongArch Stable Timer is not available in the CPU, hence this library 
cannot be used.\n"
+  ));
+ASSERT (FALSE);
+CpuDeadLoop ();
+  }
+
+  StableTimerFreq = ((ClockMultiplier * BaseFreq) / ClockDivide);
+
+  if (StableTimerFreq == 0x0) {
+ASSERT (FALSE);
+  }
+
+  return StableTimerFreq;
+}
+
+/**
+  Stalls the CPU for at least the given number of microseconds.
+
+  Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+  @param  MicroSeconds  The minimum number of microseconds to 

[edk2-devel] [PATCH v6 09/36] MdePkg: Add a new library named PeiServicesTablePointerLibKs0

[Chao Li]

Adding PeiServicesTablePointerLibKs0 for LoongArch64, which provides
setting and getting the PEI service table pointer through the CSR KS0
register.

The idea of this library is derived from
ArmPkg/Library/PeiServicesTablePointerLib/

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Laszlo Ersek 
Signed-off-by: Chao Li 
---
 .../Library/PeiServicesTablePointerLib.h  |  9 +-
 .../PeiServicesTablePointer.c | 87 +++
 .../PeiServicesTablePointerLibKs0.inf | 37 
 .../PeiServicesTablePointerLibKs0.uni | 20 +
 MdePkg/MdePkg.dsc |  3 +
 5 files changed, 152 insertions(+), 4 deletions(-)
 create mode 100644 
MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
 create mode 100644 
MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.inf
 create mode 100644 
MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.uni

diff --git a/MdePkg/Include/Library/PeiServicesTablePointerLib.h 
b/MdePkg/Include/Library/PeiServicesTablePointerLib.h
index 61635eff00..f85c38363c 100644
--- a/MdePkg/Include/Library/PeiServicesTablePointerLib.h
+++ b/MdePkg/Include/Library/PeiServicesTablePointerLib.h
@@ -52,10 +52,11 @@ SetPeiServicesTablePointer (
   immediately preceding the Interrupt Descriptor Table (IDT) in memory.
   For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
   immediately preceding the Interrupt Descriptor Table (IDT) in memory.
-  For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
-  a dedicated CPU register.  This means that there is no memory storage
-  associated with storing the PEI Services Table pointer, so no additional
-  migration actions are required for Itanium or ARM CPUs.
+  For Itanium, ARM and LoongArch CPUs, a the PEI Services Table Pointer
+  is stored in a dedicated CPU register.  This means that there is no
+  memory storage associated with storing the PEI Services Table pointer,
+  so no additional migration actions are required for Itanium, ARM and
+  LoongArch CPUs.
 
 **/
 VOID
diff --git 
a/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c 
b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
new file mode 100644
index 00..f9800936b2
--- /dev/null
+++ b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
@@ -0,0 +1,87 @@
+/** @file
+  PEI Services Table Pointer Library For Reigseter Mechanism.
+
+  This library is used for PEIM which does executed from flash device directly 
but
+  executed in memory.
+
+  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+  Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserved.
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Caches a pointer PEI Services Table.
+
+  Caches the pointer to the PEI Services Table specified by 
PeiServicesTablePointer
+  in a platform specific manner.
+
+  If PeiServicesTablePointer is NULL, then ASSERT().
+
+  @paramPeiServicesTablePointer   The address of PeiServices pointer.
+**/
+VOID
+EFIAPI
+SetPeiServicesTablePointer (
+  IN CONST EFI_PEI_SERVICES  **PeiServicesTablePointer
+  )
+{
+  ASSERT (PeiServicesTablePointer != NULL);
+  CsrWrite (LOONGARCH_CSR_KS0, (UINTN)PeiServicesTablePointer);
+}
+
+/**
+  Retrieves the cached value of the PEI Services Table pointer.
+
+  Returns the cached value of the PEI Services Table pointer in a CPU specific 
manner
+  as specified in the CPU binding section of the Platform Initialization 
Pre-EFI
+  Initialization Core Interface Specification.
+
+  If the cached PEI Services Table pointer is NULL, then ASSERT().
+
+  @return  The pointer to PeiServices.
+
+**/
+CONST EFI_PEI_SERVICES **
+EFIAPI
+GetPeiServicesTablePointer (
+  VOID
+  )
+{
+  CONST EFI_PEI_SERVICES  **PeiServices;
+
+  PeiServices = (CONST EFI_PEI_SERVICES **)(CsrRead (LOONGARCH_CSR_KS0));
+  ASSERT (PeiServices != NULL);
+  return PeiServices;
+}
+
+/**
+  Perform CPU specific actions required to migrate the PEI Services Table
+  pointer from temporary RAM to permanent RAM.
+
+  For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
+  immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+  For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
+  immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+  For Itanium, ARM and LoongArch CPUs, a the PEI Services Table Pointer
+  is stored in a dedicated CPU register.  This means that there is no
+  memory storage associated with storing the PEI Services Table pointer,
+  so no additional migration actions are required for Itanium, ARM and
+  LoongArch CPUs.
+
+**/
+VOID
+EFIAPI

[edk2-devel] [PATCH v6 08/36] MdePkg: Add IOCSR operation for LoongArch

[Chao Li]

Add IoCsrRead8, IoCsrRead16, IoCsrRead32, IoCsrRead64, IoCsrWrite8,
IoCsrWrite16, IoCsrWrite32, IoCsrWrite64 to operate the IOCSR registers
of LoongArch architecture.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Signed-off-by: Chao Li 
Acked-by: Michael D Kinney 
---
 MdePkg/Include/Library/BaseLib.h   | 112 +++
 MdePkg/Library/BaseLib/BaseLib.inf |   1 +
 MdePkg/Library/BaseLib/LoongArch64/IoCsr.S | 120 +
 3 files changed, 233 insertions(+)
 create mode 100644 MdePkg/Library/BaseLib/LoongArch64/IoCsr.S

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index beba66e1a3..aa5204682f 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -391,6 +391,118 @@ CsrXChg (
   IN UINTN   Mask
   );
 
+/**
+  IO CSR read byte operation.
+
+  @param[in]  Select   IO CSR read instruction select values.
+
+  @return The return value of iocsrrd.b instruction.
+
+**/
+UINT8
+IoCsrRead8 (
+  IN UINTN  Select
+  );
+
+/**
+  IO CSR read half word operation.
+
+  @param[in]  Select   IO CSR read instruction select values.
+
+  @return The return value of iocsrrd.h instruction.
+
+**/
+UINT16
+IoCsrRead16 (
+  IN UINTN  Select
+  );
+
+/**
+  IO CSR read word operation.
+
+  @param[in]  Select   IO CSR read instruction select values.
+
+  @return The return value of iocsrrd.w instruction.
+
+**/
+UINT32
+IoCsrRead32 (
+  IN UINTN  Select
+  );
+
+/**
+  IO CSR read double word operation. Only for LoongArch64.
+
+  @param[in]  Select   IO CSR read instruction select values.
+
+  @return The return value of iocsrrd.d instruction.
+
+**/
+UINT64
+IoCsrRead64 (
+  IN UINTN  Select
+  );
+
+/**
+  IO CSR write byte operation.
+
+  @param[in]  Select   IO CSR write instruction select values.
+  @param[in]  ValueThe iocsrwr.b will write the value.
+
+  @return VOID.
+
+**/
+VOID
+IoCsrWrite8 (
+  IN UINTN  Select,
+  IN UINT8  Value
+  );
+
+/**
+  IO CSR write half word operation.
+
+  @param[in]  Select   IO CSR write instruction select values.
+  @param[in]  ValueThe iocsrwr.h will write the value.
+
+  @return VOID.
+
+**/
+VOID
+IoCsrWrite16 (
+  IN UINTN   Select,
+  IN UINT16  Value
+  );
+
+/**
+  IO CSR write word operation.
+
+  @param[in]  Select   IO CSR write instruction select values.
+  @param[in]  ValueThe iocsrwr.w will write the value.
+
+  @return VOID.
+
+**/
+VOID
+IoCsrWrite32 (
+  IN UINTN   Select,
+  IN UINT32  Value
+  );
+
+/**
+  IO CSR write double word operation. Only for LoongArch64.
+
+  @param[in]  Select   IO CSR write instruction select values.
+  @param[in]  ValueThe iocsrwr.d will write the value.
+
+  @return VOID.
+
+**/
+VOID
+IoCsrWrite64 (
+  IN UINTN   Select,
+  IN UINT64  Value
+  );
+
 #endif // defined (MDE_CPU_LOONGARCH64)
 
 //
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index ebee563794..254d5837c4 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -412,6 +412,7 @@
   LoongArch64/Csr.c
   LoongArch64/InternalSwitchStack.c
   LoongArch64/AsmCsr.S  | GCC
+  LoongArch64/IoCsr.S   | GCC
   LoongArch64/GetInterruptState.S   | GCC
   LoongArch64/EnableInterrupts.S| GCC
   LoongArch64/DisableInterrupts.S   | GCC
diff --git a/MdePkg/Library/BaseLib/LoongArch64/IoCsr.S 
b/MdePkg/Library/BaseLib/LoongArch64/IoCsr.S
new file mode 100644
index 00..a659908bc4
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/IoCsr.S
@@ -0,0 +1,120 @@
+#--
+#
+# LoongArch ASM IO CSR operation functions
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#--
+
+ASM_GLOBAL ASM_PFX (IoCsrRead8)
+ASM_GLOBAL ASM_PFX (IoCsrRead16)
+ASM_GLOBAL ASM_PFX (IoCsrRead32)
+ASM_GLOBAL ASM_PFX (IoCsrRead64)
+
+ASM_GLOBAL ASM_PFX (IoCsrWrite8)
+ASM_GLOBAL ASM_PFX (IoCsrWrite16)
+ASM_GLOBAL ASM_PFX (IoCsrWrite32)
+ASM_GLOBAL ASM_PFX (IoCsrWrite64)
+
+#/**
+#  IO CSR read byte operation.
+#
+#  @param[in]  Select   IO CSR read instruction select values.
+#
+#  @return The return value of iocsrrd.b instruction.
+#
+#**/
+ASM_PFX (IoCsrRead8):
+  iocsrrd.b   $a0, $a0
+  jirl$zero, $ra, 0
+
+#/**
+#  IO CSR read half word operation.
+#
+#  @param[in]  Select   IO CSR read instruction select values.
+#
+#  @return The return value of iocsrrd.h instruction.
+#
+#**/
+ASM_PFX (IoCsrRead16):
+  iocsrrd.h   $a0, $a0
+  jirl$zero, $ra, 0
+
+#/**
+#  IO CSR read word operation.
+#
+#  @param[in]  Select   IO CSR read instruction select values.
+#
+#  @return The return value of iocsrrd.w instruction.
+#
+#**/
+ASM_PFX 

[edk2-devel] [PATCH v6 07/36] MdePkg: Add CSR operation for LoongArch

[Chao Li]

Add CsrRead, CsrWrite and CsrXChg functions for LoongArch, and use them
to operate the CSR register of LoongArch architecture.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Signed-off-by: Chao Li 
Co-authored-by: Bibo Mao 
Acked-by: Michael D Kinney 
---
 MdePkg/Include/Library/BaseLib.h|  45 +++
 MdePkg/Library/BaseLib/BaseLib.inf  |   2 +
 MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S | 422 
 MdePkg/Library/BaseLib/LoongArch64/Csr.c|  81 
 4 files changed, 550 insertions(+)
 create mode 100644 MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
 create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Csr.c

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index a5f0ec6ca4..beba66e1a3 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -346,6 +346,51 @@ AsmReadStableCounter (
   VOID
   );
 
+/**
+  CSR read operation.
+
+  @param[in]  Select   CSR read instruction select values.
+
+  @return The return value of csrrd instruction, return -1 means no CSR 
instruction
+  is found.
+**/
+UINTN
+CsrRead (
+  IN UINT16  Select
+  );
+
+/**
+  CSR write operation.
+
+  @param[in]  Select   CSR write instruction select values.
+  @param[in]  ValueThe csrwr will write the value.
+
+  @return The return value of csrwr instruction, that is, store the old 
value of
+  the register, return -1 means no CSR instruction is found.
+**/
+UINTN
+CsrWrite (
+  IN UINT16  Select,
+  IN UINTN   Value
+  );
+
+/**
+  CSR exchange operation.
+
+  @param[in]  Select   CSR exchange instruction select values.
+  @param[in]  ValueThe csrxchg will write the value.
+  @param[in]  Mask The csrxchg mask value.
+
+  @return The return value of csrxchg instruction, that is, store the old 
value of
+  the register, return -1 means no CSR instruction is found.
+**/
+UINTN
+CsrXChg (
+  IN UINT16  Select,
+  IN UINTN   Value,
+  IN UINTN   Mask
+  );
+
 #endif // defined (MDE_CPU_LOONGARCH64)
 
 //
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index a13734af52..ebee563794 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -409,7 +409,9 @@
 [Sources.LOONGARCH64]
   Math64.c
   Unaligned.c
+  LoongArch64/Csr.c
   LoongArch64/InternalSwitchStack.c
+  LoongArch64/AsmCsr.S  | GCC
   LoongArch64/GetInterruptState.S   | GCC
   LoongArch64/EnableInterrupts.S| GCC
   LoongArch64/DisableInterrupts.S   | GCC
diff --git a/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S 
b/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
new file mode 100644
index 00..3a879411f5
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
@@ -0,0 +1,422 @@
+#--
+#
+# LoongArch ASM CSR operation functions
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#--
+
+#include 
+
+ASM_GLOBAL ASM_PFX (AsmCsrRead)
+ASM_GLOBAL ASM_PFX (AsmCsrWrite)
+ASM_GLOBAL ASM_PFX (AsmCsrXChg)
+
+.macro AsmCsrRd Sel
+  csrrd   $a0, \Sel
+  jirl$zero, $ra, 0
+.endm
+
+.macro AsmCsrWr Sel
+  csrwr   $a0, \Sel
+  jirl$zero, $ra, 0
+.endm
+
+.macro AsmCsrXChange Sel
+  csrxchg $a0, $a1, \Sel
+  jirl$zero, $ra, 0
+.endm
+
+ASM_PFX(AsmCsrRead):
+  blt  $a0, $zero, ReadSelNumErr
+  li.w $t0, LOONGARCH_CSR_EBASE
+  bltu $t0, $a0, TlbCsrRd
+
+BasicCsrRd:
+  la.pcrel $t0, BasicCsrRead
+  alsl.d   $t0, $a0, $t0, 3
+  jirl $zero, $t0, 0
+
+TlbCsrRd:
+  li.w $t0, LOONGARCH_CSR_TLBIDX
+  bltu $a0, $t0, ReadSelNumErr
+  li.w $t0, LOONGARCH_CSR_RVACFG
+  bltu $t0, $a0, CfgCsrRd
+  la.pcrel $t0, TlbCsrRead
+  addi.w   $t1, $a0, -LOONGARCH_CSR_TLBIDX
+  alsl.d   $t0, $t1, $t0, 3
+  jirl $zero, $t0, 0
+
+CfgCsrRd:
+  li.w $t0, LOONGARCH_CSR_CPUNUM
+  bltu $a0, $t0, ReadSelNumErr
+  li.w $t0, LOONGARCH_CSR_PRCFG3
+  bltu $t0, $a0, KcsCsrRd
+  la.pcrel $t0, CfgCsrRead
+  addi.w   $t1, $a0, -LOONGARCH_CSR_CPUNUM
+  alsl.d   $t0, $t1, $t0, 3
+  jirl $zero, $t0, 0
+
+KcsCsrRd:
+  li.w $t0, LOONGARCH_CSR_KS0
+  bltu $a0, $t0, ReadSelNumErr
+  li.w $t0, LOONGARCH_CSR_KS8
+  bltu $t0, $a0, StableTimerCsrRd
+  la.pcrel $t0, KcsCsrRead
+  addi.w   $t1, $a0, -LOONGARCH_CSR_KS0
+  alsl.d   $t0, $t1, $t0, 3
+  jirl $zero, $t0, 0
+
+StableTimerCsrRd:
+  li.w $t0, LOONGARCH_CSR_TMID
+  bltu $a0, $t0, ReadSelNumErr
+  li.w $t0, LOONGARCH_CSR_TINTCLR
+  bltu $t0, $a0, TlbRefillCsrRd
+  la.pcrel $t0, StableTimerCsrRead
+  addi.w   $t1, $a0, -LOONGARCH_CSR_TMID
+  alsl.d   $t0, $t1, $t0, 3
+  jirl $zero, $t0, 0
+
+TlbRefillCsrRd:
+  li.w $t0, 

[edk2-devel] [PATCH v6 06/36] MdePkg: Add read stable counter operation for LoongArch

[Chao Li]

Add LoongArch gets stable counter ASM function.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Signed-off-by: Chao Li 
Acked-by: Michael D Kinney 
---
 MdePkg/Include/Library/BaseLib.h  | 12 ++
 MdePkg/Library/BaseLib/BaseLib.inf|  1 +
 .../BaseLib/LoongArch64/ReadStableCounter.S   | 24 +++
 3 files changed, 37 insertions(+)
 create mode 100644 MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index f99bbd2e17..a5f0ec6ca4 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -334,6 +334,18 @@ AsmCpucfg (
   OUT UINT32  *Data
   );
 
+/**
+  Gets the timer count value.
+
+  @param[] VOID
+  @retval  timer count value.
+
+**/
+UINTN
+AsmReadStableCounter (
+  VOID
+  );
+
 #endif // defined (MDE_CPU_LOONGARCH64)
 
 //
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index 64c4671297..a13734af52 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -421,6 +421,7 @@
   LoongArch64/SwitchStack.S | GCC
   LoongArch64/ExceptionBase.S   | GCC
   LoongArch64/Cpucfg.S  | GCC
+  LoongArch64/ReadStableCounter.S   | GCC
 
 [Packages]
   MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S 
b/MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S
new file mode 100644
index 00..aa74ff603e
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S
@@ -0,0 +1,24 @@
+#--
+#
+# LoongArch Read Stable Counter
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#--
+
+ASM_GLOBAL ASM_PFX(AsmReadStableCounter)
+
+#/**
+#  Gets the timer count value.
+#
+#  @param[] VOID
+#  @retval  timer count value.
+#
+#**/
+
+ASM_PFX(AsmReadStableCounter):
+  rdtime.d   $a0, $zero
+  jirl   $zero, $ra, 0
+  .end
-- 
2.27.0



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[edk2-devel] [PATCH v6 05/36] MdePkg: Add LoongArch Cpucfg function

[Chao Li]

Add LoongArch AsmCpucfg function and Cpucfg definitions.

Also added Include/Register/LoongArch64/Cpucfg.h to IgnoreFiles of
EccCheck.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Signed-off-by: Chao Li 
Acked-by: Michael D Kinney 
---
 MdePkg/Include/Library/BaseLib.h |  12 +
 MdePkg/Include/Register/LoongArch64/Cpucfg.h | 565 +++
 MdePkg/Library/BaseLib/BaseLib.inf   |   1 +
 MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S  |  26 +
 MdePkg/MdePkg.ci.yaml|   3 +-
 5 files changed, 606 insertions(+), 1 deletion(-)
 create mode 100644 MdePkg/Include/Register/LoongArch64/Cpucfg.h
 create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index e1986fc3a1..f99bbd2e17 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -322,6 +322,18 @@ DisableLocalInterrupts (
   IN UINT16
   );
 
+/**
+  Read CPUCFG register.
+
+  @param  Index  Specifies the register number of the CPUCFG to read the data.
+  @param  Data   A pointer to the variable used to store the CPUCFG register 
value.
+**/
+VOID
+AsmCpucfg (
+  IN  UINT32  Index,
+  OUT UINT32  *Data
+  );
+
 #endif // defined (MDE_CPU_LOONGARCH64)
 
 //
diff --git a/MdePkg/Include/Register/LoongArch64/Cpucfg.h 
b/MdePkg/Include/Register/LoongArch64/Cpucfg.h
new file mode 100644
index 00..570748b194
--- /dev/null
+++ b/MdePkg/Include/Register/LoongArch64/Cpucfg.h
@@ -0,0 +1,565 @@
+/** @file
+  CPUCFG definitions.
+
+  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef CPUCFG_H_
+#define CPUCFG_H_
+
+/**
+  CPUCFG REG0 Information
+
+  @code
+  CPUCFG_REG0_INFO_DATA
+ **/
+#define CPUCFG_REG0_INFO  0x0
+
+/**
+  CPUCFG REG0 Information returned data.
+  #CPUCFG_REG0_INFO
+ **/
+typedef union {
+  struct {
+///
+/// [Bit 31:0] Processor Identity.
+///
+UINT32PRID : 32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32Uint32;
+} CPUCFG_REG0_INFO_DATA;
+
+/**
+  CPUCFG REG1 Information
+
+  @code
+  CPUCFG_REG1_INFO_DATA
+ **/
+#define CPUCFG_REG1_INFO  0x1
+
+/**
+  CPUCFG REG1 Information returned data.
+  #CPUCFG_REG1_INFO
+ **/
+typedef union {
+  struct {
+///
+/// [Bit 1:0] Architecture:
+///   2'b00 indicates the implementation of simplified 
LoongAarch32;
+///   2'b01 indicates the implementation of LoongAarch32;
+///   2'b10 indicates the implementation of LoongAarch64;
+///   2'b11 reserved;
+///
+UINT32ARCH  : 2;
+///
+/// [Bit 2] Paging mapping mode. A value of 1 indicates the processor MMU 
supports
+/// page mapping mode.
+///
+UINT32PGMMU : 1;
+///
+/// [Bit 3] A value of 1 indicates the processor supports the IOCSR 
instruction.
+///
+UINT32IOCSR : 1;
+///
+/// [Bit 11:4] Physical address bits. The supported physical address bits 
PALEN value
+/// minus 1.
+///
+UINT32PALEN : 8;
+///
+/// [Bit 19:12] Virtual address bits. The supported virtual address bits 
VALEN value
+/// minus 1.
+///
+UINT32VALEN : 8;
+///
+/// [Bit 20] Non-aligned Memory Access. A value of 1 indicates the 
processor supports
+/// non-aligned memory access.
+///
+UINT32UAL   : 1;
+///
+/// [Bit 21] Page Read Inhibit. A value of 1 indicates the processor 
supports page
+/// attribute of "Read Inhibit".
+///
+UINT32RI: 1;
+///
+/// [Bit 22] Page Execution Protection. A value of 1 indicates the 
processor supports
+/// page attribute of "Execution Protection".
+///
+UINT32EP: 1;
+///
+/// [Bit 23] A value of 1 indicates the processor supports for page 
attributes of RPLV.
+///
+UINT32RPLV  : 1;
+///
+/// [Bit 24] Huge Page. A value of 1 indicates the processor supports page 
attribute
+/// of huge page.
+///
+UINT32HP: 1;
+///
+/// [Bit 25] A value of 1 indicates that the string of processor product 
information
+/// is recorded at address 0 of the IOCSR access space.
+///
+UINT32IOCSR_BRD : 1;
+///
+/// [Bit 26] A value of 1 indicates that the external interrupt uses the 
message
+/// interrupt mode, otherwise it is the level interrupt line mode.
+///
+UINT32MSG_INT   : 1;
+///
+/// [Bit 31:27] Reserved.
+///
+UINT32Reserved  : 5;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32Uint32;
+} CPUCFG_REG1_INFO_DATA;
+
+/**
+  CPUCFG REG2 Information
+
+  @code
+  CPUCFG_REG2_INFO_DATA
+ **/
+#define CPUCFG_REG2_INFO  0x2
+
+/**
+  CPUCFG REG2 Information returned data.
+  

[edk2-devel] [PATCH v6 04/36] MdePkg: Add LoongArch64 local interrupt function set into BaseLib

[Chao Li]

Adding LoongArch local interrupt function set, which is used to control
the opening or closing of the local interrupt when the global interrupt
is enabled.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Signed-off-by: Chao Li 
Acked-by: Michael D Kinney 
---
 MdePkg/Include/Library/BaseLib.h  | 20 +
 .../BaseLib/LoongArch64/DisableInterrupts.S   | 22 ++-
 .../BaseLib/LoongArch64/EnableInterrupts.S| 22 ++-
 3 files changed, 54 insertions(+), 10 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 152e95f34d..e1986fc3a1 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -302,6 +302,26 @@ SetTlbRebaseAddress (
   IN UINT64
   );
 
+/**
+  Enables local CPU interrupts.
+
+  @param  Needs to enable local interrupt bit.
+**/
+VOID
+EnableLocalInterrupts (
+  IN UINT16
+  );
+
+/**
+  Disables local CPU interrupts.
+
+  @param  Needs to disable local interrupt bit.
+**/
+VOID
+DisableLocalInterrupts (
+  IN UINT16
+  );
+
 #endif // defined (MDE_CPU_LOONGARCH64)
 
 //
diff --git a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S 
b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
index 0f228339af..8f9ee888b1 100644
--- a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
+++ b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
@@ -1,21 +1,33 @@
 #--
 #
-# LoongArch interrupt disable
+# LoongArch interrupt disable operations
 #
-# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights 
reserved.
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 #--
 
+#include 
+#include 
+
+ASM_GLOBAL ASM_PFX(DisableLocalInterrupts)
 ASM_GLOBAL ASM_PFX(DisableInterrupts)
 
 #/**
-#  Disables CPU interrupts.
+#  Disables local CPU interrupts.
+#
+#  @param  Needs to disable local interrupt bit.
 #**/
+ASM_PFX(DisableLocalInterrupts):
+  csrxchg $zero, $a0, LOONGARCH_CSR_ECFG
+  jirl$zero, $ra, 0
 
+#/**
+#  Disables global CPU interrupts.
+#**/
 ASM_PFX(DisableInterrupts):
-  li.w$t0, 0x4
-  csrxchg $zero, $t0, 0x0
+  li.w$t0, BIT2
+  csrxchg $zero, $t0, LOONGARCH_CSR_CRMD
   jirl$zero, $ra, 0
   .end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S 
b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
index 3c34fb2cdd..126c7b49b3 100644
--- a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
+++ b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
@@ -1,21 +1,33 @@
 #--
 #
-# LoongArch interrupt enable
+# LoongArch interrupt enable operations
 #
-# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights 
reserved.
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 #--
 
+#include 
+#include 
+
+ASM_GLOBAL ASM_PFX(EnableLocalInterrupts)
 ASM_GLOBAL ASM_PFX(EnableInterrupts)
 
 #/**
-#  Enables CPU interrupts.
+#  Enables local CPU interrupts.
+#
+#  @param  Needs to enable local interrupt bit.
 #**/
+ASM_PFX(EnableLocalInterrupts):
+  csrxchg $a0, $a0, LOONGARCH_CSR_ECFG
+  jirl$zero, $ra, 0
 
+#/**
+#  Enables global CPU interrupts.
+#**/
 ASM_PFX(EnableInterrupts):
-  li.w$t0, 0x4
-  csrxchg $t0, $t0, 0x0
+  li.w$t0, BIT2
+  csrxchg $t0, $t0, LOONGARCH_CSR_CRMD
   jirl$zero, $ra, 0
   .end
-- 
2.27.0



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[edk2-devel] [PATCH v6 03/36] MdePkg: Add LoongArch64 exception function set into BaseLib

[Chao Li]

Adding SetExceptionBaseAddress and SetTlbRebaseAddress functions
for LoongArch64.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Signed-off-by: Chao Li 
Acked-by: Michael D Kinney 
---
 MdePkg/Include/Library/BaseLib.h  | 20 +
 MdePkg/Library/BaseLib/BaseLib.inf|  1 +
 .../BaseLib/LoongArch64/ExceptionBase.S   | 41 +++
 3 files changed, 62 insertions(+)
 create mode 100644 MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index b71e47f41b..152e95f34d 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -282,6 +282,26 @@ typedef struct {
 
 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT  8
 
+/*
+ * Set the exception base address for LoongArch.
+ *
+ * @param  ExceptionBaseAddress   The exception base address, must be aligned 
greater than or qeual to 4K .
+ */
+VOID
+SetExceptionBaseAddress (
+  IN UINT64
+  );
+
+/*
+ * Set the TlbRebase address for LoongArch.
+ *
+ * @param  TlbRebaseAddress   The TlbRebase address, must be aligned greater 
than or qeual to 4K .
+ */
+VOID
+SetTlbRebaseAddress (
+  IN UINT64
+  );
+
 #endif // defined (MDE_CPU_LOONGARCH64)
 
 //
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index 5338938944..bb6be25a93 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -419,6 +419,7 @@
   LoongArch64/CpuPause.S| GCC
   LoongArch64/SetJumpLongJump.S | GCC
   LoongArch64/SwitchStack.S | GCC
+  LoongArch64/ExceptionBase.S   | GCC
 
 [Packages]
   MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S 
b/MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
new file mode 100644
index 00..b6e90a8f28
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
@@ -0,0 +1,41 @@
+#--
+#
+# LoongArch set exception base address operations
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#--
+
+#include 
+#include 
+
+ASM_GLOBAL ASM_PFX(SetExceptionBaseAddress)
+ASM_GLOBAL ASM_PFX(SetTlbRebaseAddress)
+
+#/**
+#  Set the exception base address for LoongArch.
+#
+#  @param  ExceptionBaseAddress   The exception base address, must be aligned 
greater than or qeual to 4K .
+#**/
+ASM_PFX(SetExceptionBaseAddress):
+  csrrd   $t0, LOONGARCH_CSR_ECFG
+  li.d$t1, ~(BIT16 | BIT17 | BIT18)
+  and $t0, $t0, $t1
+  csrwr   $t0, LOONGARCH_CSR_ECFG
+
+  move$t0, $a0
+  csrwr   $t0, LOONGARCH_CSR_EBASE
+  jirl$zero, $ra, 0
+
+#/**
+#  Set the TlbRebase address for LoongArch.
+#
+#  @param  TlbRebaseAddress   The TlbRebase address, must be aligned greater 
than or qeual to 4K .
+#**/
+ASM_PFX(SetTlbRebaseAddress):
+  move$t0, $a0
+  csrwr   $t0, LOONGARCH_CSR_TLBREBASE
+  jirl$zero, $ra, 0
+.end
-- 
2.27.0



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[edk2-devel] [PATCH v6 02/36] MdePkg: Add LoongArch64 FPU function set into BaseCpuLib

[Chao Li]

Adding InitializeFloatingPointUnits, EnableFloatingPointUnits and
DisableFloatingPointUnits functions for LoongArch64.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Signed-off-by: Chao Li 
Acked-by: Michael D Kinney 
---
 MdePkg/Include/Library/CpuLib.h   | 43 ++--
 MdePkg/Library/BaseCpuLib/BaseCpuLib.inf  |  7 ++-
 .../Library/BaseCpuLib/LoongArch/DisableFpu.S | 17 +++
 .../Library/BaseCpuLib/LoongArch/EnableFpu.S  | 17 +++
 .../BaseCpuLib/LoongArch/InitializeFpu.S  | 51 +++
 5 files changed, 128 insertions(+), 7 deletions(-)
 create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S
 create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S
 create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/InitializeFpu.S

diff --git a/MdePkg/Include/Library/CpuLib.h b/MdePkg/Include/Library/CpuLib.h
index 3f29937dc7..27f3f82ab9 100644
--- a/MdePkg/Include/Library/CpuLib.h
+++ b/MdePkg/Include/Library/CpuLib.h
@@ -8,6 +8,7 @@
   As a result, these services could not be defined in the Base Library.
 
 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -41,14 +42,16 @@ CpuFlushTlb (
   VOID
   );
 
-#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) || defined 
(MDE_CPU_LOONGARCH64)
 
 /**
+  Initialize the CPU floating point units.
+
   Initializes floating point units for requirement of UEFI specification.
-  This function initializes floating-point control word to 0x027F (all 
exceptions
-  masked,double-precision, round-to-nearest) and multimedia-extensions control 
word
-  (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to 
zero
-  for masked underflow).
+  For IA32 and X64, this function initializes floating-point control word to 
0x027F
+  (all exceptions masked,double-precision, round-to-nearest) and 
multimedia-extensions
+  control word (if supported) to 0x1F80 (all exceptions masked, 
round-to-nearest,
+  flush to zero for masked underflow).
 **/
 VOID
 EFIAPI
@@ -56,6 +59,10 @@ InitializeFloatingPointUnits (
   VOID
   );
 
+#endif
+
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+
 /**
   Determine if the standard CPU signature is "AuthenticAMD".
   @retval TRUE  The CPU signature matches.
@@ -89,4 +96,30 @@ GetCpuSteppingId (
 
 #endif
 
+#if defined (MDE_CPU_LOONGARCH64)
+
+/**
+  Enable the CPU floating point units.
+
+  Enable the CPU floating point units.
+**/
+VOID
+EFIAPI
+EnableFloatingPointUnits (
+  VOID
+  );
+
+/**
+  Disable the CPU floating point units.
+
+  Disable the CPU floating point units.
+**/
+VOID
+EFIAPI
+DisableFloatingPointUnits (
+  VOID
+  );
+
+#endif
+
 #endif
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf 
b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
index 9a162afe6d..89f6272f11 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -65,8 +65,11 @@
   RiscV/Cpu.S
 
 [Sources.LOONGARCH64]
-  LoongArch/CpuFlushTlb.S | GCC
-  LoongArch/CpuSleep.S| GCC
+  LoongArch/CpuFlushTlb.S   | GCC
+  LoongArch/CpuSleep.S  | GCC
+  LoongArch/InitializeFpu.S | GCC
+  LoongArch/EnableFpu.S | GCC
+  LoongArch/DisableFpu.S| GCC
 
 [Packages]
   MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S 
b/MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S
new file mode 100644
index 00..33c6bf3411
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S
@@ -0,0 +1,17 @@
+#--
+#
+# DisableFloatingPointUnits() for LoongArch64
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#--
+ASM_GLOBAL ASM_PFX(DisableFloatingPointUnits)
+
+ASM_PFX(DisableFloatingPointUnits):
+  li.w$t0, 0x1
+  csrxchg $zero, $t0, 0x2
+
+  jirl $zero, $ra, 0
+  .end
diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S 
b/MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S
new file mode 100644
index 00..3e4f7411f1
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S
@@ -0,0 +1,17 @@
+#--
+#
+# EnableFloatingPointUnits() for LoongArch64
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#--
+ASM_GLOBAL ASM_PFX(EnableFloatingPointUnits)
+
+ASM_PFX(EnableFloatingPointUnits):
+  li.w$t0, 0x1
+  csrxchg $t0, $t0, 

[edk2-devel] [PATCH v6 01/36] MdePkg: Add the header file named Csr.h for LoongArch64

[Chao Li]

Adding Csr.h for LoongArch64, it is use for accessing the CSR registers.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Signed-off-by: Chao Li 
Acked-by: Michael D Kinney 
---
 MdePkg/Include/Register/LoongArch64/Csr.h | 263 ++
 1 file changed, 263 insertions(+)
 create mode 100644 MdePkg/Include/Register/LoongArch64/Csr.h

diff --git a/MdePkg/Include/Register/LoongArch64/Csr.h 
b/MdePkg/Include/Register/LoongArch64/Csr.h
new file mode 100644
index 00..aa22a26564
--- /dev/null
+++ b/MdePkg/Include/Register/LoongArch64/Csr.h
@@ -0,0 +1,263 @@
+/** @file
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- EXC - Exception
+- CSR - CPU Status Register
+**/
+
+#ifndef LOONGARCH_CSR_H_
+#define LOONGARCH_CSR_H_
+
+#include 
+
+//
+// CSR register numbers
+//
+
+//
+// Basic CSR registers
+//
+#define LOONGARCH_CSR_CRMD 0x0
+#define LOONGARCH_CSR_PRMD 0x1
+#define LOONGARCH_CSR_EUEN 0x2
+#define CSR_EUEN_LBTEN_SHIFT   3
+#define CSR_EUEN_LBTEN (0x1ULL << CSR_EUEN_LBTEN_SHIFT)
+#define CSR_EUEN_LASXEN_SHIFT  2
+#define CSR_EUEN_LASXEN(0x1ULL << CSR_EUEN_LASXEN_SHIFT)
+#define CSR_EUEN_LSXEN_SHIFT   1
+#define CSR_EUEN_LSXEN (0x1ULL << CSR_EUEN_LSXEN_SHIFT)
+#define CSR_EUEN_FPEN_SHIFT0
+#define CSR_EUEN_FPEN  (0x1ULL << CSR_EUEN_FPEN_SHIFT)
+#define LOONGARCH_CSR_MISC 0x3
+#define LOONGARCH_CSR_ECFG 0x4
+
+#define LOONGARCH_CSR_ESTAT   0x5
+#define CSR_ESTAT_ESUBCODE_SHIFT  22
+#define CSR_ESTAT_ESUBCODE_WIDTH  9
+#define CSR_ESTAT_ESUBCODE(0x1ffULL << CSR_ESTAT_ESUBCODE_SHIFT)
+#define CSR_ESTAT_EXC_SHIFT   16
+#define CSR_ESTAT_EXC_WIDTH   6
+#define CSR_ESTAT_EXC (0x3FULL << CSR_ESTAT_EXC_SHIFT)
+#define CSR_ESTAT_IS_SHIFT0
+#define CSR_ESTAT_IS_WIDTH15
+#define CSR_ESTAT_IS  (0x7FFFULL << CSR_ESTAT_IS_SHIFT)
+
+#define LOONGARCH_CSR_ERA0x6
+#define LOONGARCH_CSR_BADV   0x7
+#define LOONGARCH_CSR_BADI   0x8
+#define LOONGARCH_CSR_EBASE  0xC // Exception entry base address
+
+//
+// TLB related CSR registers
+//
+#define LOONGARCH_CSR_TLBIDX  0x10  // TLB Index, EHINV, PageSize, NP
+#define LOONGARCH_CSR_TLBEHI  0x11  // TLB EntryHi
+#define LOONGARCH_CSR_TLBELO0 0x12  // TLB EntryLo0
+#define LOONGARCH_CSR_TLBELO1 0x13  // TLB EntryLo1
+#define LOONGARCH_CSR_ASID0x18  // ASID
+#define LOONGARCH_CSR_PGDL0x19  // Page table base address when 
VA[47] = 0
+#define LOONGARCH_CSR_PGDH0x1A  // Page table base address when 
VA[47] = 1
+#define LOONGARCH_CSR_PGD 0x1B  // Page table base
+#define LOONGARCH_CSR_PWCTL0  0x1C  // PWCtl0
+#define LOONGARCH_CSR_PWCTL1  0x1D  // PWCtl1
+#define LOONGARCH_CSR_STLBPGSIZE  0x1E
+#define LOONGARCH_CSR_RVACFG  0x1F
+
+///
+/// Page table property definitions
+///
+#define PAGE_VALID_SHIFT   0
+#define PAGE_DIRTY_SHIFT   1
+#define PAGE_PLV_SHIFT 2  // 2~3, two bits
+#define CACHE_SHIFT4  // 4~5, two bits
+#define PAGE_GLOBAL_SHIFT  6
+#define PAGE_HUGE_SHIFT6  // HUGE is a PMD bit
+
+#define PAGE_HGLOBAL_SHIFT  12 // HGlobal is a PMD bit
+#define PAGE_PFN_SHIFT  12
+#define PAGE_PFN_END_SHIFT  48
+#define PAGE_NO_READ_SHIFT  61
+#define PAGE_NO_EXEC_SHIFT  62
+#define PAGE_RPLV_SHIFT 63
+
+///
+/// Used by TLB hardware (placed in EntryLo*)
+///
+#define PAGE_VALID((UINTN)(1) << PAGE_VALID_SHIFT)
+#define PAGE_DIRTY((UINTN)(1) << PAGE_DIRTY_SHIFT)
+#define PAGE_PLV  ((UINTN)(3) << PAGE_PLV_SHIFT)
+#define PAGE_GLOBAL   ((UINTN)(1) << PAGE_GLOBAL_SHIFT)
+#define PAGE_HUGE ((UINTN)(1) << PAGE_HUGE_SHIFT)
+#define PAGE_HGLOBAL  ((UINTN)(1) << PAGE_HGLOBAL_SHIFT)
+#define PAGE_NO_READ  ((UINTN)(1) << PAGE_NO_READ_SHIFT)
+#define PAGE_NO_EXEC  ((UINTN)(1) << PAGE_NO_EXEC_SHIFT)
+#define PAGE_RPLV ((UINTN)(1) << PAGE_RPLV_SHIFT)
+#define CACHE_MASK((UINTN)(3) << CACHE_SHIFT)
+#define PFN_SHIFT (EFI_PAGE_SHIFT - 12 + PAGE_PFN_SHIFT)
+
+#define PLV_KERNEL  0
+#define PLV_USER3
+
+#define PAGE_USER(PLV_USER << PAGE_PLV_SHIFT)
+#define PAGE_KERNEL  (PLV_KERN << PAGE_PLV_SHIFT)
+
+#define CACHE_SUC  (0 << CACHE_SHIFT) // Strong-ordered UnCached
+#define CACHE_CC   (1 << CACHE_SHIFT) // Coherent Cached
+#define CACHE_WUC  (2 << CACHE_SHIFT) // Weak-ordered UnCached
+
+//
+// Config CSR registers
+//
+#define LOONGARCH_CSR_CPUNUM  0x20// CPU core number
+#define LOONGARCH_CSR_PRCFG1  0x21// Config1
+#define LOONGARCH_CSR_PRCFG2  0x22// Config2
+#define LOONGARCH_CSR_PRCFG3  0x23// Config3
+
+//
+// Kscratch registers
+//
+#define LOONGARCH_CSR_KS0  0x30
+#define LOONGARCH_CSR_KS1  0x31
+#define LOONGARCH_CSR_KS2  0x32
+#define LOONGARCH_CSR_KS3  0x33
+#define LOONGARCH_CSR_KS4  0x34

[edk2-devel] [PATCH v6 00/36] Enable LoongArch virtual machine in edk2

[Chao Li]

This patch set will enable LoongArch virtual machine in edk2, the new
LoongArch virtual machine is located in OvmfPkg/LoongArchVirt/, it is a
generic platform that dose not require any actual hardware.

Patch1-Patch14: Submit the common library and driver for LoongArch
virtual machine and real hardware. Such as base help functions,
exception handel, MMU library, multiprocessor library etc.

Patch15-Patch16: Add PrePiCpuIoSize for LoongArch64. and move ArmVirtPkg
two PCDs into OvmfPkg for easier use by other architectures.

Patch17-Patch29: LoongArch virtual machine private code, include SEC and
PEI phase code, some library and drivers.

Patch30: Add LoongArchVirt's self introduction-file.

Modfied modues: MdePkg, UefiCpuPkg, EmbeddedPkg, ArmVirtPkg, OvmfPkg.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

PR: https://github.com/tianocore/edk2/pull/5208

**Changes from V1 to V2:**
1. Add Ray's Ack signature to patch 13.
2. Add LoongArchVirt's self introduction-file. And made a standalone
patch for this change.

**Changes from V2 to V3:**
Compared with V2, there are 9 more patches, removed 2 libraries and 1
driver from OvmfPkg/LoongArchVrt.

New patches:
MdePkg: Add a new library named PeiServicesTablePointerLibReg
MdePkg: Add method of LoongArch64 to PeiServicesTablePointerLibReg
MdePkg: Add a PCD feature flag named PcdPciIoTranslationIsEnabled
UefiCpuPkg: Add MMIO method in CpuIo2Dxe
ArmVirtPkg: Enable UefiCpuPkg version CpuIo2Dxe
ArmPkg: Remove ArmPciCpuIo2Dxe from ArmPkg
OvmfPkg/RiscVVirt: Enable UefiCpuPkg version CpuIo2Dxe
OvmfPkg/RiscVVirt: Remove PciCpuIo2Dxe from RiscVVirt
ArmVirtPkg: Move the FdtSerialPortAddressLib to OvmfPkg
ArmVirtPkg: Move the PcdTerminalTypeGuidBuffer into OvmfPkg
ArmVirtPkg: Move PlatformBootManagerLib to OvmfPkg

For the review opinions:
1. Add MMIO method to CpuIo2Dxe driver to accommodate more ARCH that
require MMIO method, enable it on ARM, RISCV64 and LOONGARCH64.
Questioner: Gerd, Sunil.

2. Move the FdtSerialProtAddressLib to OvmfPkg and enabled it on ARM and
LOONGARCH64. Questioner: Gerd, Laszlo.

3. Add a new library in MdePkg named PeiServiceTablePointerLibReg for
the Register Mechanism and enabled it on LOONGARCH64. Questioner: Laszlo.

4. Moved the ARM version of PlatformBootManagerLib to OvmfPkg/Library, and
enabled it on ARM and LOONGARCH64. Questioner: Laszlo, Gerd.

5. Adjust the order of some inf file in ArmVirtPkg. Questioner: Sami.

6. Move the CpuMmuLib.h some architecture-specific PTE #defines into
Csr.h. Questioner: Andrei.

**Changes from V3 to V4:**
Compared with V3, 1 patch moving ArmPciCpuIo2Dxe has been removed.
Adjusted the code of the LoongArch64 CPU timer library. Rename
PeiServiceTablePointerLibReg to PeiServiceTablePointerLibKs0. Fixed some
typos. Remove some APIs of CpuMmuLib.

For the review opinions:
1. Removed the patch that removed ArmPciCpuIo2Dxe, there are 15 platforms
in edk2-platforms were affected, so wait for this patch series to be
merged, then submit a patch to remove it. Questioner: Leif.

2. Renamed the PeiServiceTablePointLibReg to PeiServiceTablePointLibKs0.
Currently, this library is specific to LoongArch architecture.
Questioner: Laszlo, Liming.

3. Adjust some logic of LoongArch64 CPU timer library. Using the safe
INT library and adjust the bit width of stable counter. Questioner: Laszlo.

4. Removed some APIs from CpuMmuLib. Change some APIs to private.
Questioner: Ray.

**Changes from V4 to V5:**
Compared with V4, 1 patch adding PcdPciIoTranslationIsEnabled in MdePkg
has been removed.
Copy ArmPciCpuIo2Dxe to UefiCpuPkg and renamed it to CpuMmio2Dxe.
Restore the definitions in MdePkg/Include/Protocol/DebugSupport.h, and
just add some comments.

For the review opinions:
1. Copy ArmPciCpuIo2Dxe to UefiCpuPkg so that more other ARCHs can use
it easily. Questioner: Ray, Ard.

2. Restore the changes of MdePkg/Include/Protocol/DebugSupport.h.
Questioner: Liming.

3. Ia32 X64 and LoongArch64 use a same API definition,
InitializeFloatingPointUnits in CpuLib.h. Questioner: Liming.

4. Adjust API definition in CpuMmuLib.h. Questioner: Ray.

**Changes from V5 to V6:**
1. Added Sunil "Reviewed-by" message to patches 20 and 21.
2. Added Bibo "Reviced-by" message to patches 27, 29, 32 and 34.
3. Added the IPI handler in SEC and PEI stage. Modified patches 11 and
15.
4. Adjust some code styles to suit CI ECC.
5. Adjust the way of AP wakeup from IPI.
6. Adjust the order between setting exceptions and copying exception
handlers.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Abner Chang 
Cc: Daniel Schaefer 
Cc: Sami Mujawar 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 
Cc: Sunil V L 
Cc: Bibo Mao 

Chao Li (36):
  MdePkg: Add the header file named Csr.h for LoongArch64
  MdePkg: Add LoongArch64 FPU function set into BaseCpuLib
  MdePkg: Add LoongArch64 exception function set into 

Re: [edk2-devel] [PATCH 1/2] UefiCpuPkg: Retrive EXTENDED_PROCESSOR_INFORMATION

[duntan]

Hi Laszlo,

Thanks for your comments. I agree with your solution. It seems simpler and 
clearer. Will change the code and keep the additional function comments in next 
version patch set.

Thanks, 
Dun

-Original Message-
From: Laszlo Ersek  
Sent: Thursday, January 4, 2024 10:53 PM
To: devel@edk2.groups.io; Tan, Dun 
Cc: Ni, Ray ; Kumar, Rahul R ; Gerd 
Hoffmann ; Xu, Min M 
Subject: Re: [edk2-devel] [PATCH 1/2] UefiCpuPkg: Retrive 
EXTENDED_PROCESSOR_INFORMATION

On 1/4/24 08:32, duntan wrote:
> Retrive EXTENDED_PROCESSOR_INFORMATION in the API
> MpInitLibGetProcessorInfo() of MpInitLibUp instance when the BIT24 of 
> input ProcessorNumber is set.
> It's to align with the behavior in PEI/DXE MpInitLib
> 
> Signed-off-by: Dun Tan 
> Cc: Ray Ni 
> Cc: Laszlo Ersek 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> Cc: Min Xu 
> ---
>  UefiCpuPkg/Include/Library/MpInitLib.h   |  2 ++
>  UefiCpuPkg/Library/MpInitLib/MpLib.c |  2 ++
>  UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c | 12 
>  3 files changed, 16 insertions(+)
> 
> diff --git a/UefiCpuPkg/Include/Library/MpInitLib.h 
> b/UefiCpuPkg/Include/Library/MpInitLib.h
> index 1853c46415..842c6f7ff9 100644
> --- a/UefiCpuPkg/Include/Library/MpInitLib.h
> +++ b/UefiCpuPkg/Include/Library/MpInitLib.h
> @@ -63,6 +63,8 @@ MpInitLibGetNumberOfProcessors (
>instant this call is made. This service may only be called from the BSP.
>  
>@param[in]  ProcessorNumber   The handle number of processor.
> +Lower 24 bits contains the actual 
> processor number.
> +BIT24 indicates if the 
> EXTENDED_PROCESSOR_INFORMATION will be retrived.
>@param[out] ProcessorInfoBuffer   A pointer to the buffer where 
> information for
>  the requested processor is deposited.
>@param[out] HealthDataReturn processor health data.
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
> b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> index a359906923..cdfb570e61 100644
> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> @@ -2333,6 +2333,8 @@ MpInitLibInitialize (
>instant this call is made. This service may only be called from the BSP.
>  
>@param[in]  ProcessorNumber   The handle number of processor.
> +Lower 24 bits contains the actual 
> processor number.
> +BIT24 indicates if the 
> EXTENDED_PROCESSOR_INFORMATION will be retrived.
>@param[out] ProcessorInfoBuffer   A pointer to the buffer where 
> information for
>  the requested processor is deposited.
>@param[out]  HealthDataReturn processor health data.
> diff --git a/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c 
> b/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
> index 86f9fbf903..3af4911d4b 100644
> --- a/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
> +++ b/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
> @@ -77,6 +77,8 @@ MpInitLibGetNumberOfProcessors (
>instant this call is made. This service may only be called from the BSP.
>  
>@param[in]  ProcessorNumber   The handle number of processor.
> +Lower 24 bits contains the actual 
> processor number.
> +BIT24 indicates if the 
> EXTENDED_PROCESSOR_INFORMATION will be retrived.
>@param[out] ProcessorInfoBuffer   A pointer to the buffer where 
> information for
>  the requested processor is deposited.
>@param[out] HealthDataReturn processor health data.
> @@ -115,6 +117,16 @@ MpInitLibGetProcessorInfo (
>ProcessorInfoBuffer->Location.Package = 0;
>ProcessorInfoBuffer->Location.Core= 0;
>ProcessorInfoBuffer->Location.Thread  = 0;
> +
> +  if ((ProcessorNumber & CPU_V2_EXTENDED_TOPOLOGY) != 0) {
> +ProcessorInfoBuffer->ExtendedInformation.Location2.Package = 0;
> +ProcessorInfoBuffer->ExtendedInformation.Location2.Die = 0;
> +ProcessorInfoBuffer->ExtendedInformation.Location2.Tile= 0;
> +ProcessorInfoBuffer->ExtendedInformation.Location2.Module  = 0;
> +ProcessorInfoBuffer->ExtendedInformation.Location2.Core= 0;
> +ProcessorInfoBuffer->ExtendedInformation.Location2.Thread  = 0;  
> + }
> +
>if (HealthData != NULL) {
>  GuidHob = GetFirstGuidHob ();
>  if (GuidHob != NULL) {

(1) For the UP implementation of MpInitLibGetProcessorInfo():

How about, for a *complete* solution (covering both pre-patch and post-patch 
functionality):

  ZeroMem (ProcessorInfoBuffer, sizeof *ProcessorInfoBuffer);
  ProcessorInfoBuffer->StatusFlag  = PROCESSOR_AS_BSP_BIT  |
 PROCESSOR_ENABLED_BIT |
 PROCESSOR_HEALTH_STATUS_BIT;

This approach is not slow (most of the time I expect the platform will have an 

Re: [edk2-devel] [edk2-redfish-client][PATCH V2] RedfishClientPkg: Add ETag PCD and revise Redfish ETag functions

[Chang, Abner via groups.io]

[AMD Official Use Only - General]

Hi Mike,
This PCD is introduced for the platform that connects to the Redfish service 
which doesn't support ETag.
We disable the client code that handles ETag with setting this PCD to FALSE. So 
client will just consume any Redfish property from service even there is 
nothing changed. This knob doesn't control Redfish service behavior on BMC.
Yes, there is no method to detect if Redfish service supports ETag or not. So 
we introduce a client side knob to disable ETag checking although it mentions 
the service "should" support ETag in Redfish spec. However, a simple Redfish 
services may not implementing ETag HTTP header.
Does above clarify the question?

Thanks
Abner

> -Original Message-
> From: Mike Maslenkin 
> Sent: Friday, January 5, 2024 8:20 AM
> To: devel@edk2.groups.io; Chang, Abner 
> Cc: Nickle Wang ; Igor Kulchytskyy 
> Subject: Re: [edk2-devel] [edk2-redfish-client][PATCH V2] RedfishClientPkg:
> Add ETag PCD and revise Redfish ETag functions
>
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> Looks good to me.
>
> But could it be possible to rephrase "ETAG is not supported on Redfish
> service." ?
> May be I misunderstand, but I assume "Redfish service" is a service at
> BMC side, while we are disabling ETAG functionality at Redfish client
> side.
> README.md says "Redfish service hosted by Board Management Controller
> (BMC) in server".
> Currently there is no method to get server features (AFAIR), so we
> disable a work with those explicitly on the client side.
>
> Regards,
> Mike.
>
> On Thu, Jan 4, 2024 at 11:57 AM Chang, Abner via groups.io
>  wrote:
> >
> > From: Abner Chang 
> >
> > Add PCD to disable ETag capability for the case Redfish
> > service doesn't support ETag.
> >
> > Signed-off-by: Abner Chang 
> > Cc: Nickle Wang 
> > Cc: Igor Kulchytskyy 
> > Cc: Mike Maslenkin 
> > ---
> >  RedfishClientPkg/RedfishClientPkg.dec |   2 +
> >  .../RedfishFeatureUtilityLib.inf  |   1 +
> >  .../Library/RedfishFeatureUtilityLib.h|  46 +++-
> >  .../Features/Bios/v1_0_9/Dxe/BiosDxe.c|  18 +-
> >  .../v1_0_4/Common/BootOptionCommon.c  |   4 +-
> >  .../BootOption/v1_0_4/Dxe/BootOptionDxe.c |  16 +-
> >  .../v1_5_0/Dxe/ComputerSystemDxe.c|  16 +-
> >  .../Features/Memory/V1_7_1/Dxe/MemoryDxe.c|  16 +-
> >  .../RedfishFeatureUtilityLib.c| 208 --
> >  9 files changed, 197 insertions(+), 130 deletions(-)
> >
> > diff --git a/RedfishClientPkg/RedfishClientPkg.dec
> b/RedfishClientPkg/RedfishClientPkg.dec
> > index b350facae0..8adef327fb 100644
> > --- a/RedfishClientPkg/RedfishClientPkg.dec
> > +++ b/RedfishClientPkg/RedfishClientPkg.dec
> > @@ -76,6 +76,8 @@
> >
> gEfiRedfishClientPkgTokenSpaceGuid.PcdDefaultRedfishVersion|L"v1"|VOID*
> |0x1004
> >## The number of seconds that the firmware will wait before system reboot
> >
> gEfiRedfishClientPkgTokenSpaceGuid.PcdRedfishSystemRebootTimeout|5|UI
> NT16|0x2002
> > +  ## Default capability of Redfish service side ETAG support
> > +
> gEfiRedfishClientPkgTokenSpaceGuid.PcdRedfishServiceEtagSupported|TRUE|
> BOOLEAN|0x1005
> >
> >  [PcdsDynamicEx]
> >## The flag used to indicate that system reboot is required due to system
> configuration change
> > diff --git
> a/RedfishClientPkg/Library/RedfishFeatureUtilityLib/RedfishFeatureUtilityLib.i
> nf
> b/RedfishClientPkg/Library/RedfishFeatureUtilityLib/RedfishFeatureUtilityLib.i
> nf
> > index 718273b248..fde6a176d0 100644
> > ---
> a/RedfishClientPkg/Library/RedfishFeatureUtilityLib/RedfishFeatureUtilityLib.i
> nf
> > +++
> b/RedfishClientPkg/Library/RedfishFeatureUtilityLib/RedfishFeatureUtilityLib.i
> nf
> > @@ -54,6 +54,7 @@
> >
> >  [Pcd]
> >gEfiRedfishClientPkgTokenSpaceGuid.PcdRedfishSystemRebootRequired
> > +  gEfiRedfishClientPkgTokenSpaceGuid.PcdRedfishServiceEtagSupported
> >
> >  [Guids]
> >
> > diff --git a/RedfishClientPkg/Include/Library/RedfishFeatureUtilityLib.h
> b/RedfishClientPkg/Include/Library/RedfishFeatureUtilityLib.h
> > index 9513a65617..834ea0fcfe 100644
> > --- a/RedfishClientPkg/Include/Library/RedfishFeatureUtilityLib.h
> > +++ b/RedfishClientPkg/Include/Library/RedfishFeatureUtilityLib.h
> > @@ -81,7 +81,7 @@ CopyConfiglanguageList (
> >
> >  /**
> >
> > -  Get number of node from the string. Node is seperated by '/'.
> > +  Get number of node from the string. Node is separated by '/'.
> >
> >@param[in]  NodeString The node string to parse.
> >
> > @@ -559,6 +559,19 @@ GetEtagWithUri (
> >IN  EFI_STRING  Uri
> >);
> >
> > +/**
> > +
> > +  This function returns a boolean of ETAG support on Redfish service side.
> > +
> > +  @retval TRUEETAG is supported on Redfish service.
> > +  @retval FALSE   ETAG is not supported on Redfish service.
> > +
> > +**/
> > +BOOLEAN
> > 

Re: [edk2-devel] [edk2-platforms][PATCH v1 0/7] Platform/Sgi: Add support for RD-N2-Cfg3 and RD-V2 platform

[Sami Mujawar]

Hi Prabin,

There are 2 patches each in this series numbered 4/7, 5/7, 6/7 , 7/7. This is 
very confusing.

[edk2-platforms][PATCH v1 7/7] Platform/Sgi: Extend SMBIOS support for RD-V2 
platform
[edk2-platforms][PATCH v1 7/7] Platform/Sgi: Add support for RD-N2-Cfg3 platform
[edk2-platforms][PATCH v1 6/7] Platform/Sgi: Define RD-V2 platform id values
[edk2-platforms][PATCH v1 6/7] Platform/Sgi: Add a PCD to specify platform 
variant
[edk2-platforms][PATCH v1 5/7] Platform/Sgi: Extend SMBIOS support for RD-V2 
platform
[edk2-platforms][PATCH v1 5/7] Platform/Sgi: Add support for RD-N2-Cfg3 platform
[edk2-platforms][PATCH v1 4/7] Platform/Sgi: Define RD-V2 platform id values
[edk2-platforms][PATCH v1 4/7] Platform/Sgi: Add a PCD to specify platform 
variant


I will not review this series until this is fixed. It will just be more chaotic.
Can you fix this and send a v2, please? 

Regards,

Sami Mujawar

On 04/01/2024, 18:49, "Prabin CA" mailto:prabin...@arm.com>> wrote:


This patch series introduces support for two reference design platforms-
RD-N2-Cfg3 and RD-V2. The RD-N2-Cfg3 FVP platform is a variant of RD-N2
platform with a different mesh size and GIC ITS count. It is based on
the Neoverse N2 CPUs and includes 16xMP1 CPUs. RD-N2-Cfg3 has 12 GIC ITS
blocks, 6 more than the other RD-N2 variants.


The Neoverse RD-V2 FVP platform includes 16xMP1 Neoverse V2 CPUs and
each CPU has 64KB of L1 instruction/data cache, 2MB of L2 cache and 32MB
of system level cache. The system architecture of the RD-V2 platform is
similar to the RD-N2 platform, except for the CPU and L2 cache size. So
existing RD-N2 SMBIOS support is extended for RD-V2 platform to reuse
rest of the RD-N2 SMBIOS configuration for the RD-V2 platform.


In addition to patches that introduce support for these two platforms,
there are three patches that update support for existing platforms. The
first patch in this series removes +nofp gcc option flag. The second
patch adds no-stack-protector flag to the gcc build option for the StMM
builds. The third patch adds VariableFlashInfoLib to the common dsc
file.


Link to github branch with the patches in this series -
https://gitlab.arm.com/infra-solutions/reference-design/platsw/edk2-platforms/-/tree/topics/rdn2cfg3_rdv2_updates
 



Omkar Anand Kulkarni (1):
Platform/Sgi: remove +nofp gcc option flag


Prabin CA (3):
Platform/Sgi: add no-stack-protector flag for StMM builds
Platform/Sgi: Add a PCD to specify platform variant
Platform/Sgi: Add support for RD-N2-Cfg3 platform


Pranav Madhu (2):
Platform/Sgi: Define RD-V2 platform id values
Platform/Sgi: Extend SMBIOS support for RD-V2 platform


Vijayenthiran Subramaniam (1):
Platform/Sgi: Add VariableFlashInfoLib to fix missing dependency


Platform/ARM/SgiPkg/SgiPlatform.dec | 5 +-
Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc | 3 +-
Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.dsc | 58 
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/{RdN2AcpiTables.inf => RdN2Cfg3AcpiTables.inf} | 
15 ++---
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 ++-
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c | 7 ++-
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 9 
++-
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 20 
++-
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 8 ++-
Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 14 -
Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.fdf.inc | 10 
12 files changed, 136 insertions(+), 23 deletions(-)
create mode 100644 Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.dsc
copy Platform/ARM/SgiPkg/AcpiTables/{RdN2AcpiTables.inf => 
RdN2Cfg3AcpiTables.inf} (90%)
create mode 100644 Platform/ARM/SgiPkg/RdN2Cfg3/RdN2Cfg3.fdf.inc


-- 
2.34.1







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Re: [edk2-devel] [RFC][PATCH 0/2] Introduce HTTPS Platform TLS policy

[Chang, Abner via groups.io]

[AMD Official Use Only - General]

Hi Michael,
We are not aware there is a TlsConnectSession() for TLS handshake using the 
default TLS configuration data and it returns a failure as expected because the 
default TLS configuration is TLS_VERIFY_HOST without certificate installed on 
system.
This happens in HttpInitSession before notifying HttpEventInitSession event,  
so we have to reconfigure TLS config data before TlsConnectSession() function.
As there is an existing HttpEventTlsConnectSession event notified after 
TlsConnectSession(), that makes sense to me to introduce a new HTTP event 
HttpEventTlsConfigured as I mentioned in previous conversation and notify 
callback functions after TlsConfigureSession().
Upper layer HTTP application then listen to HttpEventTlsConfigured event and 
reconfigure TLS configuration data in the callback function.

Please check it here: https://edk2.groups.io/g/devel/message/113224

Thanks
Abner
> -Original Message-
> From: Chang, Abner
> Sent: Wednesday, January 3, 2024 12:32 AM
> To: Michael Brown ; devel@edk2.groups.io
> Cc: Saloni Kasbekar ; Zachary Clark-williams
> ; Nickle Wang ; Igor
> Kulchytskyy 
> Subject: RE: [edk2-devel] [RFC][PATCH 0/2] Introduce HTTPS Platform TLS
> policy
>
>
>
> > -Original Message-
> > From: Michael Brown 
> > Sent: Tuesday, January 2, 2024 8:42 PM
> > To: devel@edk2.groups.io; Chang, Abner 
> > Cc: Saloni Kasbekar ; Zachary Clark-williams
> > ; Nickle Wang ;
> Igor
> > Kulchytskyy 
> > Subject: Re: [edk2-devel] [RFC][PATCH 0/2] Introduce HTTPS Platform TLS
> > policy
> >
> > Caution: This message originated from an External Source. Use proper
> caution
> > when opening attachments, clicking links, or responding.
> >
> >
> > On 02/01/2024 06:06, Chang, Abner via groups.io wrote:
> > >> What do you think about:
> > >>
> > >> - installing TLS on HTTP handle (as you have already implemented)
> > >>
> > >> - using EDKII_HTTP_CALLBACK_PROTOCOL to catch the
> > HttpEventInitSession
> > >> and perform whatever calls are needed to SetData() to modify the TLS
> > >> configuration?
> > >
> > > Leverage HttpNotify is good but still has some problems, as HttpNotify is
> > designed to notify callback owner about a specific task was done. In order 
> > to
> > keep this HttpNotify nature, we can create a callback point at the end of
> > TlsCreateChild() with a newly introduced event type says
> > HttpEventTlsChildCreated. The reason we have to create this notification
> > before TlsConfigureSession() is because this function uses the default
> > configuration data to configure TLS. However, it doesn't have to do
> > EfiTlsVerifyHost and TlsConfigCertificate if there is nothing to verify.
> > > The problem in configuring  EfiTlsVerifyHost is It always checks 
> > > verification
> > method with EFI_TLS_VERIFY_PEER, while the problem of
> TlsConfigCertificate
> > is it considers platform always can provide the certificate.  Anyway to
> > configure TLS after TlsConfigCertificate is to late as the error status 
> > already
> > returned earlier. Furthermore the design of HttpNotify doesn't provide the
> > output information for caller to determine the different code paths.  So 
> > with
> > above, how can we skip configuring TLS again with the default values in
> > HttpSupport.c even platform code already configured it before
> > TlsConfigureSession()?
> >
> > I may not have been clear enough: I'm suggesting that we allow
> > TlsConfigureSession() to perform its normal configuration, and then use
> > the HttpEventInitSession callback to modify this configuration (e.g.
> > setting EFI_TLS_VERIFY_NONE).
> >
> > Yes, this would mean that a tiny amount of unnecessary work is done
> > (e.g. first setting EFI_TLS_VERIFY_PEER, then later changing it to
> > EFI_TLS_VERIFY_NONE) but this is a negligible amount of execution time
> > and allows us to keep the code simple.
> >
> > The HttpEventInitSession callback is guaranteed to be called before the
> > calls to HttpGenRequestMessage() and HttpTransmitTcp() (even if running
> > at TPL_APPLICATION with network polling taking place) and so is
> > guaranteed to be a safe point at which to perform additional TLS
> > configuration via SetData().
> >
> > So, to expand on what I wrote before, I'm suggesting:
> >
> > - refactor TlsCreateChild() to install the TLS protocols on the HTTP
> > handle (as you have already implemented).
> >
> > - (optional) Remove TlsChildHandle and replace with a boolean flag.
> >
> Hi Michael,
> Above has no problems.
>
>
> > - No further changes required to HttpDxe, as far as I can tell.
> >
> > - In RedfishRestExDxe, install an EDKII_HTTP_CALLBACK_PROTOCOL before
> > calling EFI_HTTP_PROTOCOL.Request().
> >
> > - Allow the call to Request() to perform its normal TLS configuration
> > via TlsConfigureSession(), as though the connection were going to
> > perform host verification etc as per the platform default policy.  This
> > configuration should succeed, with no error returned.

[edk2-devel] [PATCH 5/5] RedfishPkg/RedfishRestExDxe: Update Supported function

[Chang, Abner via groups.io]

From: Abner Chang 

Update Supported function to check it the given
controller handle is already started.

Signed-off-by: Abner Chang 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
---
 RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.c 
b/RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.c
index 9a20c90d49a..38bcf28d993 100644
--- a/RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.c
+++ b/RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.c
@@ -356,6 +356,21 @@ RedfishRestExDriverBindingSupported (
   IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL
   )
 {
+  EFI_STATUS  Status;
+  UINT32  *Id;
+
+  Status = gBS->OpenProtocol (
+  ControllerHandle,
+  ,
+  (VOID **),
+  This->DriverBindingHandle,
+  ControllerHandle,
+  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+  );
+  if (!EFI_ERROR (Status)) {
+return EFI_ALREADY_STARTED;
+  }
+
   //
   // Test for the HttpServiceBinding Protocol.
   //
-- 
2.37.1.windows.1



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[edk2-devel] [PATCH 4/5] RedfishPkg/RedfishRestExDxe: Implement EDKII_HTTP_CALLBACK_PROTOCOL

[Chang, Abner via groups.io]

From: Abner Chang 

Implement EDKII_HTTP_CALLBACK_PROTOCOL that listens to
HttpEventTlsConfigured event for reconfiguring TLS configuration
data.

Signed-off-by: Abner Chang 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
---
 .../RedfishRestExDxe/RedfishRestExDxe.inf |  2 +
 .../RedfishRestExDxe/RedfishRestExDriver.h| 31 ++---
 .../RedfishRestExDxe/RedfishRestExDriver.c| 69 +++
 3 files changed, 92 insertions(+), 10 deletions(-)

diff --git a/RedfishPkg/RedfishRestExDxe/RedfishRestExDxe.inf 
b/RedfishPkg/RedfishRestExDxe/RedfishRestExDxe.inf
index 64e6343bfbf..706d5a5f15e 100644
--- a/RedfishPkg/RedfishRestExDxe/RedfishRestExDxe.inf
+++ b/RedfishPkg/RedfishRestExDxe/RedfishRestExDxe.inf
@@ -57,6 +57,8 @@
   gEfiHttpServiceBindingProtocolGuid  ## TO_START
   gEfiHttpProtocolGuid## TO_START
   gEfiDevicePathProtocolGuid  ## TO_START
+  gEdkiiHttpCallbackProtocolGuid  ## CONSUMES
+  gEfiTlsProtocolGuid ## CONSUMES
 
 [Pcd]
   gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceAccessModeInBand ## 
CONSUMES
diff --git a/RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.h 
b/RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.h
index 6b94e5814c4..8d2b9ecb80b 100644
--- a/RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.h
+++ b/RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.h
@@ -32,6 +32,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 ///
 /// Protocol instances
@@ -67,6 +69,9 @@ typedef struct _RESTEX_INSTANCE RESTEX_INSTANCE;
 #define RESTEX_INSTANCE_FROM_THIS(a)  \
   CR (a, RESTEX_INSTANCE, RestEx, RESTEX_INSTANCE_SIGNATURE)
 
+#define RESTEX_INSTANCE_FROM_HTTP_CALLBACK(a)  \
+  CR (a, RESTEX_INSTANCE, HttpCallbakFunction, RESTEX_INSTANCE_SIGNATURE)
+
 #define RESTEX_STATE_UNCONFIGED  0
 #define RESTEX_STATE_CONFIGED1
 
@@ -94,25 +99,31 @@ struct _RESTEX_SERVICE {
 #define RESTEX_INSTANCE_FLAGS_TCP_ERROR_RETRY  0x0002
 
 struct _RESTEX_INSTANCE {
-  UINT32 Signature;
-  LIST_ENTRY Link;
+  UINT32Signature;
+  LIST_ENTRYLink;
 
-  EFI_REST_EX_PROTOCOL   RestEx;
+  EFI_REST_EX_PROTOCOL  RestEx;
 
-  INTN   State;
-  BOOLEANInDestroy;
+  INTN  State;
+  BOOLEAN   InDestroy;
 
-  RESTEX_SERVICE *Service;
-  EFI_HANDLE ChildHandle;
+  RESTEX_SERVICE*Service;
+  EFI_HANDLEChildHandle;
 
-  EFI_REST_EX_CONFIG_DATAConfigData;
+  EFI_REST_EX_CONFIG_DATA   ConfigData;
 
   //
   // HTTP_IO to access the HTTP service
   //
-  HTTP_IOHttpIo;
+  HTTP_IO   HttpIo;
+
+  //
+  // EDKII_HTTP_CALLBACK_PROTOCOL that listens to
+  // HttpEventInitSession event.
+  //
+  EDKII_HTTP_CALLBACK_PROTOCOL  HttpCallbakFunction;
 
-  UINT32 Flags;
+  UINT32Flags;
 };
 
 typedef struct {
diff --git a/RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.c 
b/RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.c
index 7036aed4268..9a20c90d49a 100644
--- a/RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.c
+++ b/RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.c
@@ -585,6 +585,53 @@ RedfishRestExDriverBindingStop (
   return Status;
 }
 
+/**
+  Callback function that is invoked when HTTP event occurs.
+
+  @param[in]  ThisPointer to the EDKII_HTTP_CALLBACK_PROTOCOL 
instance.
+  @param[in]  Event   The event that occurs in the current state.
+  @param[in]  EventStatus The Status of Event, EFI_SUCCESS or other 
errors.
+**/
+VOID
+EFIAPI
+RestExHttpCallback (
+  IN EDKII_HTTP_CALLBACK_PROTOCOL  *This,
+  IN EDKII_HTTP_CALLBACK_EVENT Event,
+  IN EFI_STATUSEventStatus
+  )
+{
+  EFI_STATUSStatus;
+  EFI_TLS_PROTOCOL  *TlsProtocol;
+  RESTEX_INSTANCE   *Instance;
+  EFI_TLS_VERIFYTlsVerifyMethod;
+
+  if ((Event == HttpEventTlsConfigured) && (EventStatus == EFI_SUCCESS)) {
+// Reconfigure TLS configuration data.
+Instance = RESTEX_INSTANCE_FROM_HTTP_CALLBACK (This);
+Status   = gBS->HandleProtocol (
+  Instance->HttpIo.Handle,
+  ,
+  (VOID **)
+  );
+if (EFI_ERROR (Status)) {
+  return;
+}
+
+TlsVerifyMethod = EFI_TLS_VERIFY_NONE;
+Status  = TlsProtocol->SetSessionData (
+ TlsProtocol,
+ EfiTlsVerifyMethod,
+ ,
+ sizeof (EFI_TLS_VERIFY)
+ );
+if (!EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_MANAGEABILITY, "%a: REST EX reconfigures TLS verify 
method.\n", __func__));
+}
+  }
+
+  return;
+}
+
 /**
   Creates a 

[edk2-devel] [PATCH 3/5] NetwokrPkg/HttpDxe: Add HttpEventTlsConfigured HTTP callback event

[Chang, Abner via groups.io]

From: Abner Chang 

Add HttpEventTlsConfigured HTTP callback event and notify
callback functions when TlsConfigureSession () returns.

Signed-off-by: Abner Chang 
Cc: Saloni Kasbekar 
Cc: Zachary Clark-williams 
Cc: Michael Brown 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
---
 NetworkPkg/Include/Protocol/HttpCallback.h | 11 +++
 NetworkPkg/HttpDxe/HttpProto.c |  1 +
 NetworkPkg/HttpDxe/HttpsSupport.c  |  4 ++--
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/NetworkPkg/Include/Protocol/HttpCallback.h 
b/NetworkPkg/Include/Protocol/HttpCallback.h
index 3accd2f8424..a785c972f8f 100644
--- a/NetworkPkg/Include/Protocol/HttpCallback.h
+++ b/NetworkPkg/Include/Protocol/HttpCallback.h
@@ -39,6 +39,17 @@ typedef enum {
   ///
   HttpEventConnectTcp,
 
+  ///
+  /// The Status of Event to configure TLS configuration data.
+  /// EventStatus:
+  /// EFI_SUCCESSThe TLS is configured successfully with the 
default value.
+  /// EFI_INVALID_PARAMETER  One or more input parameters to SetSessionData() 
is invalid.
+  /// EFI_NOT_READY  Current TLS session state is NOT 
EfiTlsSessionStateNotStarted.
+  /// EFI_NOT_FOUND  Fail to get 'HttpTlsCipherList' variable.
+  /// Others Other error as indicated.
+  ///
+  HttpEventTlsConfigured,
+
   ///
   /// The Status of Event to connect one TLS session by finishing the TLS 
handshake process.
   /// EventStatus:
diff --git a/NetworkPkg/HttpDxe/HttpProto.c b/NetworkPkg/HttpDxe/HttpProto.c
index 94900328ba9..9c3b497dce2 100644
--- a/NetworkPkg/HttpDxe/HttpProto.c
+++ b/NetworkPkg/HttpDxe/HttpProto.c
@@ -1418,6 +1418,7 @@ HttpInitSession (
   //
   if (TlsConfigure) {
 Status = TlsConfigureSession (HttpInstance);
+HttpNotify (HttpEventTlsConfigured, Status);
 if (EFI_ERROR (Status)) {
   return Status;
 }
diff --git a/NetworkPkg/HttpDxe/HttpsSupport.c 
b/NetworkPkg/HttpDxe/HttpsSupport.c
index 04a830f7152..8d7bffe1e9c 100644
--- a/NetworkPkg/HttpDxe/HttpsSupport.c
+++ b/NetworkPkg/HttpDxe/HttpsSupport.c
@@ -723,7 +723,7 @@ TlsConfigureSession (
   Status = TlsConfigCertificate (HttpInstance);
   if (EFI_ERROR (Status)) {
 if (Status == EFI_NOT_FOUND) {
-  DEBUG((DEBUG_WARN, "TLS Certificate is not found on the system!\n"));
+  DEBUG ((DEBUG_WARN, "TLS Certificate is not found on the system!\n"));
   //
   // We still return EFI_SUCCESS to the caller when TlsConfigCertificate
   // returns error, for the use case the platform doesn't require
@@ -734,7 +734,7 @@ TlsConfigureSession (
   //
   Status = EFI_SUCCESS;
 } else {
-  DEBUG((DEBUG_ERROR, "TLS Certificate Config Error!\n"));
+  DEBUG ((DEBUG_ERROR, "TLS Certificate Config Error!\n"));
   return Status;
 }
   }
-- 
2.37.1.windows.1



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[edk2-devel] [PATCH 2/5] NetwokrPkg/HttpDxe: Consider TLS certificate not found as a success case

[Chang, Abner via groups.io]

From: Abner Chang 

We still return EFI_SUCCESS to the caller when TlsConfigCertificate
returns error, for the use case the platform doesn't require
certificate for the specific HTTP session. This ensures
HttpInitSession function still initiated and returns EFI_SUCCESS to
the caller. The failure is pushed back to TLS DXE driver if the
HTTP communication actually requires certificate.

Signed-off-by: Abner Chang 
Cc: Saloni Kasbekar 
Cc: Zachary Clark-williams 
Cc: Michael Brown 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
---
 NetworkPkg/HttpDxe/HttpsSupport.c | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/NetworkPkg/HttpDxe/HttpsSupport.c 
b/NetworkPkg/HttpDxe/HttpsSupport.c
index a07323ff0bd..04a830f7152 100644
--- a/NetworkPkg/HttpDxe/HttpsSupport.c
+++ b/NetworkPkg/HttpDxe/HttpsSupport.c
@@ -722,8 +722,21 @@ TlsConfigureSession (
   //
   Status = TlsConfigCertificate (HttpInstance);
   if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "TLS Certificate Config Error!\n"));
-return Status;
+if (Status == EFI_NOT_FOUND) {
+  DEBUG((DEBUG_WARN, "TLS Certificate is not found on the system!\n"));
+  //
+  // We still return EFI_SUCCESS to the caller when TlsConfigCertificate
+  // returns error, for the use case the platform doesn't require
+  // certificate for the specific HTTP session. This ensures
+  // HttpInitSession function still initiated and returns EFI_SUCCESS to
+  // the caller. The failure is pushed back to TLS DXE driver if the
+  // HTTP communication actually requires certificate.
+  //
+  Status = EFI_SUCCESS;
+} else {
+  DEBUG((DEBUG_ERROR, "TLS Certificate Config Error!\n"));
+  return Status;
+}
   }
 
   //
-- 
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[edk2-devel] [PATCH 1/5] NetwokrPkg/HttpDxe: Refactor TlsCreateChild

[Chang, Abner via groups.io]

From: Abner Chang 

- Use HTTP instance as the parameter for TlsCreateChild function.
- Install TLS protocol on the HTTP instance thats create TLS child.

Signed-off-by: Abner Chang 
Cc: Saloni Kasbekar 
Cc: Zachary Clark-williams 
Cc: Michael Brown 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
---
 NetworkPkg/HttpDxe/HttpProto.h|  3 +-
 NetworkPkg/HttpDxe/HttpsSupport.h | 18 ---
 NetworkPkg/HttpDxe/HttpImpl.c | 23 ++---
 NetworkPkg/HttpDxe/HttpProto.c|  7 +--
 NetworkPkg/HttpDxe/HttpsSupport.c | 78 ++-
 5 files changed, 64 insertions(+), 65 deletions(-)

diff --git a/NetworkPkg/HttpDxe/HttpProto.h b/NetworkPkg/HttpDxe/HttpProto.h
index 012f1f4b467..7e77b389a78 100644
--- a/NetworkPkg/HttpDxe/HttpProto.h
+++ b/NetworkPkg/HttpDxe/HttpProto.h
@@ -3,6 +3,7 @@
 
 Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
 (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -171,7 +172,7 @@ typedef struct _HTTP_PROTOCOL {
   BOOLEAN   UseHttps;
 
   EFI_SERVICE_BINDING_PROTOCOL  *TlsSb;
-  EFI_HANDLETlsChildHandle; /// Tls ChildHandle
+  BOOLEAN   TlsAlreadyCreated;
   TLS_CONFIG_DATA   TlsConfigData;
   EFI_TLS_PROTOCOL  *Tls;
   EFI_TLS_CONFIGURATION_PROTOCOL*TlsConfiguration;
diff --git a/NetworkPkg/HttpDxe/HttpsSupport.h 
b/NetworkPkg/HttpDxe/HttpsSupport.h
index 3c70825e8c3..5b44c7ac395 100644
--- a/NetworkPkg/HttpDxe/HttpsSupport.h
+++ b/NetworkPkg/HttpDxe/HttpsSupport.h
@@ -2,6 +2,7 @@
   The header files of miscellaneous routines specific to Https for HttpDxe 
driver.
 
 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -30,21 +31,18 @@ IsHttpsUrl (
 /**
   Creates a Tls child handle, open EFI_TLS_PROTOCOL and 
EFI_TLS_CONFIGURATION_PROTOCOL.
 
-  @param[in]  ImageHandle   The firmware allocated handle for the UEFI 
image.
-  @param[out] TlsSb Pointer to the TLS 
SERVICE_BINDING_PROTOCOL.
-  @param[out] TlsProto  Pointer to the EFI_TLS_PROTOCOL instance.
-  @param[out] TlsConfiguration  Pointer to the 
EFI_TLS_CONFIGURATION_PROTOCOL instance.
+  @param[in]  HttpInstance  Pointer to HTTP_PROTOCOL structure.
 
-  @return  The child handle with opened EFI_TLS_PROTOCOL and 
EFI_TLS_CONFIGURATION_PROTOCOL.
+  @return  EFI_SUCCESSTLS child handle is returned in 
HttpInstance->TlsChildHandle
+  with opened EFI_TLS_PROTOCOL and 
EFI_TLS_CONFIGURATION_PROTOCOL.
+   EFI_DEVICE_ERROR   TLS service binding protocol is not found.
+   Otherwise  Fail to create TLS chile handle.
 
 **/
-EFI_HANDLE
+EFI_STATUS
 EFIAPI
 TlsCreateChild (
-  IN  EFI_HANDLE  ImageHandle,
-  OUT EFI_SERVICE_BINDING_PROTOCOL**TlsSb,
-  OUT EFI_TLS_PROTOCOL**TlsProto,
-  OUT EFI_TLS_CONFIGURATION_PROTOCOL  **TlsConfiguration
+  IN  HTTP_PROTOCOL  *HttpInstance
   );
 
 /**
diff --git a/NetworkPkg/HttpDxe/HttpImpl.c b/NetworkPkg/HttpDxe/HttpImpl.c
index 7c5c925cf78..6606c293421 100644
--- a/NetworkPkg/HttpDxe/HttpImpl.c
+++ b/NetworkPkg/HttpDxe/HttpImpl.c
@@ -3,6 +3,7 @@
 
   Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
   (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -248,7 +249,6 @@ EfiHttpRequest (
   HTTP_TOKEN_WRAP*Wrap;
   CHAR8  *FileUrl;
   UINTN  RequestMsgSize;
-  EFI_HANDLE ImageHandle;
 
   //
   // Initializations
@@ -371,23 +371,10 @@ EfiHttpRequest (
 //
 // Check whether we need to create Tls child and open the TLS protocol.
 //
-if (HttpInstance->UseHttps && (HttpInstance->TlsChildHandle == NULL)) {
-  //
-  // Use TlsSb to create Tls child and open the TLS protocol.
-  //
-  if (HttpInstance->LocalAddressIsIPv6) {
-ImageHandle = HttpInstance->Service->Ip6DriverBindingHandle;
-  } else {
-ImageHandle = HttpInstance->Service->Ip4DriverBindingHandle;
-  }
-
-  HttpInstance->TlsChildHandle = TlsCreateChild (
-   ImageHandle,
-   &(HttpInstance->TlsSb),
-   &(HttpInstance->Tls),
-   &(HttpInstance->TlsConfiguration)
-   );
-  if (HttpInstance->TlsChildHandle == NULL) {
+if (HttpInstance->UseHttps && !HttpInstance->TlsAlreadyCreated) {
+  // Create TLS child for this HTTP instance.
+  Status = 

[edk2-devel] [PATCH 0/5] Refactor HTTP DXE to provide TLS reconfiguration capability

[Chang, Abner via groups.io]

From: Abner Chang 

For the HTTPS connetion that doesn't require TLS peer verification,
We introduce a new HTTP event HttpEventTlsConfigured to notify HTTP callback
functions after TlsConfigureSession(). With this event, the upper layer
HTTP application can listen to HttpEventTlsConfigured HTTP event and
reconfigure TLS configuration data in the callback function to set TLS verify
method to TLS_VERIFY_NONE.
The use case such as Redfish service connction which doesn't require the
TLS peer verification on the cetificate, especially to the Redfish service
connection through the in-band network interface.
The root cause we are fixing is the TLS config data is hardcoded in
TlsConfigureSession() for any TLS child in HttpSupport.c. With this hardcoded
code, HTTP application has no way to give the proper TLS config data when TLS
session is initiated.

In Patch 1/5: We agreed to refactor TlsCreateChild and install TLS on
  the given HTTP handle.
In Patch 2/5: We consider TLS certificate not found as a success case to
  ensures HTTP session is still initiated and HttpInitSession()
  returns EFI_SUCCESS to the caller. The failure is pushed back to
  TLS DXE driver if the HTTP communication actually requires
  certificate.
In Patch 3/5: Introduce HttpEventTlsConfigured HTTP callback event
In Patch 4/5: REST EX DXE provides HTTP event callback protocol
In Patch 5/5: REST EX DXE fix.

Signed-off-by: Abner Chang 
Cc: Saloni Kasbekar 
Cc: Zachary Clark-williams 
Cc: Michael Brown 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 

Abner Chang (5):
  NetwokrPkg/HttpDxe: Refactor TlsCreateChild
  NetwokrPkg/HttpDxe: Consider TLS certificate not found as a success
case
  NetwokrPkg/HttpDxe: Add HttpEventTlsConfigured HTTP callback event
  RedfishPkg/RedfishRestExDxe: Implement EDKII_HTTP_CALLBACK_PROTOCOL
  RedfishPkg/RedfishRestExDxe: Update Supported function

 .../RedfishRestExDxe/RedfishRestExDxe.inf |  2 +
 NetworkPkg/HttpDxe/HttpProto.h|  3 +-
 NetworkPkg/HttpDxe/HttpsSupport.h | 18 ++--
 NetworkPkg/Include/Protocol/HttpCallback.h| 11 +++
 .../RedfishRestExDxe/RedfishRestExDriver.h| 31 --
 NetworkPkg/HttpDxe/HttpImpl.c | 23 +
 NetworkPkg/HttpDxe/HttpProto.c|  8 +-
 NetworkPkg/HttpDxe/HttpsSupport.c | 95 ---
 .../RedfishRestExDxe/RedfishRestExDriver.c| 84 
 9 files changed, 198 insertions(+), 77 deletions(-)

-- 
2.37.1.windows.1



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