[edk2-devel] [Patch V3 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/SerialIo/IncludePrivate
* IpBlock/SerialIo/Library
* IpBlock/SerialIo/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h
| 377
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Register/SerialIoRegsVer2.h
| 108
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSerialIoAccessLib/PeiDxeSmmSerialIoAccessLib.inf
| 35 +++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSerialIoAccessLib/SerialIoAccessLib.c
| 266
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf
| 34 ++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLib.c
| 156
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibI2c.c
| 122
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibI2cVer2.c
| 70
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibInternal.h
| 20
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibSpi.c
| 122
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibSpiVer2.c
| 82
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibUart.c
| 136
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibUartVer2.c
| 82
++
13 files changed, 1610 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h
new file mode 100644
index 00..47057cd2ef
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h
@@ -0,0 +1,377 @@
+/** @file
+ Header file for Serial IO Private Lib implementation.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_PRIVATE_LIB_H_
+#define _SERIAL_IO_PRIVATE_LIB_H_
+
+#include
+#include
+
+/**
+ Serial Io Pci Device State structure.
+ Used to preserve current information about the device when it is configured
in Pci mode prior to Pch Initialization.
+**/
+typedef struct {
+ UINT64 PciCfgBar0; ///< Pci Config Space Base Address Register
+ UINT8 PciCfgCommand;///< Pci Config Space Command Register
+ UINT8 PciCfgPmeCtrlSts; ///< Pci Config Space Pme Control Status
+ UINT8 PprReset; ///< MMIO Proprietary Reset Register
+} SERIAL_IO_PCI_DEVICE_STATE;
+
+/**
+ Checks if higher functions are enabled.
+ Used for Function 0 Seri
[edk2-devel] [Patch V3 19/40] TigerlakeSiliconPkg/IpBlock: Add Hda component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/Hda/IncludePrivate * IpBlock/Hda/Library * IpBlock/Hda/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Library/DxeHdaPolicyLib.h | 55 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Register/HdaRegs.h | 46 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/Library/DxeHdaNhltLib/DxeHdaNhltLib.c | 383 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/Library/DxeHdaNhltLib/DxeHdaNhltLib.inf | 31 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/LibraryPrivate/DxeHdaPolicyLib/DxeHdaPolicyLib.c | 92 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/LibraryPrivate/DxeHdaPolicyLib/DxeHdaPolicyLib.inf | 31 +++ 6 files changed, 638 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Library/DxeHdaPolicyLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Library/DxeHdaPolicyLib.h new file mode 100644 index 00..9c42bf5611 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Library/DxeHdaPolicyLib.h @@ -0,0 +1,55 @@ +/** @file + DXE Hda policy library. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _DXE_HDA_POLICY_LIB_H_ +#define _DXE_HDA_POLICY_LIB_H_ + +#include + +/** + Print HDAUDIO_DXE_CONFIG and serial out. + + @param[in] PchPolicyPointer to a PCH_POLICY_PROTOCOL +**/ +VOID +HdaDxePrintConfig ( + IN PCH_POLICY_PROTOCOL*PchPolicy + ); + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +HdaDxeLoadConfigDefault ( + IN VOID *ConfigBlockPointer + ); + +/** + Get Hda config block table size. + + @retval Size of config block +**/ +UINT16 +HdaDxeGetConfigBlockTotalSize ( + VOID + ); + +/** + Add Hda ConfigBlock. + + @param[in] ConfigBlockTableAddressThe pointer to config block table + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +HdaDxeAddConfigBlock ( + IN VOID *ConfigBlockTableAddress + ); + +#endif // _DXE_HDA_POLICY_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Register/HdaRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Register/HdaRegs.h new file mode 100644 index 00..b165e7bb22 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Register/HdaRegs.h @@ -0,0 +1,46 @@ +/** @file + Register names for High Definition Audio device. + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName + - Prefix: +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values within the bits +Definitions beginning with "S_" are register size +Definitions beginning with "N_" are the bit position + - [GenerationName]: +Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). +Register name without GenerationName applies to all generations. + - [ComponentName]: +This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) +Register name without ComponentName applies to all components. +Register that is specific to -LP denoted by "_PCH_LP_" in component name. + - SubsystemName: +This field indicates the subsystem name of the component that the register belongs to +(e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: +MEM - MMIO space register of subsystem. +IO - IO space register of subsystem. +PCR - Private configuration register of subsystem. +CFG - PCI configuration space register of subsystem. + - RegisterName: +Full register name. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _HDA_REGS_
[edk2-devel] [Patch V3 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Psf/IncludePrivate
* IpBlock/Psf/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h
| 520
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PeiDxeSmmPsfLibVer2.inf
| 40
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLib.c
| 203
+++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibInternal.h
| 470
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibVer2.c
| 115
+++
5 files changed, 1348 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h
new file mode 100644
index 00..f333be48d2
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h
@@ -0,0 +1,520 @@
+/** @file
+ Header file for PchPsfPrivateLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PSF_PRIVATE_LIB_H_
+#define _PCH_PSF_PRIVATE_LIB_H_
+
+#include
+#include
+
+typedef struct {
+ UINT32 Id;
+ PCH_SBI_PID SbPid;
+} PSF_SEGMENT;
+
+/**
+ Get list of supported PSF segments.
+
+ @param[out] PsfTableArray of supported PSF segments
+ @param[out] PsfTableLength Length of PsfTable
+**/
+VOID
+PsfSegments (
+ OUT PSF_SEGMENT **PsfTable,
+ OUT UINT32 *PsfTableLength
+ );
+
+//
+// Structure for storing data on both PSF SideBand Port ID and
+// PSF port register offset for specific device
+//
+typedef struct {
+ PCH_SBI_PID PsfPid;
+ UINT16 RegBase;
+} PSF_PORT;
+
+/**
+ Disable device at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+**/
+VOID
+PsfDisableDevice (
+ IN PSF_PORT PsfPort
+ );
+
+/**
+ Enable device at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+**/
+VOID
+PsfEnableDevice (
+ IN PSF_PORT PsfPort
+ );
+
+/**
+ Hide PciCfgSpace of device at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+**/
+VOID
+PsfHideDevice (
+ IN PSF_PORT PsfPort
+ );
+
+/**
+ Unhide PciCfgSpace of device at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+**/
+VOID
+PsfUnhideDevice (
+ IN PSF_PORT PsfPort
+ );
+
+/**
+ Disable device BARs at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+ @param[in] BarDisMask BIT0-BAR0, BIT1-BAR1,...
+ Mask corresponds to 32bit wide BARs
+**/
+VOID
+PsfDisableDeviceBar (
+ IN PSF_PORT PsfPort,
+ IN UINT32BarDisMask
+ );
+
+/**
+ Enable device BARs at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+ @param[in] BarEnMask BIT0-BAR0, BIT1-BAR1,...
+ Mask corresponds to 32bit wide BARs
+**/
+VOID
+PsfEnableDeviceBar (
+ IN PSF_PORT PsfPort,
+ IN UINT32BarEnMask
+ );
+
+/**
+ Disable IDER device at PSF level
+**/
+VOID
+PsfDisableIderDevice (
+ VOID
+ );
+
+/**
+ Enable SOL device at PSF level
+**/
+VOID
+PsfEnableSolDevice (
+ VOID
+ );
+
+/**
+ Disable SOL device at PSF level
+**/
+VOID
[edk2-devel] [Patch V3 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Sata/Library
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
| 32
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
| 138
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLibVer2.c
| 83
+++
3 files changed, 253 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
new file mode 100644
index 00..1c304fed59
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
@@ -0,0 +1,32 @@
+## @file
+# PEI/DXE/SMM PCH SATA library Ver2
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchSataLibVer2
+FILE_GUID = 2519ADE8-D971-4551-8A8E-2EB55DFC555B
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SataLib
+
+[LibraryClasses]
+BaseLib
+PciSegmentLib
+PchInfoLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+TigerlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+SataLib.c
+SataLibVer2.c
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
new file mode 100644
index 00..49cba49910
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
@@ -0,0 +1,138 @@
+/** @file
+ Pch SATA library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Get SATA controller address that can be passed to the PCI Segment Library
functions.
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller address in PCI Segment Library representation
+**/
+UINT64
+SataRegBase (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+
+ return SataPciCfgBase (SataCtrlIndex);
+}
+
+/**
+ Get SATA controller's Port Present Status
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval Port Present Status
+**/
+UINT8
+GetSataPortPresentStatus (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+
+ return PciSegmentRead8 (SataPciCfgBase (SataCtrlIndex) + R_SATA_CFG_PCS + 2);
+}
+
+/**
+ Get SATA controller Function Disable Status
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval 0 SATA Controller is not Function Disabled
+ @retval 1 SATA Controller is Function Disabled
+**/
+BOOLEAN
+SataControllerFunctionDisableStatus (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ UINT32 SataGc;
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+ SataGc = PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) +
R_SATA_CFG_SATAGC);
+ return !!(SataGc & BIT10);
+}
+
+/**
+ Get SATA controller ABAR size
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller ABAR size
+**/
+UINT32
+GetSataAbarSize (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ UINT32 SataGc;
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+ SataGc = PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) +
R_SATA_CFG_SATAGC);
+
+ switch (SataGc & B_SATA_CFG_SATAGC_ASSEL) {
+case V_SATA_CFG_SATAGC_ASSEL_2K:
+ return SIZE_2KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_16K:
+ return SIZE_16KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_32K:
+ return SIZE_32KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_64K:
+ return SIZE_64KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_128K:
+ return SIZE_128KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_512K:
+ return SIZE_256KB;
+ break;
+
+default:
+ return SIZE_2KB;
+ break;
+ }
+}
+
+/**
+ Get SATA controller AHCI base address
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller AHCI base address
+**/
+UIN
[edk2-devel] [Patch V3 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Pmc/IncludePrivate
* IpBlock/Pmc/Library
* IpBlock/Pmc/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
| 120
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Register/PmcRegsVer2.h
| 52
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
| 42 ++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
| 545
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
| 39 +++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf
| 40
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
| 166
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLibWithS3.c
| 122
++
8 files changed, 1126 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 00..0f2f251d57
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,120 @@
+/** @file
+ Header file for private PmcLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include
+#include "Register/PmcRegs.h"
+
+/**
+ This function checks if GbE device is supported (not disabled by fuse)
+
+ @retval GbE support state
+**/
+BOOLEAN
+PmcIsGbeSupported (
+ VOID
+ );
+
+/**
+ This function checks if LAN wake from DeepSx is enabled
+
+ @retval Lan Wake state
+**/
+BOOLEAN
+PmcIsLanDeepSxWakeEnabled (
+ VOID
+ );
+
+/**
+ This function sets SMI Lock with S3 Boot Script programming
+**/
+VOID
+PmcLockSmiWithS3BootScript (
+ VOID
+ );
+
+/**
+ This function sets eSPI SMI Lock
+ @attention This function must be called after eSPI SMI generation has been
enabled.
+This setting is required in all boot modes and before EndOfDxe.
+If set value will be restored upon S3 resume by bootscript.
+**/
+VOID
+PmcLockEspiSmiWithS3BootScript (
+ VOID
+ );
+
+/**
+ This function checks if eSPI SMI Lock is set
+
+ @retval eSPI SMI Lock state
+**/
+BOOLEAN
+PmcIsEspiSmiLockSet (
+ VOID
+ );
+
+typedef enum {
+ PmcSwSmiRate1p5ms = 0,
+ PmcSwSmiRate16ms,
+ PmcSwSmiRate32ms,
+ PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRateRefer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ );
+
+typedef enum {
+ PmcPeriodicSmiRate8s = 0,
+ PmcPeriodicSmiRate16s,
+ PmcPeriodicSmiRate32s,
+ PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRateRefer to PMC_PERIODIC_SMI_RATE for
possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATEPeriodicSmiRate
+ );
+
+/**
+ This function reads Power Button Level
+
+ @retval State of PWRBTN# signal (0: Low, 1: High)
+**/
+UINT8
+PmcGetPwrBtnLevel (
+ VOID
+ );
+
+/**
+ This function gets Group to GPE0 configuration
+
+ @param[out] GpeDw0Value GPIO Group to GPE_DW0 assignment
+ @param[out] GpeDw1Value GPIO Group to GPE_DW1 assignment
[edk2-devel] [Patch V3 23/40] TigerlakeSiliconPkg/IpBlock: Add PcieRp component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/PcieRp/IncludePrivate * IpBlock/PcieRp/Library * IpBlock/PcieRp/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/DxePchPcieRpPolicyLib.h | 55 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/PciExpressHelpersLib.h | 173 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/PcieRpLib.h | 109 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Register/PcieSipRegs.h | 45 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/BasePcieHelperLib/BasePcieHelperLib.c | 315 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/BasePcieHelperLib/BasePcieHelperLib.inf | 37 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLib.c | 69 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h | 20 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c | 128 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf | 39 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c | 179 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.inf | 30 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PciExpressHelpersLibrary/PciExpressHelpersLibrary.c | 1997 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PciExpressHelpersLibrary/PciExpressHelpersLibrary.h | 40 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PciExpressHelpersLibrary/PeiDxeSmmPciExpressHelpersLib.inf | 49 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c | 247 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.inf | 43 +++ 17 files changed, 3575 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/DxePchPcieRpPolicyLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/DxePchPcieRpPolicyLib.h new file mode 100644 index 00..1dea61388e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/DxePchPcieRpPolicyLib.h @@ -0,0 +1,55 @@ +/** @file + DXE PcieRp policy library. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _DXE_PCH_PCIERP_POLICY_LIB_H_ +#define _DXE_PCH_PCIERP_POLICY_LIB_H_ + +#include + +/** + Load DXE Config block default for Pch PCIE RP + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadPchPcieRpDxeConfigDefault ( + IN VOID *ConfigBlockPointer
[edk2-devel] [Patch V3 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/PchDmi/IncludePrivate * IpBlock/PchDmi/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h | 175 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c | 50 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h | 34 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c | 269 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiWithS3Lib.c | 73 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf | 42 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf | 41 + 7 files changed, 684 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h new file mode 100644 index 00..77db69c75a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h @@ -0,0 +1,175 @@ +/** @file + Header file for PchDmiLib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_DMI_LIB_H_ +#define _PCH_DMI_LIB_H_ + +/** + This function checks if DMI Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmiLocked ( + VOID + ); + +/** + Get PCH TCO base address. + + @retval Address Address of TCO base address. +**/ +UINT16 +PchDmiGetTcoBase ( + VOID + ); + +/** + Set PCH LPC/eSPI generic IO range decoding in DMI + + @param[in] AddressAddress for generic IO range base address. + @param[in] Length Length of generic IO range. + @param[in] RangeIndex Index of choosen range + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcGenIoRange ( + IN UINT32Address, + IN UINT32Length, + IN UINT32RangeIndex + ); + +/** + Set PCH eSPI eSPI CS1# generic IO range decoding in DMI + + @param[in] AddressAddress for generic IO range base address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetEspiCs1GenIoRange ( + IN UINT32Address, + IN UINT32Length + ); + +/** + Set PCH LPC/eSPI memory range decoding in DMI + + @param[in] AddressAddress for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcMemRange ( + IN UINT32Address + ); + +/** + Set PCH eSPI CS1# memory range decoding in DMI + + @param[in] AddressAddress for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetEspiCs1MemRange ( + IN UINT32Address + ); + +/** + Check if Boot BIOS Strap is set for SPI. + + @retval TRUEBoot BIOS Strap set for SPI + @retval FALSE Boot BIOS Strap set for LPC/eSPI +**/ +BOOLEAN +PchDmiIsBootBiosStrapSetForSpi ( + VOID + ); + +/** + Set PCH BIOS range decoding in DMI + Please check EDS for detail of BiosDecodeEnable bit definition. +bit 15: F8-FF Enable +bit 14: F0-F8 Enable +bit 13: E8-EF Enable +bit 12: E0-E8 Enable +bit 11: D8-DF Enable +bit 10: D0-D7 Enable +bit 9: C8-CF
[edk2-devel] [Patch V3 21/40] TigerlakeSiliconPkg/IpBlock: Add P2sb component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/P2sb/IncludePrivate
* IpBlock/P2sb/Library
* IpBlock/P2sb/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
| 112
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
| 65
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuRegbarAccessLib/CpuRegbarAccessLib.c
| 494
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuRegbarAccessLib/PeiDxeSmmCpuRegbarAccessLib.inf
| 35 +++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
| 313
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
| 35 +++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
| 253
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
| 36
8 files changed, 1343 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
new file mode 100644
index 00..3fab933bbd
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
@@ -0,0 +1,112 @@
+/** @file
+ Header file for PchSbiAccessLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SBI_ACCESS_LIB_H_
+#define _PCH_SBI_ACCESS_LIB_H_
+
+#include
+
+/**
+ PCH SBI opcode definitions
+**/
+typedef enum {
+ MemoryRead = 0x0,
+ MemoryWrite= 0x1,
+ PciConfigRead = 0x4,
+ PciConfigWrite = 0x5,
+ PrivateControlRead = 0x6,
+ PrivateControlWrite= 0x7,
+ GpioLockUnlock = 0x13
+} PCH_SBI_OPCODE;
+
+/**
+ PCH SBI response status definitions
+**/
+typedef enum {
+ SBI_SUCCESSFUL = 0,
+ SBI_UNSUCCESSFUL= 1,
+ SBI_POWERDOWN = 2,
+ SBI_MIXED = 3,
+ SBI_INVALID_RESPONSE
+} PCH_SBI_RESPONSE;
+
+/**
+ Execute PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in
both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If
more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after
done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be
checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would
provide additional information
+ when needed.
+
+ @param[in] PidPort ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in, out] Data32Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully complete
[edk2-devel] [Patch V3 20/40] TigerlakeSiliconPkg/IpBlock: Add HostBridge component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/HostBridge/IncludePrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
| 25 +
1 file changed, 25 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
new file mode 100644
index 00..41e92da4df
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
@@ -0,0 +1,25 @@
+/** @file
+ The GUID definition for Host Bridge Data Hob
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _HOST_BRIDGE_DATA_HOB_H_
+#define _HOST_BRIDGE_DATA_HOB_H_
+
+#include
+
+extern EFI_GUID gHostBridgeDataHobGuid;
+#pragma pack (push,1)
+
+///
+/// Host Bridge Data Hob
+///
+typedef struct {
+ EFI_HOB_GUID_TYPEEfiHobGuidType; ///< GUID Hob
type structure for gSaDataHobGuid
+ UINT8EnableAbove4GBMmio; ///<
0=Disable above 4GB MMIO resource support, 1=Enable above 4GB MMIO resource
support
+ BOOLEAN SkipPamLock; ///< 0=All
PAM registers will be locked in System Agent code, 1=Do not lock PAM registers
in System Agent code.
+ UINT8Rsvd1[2]; ///< Reserved
for future use
+} HOST_BRIDGE_DATA_HOB;
+#pragma pack (pop)
+#endif
--
2.24.0.windows.2
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[edk2-devel] [Patch V3 15/40] TigerlakeSiliconPkg/IpBlock: Add Espi component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Espi/Library
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
| 469
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
| 38 ++
2 files changed, 507 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
new file mode 100644
index 00..2d1928ce18
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
@@ -0,0 +1,469 @@
+/** @file
+ This file contains routines for eSPI
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CHANNEL_RESET_TIMEOUT 100 ///< Channel reset timeout in us after
which to report error
+#define SLAVE_CHANNELS_MAX7 ///< Max number of channels
+
+//
+// eSPI Slave registers
+//
+#define R_ESPI_SLAVE_GENCAP 0x08 ///< General Capabilities
and Configurations
+#define B_ESPI_SLAVE_GENCAP_SUPPCHAN 0xFF ///< Channels supported
bit mask
+#define R_ESPI_SLAVE_CHACAP_BASE 0x10 ///< Base address from
which channel Cap and Conf registers start on slave
+#define S_ESPI_SLAVE_CHACAP_OFFSET0x10 ///< Offset for each
channel from base
+#define B_ESPI_SLAVE_CHACAP_CHEN BIT0 ///< Slave Channel enable
bit
+#define B_ESPI_SLAVE_CHACAP_CHRDY BIT1 ///< Slave Channel ready
bit
+
+/**
+ Checks if second slave capability is enabled
+
+ @retval TRUE There's second slave
+ @retval FALSE There's no second slave
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+/**
+ Checks in slave General Capabilities register if it supports channel with
requested number
+
+ @param[in] SlaveId Id of slave to check
+ @param[in] ChannelNumber Number of channel of which to check
+
+ @retval TRUE Channel with requested number is supported by slave device
+ @retval FALSE Channel with requested number is not supported by slave
device
+**/
+BOOLEAN
+IsEspiSlaveChannelSupported (
+ UINT8 SlaveId,
+ UINT8 ChannelNumber
+ )
+{
+ UINT32 Data32;
+ UINT8 SupportedChannels;
+
+ PchEspiSlaveGetConfig (SlaveId, R_ESPI_SLAVE_GENCAP, );
+ SupportedChannels = (UINT8) (Data32 & B_ESPI_SLAVE_GENCAP_SUPPCHAN);
+
+ DEBUG ((DEBUG_INFO, "Slave %d supported channels 0x%4X\n", SlaveId,
SupportedChannels));
+
+ if (ChannelNumber > SLAVE_CHANNELS_MAX || !(SupportedChannels & (BIT0 <<
ChannelNumber))) {
+// Incorrect channel number was specified. Either exceeded max or Slave
doesn't support that channel.
+return FALSE;
+ }
+
+ return TRUE;
+}
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ )
+{
+ return (PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_CFG_VAL) &
B_ESPI_PCR_CFG_VAL_ESPI_EN) != 0;
+}
+
+/**
+ eSPI helper function to clear slave configuration register status
+
+ @retval EFI_SUCCESS Write to private config space succeed
+ @retval others Read / Write failed
+**/
+STATIC
+VOID
+EspiClearScrs (
+ VOID
+ )
+{
+ PchPcrAndThenOr32 (
+PID_ESPISPI,
+R_ESPI_PCR_SLV_CFG_REG_CTL,
+(UINT32) ~0,
+ B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS
+ );
+}
+
+/**
+ eSPI helper function to poll slave configuration register enable for 0
+ and to check for slave configuration register status
+
+ @retval EFI_SUCCESS Enable bit is zero and no error in status bits
+ @retval EFI_DEVICE_ERROR Error in SCRS
+ @retval othersRead / Write to private config space failed
+**/
+STATIC
+EFI_STATUS
+EspiPollScreAndCheckScrs (
+ VOID
+ )
+{
+ UINT32 ScrStat;
+
+ do {
+ScrStat = PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_SLV_CFG_REG_CTL);
+ } while ((ScrStat & B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE) != 0);
+
+ ScrStat = (ScrStat & B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS) >>
N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS;
[edk2-devel] [Patch V3 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/Gbe/IncludePrivate * IpBlock/Gbe/Library * IpBlock/Gbe/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h | 324 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Register/GbeRegs.h | 68 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/GbeLib.c | 121 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/PeiDxeSmmGbeLib.inf | 43 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGbeMdiLib/GbeMdiLib.c | 388 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGbeMdiLib/PeiDxeSmmGbeMdiLib.inf | 34 ++ 6 files changed, 978 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h new file mode 100644 index 00..b8274ed3dc --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h @@ -0,0 +1,324 @@ +/** @file + Header file for GbeMdiLib. + + Conventions: + + - Prefixes: +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values within the bits +Definitions beginning with "S_" are register sizes +Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by +"_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. +Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. +e.g., "_PCH_LP_" +Registers / bits names without or _LP_ apply for LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" +at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named +as "_PCH_" without [generation_name] inserted. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GBE_MDI_LIB_H_ +#define _GBE_MDI_LIB_H_ + +// +// Maximum loop time for GbE status check +// 4000 * 50 = 200 mSec in total +// +#define GBE_MAX_LOOP_TIME 4000 +#define GBE_ACQUIRE_MDIO_DELAY 50 +#define GBE_MDI_SET_PAGE_DELAY 4000 // 4 mSec delay after setting page + +// +// LAN PHY MDI settings +// +// MDI Control Register Bits +// 31:30 Reserved +// This field is reserved and returns 0. +// 29Interrupt Enable. +// When this bit is set to 1 by software, it causes the device to assert +// an interrupt indicating the end of an MDI cycle. +// 28Ready. +// Set to 1 by the device at the end of MDI transaction (i.e., indicates a Read or +// Write has been completed. It should be reset to 0 by software at the same time the +// command is written. +// 27:26 Opcode +// For an MDI write, the opcode equals 01b, and for MDI read, 10b. 00b and +// 11b are reserved and should not be used. +// 25:21 PHYAdd +// PHY Address +// 20:16 RegAdd +// PHY Register Address +// 15:0 Data + +#define B_PHY_MDI_READYBIT28 +#define B_PHY_MDI_READ BIT27 +#define B_PHY_MDI_WRITEBIT26 +// +// PHY SPECIFIC registers +// +#define B_PHY_MDI_PHY_ADDRESS_02 BIT22 +// +// PHY GENERAL registers +// Regi
[edk2-devel] [Patch V3 13/40] TigerlakeSiliconPkg/IpBlock: Add Cnvi component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Cnvi/IncludePrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Cnvi/IncludePrivate/CnviConfigHob.h
| 27 +++
1 file changed, 27 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Cnvi/IncludePrivate/CnviConfigHob.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Cnvi/IncludePrivate/CnviConfigHob.h
new file mode 100644
index 00..e881e49d62
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Cnvi/IncludePrivate/CnviConfigHob.h
@@ -0,0 +1,27 @@
+/** @file
+ This file defines the CNVi CONFIG HOB
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CNVI_CONFIG_HOB_H_
+#define _CNVI_CONFIG_HOB_H_
+
+#include
+
+extern EFI_GUID gCnviConfigHobGuid;
+#pragma pack (push,1)
+
+/**
+ This HOB is used to pass CNVi related private information to DXE phase
+**/
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID HOB type structure for
gCnviConfigHobGuid
+ UINT32 Mode : 1; ///< 0: Disabled, 1: Auto
+ UINT32 BtCore : 1; ///< 0: Disabled, 1: Enabled
+ UINT32 BtAudioOffload : 1; ///< 0: Disabled, 1: Enabled
+ UINT32 RsvdBits0 : 29; ///< Reserved bits
+} CNVI_CONFIG_HOB;
+#pragma pack (pop)
+
+#endif // _CNVI_CONFIG_HOB_H_
--
2.24.0.windows.2
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[edk2-devel] [Patch V3 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/CpuPcieRp/Include * IpBlock/CpuPcieRp/IncludePrivate * IpBlock/CpuPcieRp/Library * IpBlock/CpuPcieRp/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h | 31 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h | 353 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieRpLib.h | 47 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Library/DxeCpuPcieRpLib.h | 18 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/CpuPcieInitCommon.c | 445 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf | 33 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/CpuPcieRpLib.c | 48 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf | 32 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.c | 62 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf | 40 10 files changed, 1109 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h new file mode 100644 index 00..15eeab0ecf --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h @@ -0,0 +1,31 @@ +/** @file + This file contains definitions of PCIe controller information + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_PCIE_INFO_H_ +#define _CPU_PCIE_INFO_H_ + +#define PCIE_HWEQ_COEFFS_MAX5 + +// +// Device 1 Memory Mapped IO Register Offset Equates +// +#define SA_PEG_DEV_NUM 0x01 +#define SA_PEG0_DEV_NUMSA_PEG_DEV_NUM +#define SA_PEG3_DEV_NUM0x06 + +// +// SA PCI Express* Port configuration +// + +#define CPU_PCIE_MAX_ROOT_PORTS4 + +#define SA_PEG_MAX_FUN 0x04 +#define SA_PEG_MAX_LANE 0x14 +#define SA_PEG_MAX_FUN_GEN3 0x03 +#define SA_PEG_MAX_LANE_GEN3 0x10 +#define SA_PEG_MAX_BUNDLE_GEN3 0x08 + +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h new file mode 100644 index 00..79b255c273 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h @@ -0,0 +1,353 @@ +/** @file +Header file for CpuPcieInitCommonLib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_PCIE_INIT_COMMON_H_ +#define _CPU_PCIE_INIT_COMMON_H_ + +#include + +/** + Print registers value + + @param[in] PrintMmioBase Mmio base address + @param[in] PrintSize Number of registers + @param[in] OffsetFromBase Offset from mmio base address + + @retval None +**/ +VOID +SaPrintRegisters ( + IN UINTNPrintMmioBase, + IN UINT32 PrintSize, + IN UINT32 OffsetFromBase + ); + +/** + Print registers value + + @param[in] PrintPciSegmentBase Pci segment base address + @param[in] PrintSize Number of registers
[edk2-devel] [Patch V3 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Fru/TglPch/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h | 66 ++ 1 file changed, 66 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h new file mode 100644 index 00..4987d21f09 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h @@ -0,0 +1,66 @@ +/** @file + Register names for PCH private chipset register + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName + - Prefix: +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values within the bits +Definitions beginning with "S_" are register size +Definitions beginning with "N_" are the bit position + - [GenerationName]: +Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). +Register name without GenerationName applies to all generations. + - [ComponentName]: +This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) +Register name without ComponentName applies to all components. +Register that is specific to -LP denoted by "_PCH_LP_" in component name. + - SubsystemName: +This field indicates the subsystem name of the component that the register belongs to +(e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: +MEM - MMIO space register of subsystem. +IO - IO space register of subsystem. +PCR - Private configuration register of subsystem. +CFG - PCI configuration space register of subsystem. + - RegisterName: +Full register name. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_REGS_PCR_H_ +#define _PCH_REGS_PCR_H_ + +/** + Definition for SBI PID + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well. +**/ +#define PID_CNVI 0x73 +#define PID_ICLK 0xAD +#define PID_DMI0x88 +#define PID_PSTH 0x89 +#define PID_ESPISPI0x72 +#define PID_SPF0x85 +#define PID_SPE0x84 +#define PID_SPD0x83 +#define PID_SPC0x82 +#define PID_SPB0x81 +#define PID_SPA0x80 +#define PID_PSF6 0x7F +#define PID_PSF4 0xBD +#define PID_PSF3 0xBC +#define PID_PSF2 0xBB +#define PID_PSF1 0xBA +#define PID_GPIOCOM0 0x6E +#define PID_GPIOCOM1 0x6D +#define PID_GPIOCOM2 0x6C +#define PID_GPIOCOM3 0x6B +#define PID_GPIOCOM4 0x6A +#define PID_GPIOCOM5 0x69 +#define PID_CSME_PSF 0x8F + +#endif -- 2.24.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#71315): https://edk2.groups.io/g/devel/message/71315 Mute This Topic: https://groups.io/mt/80401144/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [Patch V3 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Fru/TglPch/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h | 326 ++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.h| 16 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResources.h | 55 +++ 3 files changed, 397 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h new file mode 100644 index 00..0d00f25d5e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h @@ -0,0 +1,326 @@ +/** @file + Header file for TigerLake PCH devices PCI Bus Device Function map. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_BDF_ASSIGNMENT_H_ +#define _PCH_BDF_ASSIGNMENT_H_ + +#define NOT_PRESENT 0xFF + +#define MAX_SATA_CONTROLLER 1 + +// +// PCH PCIe Controllers +// +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 NOT_PRESENT + +// +// USB3 (XHCI) Controller PCI config +// +#define PCI_DEVICE_NUMBER_PCH_XHCI20 +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 + +// +// xDCI (OTG) USB Device Controller +// +#define PCI_DEVICE_NUMBER_PCH_XDCI20 +#define PCI_FUNCTION_NUMBER_PCH_XDCI 1 + +// +// Thermal Device +// +#define PCI_DEVICE_NUMBER_PCH_THERMAL NOT_PRESENT +#define PCI_FUNCTION_NUMBER_PCH_THERMAL NOT_PRESENT + +// +// CSME HECI #1 +// +#define PCI_DEVICE_NUMBER_PCH_HECI1 22 +#define PCI_FUNCTION_NUMBER_PCH_HECI1 0 + +// +// CSME HECI #2 +// +#define PCI_DEVICE_NUMBER_PCH_HECI2 22 +#define PCI_FUNCTION_NUMBER_PCH_HECI2 1 + +// +// CSME IDE-Redirection (IDE-R) +// +#define PCI_DEVICE_NUMBER_PCH_IDER22 +#define PCI_FUNCTION_NUMBER_PCH_IDER 2 + +// +// CSME Keyboard and Text (KT) Redirection +// +#define PCI_DEVICE_NUMBER_PCH_KTR 22 +#define PCI_FUNCTION_NUMBER_PCH_KTR 3 + +// +// CSME HECI #3 +// +#define PCI_DEVICE_NUMBER_PCH_HECI3 22 +#define PCI_FUNCTION_NUMBER_PCH_HECI3 4 + +// +// CSME HECI #4 +// +#define PCI_DEVICE_NUMBER_PCH_HECI4 22 +#define PCI_FUNCTION_NUMBER_PCH_HECI4 5 + +// +// CSME MROM +// +#define PCI_DEVICE_NUMBER_PCH_MROMNOT_PRESENT +#define PCI_FUNCTION_NUMBER_PCH_MROM NOT_PRESENT + +// +// CSME WLAN +// +#define PCI_DEVICE_NUMBER_PCH_WLAN22 +#define PCI_FUNCTION_NUMBER_PCH_WLAN 7 + +// +// SATA
[edk2-devel] [Patch V3 06/40] TigerlakeSiliconPkg/Pch: Add IncludePrivate headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Pch/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h | 47 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h | 26 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h | 269 + Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchHybridStorageHob.h | 21 + Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchNvsAreaDef.h | 319 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchRstHob.h | 58 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PchNvsArea.h | 30 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PcieIoTrap.h | 35 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/SiScheduleResetHob.h | 21 + 9 files changed, 826 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h new file mode 100644 index 00..2ad80a0269 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h @@ -0,0 +1,47 @@ +/** @file + Reset scheduling library services + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_SCHEDULE_RESET_LIB_H_ +#define _SI_SCHEDULE_RESET_LIB_H_ + +#include +#include + +/** + This function updates the reset information in SiScheduleResetHob + @param[in] ResetTypeUEFI defined reset type. + @param[in] ResetDataOptional element used to introduce a platform specific reset. + The exact type of the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. +**/ +VOID +SiScheduleResetSetType ( + IN EFI_RESET_TYPE ResetType, + IN PCH_RESET_DATA *ResetData OPTIONAL + ); + +/** + This function returns TRUE or FALSE depending on whether a reset is required based on SiScheduleResetHob + + @retval BOOLEAN The function returns FALSE if no reset is required +**/ +BOOLEAN +SiScheduleResetIsRequired ( + VOID + ); + +/** + This function performs reset based on SiScheduleResetHob + + @retval BOOLEAN The function returns FALSE if no reset is required +**/ +BOOLEAN +SiScheduleResetPerformReset ( + VOID + ); + +#endif //_SI_SCHEDULE_RESET_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h new file mode 100644 index 00..955dac5a82 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h @@ -0,0 +1,26 @@ +/** @file + Header file for private PCH SMM Lib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SMM_PCH_PRIVATE_LIB_H_ +#define _SMM_PCH_PRIVATE_LIB_H_ + +/** + Set InSmm.Sts bit +**/ +VOID +PchSetInSmmSts ( + VOID + ); + +/** + Clear InSmm.Sts bit +**/ +VOID +PchClearInSmmSts ( + VOID + ); + +#endif // _SMM_PCH_PRIVATE_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h new file mode 100644 index 00..13a41f8d04 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h @@ -0,0 +1,269 @@ +/** @file + The GUID definition for PchConfigHob + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_CONFIG_HOB_H_ +#define _PCH_CONFIG_HOB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +extern EFI_GUID gPchConfigHobGuid; + +#pragma pack (push,1
[edk2-devel] [Patch V3 07/40] TigerlakeSiliconPkg/SystemAgent: Add include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following header files:
* SystemAgent/Include
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
| 123
+++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieDxeConfig.h
| 114
++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PramPreMemConfig.h
| 34 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiConfig.h
| 24
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h
| 104
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/SaPlatformLib.h
| 48
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h
| 245
+
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h
| 61 +
8 files changed, 753 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
new file mode 100644
index 00..451e295b49
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
@@ -0,0 +1,123 @@
+/** @file
+ Memory DXE Policy definitions
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MEMORY_DXE_CONFIG_H_
+#define _MEMORY_DXE_CONFIG_H_
+
+#pragma pack(push, 1)
+
+#define MEMORY_DXE_CONFIG_REVISION 1
+
+typedef struct _MEMORY_DXE_CONFIG MEMORY_DXE_CONFIG;
+
+/**
+ Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator
field.
+ Implementation of this function is optional, if this function pointer is
NULL then
+ the reference implementation of DeviceLocator will be used.
+
+ @param[in] This A pointer to this instance of
MEMORY_DXE_CONFIG.
+ @param[in] ControllerDesired Controller to get a
DeviceLocator string for.
+ @param[in] Dimm Desired DIMM to get a
DeviceLocator string for.
+ @param[in] MdSocket 0 = Memory Down, 1 = Socketed.
+
+ @retval The DeviceLocator string
+ @retval NULL If the return value is NULL, the
default value will be used.
+**/
+typedef
+CHAR8*
+(EFIAPI *MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING)(
+ IN CONSTMEMORY_DXE_CONFIG *This,
+ IN UINT8 Controller,
+ IN UINT8 Dimm,
+ IN UINT8 MdSocket
+ );
+
+/**
+ Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator
field.
+ Implementation of this function is optional, if this function pointer is
NULL then
+ the reference implementation of DeviceLocator will be used.
+
+ @param[in] This A pointer to this instance of
MEMORY_DXE_CONFIG.
+ @param[in] ControllerDesired Controller to get a
BankLocator string for.
+ @param[in] Dimm Desired DIMM to get a BankLocator
string for.
+ @param[in] MdSocket 0 = Memory Down, 1 = Socketed.
+
+ @retval The BankLocator string
+ @retval NULL If the return value is NULL, the
default value will be used.
+**/
+typedef
+CHAR8*
+(EFIAPI *MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING)(
+ IN CONSTMEMORY_DXE_CONFIG *This,
+ IN UINT8 Controller,
+ IN UINT8 Dimm,
+ IN UINT8 MdSocket
+ );
+
+/**
+ The Memory Configuration includes DIMM SPD address Map and DIMM Slot
Mechanical present bit map.
+ The data elements should be initialized by a Platform Module.\n
+ Revision 1:
+ - Initial version.
+**/
+struct _MEMORY_DXE_CONFIG {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config
Block Header
+/**
+ Offset 28:
+ Dimm SPD address
+ Only Server support 2 channels * 3 slots per channel
[edk2-devel] [Patch V3 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Fru/TglCpu/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFruLib.h | 18 ++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPcieRegs.h | 24 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs.h | 42 ++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuRegs.h | 31 +++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/VtdRegs.h | 22 ++ 5 files changed, 137 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFruLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFruLib.h new file mode 100644 index 00..a46b29cbbe --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFruLib.h @@ -0,0 +1,18 @@ +/** @file + Vtd Initialization Fru Library header file + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _VTD_INIT_FRU_LIB_H_ +#define _VTD_INIT_FRU_LIB_H_ + +/// +/// TCSS DMA controller RMRR buffer 4MB for each DMA controller +/// +#define RMRR_TCSS_DMA_SIZE 0x40 + +extern UINT16 mDevEnMap[][2]; +extern UINTN mDevEnMapSize; + +#endif // _VTD_INIT_FRU_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPcieRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPcieRegs.h new file mode 100644 index 00..a571381202 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPcieRegs.h @@ -0,0 +1,24 @@ +/** @file + This file contains definitions of PCIe Configuration + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PCIE_REGS_H_ +#define _CPU_PCIE_REGS_H_ + +#define R_PCIE_LCAP 0x4C +#define R_PCIE_LCTL 0x50 +#define R_PCIE_LSTS 0x52 +#define R_PCIE_SLCAP 0x54 +#define R_PCIE_SLSTS 0x5A +#define R_PCIE_LCTL2 0x70 +#define R_PCIE_MPC 0xD8 +#define B_PCIE_MPC_HPME BIT1 +#define R_PCIE_PGTHRES 0x5C0 +#define B_PCIE_PGTHRES_L1PGLTREN BIT0 +#define R_PCIE_LCTL3 0xA34 +#define B_PCIE_LCTL3_PE BIT0 + +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs.h new file mode 100644 index 00..f0b30107f4 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs.h @@ -0,0 +1,42 @@ +/** @file + Register names for IGD block + Conventions: + - Prefixes: +- Definitions beginning with "R_" are registers +- Definitions beginning with "B_" are bits within registers +- Definitions beginning with "V_" are meaningful values of bits within the registers +- Definitions beginning with "S_" are register sizes +- Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted by +"_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" +at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be just named +as "_SA_" without [generation_name] inserted. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _IGD_REGS_H_ +#define _IGD_REGS_H_ + +/// +/// Device 2 Register Equates +/// +// +// The following equates must be reviewed and revised when the specification is ready. +// +#define IGD_BUS_NUM 0x00 +#define IGD_DEV_NUM 0x02 +#define IGD_FUN_NUM 0x00 + +/// +/// GTTMMADR aligned to 16MB (Base address = [38:24]) +/// +#define R_SA_IGD_GTTMMADR 0x10 + +#define R_SA_IGD_SWSCI_OFFSET 0x00E8 +#define R_SA_IGD_ASLS_OFFSET 0x00FC ///< ASL Storage + +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuRegs.h b/Silicon/Intel/TigerlakeSi
[edk2-devel] [Patch V3 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Fru/TglCpu/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruLib.h | 57 + Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBridge.h | 145 + Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h | 12 3 files changed, 214 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruLib.h new file mode 100644 index 00..89cf952717 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruLib.h @@ -0,0 +1,57 @@ +/** @file + Header file for CpuPcieInfoFruLib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_PCIE_INFO_FRU_LIB_H_ +#define _CPU_PCIE_INFO_FRU_LIB_H_ + +#include + +#define CPU_PCIE_MAX_ROOT_PORTS 4 + +#define CPU_PCIE_ULT_ULX_MAX_ROOT_PORT 1 + +#include + +/** + Get CPU Maximum Pcie Root Port Number + + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number +**/ +UINT8 +GetMaxCpuPciePortNum ( + VOID + ); + +/** + Get CPU Pcie Root Port Device and Function Number by Root Port physical Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device number. + @param[out] RpFun Return corresponding root port function number. + + @retval EFI_SUCCESS Root port device and function is retrieved + @retval EFI_INVALID_PARAMETER RpNumber is invalid +**/ +EFI_STATUS +EFIAPI +GetCpuPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ); + +/** + Gets pci segment base address of PCIe root port. + + @param RpIndexRoot Port Index (0 based) + @return PCIe port base address. +**/ +UINT64 +CpuPcieBase ( + IN UINT32 RpIndex + ); + +#endif // _CPU_PCIE_INFO_FRU_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBridge.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBridge.h new file mode 100644 index 00..32e38fa072 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBridge.h @@ -0,0 +1,145 @@ +/** @file + Register names for Host Bridge block + Conventions: + - Prefixes: +- Definitions beginning with "R_" are registers +- Definitions beginning with "B_" are bits within registers +- Definitions beginning with "V_" are meaningful values of bits within the registers +- Definitions beginning with "S_" are register sizes +- Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted by +"_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" +at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be just named +as "_SA_" without [generation_name] inserted. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SA_REGS_HOST_BRIDGE_H_ +#define _SA_REGS_HOST_BRIDGE_H_ + +#define SA_SEG_NUM 0x00 +#define V_SA_DEVICE_ID_INVALID 0x +// +// DEVICE 0 (Memory Controller Hub) +// +#define SA_MC_BUS 0x00 +#define SA_MC_DEV 0x00 +#define SA_MC_FUN 0x00 +#define V_SA_MC_VID0x8086 +#define R_SA_MC_DEVICE_ID 0x02 +#define R_SA_MC_CAPID0_B 0xE8 + +// +// SA DMI configuration +// + +// +// Maximum DMI lanes and bundles supported (x8 and 4 lanes) +// +#define SA_DMI_MAX_LANE 0x08 +#define SA_DMI_MAX_BUNDLE0x04 +#define SA_DMI_MAX_LANE_VER1 0x04 +#define SA_DMI_MAX_BUNDLE_VER1 0x02 + + +// +// TigerLake Mobile SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_MB_ULT_1 0x9A14 ///< TigerLake Ult (TGL-U 4+2) +#define V_SA_DEVICE_ID_MB_ULT_2 0x9A04 ///< TigerLake Ult (TGL-U 2+2) + +#define V_SA_DEVICE_ID_MB_ULX_1 0x9A12 ///< TigerLake Ulx (TGL-Y 4+2) +#define V_SA_DEVICE_ID_MB_ULX_2 0x9A02 ///< TigerLake Ulx (TGL-Y 2+2) + +/** + Description: + - This is the base addres
[edk2-devel] [Patch V3 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivate headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following header files:
* SystemAgent/IncludePrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h
| 42 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
| 30 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h
| 50 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvsAreaDef.h
| 222
++
4 files changed, 344 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h
new file mode 100644
index 00..2e86d497f9
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h
@@ -0,0 +1,42 @@
+/** @file
+ This file defines the SA Iotrap SMI Protocol to provide the
+ I/O address for registered Iotrap SMI.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SA_IOTRAP_SMI_PROTOCOL_H_
+#define _SA_IOTRAP_SMI_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gSaIotrapSmiProtocolGuid;
+
+#define SA_IOTRAP_SMI_PROTOCOL_REVISION_1 1
+
+//
+// SA IO Trap SMI Protocol definition (Private protocol for RC internal use
only)
+//
+typedef struct {
+/*
+ Protocol revision number
+ Any backwards compatible changes to this protocol will result in an update in
the revision number
+ Major changes will require publication of a new protocol
+
+ Revision 1:
+- First version
+*/
+ UINT8 Revision;
+ UINT16 SaIotrapSmiAddress;
+} SA_IOTRAP_SMI_PROTOCOL;
+
+///
+/// Pcie Trap valid types
+///
+typedef enum {
+ CpuPciePmTrap,
+ CpuPcieTrapTypeMaximum
+} CPU_PCIE_TRAP_TYPE;
+
+#endif
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
new file mode 100644
index 00..785a808cf4
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
@@ -0,0 +1,30 @@
+/** @file
+ Definition of the System Agent global NVS area protocol.
+ This protocol publishes the address and format of a global ACPI NVS buffer
+ used as a communications buffer between SMM/DXE/PEI code and ASL code.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SYSTEM_AGENT_NVS_AREA_H_
+#define _SYSTEM_AGENT_NVS_AREA_H_
+
+//
+// SA NVS Area definition
+//
+#include
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gSaNvsAreaProtocolGuid;
+
+///
+/// System Agent Global NVS Area Protocol
+///
+typedef struct {
+ SYSTEM_AGENT_NVS_AREA *Area;///< System Agent Global NVS Area
Structure
+} SYSTEM_AGENT_NVS_AREA_PROTOCOL;
+
+#endif // _SYSTEM_AGENT_NVS_AREA_H_
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h
new file mode 100644
index 00..65622069e6
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h
@@ -0,0 +1,50 @@
+/** @file
+ The GUID definition for SaConfigHob
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SA_CONFIG_HOB_H_
+#define _SA_CONFIG_HOB_H_
+
+#include
+#include
+#include "CpuPcieInfo.h"
+#include
+
+extern EFI_GUID gSaConfigHobGuid;
+#define SA_VTD_ENGINE_NUMBER3
+
+#pragma pack (push,1)
+///
+/// DPR Directory Types
+///
+typedef enum {
+ EnumDprDirectoryTxt = 0,
+} DPR_DIRECTORY_ELEMENT;
+
+#define DPR_DIRECTORY_TYPE_TXT 0x01 ///< DPR directory type - TXT
+#define DPR_DIRECTORY_TYPE_BIOSGUARD0x02 ///< DPR directory type -
BIOS Guard
+#define DPR_DIRECTORY_MAX 1 ///< DPR Maximum Size
+
+///
+/// DPR directory entry definition
+///
+typedef struct {
+ UINT8 Type; ///< DPR Directory Type
+ UINT8 Size; ///< DPR Size in MB
+ UINT32 PhysBase; ///< Must be 4K aligned (bits 11..0 must be clear)
+ UINT16 Reserved; ///< Must be 0
+} DPR_DIRECTORY_ENTRY;
+
+///
+/// System Agent Config Hob
+///
+typedef struct {
+ EFI_HOB_GUID_TYPEEfiHobGuidType;
[edk2-devel] [Patch V3 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register and other include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following header files:
* Include/Pins
* Include/Register
* Include/*.h
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h| 53
+
Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h | 38
++
Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h | 75
+++
Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h | 138
++
Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h| 57
+
Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h | 24
Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h | 155
+++
Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h| 110
++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h | 72
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h | 121
+
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h | 226
++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h | 16
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h| 36
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h | 93
+
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h | 258
++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h | 45
+
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h | 56
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h | 47
+++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h | 51
+++
Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h| 213
+
Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h| 17
+
Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h | 64
22 files changed, 1965 insertions(+)
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 00..ad34e4ea42
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include
+#include
+#include
+#include
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+ EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID
extension HOB header
+ UINT8 Revision; ///< Offset 24Revision
of this config block
+ UINT8 Attributes; ///< Offset 25The main
revision for config block
+ UINT8 Reserved[2]; ///< Offset 26-27 Reserved
for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+
[edk2-devel] [Patch V3 05/40] TigerlakeSiliconPkg/Pch: Add include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Pch/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h | 55 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h | 57 + Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h | 58 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h | 64 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h | 61 + Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h | 38 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h | 72 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h | 258 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h | 590 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h | 552 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h | 70 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h | 67 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h | 55 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h | 56 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h | 21 + Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.h | 184 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h | 134 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h | 144 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h | 166 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h | 40 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h | 132
[edk2-devel] [Patch V3 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds header files common to CPU modules.
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
| 83
+++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
| 148
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfig.h
| 52
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtBasicConfig.h
| 226
++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtCustomConfig.h
| 76
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtPsysConfig.h
| 36
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtTestConfig.h
| 150
++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPreMemConfig.h
| 63 +++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h
| 51 +++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h
| 12
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h
| 21 +
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h
| 23 +++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h
| 18 ++
13 files changed, 959 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
new file mode 100644
index 00..d837500a38
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
@@ -0,0 +1,83 @@
+/** @file
+ CPU Config Block.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_CONFIG_H_
+#define _CPU_CONFIG_H_
+
+#define CPU_CONFIG_REVISION 3
+
+extern EFI_GUID gCpuConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ CPU Configuration Structure.
+
+ Revision 1:
+ - Initial version.
+ Revision 2:
+ - Add SmbiosType4MaxSpeedOverride.
+ Revision 3:
+ - Add AvxDisable & Avx3Disable.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32MicrocodePatchRegionSize;
+ EFI_PHYSICAL_ADDRESS MicrocodePatchAddress;///< Pointer to microcode
patch that is suitable for this processor.
+ /**
+Enable or Disable Advanced Encryption Standard (AES) feature.
+For some countries, this should be disabled for legal reasons.
+-0: Disable
+- 1: Enable
+ **/
+ UINT32 AesEnable : 1;
+ /**
+Enable or Disable Trusted Execution Technology (TXT) feature.
+-0: Disable
+- 1: Enable
+ **/
+ UINT32 TxtEnable : 1;
+ UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon
Initialization will skip MP Initialization (including BSP) if enabled. For
non-FSP, this should always be 0.
+ /**
+Enable or Disable or Auto for PPIN Support to view Protected Processor
Inventory Number.
+- 0: Disable
+-1: Enable
+-2: Auto : Feature is based on End Of Manufacturing (EOM) flag. If EOM
is set, it is disabled.
+ **/
+ UINT32 PpinSupport : 2;
+ /**
+Enable or Disable #AC machine check on split lock.
+- 0: Disable
+-1: Enable
+ **/
+ UINT32 AcSplitLock : 1;
+ /**
+ Enable or Disable Avx.
+ - 1: Disable
+ - 0: Enable
+ **/
+ UINT32 AvxDisable : 1;
+ /**
+ Enable or Disable Avx3.
+ - 1: Disable
+ - 0: Enable
+ **/
+ UINT32 Avx3Disable : 1;
+ UINT32 RsvdBits: 24;///< Reserved for future use
+ /**
+Provide the option for platform to override the MaxSpeed field of Smbios
Type 4.
+Value 4000 means 4000MHz.
+If this value is not zero, it dominates the field.
+If this value is zero, CPU RC will
[edk2-devel] [Patch V2 40/40] Maintainers.txt: Add TigerlakeSiliconPkg maintainers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Maintainers.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 56e16fc48c..34f0b58581 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -242,6 +242,12 @@ F: Silicon/Intel/KabylakeSiliconPkg/ M: Chasel Chiu M: Sai Chaganty +Silicon/Intel/TigerlakeSiliconPkg +F: Silicon/Intel/TigerlakeSiliconPkg/ +M: Sai Chaganty +M: Nate DeSimone +R: Heng Luo + Silicon/Intel/SimicsX58SktPkg F: Silicon/Intel/SimicsX58SktPkg/ M: Agyeman Prince -- 2.24.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#71270): https://edk2.groups.io/g/devel/message/71270 Mute This Topic: https://groups.io/mt/80389531/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [Patch V2 38/40] TigerlakeSiliconPkg/Fru: Add Fru DSC files
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following DSC files: * Fru/TglCpu * Fru/TglPch Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc | 11 +++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc | 9 + Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc| 20 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc | 8 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc| 7 +++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc | 30 ++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Dxe.dsc | 9 + Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/DxeLib.dsc| 13 + Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Pei.dsc | 8 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/PeiLib.dsc| 10 ++ 10 files changed, 125 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc new file mode 100644 index 00..99ee0eccac --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc @@ -0,0 +1,11 @@ +## @file +# Component description file for the TigerLake CPU Common FRU libraries. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +VtdInfoLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoLib/PeiDxeSmmVtdInfoLib.inf +CpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf +CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc new file mode 100644 index 00..874e4cbaad --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc @@ -0,0 +1,9 @@ +## @file +# Component description file for the Tigerlake CPU DXE FRU drivers. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc new file mode 100644 index 00..5c72c2ac61 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc @@ -0,0 +1,20 @@ +## @file +# Component description file for the Tigerlake CPU DXE FRU libraries. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +DxeGraphicsPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf +DxeGraphicsInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeGraphicsInitLib/DxeGraphicsInitLib.inf +DxeIgdOpRegionInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf +DxeVtdInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.inf +DxeVtdPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/LibraryPrivate/DxeVtdPolicyLib/DxeVtdPolicyLib.inf +DxeVtdInitFruLib|$(PLATFORM_SI_PACKAGE)/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.inf + + +# +# CPU PCIe IpBlock +# +DxeCpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc new file mode 100644 index 00..de8288364a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc @@ -0,0 +1,8 @@ +## @file +# Component description file for the Tigerlake CPU PEI FRU drivers. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc new file mode 100644 index 00..5355ecb288 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc @@ -0,0 +1,7 @@ +## @file +# Component description file for the Tigerlake CPU PEI FRU ibraries. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc new file mode 100644 index 00..b7ba1f752c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc @@ -0,0 +1,30 @@ +## @file +# Component description file for the Tigerlake PCH Common FRU libraries. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier
[edk2-devel] [Patch V2 39/40] TigerlakeSiliconPkg: Add package DSC files
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc| 122 ++ Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc | 43 +++ Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc| 47 +++ Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc | 40 Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc| 20 Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc | 20 Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc | 229 + 7 files changed, 521 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc new file mode 100644 index 00..51c40812ea --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc @@ -0,0 +1,122 @@ +## @file +# Silicon build option configuration file. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[BuildOptions] +# Define Build Options both for EDK and EDKII drivers. + + DEFINE PCH_BUILD_OPTIONS = -DPCH_TGL +# +# SA +# +!if gSiPkgTokenSpaceGuid.PcdBdatEnable == TRUE + DEFINE BDAT_BUILD_OPTION = -DBDAT_SUPPORT=1 +!else + DEFINE BDAT_BUILD_OPTION = +!endif + + DEFINE SLE_BUILD_OPTIONS = +!if $(TARGET) == RELEASE +!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE + DEFINE DEBUG_BUILD_OPTIONS = +!else + # MDEPKG_NDEBUG is introduced for the intention + # of size reduction when compiler optimization is disabled. If MDEPKG_NDEBUG is + # defined, then debug and assert related macros wrapped by it are the NULL implementations. + DEFINE DEBUG_BUILD_OPTIONS = -DMDEPKG_NDEBUG +!endif +!else + DEFINE DEBUG_BUILD_OPTIONS = +!endif + +!if ($(TARGET) == RELEASE) AND (gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE) + DEFINE RELEASE_CATALOG_BUILD_OPTIONS = -DRELEASE_CATALOG +!else + DEFINE RELEASE_CATALOG_BUILD_OPTIONS = +!endif + +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE + DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL- +!else + DEFINE OPTIMIZE_DISABLE_OPTIONS = +!endif + + DEFINE HSLE_BUILD_OPTIONS = + + + DEFINE CPU_FLAGS = -DCPU_ICL -DCPU_TGL + + + DEFINE RESTRICTED_OPTION = + +!if gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported == FALSE + *_*_*_MRC_NDEBUG = -DMDEPKG_NDEBUG +!endif + +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS = $(BDAT_BUILD_OPTION) $(DEBUG_BUILD_OPTIONS) +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(PCH_BUILD_OPTIONS) $(CPU_FLAGS) $(HSLE_BUILD_OPTIONS) + +!if gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == TRUE + *_*_X64_GENFW_FLAGS = --keepexceptiontable +!endif + +[BuildOptions.Common.EDKII] + +# +# For IA32 Global Build Flag +# + *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI + *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + +# +# For IA32 Specific Build Flag +# +GCC: *_*_IA32_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_IA32_ASM_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI /w34668 +MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) + +# +# For X64 Global Build Flag +# + *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 + *_*_X64_VFRPP_FLAGS= $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLPP_FLAGS= $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLCC_FLAGS= $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + +# +# For X64 Specific Build Flag +# +GCC: *_*_X64_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) +MSFT
[edk2-devel] [Patch V2 30/40] TigerlakeSiliconPkg/IpBlock: Add Vtd component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/Vtd/IncludePrivate * IpBlock/Vtd/Library * IpBlock/Vtd/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdInitLib.h | 62 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdPolicyLib.h | 67 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/VtdDataHob.h | 32 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoLib/PeiDxeSmmVtdInfoLib.inf | 45 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoLib/VtdInfoLib.c | 86 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c | 684 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.inf | 71 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdPolicyLib/DxeVtdPolicyLib.c | 90 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdPolicyLib/DxeVtdPolicyLib.inf | 35 +++ 9 files changed, 1172 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdInitLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdInitLib.h new file mode 100644 index 00..e439cfbac2 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdInitLib.h @@ -0,0 +1,62 @@ +/** @file + Header file for DXE VTD Init Lib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _DXE_VTD_INIT_LIB_H_ +#define _DXE_VTD_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Locate the VT-d ACPI tables data file and read ACPI SSDT tables. + Publish the appropriate SSDT based on current configuration and capabilities. + + @param[in] SaPolicySA DXE Policy protocol + + @retval EFI_SUCCESS - Vtd initialization complete + @retval Other - No Vtd function initiated +**/ +EFI_STATUS +VtdInit ( + IN SA_POLICY_PROTOCOL*SaPolicy + ); + +/** + EndOfPcieEnum routine for update DMAR +**/ +VOID +UpdateDmarEndOfPcieEnum ( + VOID + ); +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdPolicyLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdPolicyLib.h new file mode 100644 index 00..d55cf6bc34 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdPolicyLib.h @@ -0,0 +1,67 @@ +/** @file + Prototype of the DXE VTD Policy Init library. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _DXE_VTD_POLICY_INIT_LIB_H_ +#define _DXE_VTD_POLICY_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern EFI_GUID gVtdDxeConfigGuid; + +/** + This function Load default Vtd DXE policy. + + @param[in] ConfigBlockPointerThe pointer to add VTD config block +**/ +VOID +VtdLoadDefaultDxe ( + IN VOID*ConfigBlockPointer + ); + +/** + This function prints the DXE phase VTD policy. + + @param[in] SaPolicy - Instance of SA_POLICY_PROTOCOL +**/ +VOID +VtdPrintPolicyDxe ( + IN SA_POLICY_PROTOCOL
[edk2-devel] [Patch V2 37/40] TigerlakeSiliconPkg/SystemAgent: Add SystemAgent modules
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* SystemAgent/SaInit/Dxe
* SystemAgent/SaInit/Smm
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c |
431
+++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c |
120
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h |
58 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c |
181
+
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h |
136
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf |
117
+
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/CpuPcieSmm.c |
454
++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm.c |
112
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm.h |
122
++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm.inf |
72
10 files changed, 1803 insertions(+)
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c
new file mode 100644
index 00..d84a0c1fa4
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c
@@ -0,0 +1,431 @@
+/** @file
+ This is the driver that initializes the Intel System Agent.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "SaInitDxe.h"
+#include "SaInit.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+///
+/// Global Variables
+///
+GLOBAL_REMOVE_IF_UNREFERENCED SYSTEM_AGENT_NVS_AREA_PROTOCOL
mSaNvsAreaProtocol;
+GLOBAL_REMOVE_IF_UNREFERENCED SA_POLICY_PROTOCOL *mSaPolicy;
+extern SA_CONFIG_HOB *mSaConfigHob;
+
+/**
+ A protocol callback which updates 64bits MMIO Base and Length in SA GNVS area
+**/
+VOID
+UpdateSaGnvsForMmioResourceBaseLength (
+ VOID
+ )
+{
+ EFI_PHYSICAL_ADDRESS PciBaseAddress;
+ UINT32Tolud;
+ UINT64Length;
+ UINT64McD0BaseAddress;
+ UINTN ResMemLimit1;
+ UINT8 EnableAbove4GBMmioBiosAssignemnt;
+ HOST_BRIDGE_DATA_HOB *HostBridgeDataHob;
+
+ PciBaseAddress = 0;
+ Tolud = 0;
+ Length = 0;
+ ResMemLimit1 = 0;
+ EnableAbove4GBMmioBiosAssignemnt = 0;
+ HostBridgeDataHob = NULL;
+ //
+ // Read memory map registers
+ //
+ McD0BaseAddress= PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0,
0, 0);
+ Tolud = PciSegmentRead32 (McD0BaseAddress + R_SA_TOLUD) &
B_SA_TOLUD_TOLUD_MASK;
+ PciBaseAddress = Tolud;
+
+ ResMemLimit1 = (UINTN) PcdGet64 (PcdSiPciExpressBaseAddress);
+
+ Length = ResMemLimit1 - PciBaseAddress;
+
+ //
+ // Get HostBridgeData HOB and see if above 4GB MMIO BIOS assignment enabled
+ //
+ HostBridgeDataHob = (HOST_BRIDGE_DATA_HOB *) GetFirstGuidHob
();
+
[edk2-devel] [Patch V2 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and Vtd library instances
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib
* Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
| 81
+
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
| 36
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c
| 18 ++
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.inf
| 39 +++
4 files changed, 174 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
new file mode 100644
index 00..6a9bc89ecf
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
@@ -0,0 +1,81 @@
+/** @file
+ CPU PCIe information library.
+
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Get Maximum CPU Pcie Root Port Number
+
+ @retval Maximum CPU Pcie Root Port Number
+**/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ )
+{
+ return CPU_PCIE_ULT_ULX_MAX_ROOT_PORT;
+}
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port physical
Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device
number.
+ @param[out] RpFun Return corresponding root port function
number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ )
+{
+ if (RpNumber > GetMaxCpuPciePortNum ()) {
+DEBUG ((DEBUG_ERROR, "GetCpuPcieRpDevFun invalid RpNumber %x", RpNumber));
+ASSERT (FALSE);
+return EFI_INVALID_PARAMETER;
+ }
+ //
+ // For TGL - U/Y only one CPU PCIE Root port is present
+ //
+ *RpDev = 6;
+ *RpFun = 0;
+ return EFI_SUCCESS;
+}
+/**
+
+ Gets pci segment base address of PCIe root port.
+
+ @param RpIndexRoot Port Index (0 based)
+
+ @return PCIe port base address.
+**/
+UINT64
+CpuPcieBase (
+ IN UINT32 RpIndex
+ )
+{
+ UINTN RpDevice;
+ UINTN RpFunction;
+ GetCpuPcieRpDevFun (RpIndex, , );
+ return PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, (UINT32) RpDevice,
(UINT32) RpFunction, 0);
+}
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
new file mode 100644
index 00..b6a40b2f7c
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
@@ -0,0 +1,36 @@
+## @file
+# CPU PCIe information library for TigerLake PCH.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmCpuPcieInfoFruLib
+FILE_GUID = 59CA5352-ED46-4449-BF1C-0D0074C4D5B1
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuPcieInfoFruLib
+
+
+[LibraryClasses]
+IoLib
+BaseLib
+DebugLib
+PrintLib
+PcdLib
+ConfigBlockLib
+CpuPcieInitCommonLib
+
+[Packages]
+MdePkg/MdePkg.dec
+TigerlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+CpuPcieInfoFruLib.c
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c
new file mode 100644
index 00..d6e8096da6
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c
@@ -0,0 +1,18 @@
+/** @file
+ DXE FRU Library to initialize Vtd
+
+ Copyright (c) 2021, Inte
[edk2-devel] [Patch V2 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and library instances
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * SystemAgent/AcpiTables * SystemAgent/Library/DxeSaPolicyLib * SystemAgent/Library/PeiDxeSmmSaPlatformLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRp.asl | 252 +++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRpCommon.asl | 289 +++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegCommon.asl | 1344 +++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegRtd3.asl | 124 ++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.asl | 26 ++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl | 20 ++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf | 22 +++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c | 254 Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf | 48 Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h | 33 ++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf | 32 ++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.c | 68 + Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.h | 21 ++ 13 files changed, 2533 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRp.asl b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRp.asl new file mode 100644 index 00..0babf047ed --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRp.asl @@ -0,0 +1,252 @@ +/** @file + This file contains the CPU PCIe Root Port configuration + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +External(LTRX) // CPU PCIe Root Port 0 Latency Tolerance Reporting Enable +External(LTRY) // CPU PCIe Root Port 1 Latency Tolerance Reporting Enable +External(LTRZ) // CPU PCIe Root Port 2 Latency Tolerance Reporting Enable +External(LTRW) // CPU PCIe Root Port 3 Latency Tolerance Reporting Enable +External(SMSL) // CPU PCIe Root Port Latency Tolerance Reporting Max Snoop Latency +External(SNSL) // CPU PCIe Root Port Latency Tolerance Reporting Max No Snoop Latency +External(PG0E) // CpuPcieRp0Enable 0: Disable; 1: Enable +External(PG1E) // CpuPcieRp1Enable 0: Disable; 1: Enable +External(PG2E) // CpuPcieRp2Enable 0: Disable; 1: Enable +External(PG3E) // CpuPcieRp3Enable 0: Disable; 1: Enable +External(\_SB.PC00.PEG0, DeviceObj) +External(\_SB.PC00.PEG1, DeviceObj) +External(\_SB.PC00.PEG2, DeviceObj) +External(\_SB.PC00.PEG3, DeviceObj) +External(\_SB.PC00.PEG0.PEGP, DeviceObj) +External(\_SB.PC00.PEG1.PEGP, DeviceObj) +External(\_SB.PC00.PEG2.PEGP, DeviceObj) +External
[edk2-devel] [Patch V2 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/Gbe/IncludePrivate * IpBlock/Gbe/Library * IpBlock/Gbe/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h | 324 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Register/GbeRegs.h | 68 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/GbeLib.c | 121 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/PeiDxeSmmGbeLib.inf | 43 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGbeMdiLib/GbeMdiLib.c | 388 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGbeMdiLib/PeiDxeSmmGbeMdiLib.inf | 34 ++ 6 files changed, 978 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h new file mode 100644 index 00..b8274ed3dc --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h @@ -0,0 +1,324 @@ +/** @file + Header file for GbeMdiLib. + + Conventions: + + - Prefixes: +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values within the bits +Definitions beginning with "S_" are register sizes +Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by +"_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. +Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. +e.g., "_PCH_LP_" +Registers / bits names without or _LP_ apply for LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" +at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named +as "_PCH_" without [generation_name] inserted. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GBE_MDI_LIB_H_ +#define _GBE_MDI_LIB_H_ + +// +// Maximum loop time for GbE status check +// 4000 * 50 = 200 mSec in total +// +#define GBE_MAX_LOOP_TIME 4000 +#define GBE_ACQUIRE_MDIO_DELAY 50 +#define GBE_MDI_SET_PAGE_DELAY 4000 // 4 mSec delay after setting page + +// +// LAN PHY MDI settings +// +// MDI Control Register Bits +// 31:30 Reserved +// This field is reserved and returns 0. +// 29Interrupt Enable. +// When this bit is set to 1 by software, it causes the device to assert +// an interrupt indicating the end of an MDI cycle. +// 28Ready. +// Set to 1 by the device at the end of MDI transaction (i.e., indicates a Read or +// Write has been completed. It should be reset to 0 by software at the same time the +// command is written. +// 27:26 Opcode +// For an MDI write, the opcode equals 01b, and for MDI read, 10b. 00b and +// 11b are reserved and should not be used. +// 25:21 PHYAdd +// PHY Address +// 20:16 RegAdd +// PHY Register Address +// 15:0 Data + +#define B_PHY_MDI_READYBIT28 +#define B_PHY_MDI_READ BIT27 +#define B_PHY_MDI_WRITEBIT26 +// +// PHY SPECIFIC registers +// +#define B_PHY_MDI_PHY_ADDRESS_02 BIT22 +// +// PHY GENERAL registers +// Regi
[edk2-devel] [Patch V2 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/CpuPcieRp/Include * IpBlock/CpuPcieRp/IncludePrivate * IpBlock/CpuPcieRp/Library * IpBlock/CpuPcieRp/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h | 31 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h | 353 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieRpLib.h | 47 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Library/DxeCpuPcieRpLib.h | 18 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/CpuPcieInitCommon.c | 445 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf | 33 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/CpuPcieRpLib.c | 48 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf | 32 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.c | 62 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf | 40 10 files changed, 1109 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h new file mode 100644 index 00..15eeab0ecf --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h @@ -0,0 +1,31 @@ +/** @file + This file contains definitions of PCIe controller information + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_PCIE_INFO_H_ +#define _CPU_PCIE_INFO_H_ + +#define PCIE_HWEQ_COEFFS_MAX5 + +// +// Device 1 Memory Mapped IO Register Offset Equates +// +#define SA_PEG_DEV_NUM 0x01 +#define SA_PEG0_DEV_NUMSA_PEG_DEV_NUM +#define SA_PEG3_DEV_NUM0x06 + +// +// SA PCI Express* Port configuration +// + +#define CPU_PCIE_MAX_ROOT_PORTS4 + +#define SA_PEG_MAX_FUN 0x04 +#define SA_PEG_MAX_LANE 0x14 +#define SA_PEG_MAX_FUN_GEN3 0x03 +#define SA_PEG_MAX_LANE_GEN3 0x10 +#define SA_PEG_MAX_BUNDLE_GEN3 0x08 + +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h new file mode 100644 index 00..79b255c273 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h @@ -0,0 +1,353 @@ +/** @file +Header file for CpuPcieInitCommonLib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_PCIE_INIT_COMMON_H_ +#define _CPU_PCIE_INIT_COMMON_H_ + +#include + +/** + Print registers value + + @param[in] PrintMmioBase Mmio base address + @param[in] PrintSize Number of registers + @param[in] OffsetFromBase Offset from mmio base address + + @retval None +**/ +VOID +SaPrintRegisters ( + IN UINTNPrintMmioBase, + IN UINT32 PrintSize, + IN UINT32 OffsetFromBase + ); + +/** + Print registers value + + @param[in] PrintPciSegmentBase Pci segment base address + @param[in] PrintSize Number of registers
[edk2-devel] [Patch V2 15/40] TigerlakeSiliconPkg/IpBlock: Add Espi component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Espi/Library
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
| 469
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
| 38 ++
2 files changed, 507 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
new file mode 100644
index 00..2d1928ce18
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
@@ -0,0 +1,469 @@
+/** @file
+ This file contains routines for eSPI
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CHANNEL_RESET_TIMEOUT 100 ///< Channel reset timeout in us after
which to report error
+#define SLAVE_CHANNELS_MAX7 ///< Max number of channels
+
+//
+// eSPI Slave registers
+//
+#define R_ESPI_SLAVE_GENCAP 0x08 ///< General Capabilities
and Configurations
+#define B_ESPI_SLAVE_GENCAP_SUPPCHAN 0xFF ///< Channels supported
bit mask
+#define R_ESPI_SLAVE_CHACAP_BASE 0x10 ///< Base address from
which channel Cap and Conf registers start on slave
+#define S_ESPI_SLAVE_CHACAP_OFFSET0x10 ///< Offset for each
channel from base
+#define B_ESPI_SLAVE_CHACAP_CHEN BIT0 ///< Slave Channel enable
bit
+#define B_ESPI_SLAVE_CHACAP_CHRDY BIT1 ///< Slave Channel ready
bit
+
+/**
+ Checks if second slave capability is enabled
+
+ @retval TRUE There's second slave
+ @retval FALSE There's no second slave
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+/**
+ Checks in slave General Capabilities register if it supports channel with
requested number
+
+ @param[in] SlaveId Id of slave to check
+ @param[in] ChannelNumber Number of channel of which to check
+
+ @retval TRUE Channel with requested number is supported by slave device
+ @retval FALSE Channel with requested number is not supported by slave
device
+**/
+BOOLEAN
+IsEspiSlaveChannelSupported (
+ UINT8 SlaveId,
+ UINT8 ChannelNumber
+ )
+{
+ UINT32 Data32;
+ UINT8 SupportedChannels;
+
+ PchEspiSlaveGetConfig (SlaveId, R_ESPI_SLAVE_GENCAP, );
+ SupportedChannels = (UINT8) (Data32 & B_ESPI_SLAVE_GENCAP_SUPPCHAN);
+
+ DEBUG ((DEBUG_INFO, "Slave %d supported channels 0x%4X\n", SlaveId,
SupportedChannels));
+
+ if (ChannelNumber > SLAVE_CHANNELS_MAX || !(SupportedChannels & (BIT0 <<
ChannelNumber))) {
+// Incorrect channel number was specified. Either exceeded max or Slave
doesn't support that channel.
+return FALSE;
+ }
+
+ return TRUE;
+}
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ )
+{
+ return (PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_CFG_VAL) &
B_ESPI_PCR_CFG_VAL_ESPI_EN) != 0;
+}
+
+/**
+ eSPI helper function to clear slave configuration register status
+
+ @retval EFI_SUCCESS Write to private config space succeed
+ @retval others Read / Write failed
+**/
+STATIC
+VOID
+EspiClearScrs (
+ VOID
+ )
+{
+ PchPcrAndThenOr32 (
+PID_ESPISPI,
+R_ESPI_PCR_SLV_CFG_REG_CTL,
+(UINT32) ~0,
+ B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS
+ );
+}
+
+/**
+ eSPI helper function to poll slave configuration register enable for 0
+ and to check for slave configuration register status
+
+ @retval EFI_SUCCESS Enable bit is zero and no error in status bits
+ @retval EFI_DEVICE_ERROR Error in SCRS
+ @retval othersRead / Write to private config space failed
+**/
+STATIC
+EFI_STATUS
+EspiPollScreAndCheckScrs (
+ VOID
+ )
+{
+ UINT32 ScrStat;
+
+ do {
+ScrStat = PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_SLV_CFG_REG_CTL);
+ } while ((ScrStat & B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE) != 0);
+
+ ScrStat = (ScrStat & B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS) >>
N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS;
[edk2-devel] [Patch V2 29/40] TigerlakeSiliconPkg/IpBlock: Add Spi component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/Spi/IncludePrivate * IpBlock/Spi/Library * IpBlock/Spi/LibraryPrivate * IpBlock/Spi/Smm Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiAccessPrivateLib.h | 40 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h | 364 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h | 136 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/Library/PeiDxeSmmSpiAccessLib/PeiDxeSmmSpiAccessLib.inf | 33 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/Library/PeiDxeSmmSpiAccessLib/SpiAccessLib.c | 477 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf | 31 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c | 1115 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/PeiDxeSmmSpiAccessPrivateLib/PeiDxeSmmSpiAccessPrivateLib.inf | 40 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/PeiDxeSmmSpiAccessPrivateLib/SpiAccessPrivateLib.c | 133 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c | 296 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf | 47 + 11 files changed, 2712 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiAccessPrivateLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiAccessPrivateLib.h new file mode 100644 index 00..6da88a9047 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiAccessPrivateLib.h @@ -0,0 +1,40 @@ +/** @file + SPI library header for abstraction of SPI HW registers accesses + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SPI_ACCESS_PRIVATE_LIB_H_ +#define _SPI_ACCESS_PRIVATE_LIB_H_ + +/** + Disable EISS (Enable InSMM.STS) +**/ +VOID +SpiDisableEiss ( + VOID + ); + +/** + Configure BiosLockEnable bit and BiosInterfaceLock bit according to policy setting. + + @param[in] BiosLockEnable Policy for BiosLockEnable bit programming + @param[in] BiosInterfaceLock Policy for BiosInterfaceLock bit programming + +**/ +VOID +SpiBiosLockEnableAndBiosInterfaceLockWithS3BootScript ( + IN BOOLEAN BiosLockEnable, + IN BOOLEAN
[edk2-devel] [Patch V2 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/SerialIo/IncludePrivate
* IpBlock/SerialIo/Library
* IpBlock/SerialIo/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h
| 377
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Register/SerialIoRegsVer2.h
| 108
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSerialIoAccessLib/PeiDxeSmmSerialIoAccessLib.inf
| 35 +++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSerialIoAccessLib/SerialIoAccessLib.c
| 266
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf
| 34 ++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLib.c
| 156
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibI2c.c
| 122
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibI2cVer2.c
| 70
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibInternal.h
| 20
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibSpi.c
| 122
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibSpiVer2.c
| 82
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibUart.c
| 136
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibUartVer2.c
| 82
++
13 files changed, 1610 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h
new file mode 100644
index 00..47057cd2ef
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h
@@ -0,0 +1,377 @@
+/** @file
+ Header file for Serial IO Private Lib implementation.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_PRIVATE_LIB_H_
+#define _SERIAL_IO_PRIVATE_LIB_H_
+
+#include
+#include
+
+/**
+ Serial Io Pci Device State structure.
+ Used to preserve current information about the device when it is configured
in Pci mode prior to Pch Initialization.
+**/
+typedef struct {
+ UINT64 PciCfgBar0; ///< Pci Config Space Base Address Register
+ UINT8 PciCfgCommand;///< Pci Config Space Command Register
+ UINT8 PciCfgPmeCtrlSts; ///< Pci Config Space Pme Control Status
+ UINT8 PprReset; ///< MMIO Proprietary Reset Register
+} SERIAL_IO_PCI_DEVICE_STATE;
+
+/**
+ Checks if higher functions are enabled.
+ Used for Function 0 Seri
[edk2-devel] [Patch V2 32/40] TigerlakeSiliconPkg/Pch: Add Pch common library instances
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * Pch/Library/BasePchPciBdfLib * Pch/Library/BaseResetSystemLib * Pch/Library/DxePchPolicyLib * Pch/Library/PeiDxeSmmPchCycleDecodingLib * Pch/Library/PeiDxeSmmPchInfoLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf | 33 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLib.c | 1092 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c | 158 Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf | 38 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.c | 198 Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.inf | 43 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c | 587 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf | 42 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLib.c | 127 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h | 58 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibTgl.c | 715 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibTgl.inf | 43 +++ 12 files changed, 3134 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf new file mode 100644 index 00..4f4096a409 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf @@ -0,0 +1,33 @@ +## @file +# PCH PCIe Bus Device Function Library. +# +# All functions from this library are available in PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent
[edk2-devel] [Patch V2 13/40] TigerlakeSiliconPkg/IpBlock: Add Cnvi component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Cnvi/IncludePrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Cnvi/IncludePrivate/CnviConfigHob.h
| 27 +++
1 file changed, 27 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Cnvi/IncludePrivate/CnviConfigHob.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Cnvi/IncludePrivate/CnviConfigHob.h
new file mode 100644
index 00..e881e49d62
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Cnvi/IncludePrivate/CnviConfigHob.h
@@ -0,0 +1,27 @@
+/** @file
+ This file defines the CNVi CONFIG HOB
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CNVI_CONFIG_HOB_H_
+#define _CNVI_CONFIG_HOB_H_
+
+#include
+
+extern EFI_GUID gCnviConfigHobGuid;
+#pragma pack (push,1)
+
+/**
+ This HOB is used to pass CNVi related private information to DXE phase
+**/
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID HOB type structure for
gCnviConfigHobGuid
+ UINT32 Mode : 1; ///< 0: Disabled, 1: Auto
+ UINT32 BtCore : 1; ///< 0: Disabled, 1: Enabled
+ UINT32 BtAudioOffload : 1; ///< 0: Disabled, 1: Enabled
+ UINT32 RsvdBits0 : 29; ///< Reserved bits
+} CNVI_CONFIG_HOB;
+#pragma pack (pop)
+
+#endif // _CNVI_CONFIG_HOB_H_
--
2.24.0.windows.2
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[edk2-devel] [Patch V2 33/40] TigerlakeSiliconPkg/Pch: Add Pch private library instances
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* Pch/LibraryPrivate/BaseSiScheduleResetLib
* Pch/LibraryPrivate/SmmPchPrivateLib
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetLib/BaseSiScheduleResetLib.c
| 171
+++
Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetLib/BaseSiScheduleResetLib.inf
| 37 +
Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/SmmPchPrivateLib.c
| 57 +
Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/SmmPchPrivateLib.inf
| 31 +++
4 files changed, 296 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetLib/BaseSiScheduleResetLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetLib/BaseSiScheduleResetLib.c
new file mode 100644
index 00..1880244a01
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetLib/BaseSiScheduleResetLib.c
@@ -0,0 +1,171 @@
+/** @file
+ Reset scheduling library services
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ This function returns SiScheduleResetHob for library use
+**/
+STATIC
+SI_SCHEDULE_RESET_HOB *
+SiScheduleGetResetData (
+ VOID
+ )
+{
+ STATIC SI_SCHEDULE_RESET_HOB *SiScheduleResetHob = NULL;
+ SI_SCHEDULE_RESET_HOB*SiScheduleResetHobTemp;
+ VOID *HobPtr;
+
+ if (SiScheduleResetHob != NULL) {
+return SiScheduleResetHob;
+ }
+
+ HobPtr = GetFirstGuidHob ();
+ if (HobPtr == NULL) {
+SiScheduleResetHobTemp = BuildGuidHob (, sizeof
(SI_SCHEDULE_RESET_HOB));
+if (SiScheduleResetHobTemp == NULL) {
+ ASSERT (FALSE);
+ return SiScheduleResetHobTemp;
+}
+SiScheduleResetHobTemp->ResetType = 0xFF;
+DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : Init SiScheduleResetHob\n"));
+ } else {
+SiScheduleResetHobTemp = (SI_SCHEDULE_RESET_HOB*) GET_GUID_HOB_DATA
(HobPtr);
+ }
+ SiScheduleResetHob = SiScheduleResetHobTemp;
+ return SiScheduleResetHobTemp;
+}
+
+/**
+ This function updates the reset information in SiScheduleResetHob
+ @param[in] ResetTypeUEFI defined reset type.
+ @param[in] ResetDataOptional element used to introduce a platform
specific reset.
+ The exact type of the reset is defined by the
EFI_GUID that follows
+ the Null-terminated Unicode string.
+**/
+VOID
+SiScheduleResetSetType (
+ IN EFI_RESET_TYPE ResetType,
+ IN PCH_RESET_DATA *ResetData OPTIONAL
+ )
+{
+ SI_SCHEDULE_RESET_HOB *SiScheduleResetHob;
+ if (ResetType > EfiResetPlatformSpecific) {
+DEBUG ((DEBUG_INFO, "Unsupported Reset Type Requested\n"));
+return;
+ }
+ SiScheduleResetHob = SiScheduleGetResetData ();
+ if (SiScheduleResetHob == NULL) {
+return;
+ }
+ DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : Current Reset Type = 0x%x\n",
SiScheduleResetHob->ResetType));
+ if (SiScheduleResetHob->ResetType == ResetType) {
+DEBUG ((DEBUG_INFO, "Current Reset Type is same as requested Reset
Type\n"));
+return;
+ }
+ if (SiScheduleResetHob->ResetType == 0xFF) {
+// Init Reset Type to lowest ResetType
+SiScheduleResetHob->ResetType = EfiResetWarm;
+ }
+ //
+ // ResetType Priority set as : ResetPlatformSpecific(3) > ResetShutdown(2) >
ResetCold(0) > ResetWarm(1)
+ //
+ switch (ResetType) {
+case EfiResetWarm:
+ break;
+
+case EfiResetCold:
+ if (SiScheduleResetHob->ResetType == EfiResetWarm) {
+SiScheduleResetHob->ResetType = ResetType;
+ }
+ break;
+
+case EfiResetShutdown:
+ if (SiScheduleResetHob->ResetType < ResetType)
+ SiScheduleResetHob->ResetType = ResetType;
+ break;
+
+case EfiResetPlatformSpecific:
+ SiScheduleResetHob->ResetType = ResetType;
+ SiScheduleResetHob->ResetData = *ResetData;
+ break;
+ }
+ DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : New Reset Type = 0x%x\n",
SiScheduleResetHob->ResetType));
+}
+
+/**
+ This function returns TRUE or FALSE depending on whether a reset is required
based on SiScheduleResetHob
+
+ @retval BOOLEAN The function returns FALSE if no reset is required
+**/
+BOOLEAN
+SiScheduleResetIsRequired (
+ VOID
+ )
+{
+ VOI
[edk2-devel] [Patch V2 31/40] TigerlakeSiliconPkg/Library: Add package common library instances
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * Library/BasePciSegmentMultiSegLibPci * Library/BaseSiConfigBlockLib * Library/PeiDxeSmmMmPciLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf | 38 +++ Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni | 14 ++ Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/PciSegmentLib.c | 1280 +++ Silicon/Intel/TigerlakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.c | 86 Silicon/Intel/TigerlakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf | 33 +++ Silicon/Intel/TigerlakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c | 35 + Silicon/Intel/TigerlakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf | 43 ++ 7 files changed, 1529 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf new file mode 100644 index 00..b04bce9cf0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf @@ -0,0 +1,38 @@ +## @file +# Instance of PCI Segment Library based on PCI Library. +# +# PCI Segment Library that layers on top of the PCI Library which only +# supports segment 0 and segment 1 PCI configuration access. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION= 0x00010005 + BASE_NAME = BasePciSegmentMultiSegLibPci + MODULE_UNI_FILE= BasePciSegmentMultiSegLibPci.uni + FILE_GUID = AC65B409-DF03-466e-8D2B-6FCE1079F0B2 + MODULE_TYPE= BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciSegmentLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources] + PciSegmentLib.c + +[Packages] + MdePkg/MdePkg.dec + TigerlakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + BaseLib + PciLib + DebugLib + PcdLib diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni new file mode 100644 index 00..09bd0f5cfc --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni @@ -0,0 +1,14 @@ +/** @file + Instance of PCI Segment Library based on PCI Library. + + PCI Segment Library that layers on top of the PCI Library which only + supports segment 0 and segment 1 PCI configuration access. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +#string STR_MODULE_ABSTRACT #language en-US "Instance of PCI Segment Library based on PCI Library." + +#string STR_MODULE_DESCRIPTION #language en-US "PCI Segment Library that layers on top of the PCI Library which only supports segment 0 and segment 1 PCI configuration access." diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/PciSegmentLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/PciSegmentLib.c new file mode 100644 index 00..0d0c64be3f --- /dev/null +++ b/Silicon/Intel/Tigerla
[edk2-devel] [Patch V2 28/40] TigerlakeSiliconPkg/IpBlock: Add Smbus component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/Smbus/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Smbus/IncludePrivate/Register/SmbusRegs.h | 50 ++ 1 file changed, 50 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Smbus/IncludePrivate/Register/SmbusRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Smbus/IncludePrivate/Register/SmbusRegs.h new file mode 100644 index 00..c863615583 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Smbus/IncludePrivate/Register/SmbusRegs.h @@ -0,0 +1,50 @@ +/** @file + Register names for PCH Smbus Device. + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName + - Prefix: +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values within the bits +Definitions beginning with "S_" are register size +Definitions beginning with "N_" are the bit position + - [GenerationName]: +Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). +Register name without GenerationName applies to all generations. + - [ComponentName]: +This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) +Register name without ComponentName applies to all components. +Register that is specific to -LP denoted by "_PCH_LP_" in component name. + - SubsystemName: +This field indicates the subsystem name of the component that the register belongs to +(e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: +MEM - MMIO space register of subsystem. +IO - IO space register of subsystem. +PCR - Private configuration register of subsystem. +CFG - PCI configuration space register of subsystem. + - RegisterName: +Full register name. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_REGS_SMBUS_H_ +#define _PCH_REGS_SMBUS_H_ + +// +// SMBus Controller Registers +// +#define R_SMBUS_CFG_BASE 0x20 +#define B_SMBUS_CFG_BASE_BAR 0xFFE0 + +// +// SMBus I/O Registers +// +#define R_SMBUS_IO_HSTS 0x00 ///< Host Status Register R/W +#define B_SMBUS_IO_SMBALERT_STS 0x20 + +#endif -- 2.24.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#71212): https://edk2.groups.io/g/devel/message/71212 Mute This Topic: https://groups.io/mt/80375670/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [Patch V2 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Sata/Library
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
| 32
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
| 138
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLibVer2.c
| 83
+++
3 files changed, 253 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
new file mode 100644
index 00..1c304fed59
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
@@ -0,0 +1,32 @@
+## @file
+# PEI/DXE/SMM PCH SATA library Ver2
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchSataLibVer2
+FILE_GUID = 2519ADE8-D971-4551-8A8E-2EB55DFC555B
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SataLib
+
+[LibraryClasses]
+BaseLib
+PciSegmentLib
+PchInfoLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+TigerlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+SataLib.c
+SataLibVer2.c
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
new file mode 100644
index 00..49cba49910
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
@@ -0,0 +1,138 @@
+/** @file
+ Pch SATA library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Get SATA controller address that can be passed to the PCI Segment Library
functions.
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller address in PCI Segment Library representation
+**/
+UINT64
+SataRegBase (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+
+ return SataPciCfgBase (SataCtrlIndex);
+}
+
+/**
+ Get SATA controller's Port Present Status
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval Port Present Status
+**/
+UINT8
+GetSataPortPresentStatus (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+
+ return PciSegmentRead8 (SataPciCfgBase (SataCtrlIndex) + R_SATA_CFG_PCS + 2);
+}
+
+/**
+ Get SATA controller Function Disable Status
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval 0 SATA Controller is not Function Disabled
+ @retval 1 SATA Controller is Function Disabled
+**/
+BOOLEAN
+SataControllerFunctionDisableStatus (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ UINT32 SataGc;
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+ SataGc = PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) +
R_SATA_CFG_SATAGC);
+ return !!(SataGc & BIT10);
+}
+
+/**
+ Get SATA controller ABAR size
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller ABAR size
+**/
+UINT32
+GetSataAbarSize (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ UINT32 SataGc;
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+ SataGc = PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) +
R_SATA_CFG_SATAGC);
+
+ switch (SataGc & B_SATA_CFG_SATAGC_ASSEL) {
+case V_SATA_CFG_SATAGC_ASSEL_2K:
+ return SIZE_2KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_16K:
+ return SIZE_16KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_32K:
+ return SIZE_32KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_64K:
+ return SIZE_64KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_128K:
+ return SIZE_128KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_512K:
+ return SIZE_256KB;
+ break;
+
+default:
+ return SIZE_2KB;
+ break;
+ }
+}
+
+/**
+ Get SATA controller AHCI base address
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller AHCI base address
+**/
+UIN
[edk2-devel] [Patch V2 19/40] TigerlakeSiliconPkg/IpBlock: Add Hda component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/Hda/IncludePrivate * IpBlock/Hda/Library * IpBlock/Hda/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Library/DxeHdaPolicyLib.h | 55 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Register/HdaRegs.h | 46 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/Library/DxeHdaNhltLib/DxeHdaNhltLib.c | 383 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/Library/DxeHdaNhltLib/DxeHdaNhltLib.inf | 31 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/LibraryPrivate/DxeHdaPolicyLib/DxeHdaPolicyLib.c | 92 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/LibraryPrivate/DxeHdaPolicyLib/DxeHdaPolicyLib.inf | 31 +++ 6 files changed, 638 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Library/DxeHdaPolicyLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Library/DxeHdaPolicyLib.h new file mode 100644 index 00..9c42bf5611 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Library/DxeHdaPolicyLib.h @@ -0,0 +1,55 @@ +/** @file + DXE Hda policy library. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _DXE_HDA_POLICY_LIB_H_ +#define _DXE_HDA_POLICY_LIB_H_ + +#include + +/** + Print HDAUDIO_DXE_CONFIG and serial out. + + @param[in] PchPolicyPointer to a PCH_POLICY_PROTOCOL +**/ +VOID +HdaDxePrintConfig ( + IN PCH_POLICY_PROTOCOL*PchPolicy + ); + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +HdaDxeLoadConfigDefault ( + IN VOID *ConfigBlockPointer + ); + +/** + Get Hda config block table size. + + @retval Size of config block +**/ +UINT16 +HdaDxeGetConfigBlockTotalSize ( + VOID + ); + +/** + Add Hda ConfigBlock. + + @param[in] ConfigBlockTableAddressThe pointer to config block table + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +HdaDxeAddConfigBlock ( + IN VOID *ConfigBlockTableAddress + ); + +#endif // _DXE_HDA_POLICY_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Register/HdaRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Register/HdaRegs.h new file mode 100644 index 00..b165e7bb22 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Register/HdaRegs.h @@ -0,0 +1,46 @@ +/** @file + Register names for High Definition Audio device. + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName + - Prefix: +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values within the bits +Definitions beginning with "S_" are register size +Definitions beginning with "N_" are the bit position + - [GenerationName]: +Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). +Register name without GenerationName applies to all generations. + - [ComponentName]: +This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) +Register name without ComponentName applies to all components. +Register that is specific to -LP denoted by "_PCH_LP_" in component name. + - SubsystemName: +This field indicates the subsystem name of the component that the register belongs to +(e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: +MEM - MMIO space register of subsystem. +IO - IO space register of subsystem. +PCR - Private configuration register of subsystem. +CFG - PCI configuration space register of subsystem. + - RegisterName: +Full register name. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _HDA_REGS_
[edk2-devel] [Patch V2 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Psf/IncludePrivate
* IpBlock/Psf/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h
| 520
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PeiDxeSmmPsfLibVer2.inf
| 40
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLib.c
| 203
+++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibInternal.h
| 470
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibVer2.c
| 115
+++
5 files changed, 1348 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h
new file mode 100644
index 00..f333be48d2
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h
@@ -0,0 +1,520 @@
+/** @file
+ Header file for PchPsfPrivateLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PSF_PRIVATE_LIB_H_
+#define _PCH_PSF_PRIVATE_LIB_H_
+
+#include
+#include
+
+typedef struct {
+ UINT32 Id;
+ PCH_SBI_PID SbPid;
+} PSF_SEGMENT;
+
+/**
+ Get list of supported PSF segments.
+
+ @param[out] PsfTableArray of supported PSF segments
+ @param[out] PsfTableLength Length of PsfTable
+**/
+VOID
+PsfSegments (
+ OUT PSF_SEGMENT **PsfTable,
+ OUT UINT32 *PsfTableLength
+ );
+
+//
+// Structure for storing data on both PSF SideBand Port ID and
+// PSF port register offset for specific device
+//
+typedef struct {
+ PCH_SBI_PID PsfPid;
+ UINT16 RegBase;
+} PSF_PORT;
+
+/**
+ Disable device at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+**/
+VOID
+PsfDisableDevice (
+ IN PSF_PORT PsfPort
+ );
+
+/**
+ Enable device at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+**/
+VOID
+PsfEnableDevice (
+ IN PSF_PORT PsfPort
+ );
+
+/**
+ Hide PciCfgSpace of device at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+**/
+VOID
+PsfHideDevice (
+ IN PSF_PORT PsfPort
+ );
+
+/**
+ Unhide PciCfgSpace of device at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+**/
+VOID
+PsfUnhideDevice (
+ IN PSF_PORT PsfPort
+ );
+
+/**
+ Disable device BARs at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+ @param[in] BarDisMask BIT0-BAR0, BIT1-BAR1,...
+ Mask corresponds to 32bit wide BARs
+**/
+VOID
+PsfDisableDeviceBar (
+ IN PSF_PORT PsfPort,
+ IN UINT32BarDisMask
+ );
+
+/**
+ Enable device BARs at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+ @param[in] BarEnMask BIT0-BAR0, BIT1-BAR1,...
+ Mask corresponds to 32bit wide BARs
+**/
+VOID
+PsfEnableDeviceBar (
+ IN PSF_PORT PsfPort,
+ IN UINT32BarEnMask
+ );
+
+/**
+ Disable IDER device at PSF level
+**/
+VOID
+PsfDisableIderDevice (
+ VOID
+ );
+
+/**
+ Enable SOL device at PSF level
+**/
+VOID
+PsfEnableSolDevice (
+ VOID
+ );
+
+/**
+ Disable SOL device at PSF level
+**/
+VOID
[edk2-devel] [Patch V2 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Pmc/IncludePrivate
* IpBlock/Pmc/Library
* IpBlock/Pmc/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
| 120
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Register/PmcRegsVer2.h
| 52
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
| 42 ++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
| 545
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
| 39 +++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf
| 40
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
| 166
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLibWithS3.c
| 122
++
8 files changed, 1126 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 00..0f2f251d57
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,120 @@
+/** @file
+ Header file for private PmcLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include
+#include "Register/PmcRegs.h"
+
+/**
+ This function checks if GbE device is supported (not disabled by fuse)
+
+ @retval GbE support state
+**/
+BOOLEAN
+PmcIsGbeSupported (
+ VOID
+ );
+
+/**
+ This function checks if LAN wake from DeepSx is enabled
+
+ @retval Lan Wake state
+**/
+BOOLEAN
+PmcIsLanDeepSxWakeEnabled (
+ VOID
+ );
+
+/**
+ This function sets SMI Lock with S3 Boot Script programming
+**/
+VOID
+PmcLockSmiWithS3BootScript (
+ VOID
+ );
+
+/**
+ This function sets eSPI SMI Lock
+ @attention This function must be called after eSPI SMI generation has been
enabled.
+This setting is required in all boot modes and before EndOfDxe.
+If set value will be restored upon S3 resume by bootscript.
+**/
+VOID
+PmcLockEspiSmiWithS3BootScript (
+ VOID
+ );
+
+/**
+ This function checks if eSPI SMI Lock is set
+
+ @retval eSPI SMI Lock state
+**/
+BOOLEAN
+PmcIsEspiSmiLockSet (
+ VOID
+ );
+
+typedef enum {
+ PmcSwSmiRate1p5ms = 0,
+ PmcSwSmiRate16ms,
+ PmcSwSmiRate32ms,
+ PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRateRefer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ );
+
+typedef enum {
+ PmcPeriodicSmiRate8s = 0,
+ PmcPeriodicSmiRate16s,
+ PmcPeriodicSmiRate32s,
+ PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRateRefer to PMC_PERIODIC_SMI_RATE for
possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATEPeriodicSmiRate
+ );
+
+/**
+ This function reads Power Button Level
+
+ @retval State of PWRBTN# signal (0: Low, 1: High)
+**/
+UINT8
+PmcGetPwrBtnLevel (
+ VOID
+ );
+
+/**
+ This function gets Group to GPE0 configuration
+
+ @param[out] GpeDw0Value GPIO Group to GPE_DW0 assignment
+ @param[out] GpeDw1Value GPIO Group to GPE_DW1 assignment
[edk2-devel] [Patch V2 23/40] TigerlakeSiliconPkg/IpBlock: Add PcieRp component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/PcieRp/IncludePrivate * IpBlock/PcieRp/Library * IpBlock/PcieRp/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/DxePchPcieRpPolicyLib.h | 55 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/PciExpressHelpersLib.h | 173 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/PcieRpLib.h | 109 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Register/PcieSipRegs.h | 45 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/BasePcieHelperLib/BasePcieHelperLib.c | 315 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/BasePcieHelperLib/BasePcieHelperLib.inf | 37 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLib.c | 69 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h | 20 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c | 128 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf | 39 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c | 179 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.inf | 30 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PciExpressHelpersLibrary/PciExpressHelpersLibrary.c | 1997 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PciExpressHelpersLibrary/PciExpressHelpersLibrary.h | 40 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PciExpressHelpersLibrary/PeiDxeSmmPciExpressHelpersLib.inf | 49 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c | 247 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.inf | 43 +++ 17 files changed, 3575 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/DxePchPcieRpPolicyLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/DxePchPcieRpPolicyLib.h new file mode 100644 index 00..1dea61388e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/DxePchPcieRpPolicyLib.h @@ -0,0 +1,55 @@ +/** @file + DXE PcieRp policy library. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _DXE_PCH_PCIERP_POLICY_LIB_H_ +#define _DXE_PCH_PCIERP_POLICY_LIB_H_ + +#include + +/** + Load DXE Config block default for Pch PCIE RP + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadPchPcieRpDxeConfigDefault ( + IN VOID *ConfigBlockPointer
[edk2-devel] [Patch V2 21/40] TigerlakeSiliconPkg/IpBlock: Add P2sb component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/P2sb/IncludePrivate
* IpBlock/P2sb/Library
* IpBlock/P2sb/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
| 112
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
| 65
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuRegbarAccessLib/CpuRegbarAccessLib.c
| 494
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuRegbarAccessLib/PeiDxeSmmCpuRegbarAccessLib.inf
| 35 +++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
| 313
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
| 35 +++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
| 253
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
| 36
8 files changed, 1343 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
new file mode 100644
index 00..3fab933bbd
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
@@ -0,0 +1,112 @@
+/** @file
+ Header file for PchSbiAccessLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SBI_ACCESS_LIB_H_
+#define _PCH_SBI_ACCESS_LIB_H_
+
+#include
+
+/**
+ PCH SBI opcode definitions
+**/
+typedef enum {
+ MemoryRead = 0x0,
+ MemoryWrite= 0x1,
+ PciConfigRead = 0x4,
+ PciConfigWrite = 0x5,
+ PrivateControlRead = 0x6,
+ PrivateControlWrite= 0x7,
+ GpioLockUnlock = 0x13
+} PCH_SBI_OPCODE;
+
+/**
+ PCH SBI response status definitions
+**/
+typedef enum {
+ SBI_SUCCESSFUL = 0,
+ SBI_UNSUCCESSFUL= 1,
+ SBI_POWERDOWN = 2,
+ SBI_MIXED = 3,
+ SBI_INVALID_RESPONSE
+} PCH_SBI_RESPONSE;
+
+/**
+ Execute PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in
both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If
more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after
done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be
checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would
provide additional information
+ when needed.
+
+ @param[in] PidPort ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in, out] Data32Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully complete
[edk2-devel] [Patch V2 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/PchDmi/IncludePrivate * IpBlock/PchDmi/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h | 175 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c | 50 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h | 34 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c | 269 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiWithS3Lib.c | 73 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf | 42 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf | 41 + 7 files changed, 684 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h new file mode 100644 index 00..77db69c75a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h @@ -0,0 +1,175 @@ +/** @file + Header file for PchDmiLib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_DMI_LIB_H_ +#define _PCH_DMI_LIB_H_ + +/** + This function checks if DMI Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmiLocked ( + VOID + ); + +/** + Get PCH TCO base address. + + @retval Address Address of TCO base address. +**/ +UINT16 +PchDmiGetTcoBase ( + VOID + ); + +/** + Set PCH LPC/eSPI generic IO range decoding in DMI + + @param[in] AddressAddress for generic IO range base address. + @param[in] Length Length of generic IO range. + @param[in] RangeIndex Index of choosen range + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcGenIoRange ( + IN UINT32Address, + IN UINT32Length, + IN UINT32RangeIndex + ); + +/** + Set PCH eSPI eSPI CS1# generic IO range decoding in DMI + + @param[in] AddressAddress for generic IO range base address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetEspiCs1GenIoRange ( + IN UINT32Address, + IN UINT32Length + ); + +/** + Set PCH LPC/eSPI memory range decoding in DMI + + @param[in] AddressAddress for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcMemRange ( + IN UINT32Address + ); + +/** + Set PCH eSPI CS1# memory range decoding in DMI + + @param[in] AddressAddress for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetEspiCs1MemRange ( + IN UINT32Address + ); + +/** + Check if Boot BIOS Strap is set for SPI. + + @retval TRUEBoot BIOS Strap set for SPI + @retval FALSE Boot BIOS Strap set for LPC/eSPI +**/ +BOOLEAN +PchDmiIsBootBiosStrapSetForSpi ( + VOID + ); + +/** + Set PCH BIOS range decoding in DMI + Please check EDS for detail of BiosDecodeEnable bit definition. +bit 15: F8-FF Enable +bit 14: F0-F8 Enable +bit 13: E8-EF Enable +bit 12: E0-E8 Enable +bit 11: D8-DF Enable +bit 10: D0-D7 Enable +bit 9: C8-CF
[edk2-devel] [Patch V2 20/40] TigerlakeSiliconPkg/IpBlock: Add HostBridge component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/HostBridge/IncludePrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
| 25 +
1 file changed, 25 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
new file mode 100644
index 00..41e92da4df
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
@@ -0,0 +1,25 @@
+/** @file
+ The GUID definition for Host Bridge Data Hob
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _HOST_BRIDGE_DATA_HOB_H_
+#define _HOST_BRIDGE_DATA_HOB_H_
+
+#include
+
+extern EFI_GUID gHostBridgeDataHobGuid;
+#pragma pack (push,1)
+
+///
+/// Host Bridge Data Hob
+///
+typedef struct {
+ EFI_HOB_GUID_TYPEEfiHobGuidType; ///< GUID Hob
type structure for gSaDataHobGuid
+ UINT8EnableAbove4GBMmio; ///<
0=Disable above 4GB MMIO resource support, 1=Enable above 4GB MMIO resource
support
+ BOOLEAN SkipPamLock; ///< 0=All
PAM registers will be locked in System Agent code, 1=Do not lock PAM registers
in System Agent code.
+ UINT8Rsvd1[2]; ///< Reserved
for future use
+} HOST_BRIDGE_DATA_HOB;
+#pragma pack (pop)
+#endif
--
2.24.0.windows.2
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[edk2-devel] [Patch V2 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Fru/TglCpu/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFruLib.h | 18 ++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPcieRegs.h | 24 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs.h | 42 ++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuRegs.h | 31 +++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/VtdRegs.h | 22 ++ 5 files changed, 137 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFruLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFruLib.h new file mode 100644 index 00..a46b29cbbe --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFruLib.h @@ -0,0 +1,18 @@ +/** @file + Vtd Initialization Fru Library header file + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _VTD_INIT_FRU_LIB_H_ +#define _VTD_INIT_FRU_LIB_H_ + +/// +/// TCSS DMA controller RMRR buffer 4MB for each DMA controller +/// +#define RMRR_TCSS_DMA_SIZE 0x40 + +extern UINT16 mDevEnMap[][2]; +extern UINTN mDevEnMapSize; + +#endif // _VTD_INIT_FRU_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPcieRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPcieRegs.h new file mode 100644 index 00..a571381202 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPcieRegs.h @@ -0,0 +1,24 @@ +/** @file + This file contains definitions of PCIe Configuration + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PCIE_REGS_H_ +#define _CPU_PCIE_REGS_H_ + +#define R_PCIE_LCAP 0x4C +#define R_PCIE_LCTL 0x50 +#define R_PCIE_LSTS 0x52 +#define R_PCIE_SLCAP 0x54 +#define R_PCIE_SLSTS 0x5A +#define R_PCIE_LCTL2 0x70 +#define R_PCIE_MPC 0xD8 +#define B_PCIE_MPC_HPME BIT1 +#define R_PCIE_PGTHRES 0x5C0 +#define B_PCIE_PGTHRES_L1PGLTREN BIT0 +#define R_PCIE_LCTL3 0xA34 +#define B_PCIE_LCTL3_PE BIT0 + +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs.h new file mode 100644 index 00..f0b30107f4 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs.h @@ -0,0 +1,42 @@ +/** @file + Register names for IGD block + Conventions: + - Prefixes: +- Definitions beginning with "R_" are registers +- Definitions beginning with "B_" are bits within registers +- Definitions beginning with "V_" are meaningful values of bits within the registers +- Definitions beginning with "S_" are register sizes +- Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted by +"_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" +at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be just named +as "_SA_" without [generation_name] inserted. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _IGD_REGS_H_ +#define _IGD_REGS_H_ + +/// +/// Device 2 Register Equates +/// +// +// The following equates must be reviewed and revised when the specification is ready. +// +#define IGD_BUS_NUM 0x00 +#define IGD_DEV_NUM 0x02 +#define IGD_FUN_NUM 0x00 + +/// +/// GTTMMADR aligned to 16MB (Base address = [38:24]) +/// +#define R_SA_IGD_GTTMMADR 0x10 + +#define R_SA_IGD_SWSCI_OFFSET 0x00E8 +#define R_SA_IGD_ASLS_OFFSET 0x00FC ///< ASL Storage + +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuRegs.h b/Silicon/Intel/TigerlakeSi
[edk2-devel] [Patch V2 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Fru/TglPch/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h | 66 ++ 1 file changed, 66 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h new file mode 100644 index 00..4987d21f09 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h @@ -0,0 +1,66 @@ +/** @file + Register names for PCH private chipset register + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName + - Prefix: +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values within the bits +Definitions beginning with "S_" are register size +Definitions beginning with "N_" are the bit position + - [GenerationName]: +Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). +Register name without GenerationName applies to all generations. + - [ComponentName]: +This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) +Register name without ComponentName applies to all components. +Register that is specific to -LP denoted by "_PCH_LP_" in component name. + - SubsystemName: +This field indicates the subsystem name of the component that the register belongs to +(e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: +MEM - MMIO space register of subsystem. +IO - IO space register of subsystem. +PCR - Private configuration register of subsystem. +CFG - PCI configuration space register of subsystem. + - RegisterName: +Full register name. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_REGS_PCR_H_ +#define _PCH_REGS_PCR_H_ + +/** + Definition for SBI PID + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well. +**/ +#define PID_CNVI 0x73 +#define PID_ICLK 0xAD +#define PID_DMI0x88 +#define PID_PSTH 0x89 +#define PID_ESPISPI0x72 +#define PID_SPF0x85 +#define PID_SPE0x84 +#define PID_SPD0x83 +#define PID_SPC0x82 +#define PID_SPB0x81 +#define PID_SPA0x80 +#define PID_PSF6 0x7F +#define PID_PSF4 0xBD +#define PID_PSF3 0xBC +#define PID_PSF2 0xBB +#define PID_PSF1 0xBA +#define PID_GPIOCOM0 0x6E +#define PID_GPIOCOM1 0x6D +#define PID_GPIOCOM2 0x6C +#define PID_GPIOCOM3 0x6B +#define PID_GPIOCOM4 0x6A +#define PID_GPIOCOM5 0x69 +#define PID_CSME_PSF 0x8F + +#endif -- 2.24.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#71201): https://edk2.groups.io/g/devel/message/71201 Mute This Topic: https://groups.io/mt/80375657/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [Patch V2 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Fru/TglPch/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h | 326 ++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.h| 16 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResources.h | 55 +++ 3 files changed, 397 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h new file mode 100644 index 00..0d00f25d5e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h @@ -0,0 +1,326 @@ +/** @file + Header file for TigerLake PCH devices PCI Bus Device Function map. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_BDF_ASSIGNMENT_H_ +#define _PCH_BDF_ASSIGNMENT_H_ + +#define NOT_PRESENT 0xFF + +#define MAX_SATA_CONTROLLER 1 + +// +// PCH PCIe Controllers +// +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 NOT_PRESENT + +// +// USB3 (XHCI) Controller PCI config +// +#define PCI_DEVICE_NUMBER_PCH_XHCI20 +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 + +// +// xDCI (OTG) USB Device Controller +// +#define PCI_DEVICE_NUMBER_PCH_XDCI20 +#define PCI_FUNCTION_NUMBER_PCH_XDCI 1 + +// +// Thermal Device +// +#define PCI_DEVICE_NUMBER_PCH_THERMAL NOT_PRESENT +#define PCI_FUNCTION_NUMBER_PCH_THERMAL NOT_PRESENT + +// +// CSME HECI #1 +// +#define PCI_DEVICE_NUMBER_PCH_HECI1 22 +#define PCI_FUNCTION_NUMBER_PCH_HECI1 0 + +// +// CSME HECI #2 +// +#define PCI_DEVICE_NUMBER_PCH_HECI2 22 +#define PCI_FUNCTION_NUMBER_PCH_HECI2 1 + +// +// CSME IDE-Redirection (IDE-R) +// +#define PCI_DEVICE_NUMBER_PCH_IDER22 +#define PCI_FUNCTION_NUMBER_PCH_IDER 2 + +// +// CSME Keyboard and Text (KT) Redirection +// +#define PCI_DEVICE_NUMBER_PCH_KTR 22 +#define PCI_FUNCTION_NUMBER_PCH_KTR 3 + +// +// CSME HECI #3 +// +#define PCI_DEVICE_NUMBER_PCH_HECI3 22 +#define PCI_FUNCTION_NUMBER_PCH_HECI3 4 + +// +// CSME HECI #4 +// +#define PCI_DEVICE_NUMBER_PCH_HECI4 22 +#define PCI_FUNCTION_NUMBER_PCH_HECI4 5 + +// +// CSME MROM +// +#define PCI_DEVICE_NUMBER_PCH_MROMNOT_PRESENT +#define PCI_FUNCTION_NUMBER_PCH_MROM NOT_PRESENT + +// +// CSME WLAN +// +#define PCI_DEVICE_NUMBER_PCH_WLAN22 +#define PCI_FUNCTION_NUMBER_PCH_WLAN 7 + +// +// SATA
[edk2-devel] [Patch V2 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Fru/TglCpu/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruLib.h | 57 + Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBridge.h | 145 + Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h | 12 3 files changed, 214 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruLib.h new file mode 100644 index 00..89cf952717 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruLib.h @@ -0,0 +1,57 @@ +/** @file + Header file for CpuPcieInfoFruLib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_PCIE_INFO_FRU_LIB_H_ +#define _CPU_PCIE_INFO_FRU_LIB_H_ + +#include + +#define CPU_PCIE_MAX_ROOT_PORTS 4 + +#define CPU_PCIE_ULT_ULX_MAX_ROOT_PORT 1 + +#include + +/** + Get CPU Maximum Pcie Root Port Number + + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number +**/ +UINT8 +GetMaxCpuPciePortNum ( + VOID + ); + +/** + Get CPU Pcie Root Port Device and Function Number by Root Port physical Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device number. + @param[out] RpFun Return corresponding root port function number. + + @retval EFI_SUCCESS Root port device and function is retrieved + @retval EFI_INVALID_PARAMETER RpNumber is invalid +**/ +EFI_STATUS +EFIAPI +GetCpuPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ); + +/** + Gets pci segment base address of PCIe root port. + + @param RpIndexRoot Port Index (0 based) + @return PCIe port base address. +**/ +UINT64 +CpuPcieBase ( + IN UINT32 RpIndex + ); + +#endif // _CPU_PCIE_INFO_FRU_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBridge.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBridge.h new file mode 100644 index 00..32e38fa072 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBridge.h @@ -0,0 +1,145 @@ +/** @file + Register names for Host Bridge block + Conventions: + - Prefixes: +- Definitions beginning with "R_" are registers +- Definitions beginning with "B_" are bits within registers +- Definitions beginning with "V_" are meaningful values of bits within the registers +- Definitions beginning with "S_" are register sizes +- Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted by +"_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" +at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be just named +as "_SA_" without [generation_name] inserted. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SA_REGS_HOST_BRIDGE_H_ +#define _SA_REGS_HOST_BRIDGE_H_ + +#define SA_SEG_NUM 0x00 +#define V_SA_DEVICE_ID_INVALID 0x +// +// DEVICE 0 (Memory Controller Hub) +// +#define SA_MC_BUS 0x00 +#define SA_MC_DEV 0x00 +#define SA_MC_FUN 0x00 +#define V_SA_MC_VID0x8086 +#define R_SA_MC_DEVICE_ID 0x02 +#define R_SA_MC_CAPID0_B 0xE8 + +// +// SA DMI configuration +// + +// +// Maximum DMI lanes and bundles supported (x8 and 4 lanes) +// +#define SA_DMI_MAX_LANE 0x08 +#define SA_DMI_MAX_BUNDLE0x04 +#define SA_DMI_MAX_LANE_VER1 0x04 +#define SA_DMI_MAX_BUNDLE_VER1 0x02 + + +// +// TigerLake Mobile SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_MB_ULT_1 0x9A14 ///< TigerLake Ult (TGL-U 4+2) +#define V_SA_DEVICE_ID_MB_ULT_2 0x9A04 ///< TigerLake Ult (TGL-U 2+2) + +#define V_SA_DEVICE_ID_MB_ULX_1 0x9A12 ///< TigerLake Ulx (TGL-Y 4+2) +#define V_SA_DEVICE_ID_MB_ULX_2 0x9A02 ///< TigerLake Ulx (TGL-Y 2+2) + +/** + Description: + - This is the base addres
[edk2-devel] [Patch V2 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivate headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following header files:
* SystemAgent/IncludePrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h
| 42 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
| 30 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h
| 50 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvsAreaDef.h
| 222
++
4 files changed, 344 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h
new file mode 100644
index 00..2e86d497f9
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h
@@ -0,0 +1,42 @@
+/** @file
+ This file defines the SA Iotrap SMI Protocol to provide the
+ I/O address for registered Iotrap SMI.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SA_IOTRAP_SMI_PROTOCOL_H_
+#define _SA_IOTRAP_SMI_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gSaIotrapSmiProtocolGuid;
+
+#define SA_IOTRAP_SMI_PROTOCOL_REVISION_1 1
+
+//
+// SA IO Trap SMI Protocol definition (Private protocol for RC internal use
only)
+//
+typedef struct {
+/*
+ Protocol revision number
+ Any backwards compatible changes to this protocol will result in an update in
the revision number
+ Major changes will require publication of a new protocol
+
+ Revision 1:
+- First version
+*/
+ UINT8 Revision;
+ UINT16 SaIotrapSmiAddress;
+} SA_IOTRAP_SMI_PROTOCOL;
+
+///
+/// Pcie Trap valid types
+///
+typedef enum {
+ CpuPciePmTrap,
+ CpuPcieTrapTypeMaximum
+} CPU_PCIE_TRAP_TYPE;
+
+#endif
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
new file mode 100644
index 00..785a808cf4
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
@@ -0,0 +1,30 @@
+/** @file
+ Definition of the System Agent global NVS area protocol.
+ This protocol publishes the address and format of a global ACPI NVS buffer
+ used as a communications buffer between SMM/DXE/PEI code and ASL code.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SYSTEM_AGENT_NVS_AREA_H_
+#define _SYSTEM_AGENT_NVS_AREA_H_
+
+//
+// SA NVS Area definition
+//
+#include
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gSaNvsAreaProtocolGuid;
+
+///
+/// System Agent Global NVS Area Protocol
+///
+typedef struct {
+ SYSTEM_AGENT_NVS_AREA *Area;///< System Agent Global NVS Area
Structure
+} SYSTEM_AGENT_NVS_AREA_PROTOCOL;
+
+#endif // _SYSTEM_AGENT_NVS_AREA_H_
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h
new file mode 100644
index 00..65622069e6
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h
@@ -0,0 +1,50 @@
+/** @file
+ The GUID definition for SaConfigHob
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SA_CONFIG_HOB_H_
+#define _SA_CONFIG_HOB_H_
+
+#include
+#include
+#include "CpuPcieInfo.h"
+#include
+
+extern EFI_GUID gSaConfigHobGuid;
+#define SA_VTD_ENGINE_NUMBER3
+
+#pragma pack (push,1)
+///
+/// DPR Directory Types
+///
+typedef enum {
+ EnumDprDirectoryTxt = 0,
+} DPR_DIRECTORY_ELEMENT;
+
+#define DPR_DIRECTORY_TYPE_TXT 0x01 ///< DPR directory type - TXT
+#define DPR_DIRECTORY_TYPE_BIOSGUARD0x02 ///< DPR directory type -
BIOS Guard
+#define DPR_DIRECTORY_MAX 1 ///< DPR Maximum Size
+
+///
+/// DPR directory entry definition
+///
+typedef struct {
+ UINT8 Type; ///< DPR Directory Type
+ UINT8 Size; ///< DPR Size in MB
+ UINT32 PhysBase; ///< Must be 4K aligned (bits 11..0 must be clear)
+ UINT16 Reserved; ///< Must be 0
+} DPR_DIRECTORY_ENTRY;
+
+///
+/// System Agent Config Hob
+///
+typedef struct {
+ EFI_HOB_GUID_TYPEEfiHobGuidType;
[edk2-devel] [Patch V2 07/40] TigerlakeSiliconPkg/SystemAgent: Add include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following header files:
* SystemAgent/Include
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
| 123
+++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieDxeConfig.h
| 114
++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PramPreMemConfig.h
| 34 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiConfig.h
| 24
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h
| 104
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/SaPlatformLib.h
| 48
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h
| 264
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h
| 61 +
8 files changed, 772 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
new file mode 100644
index 00..451e295b49
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
@@ -0,0 +1,123 @@
+/** @file
+ Memory DXE Policy definitions
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MEMORY_DXE_CONFIG_H_
+#define _MEMORY_DXE_CONFIG_H_
+
+#pragma pack(push, 1)
+
+#define MEMORY_DXE_CONFIG_REVISION 1
+
+typedef struct _MEMORY_DXE_CONFIG MEMORY_DXE_CONFIG;
+
+/**
+ Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator
field.
+ Implementation of this function is optional, if this function pointer is
NULL then
+ the reference implementation of DeviceLocator will be used.
+
+ @param[in] This A pointer to this instance of
MEMORY_DXE_CONFIG.
+ @param[in] ControllerDesired Controller to get a
DeviceLocator string for.
+ @param[in] Dimm Desired DIMM to get a
DeviceLocator string for.
+ @param[in] MdSocket 0 = Memory Down, 1 = Socketed.
+
+ @retval The DeviceLocator string
+ @retval NULL If the return value is NULL, the
default value will be used.
+**/
+typedef
+CHAR8*
+(EFIAPI *MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING)(
+ IN CONSTMEMORY_DXE_CONFIG *This,
+ IN UINT8 Controller,
+ IN UINT8 Dimm,
+ IN UINT8 MdSocket
+ );
+
+/**
+ Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator
field.
+ Implementation of this function is optional, if this function pointer is
NULL then
+ the reference implementation of DeviceLocator will be used.
+
+ @param[in] This A pointer to this instance of
MEMORY_DXE_CONFIG.
+ @param[in] ControllerDesired Controller to get a
BankLocator string for.
+ @param[in] Dimm Desired DIMM to get a BankLocator
string for.
+ @param[in] MdSocket 0 = Memory Down, 1 = Socketed.
+
+ @retval The BankLocator string
+ @retval NULL If the return value is NULL, the
default value will be used.
+**/
+typedef
+CHAR8*
+(EFIAPI *MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING)(
+ IN CONSTMEMORY_DXE_CONFIG *This,
+ IN UINT8 Controller,
+ IN UINT8 Dimm,
+ IN UINT8 MdSocket
+ );
+
+/**
+ The Memory Configuration includes DIMM SPD address Map and DIMM Slot
Mechanical present bit map.
+ The data elements should be initialized by a Platform Module.\n
+ Revision 1:
+ - Initial version.
+**/
+struct _MEMORY_DXE_CONFIG {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config
Block Header
+/**
+ Offset 28:
+ Dimm SPD address
+ Only Server support 2 channels
[edk2-devel] [Patch V2 06/40] TigerlakeSiliconPkg/Pch: Add IncludePrivate headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Pch/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h | 47 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h | 26 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h | 269 + Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchHybridStorageHob.h | 21 + Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchNvsAreaDef.h | 319 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchRstHob.h | 58 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PchNvsArea.h | 30 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PcieIoTrap.h | 35 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/SiScheduleResetHob.h | 21 + 9 files changed, 826 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h new file mode 100644 index 00..2ad80a0269 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h @@ -0,0 +1,47 @@ +/** @file + Reset scheduling library services + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_SCHEDULE_RESET_LIB_H_ +#define _SI_SCHEDULE_RESET_LIB_H_ + +#include +#include + +/** + This function updates the reset information in SiScheduleResetHob + @param[in] ResetTypeUEFI defined reset type. + @param[in] ResetDataOptional element used to introduce a platform specific reset. + The exact type of the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. +**/ +VOID +SiScheduleResetSetType ( + IN EFI_RESET_TYPE ResetType, + IN PCH_RESET_DATA *ResetData OPTIONAL + ); + +/** + This function returns TRUE or FALSE depending on whether a reset is required based on SiScheduleResetHob + + @retval BOOLEAN The function returns FALSE if no reset is required +**/ +BOOLEAN +SiScheduleResetIsRequired ( + VOID + ); + +/** + This function performs reset based on SiScheduleResetHob + + @retval BOOLEAN The function returns FALSE if no reset is required +**/ +BOOLEAN +SiScheduleResetPerformReset ( + VOID + ); + +#endif //_SI_SCHEDULE_RESET_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h new file mode 100644 index 00..955dac5a82 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h @@ -0,0 +1,26 @@ +/** @file + Header file for private PCH SMM Lib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SMM_PCH_PRIVATE_LIB_H_ +#define _SMM_PCH_PRIVATE_LIB_H_ + +/** + Set InSmm.Sts bit +**/ +VOID +PchSetInSmmSts ( + VOID + ); + +/** + Clear InSmm.Sts bit +**/ +VOID +PchClearInSmmSts ( + VOID + ); + +#endif // _SMM_PCH_PRIVATE_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h new file mode 100644 index 00..13a41f8d04 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h @@ -0,0 +1,269 @@ +/** @file + The GUID definition for PchConfigHob + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_CONFIG_HOB_H_ +#define _PCH_CONFIG_HOB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +extern EFI_GUID gPchConfigHobGuid; + +#pragma pack (push,1
[edk2-devel] [Patch V2 05/40] TigerlakeSiliconPkg/Pch: Add include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Pch/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h | 55 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h | 57 + Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h | 58 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h | 64 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h | 61 + Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h | 38 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h | 72 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h | 258 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h | 590 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h | 552 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h | 70 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h | 67 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h | 55 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h | 56 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h | 21 + Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.h | 184 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h | 134 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h | 144 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h | 166 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h | 40 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h | 132
[edk2-devel] [Patch V2 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds header files common to CPU modules.
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
| 83
+++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
| 148
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfig.h
| 52
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtBasicConfig.h
| 226
++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtCustomConfig.h
| 76
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtPsysConfig.h
| 36
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtTestConfig.h
| 150
++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPreMemConfig.h
| 63 +++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h
| 51 +++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h
| 12
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h
| 21 +
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h
| 23 +++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h
| 18 ++
13 files changed, 959 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
new file mode 100644
index 00..d837500a38
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
@@ -0,0 +1,83 @@
+/** @file
+ CPU Config Block.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_CONFIG_H_
+#define _CPU_CONFIG_H_
+
+#define CPU_CONFIG_REVISION 3
+
+extern EFI_GUID gCpuConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ CPU Configuration Structure.
+
+ Revision 1:
+ - Initial version.
+ Revision 2:
+ - Add SmbiosType4MaxSpeedOverride.
+ Revision 3:
+ - Add AvxDisable & Avx3Disable.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32MicrocodePatchRegionSize;
+ EFI_PHYSICAL_ADDRESS MicrocodePatchAddress;///< Pointer to microcode
patch that is suitable for this processor.
+ /**
+Enable or Disable Advanced Encryption Standard (AES) feature.
+For some countries, this should be disabled for legal reasons.
+-0: Disable
+- 1: Enable
+ **/
+ UINT32 AesEnable : 1;
+ /**
+Enable or Disable Trusted Execution Technology (TXT) feature.
+-0: Disable
+- 1: Enable
+ **/
+ UINT32 TxtEnable : 1;
+ UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon
Initialization will skip MP Initialization (including BSP) if enabled. For
non-FSP, this should always be 0.
+ /**
+Enable or Disable or Auto for PPIN Support to view Protected Processor
Inventory Number.
+- 0: Disable
+-1: Enable
+-2: Auto : Feature is based on End Of Manufacturing (EOM) flag. If EOM
is set, it is disabled.
+ **/
+ UINT32 PpinSupport : 2;
+ /**
+Enable or Disable #AC machine check on split lock.
+- 0: Disable
+-1: Enable
+ **/
+ UINT32 AcSplitLock : 1;
+ /**
+ Enable or Disable Avx.
+ - 1: Disable
+ - 0: Enable
+ **/
+ UINT32 AvxDisable : 1;
+ /**
+ Enable or Disable Avx3.
+ - 1: Disable
+ - 0: Enable
+ **/
+ UINT32 Avx3Disable : 1;
+ UINT32 RsvdBits: 24;///< Reserved for future use
+ /**
+Provide the option for platform to override the MaxSpeed field of Smbios
Type 4.
+Value 4000 means 4000MHz.
+If this value is not zero, it dominates the field.
+If this value is zero, CPU RC will
[edk2-devel] [Patch V2 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register and other include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following header files:
* Include/Pins
* Include/Register
* Include/*.h
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h| 53
+
Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h | 38
++
Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h | 75
+++
Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h | 138
++
Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h| 57
+
Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h | 24
Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h | 155
+++
Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h| 110
++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h | 72
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h | 121
+
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h | 226
++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h | 16
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h| 36
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h | 93
+
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h | 258
++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h | 45
+
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h | 56
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h | 47
+++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h | 51
+++
Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h| 213
+
Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h| 17
+
Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h | 64
22 files changed, 1965 insertions(+)
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 00..ad34e4ea42
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include
+#include
+#include
+#include
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+ EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID
extension HOB header
+ UINT8 Revision; ///< Offset 24Revision
of this config block
+ UINT8 Attributes; ///< Offset 25The main
revision for config block
+ UINT8 Reserved[2]; ///< Offset 26-27 Reserved
for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+
Re: [edk2-devel] [PATCH 40/40] Maintainers.txt: Add TigerlakeSiliconPkg maintainers
Thank Nate, I will send out Patch V2 following you comments. > -Original Message- > From: Desimone, Nathaniel L > Sent: Thursday, February 4, 2021 11:51 AM > To: Luo, Heng ; devel@edk2.groups.io > Cc: Chaganty, Rangasai V > Subject: RE: [PATCH 40/40] Maintainers.txt: Add TigerlakeSiliconPkg > maintainers > > Hi Heng, > > Thank you so much for all your work on this! I have a couple of minor > comments, > however due to the size of this patch series I produced a summary of these > comments here for your convenience: > > [PATCH 01/40] > > #1) CpuPcieConfigGen3.h is only used on Rocket Lake boards for backwards > socket compatibility with Comet Lake. It is not needed for Tiger Lake. Please > remove it. > #2) CpuPcieConfig.h - CPU_PCIE_CONFIG Is missing the following from its > definition: > > CPU_PCIE_ROOT_PORT_CONFIG2 > RootPort2[CPU_PCIE_MAX_ROOT_PORTS]; > PCIE_COMMON_CONFIG2PcieCommonConfig2; > > [PATCH 02/40] > > #1) FspmArchConfigPpi.h is a duplicate of a header file in IntelFsp2Pkg, > please > remove this duplicate > #2) SiPolicy.h - Please also remove the #include for CpuPcieConfigGen3.h > > [PATCH 34/40] > > #1) DxeSaPolicyLib.c - There is an old comment that is no longer relevant, > please > delete. > #2) DxeSaPolicyLibrary.h - Please also remove the #include for > CpuPcieConfigGen3.h > > [PATCH 35/40] > > #1) DxeVtdInitFruLib.c - Comment on line 2 has a typo "Flu" should be "FRU" > > [PATCH 36/40] > > #1) PchSmiHelper.h - Comment on line 2 has a typo: "eSPI SMI Dispatch header" > should be "PCH SMI Helper Header" > > [PATCH 39/40] > > #1) SiPkgCommonLib.dsc - The DEFINE PCH = Cnl is unused, please delete it. > > Thanks, > Nate > > > -Original Message- > > From: Luo, Heng > > Sent: Sunday, January 31, 2021 5:37 PM > > To: devel@edk2.groups.io > > Cc: Chaganty, Rangasai V ; Desimone, > > Nathaniel L > > Subject: [PATCH 40/40] Maintainers.txt: Add TigerlakeSiliconPkg > > maintainers > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 > > > > Cc: Sai Chaganty > > Cc: Nate DeSimone > > Signed-off-by: Heng Luo > > --- > > Maintainers.txt | 6 ++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/Maintainers.txt b/Maintainers.txt index > > 56e16fc48c..34f0b58581 > > 100644 > > --- a/Maintainers.txt > > +++ b/Maintainers.txt > > @@ -242,6 +242,12 @@ F: Silicon/Intel/KabylakeSiliconPkg/ > > M: Chasel Chiu M: Sai Chaganty > > +Silicon/Intel/TigerlakeSiliconPkg+F: > > Silicon/Intel/TigerlakeSiliconPkg/+M: Sai Chaganty > > +M: Nate DeSimone > > +R: Heng Luo + > > Silicon/Intel/SimicsX58SktPkg F: Silicon/Intel/SimicsX58SktPkg/ M: > > Agyeman Prince -- > > 2.24.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#71189): https://edk2.groups.io/g/devel/message/71189 Mute This Topic: https://groups.io/mt/80274157/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 40/40] Maintainers.txt: Add TigerlakeSiliconPkg maintainers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Maintainers.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 56e16fc48c..34f0b58581 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -242,6 +242,12 @@ F: Silicon/Intel/KabylakeSiliconPkg/ M: Chasel Chiu M: Sai Chaganty +Silicon/Intel/TigerlakeSiliconPkg +F: Silicon/Intel/TigerlakeSiliconPkg/ +M: Sai Chaganty +M: Nate DeSimone +R: Heng Luo + Silicon/Intel/SimicsX58SktPkg F: Silicon/Intel/SimicsX58SktPkg/ M: Agyeman Prince -- 2.24.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70990): https://edk2.groups.io/g/devel/message/70990 Mute This Topic: https://groups.io/mt/80274157/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 39/40] TigerlakeSiliconPkg: Add package DSC files
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc| 122 ++ Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc | 49 + Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc| 47 +++ Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc | 40 Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc| 20 Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc | 20 Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc | 229 + 7 files changed, 527 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc new file mode 100644 index 00..51c40812ea --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc @@ -0,0 +1,122 @@ +## @file +# Silicon build option configuration file. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[BuildOptions] +# Define Build Options both for EDK and EDKII drivers. + + DEFINE PCH_BUILD_OPTIONS = -DPCH_TGL +# +# SA +# +!if gSiPkgTokenSpaceGuid.PcdBdatEnable == TRUE + DEFINE BDAT_BUILD_OPTION = -DBDAT_SUPPORT=1 +!else + DEFINE BDAT_BUILD_OPTION = +!endif + + DEFINE SLE_BUILD_OPTIONS = +!if $(TARGET) == RELEASE +!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE + DEFINE DEBUG_BUILD_OPTIONS = +!else + # MDEPKG_NDEBUG is introduced for the intention + # of size reduction when compiler optimization is disabled. If MDEPKG_NDEBUG is + # defined, then debug and assert related macros wrapped by it are the NULL implementations. + DEFINE DEBUG_BUILD_OPTIONS = -DMDEPKG_NDEBUG +!endif +!else + DEFINE DEBUG_BUILD_OPTIONS = +!endif + +!if ($(TARGET) == RELEASE) AND (gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE) + DEFINE RELEASE_CATALOG_BUILD_OPTIONS = -DRELEASE_CATALOG +!else + DEFINE RELEASE_CATALOG_BUILD_OPTIONS = +!endif + +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE + DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL- +!else + DEFINE OPTIMIZE_DISABLE_OPTIONS = +!endif + + DEFINE HSLE_BUILD_OPTIONS = + + + DEFINE CPU_FLAGS = -DCPU_ICL -DCPU_TGL + + + DEFINE RESTRICTED_OPTION = + +!if gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported == FALSE + *_*_*_MRC_NDEBUG = -DMDEPKG_NDEBUG +!endif + +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS = $(BDAT_BUILD_OPTION) $(DEBUG_BUILD_OPTIONS) +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(PCH_BUILD_OPTIONS) $(CPU_FLAGS) $(HSLE_BUILD_OPTIONS) + +!if gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == TRUE + *_*_X64_GENFW_FLAGS = --keepexceptiontable +!endif + +[BuildOptions.Common.EDKII] + +# +# For IA32 Global Build Flag +# + *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI + *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + +# +# For IA32 Specific Build Flag +# +GCC: *_*_IA32_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_IA32_ASM_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI /w34668 +MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) + +# +# For X64 Global Build Flag +# + *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 + *_*_X64_VFRPP_FLAGS= $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLPP_FLAGS= $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLCC_FLAGS= $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + +# +# For X64 Specific Build Flag +# +GCC: *_*_X64_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) +MSFT
[edk2-devel] [PATCH 38/40] TigerlakeSiliconPkg/Fru: Add Fru DSC files
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following DSC files: * Fru/TglCpu * Fru/TglPch Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc | 11 +++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc | 9 + Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc| 20 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc | 8 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc| 7 +++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc | 30 ++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Dxe.dsc | 9 + Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/DxeLib.dsc| 13 + Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Pei.dsc | 8 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/PeiLib.dsc| 10 ++ 10 files changed, 125 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc new file mode 100644 index 00..99ee0eccac --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc @@ -0,0 +1,11 @@ +## @file +# Component description file for the TigerLake CPU Common FRU libraries. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +VtdInfoLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoLib/PeiDxeSmmVtdInfoLib.inf +CpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf +CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc new file mode 100644 index 00..874e4cbaad --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc @@ -0,0 +1,9 @@ +## @file +# Component description file for the Tigerlake CPU DXE FRU drivers. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc new file mode 100644 index 00..5c72c2ac61 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc @@ -0,0 +1,20 @@ +## @file +# Component description file for the Tigerlake CPU DXE FRU libraries. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +DxeGraphicsPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf +DxeGraphicsInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeGraphicsInitLib/DxeGraphicsInitLib.inf +DxeIgdOpRegionInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf +DxeVtdInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.inf +DxeVtdPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/LibraryPrivate/DxeVtdPolicyLib/DxeVtdPolicyLib.inf +DxeVtdInitFruLib|$(PLATFORM_SI_PACKAGE)/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.inf + + +# +# CPU PCIe IpBlock +# +DxeCpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc new file mode 100644 index 00..de8288364a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc @@ -0,0 +1,8 @@ +## @file +# Component description file for the Tigerlake CPU PEI FRU drivers. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc new file mode 100644 index 00..5355ecb288 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc @@ -0,0 +1,7 @@ +## @file +# Component description file for the Tigerlake CPU PEI FRU ibraries. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc new file mode 100644 index 00..b7ba1f752c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc @@ -0,0 +1,30 @@ +## @file +# Component description file for the Tigerlake PCH Common FRU libraries. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier
[edk2-devel] [PATCH 37/40] TigerlakeSiliconPkg/SystemAgent: Add SystemAgent modules
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* SystemAgent/SaInit/Dxe
* SystemAgent/SaInit/Smm
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c |
431
+++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c |
120
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h |
58 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c |
181
+
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h |
136
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf |
117
+
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/CpuPcieSmm.c |
454
++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm.c |
112
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm.h |
122
++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm.inf |
72
10 files changed, 1803 insertions(+)
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c
new file mode 100644
index 00..d84a0c1fa4
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c
@@ -0,0 +1,431 @@
+/** @file
+ This is the driver that initializes the Intel System Agent.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "SaInitDxe.h"
+#include "SaInit.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+///
+/// Global Variables
+///
+GLOBAL_REMOVE_IF_UNREFERENCED SYSTEM_AGENT_NVS_AREA_PROTOCOL
mSaNvsAreaProtocol;
+GLOBAL_REMOVE_IF_UNREFERENCED SA_POLICY_PROTOCOL *mSaPolicy;
+extern SA_CONFIG_HOB *mSaConfigHob;
+
+/**
+ A protocol callback which updates 64bits MMIO Base and Length in SA GNVS area
+**/
+VOID
+UpdateSaGnvsForMmioResourceBaseLength (
+ VOID
+ )
+{
+ EFI_PHYSICAL_ADDRESS PciBaseAddress;
+ UINT32Tolud;
+ UINT64Length;
+ UINT64McD0BaseAddress;
+ UINTN ResMemLimit1;
+ UINT8 EnableAbove4GBMmioBiosAssignemnt;
+ HOST_BRIDGE_DATA_HOB *HostBridgeDataHob;
+
+ PciBaseAddress = 0;
+ Tolud = 0;
+ Length = 0;
+ ResMemLimit1 = 0;
+ EnableAbove4GBMmioBiosAssignemnt = 0;
+ HostBridgeDataHob = NULL;
+ //
+ // Read memory map registers
+ //
+ McD0BaseAddress= PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0,
0, 0);
+ Tolud = PciSegmentRead32 (McD0BaseAddress + R_SA_TOLUD) &
B_SA_TOLUD_TOLUD_MASK;
+ PciBaseAddress = Tolud;
+
+ ResMemLimit1 = (UINTN) PcdGet64 (PcdSiPciExpressBaseAddress);
+
+ Length = ResMemLimit1 - PciBaseAddress;
+
+ //
+ // Get HostBridgeData HOB and see if above 4GB MMIO BIOS assignment enabled
+ //
+ HostBridgeDataHob = (HOST_BRIDGE_DATA_HOB *) GetFirstGuidHob
();
+
[edk2-devel] [PATCH 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and Vtd library instances
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib
* Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
| 81
+
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
| 36
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c
| 18 ++
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.inf
| 39 +++
4 files changed, 174 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
new file mode 100644
index 00..6a9bc89ecf
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
@@ -0,0 +1,81 @@
+/** @file
+ CPU PCIe information library.
+
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Get Maximum CPU Pcie Root Port Number
+
+ @retval Maximum CPU Pcie Root Port Number
+**/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ )
+{
+ return CPU_PCIE_ULT_ULX_MAX_ROOT_PORT;
+}
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port physical
Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device
number.
+ @param[out] RpFun Return corresponding root port function
number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ )
+{
+ if (RpNumber > GetMaxCpuPciePortNum ()) {
+DEBUG ((DEBUG_ERROR, "GetCpuPcieRpDevFun invalid RpNumber %x", RpNumber));
+ASSERT (FALSE);
+return EFI_INVALID_PARAMETER;
+ }
+ //
+ // For TGL - U/Y only one CPU PCIE Root port is present
+ //
+ *RpDev = 6;
+ *RpFun = 0;
+ return EFI_SUCCESS;
+}
+/**
+
+ Gets pci segment base address of PCIe root port.
+
+ @param RpIndexRoot Port Index (0 based)
+
+ @return PCIe port base address.
+**/
+UINT64
+CpuPcieBase (
+ IN UINT32 RpIndex
+ )
+{
+ UINTN RpDevice;
+ UINTN RpFunction;
+ GetCpuPcieRpDevFun (RpIndex, , );
+ return PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, (UINT32) RpDevice,
(UINT32) RpFunction, 0);
+}
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
new file mode 100644
index 00..b6a40b2f7c
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
@@ -0,0 +1,36 @@
+## @file
+# CPU PCIe information library for TigerLake PCH.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmCpuPcieInfoFruLib
+FILE_GUID = 59CA5352-ED46-4449-BF1C-0D0074C4D5B1
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuPcieInfoFruLib
+
+
+[LibraryClasses]
+IoLib
+BaseLib
+DebugLib
+PrintLib
+PcdLib
+ConfigBlockLib
+CpuPcieInitCommonLib
+
+[Packages]
+MdePkg/MdePkg.dec
+TigerlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+CpuPcieInfoFruLib.c
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c
new file mode 100644
index 00..8a0a8b6335
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c
@@ -0,0 +1,18 @@
+/** @file
+ DXE Flu Library to initialize Vtd
+
+ Copyright (c) 2021, Inte
[edk2-devel] [PATCH 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and library instances
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * SystemAgent/AcpiTables * SystemAgent/Library/DxeSaPolicyLib * SystemAgent/Library/PeiDxeSmmSaPlatformLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRp.asl | 252 +++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRpCommon.asl | 289 +++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegCommon.asl | 1344 +++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegRtd3.asl | 124 ++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.asl | 26 ++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl | 20 ++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf | 22 +++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c | 264 +++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf | 48 Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h | 34 +++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf | 32 ++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.c | 68 + Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.h | 21 ++ 13 files changed, 2544 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRp.asl b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRp.asl new file mode 100644 index 00..0babf047ed --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRp.asl @@ -0,0 +1,252 @@ +/** @file + This file contains the CPU PCIe Root Port configuration + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +External(LTRX) // CPU PCIe Root Port 0 Latency Tolerance Reporting Enable +External(LTRY) // CPU PCIe Root Port 1 Latency Tolerance Reporting Enable +External(LTRZ) // CPU PCIe Root Port 2 Latency Tolerance Reporting Enable +External(LTRW) // CPU PCIe Root Port 3 Latency Tolerance Reporting Enable +External(SMSL) // CPU PCIe Root Port Latency Tolerance Reporting Max Snoop Latency +External(SNSL) // CPU PCIe Root Port Latency Tolerance Reporting Max No Snoop Latency +External(PG0E) // CpuPcieRp0Enable 0: Disable; 1: Enable +External(PG1E) // CpuPcieRp1Enable 0: Disable; 1: Enable +External(PG2E) // CpuPcieRp2Enable 0: Disable; 1: Enable +External(PG3E) // CpuPcieRp3Enable 0: Disable; 1: Enable +External(\_SB.PC00.PEG0, DeviceObj) +External(\_SB.PC00.PEG1, DeviceObj) +External(\_SB.PC00.PEG2, DeviceObj) +External(\_SB.PC00.PEG3, DeviceObj) +External(\_SB.PC00.PEG0.PEGP, DeviceObj) +External(\_SB.PC00.PEG1.PEGP, DeviceObj) +External(\_SB.PC00.PEG2.PEGP, DeviceObj) +External
[edk2-devel] [PATCH 33/40] TigerlakeSiliconPkg/Pch: Add Pch private library instances
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* Pch/LibraryPrivate/BaseSiScheduleResetLib
* Pch/LibraryPrivate/SmmPchPrivateLib
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetLib/BaseSiScheduleResetLib.c
| 171
+++
Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetLib/BaseSiScheduleResetLib.inf
| 37 +
Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/SmmPchPrivateLib.c
| 57 +
Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/SmmPchPrivateLib.inf
| 31 +++
4 files changed, 296 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetLib/BaseSiScheduleResetLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetLib/BaseSiScheduleResetLib.c
new file mode 100644
index 00..1880244a01
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetLib/BaseSiScheduleResetLib.c
@@ -0,0 +1,171 @@
+/** @file
+ Reset scheduling library services
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ This function returns SiScheduleResetHob for library use
+**/
+STATIC
+SI_SCHEDULE_RESET_HOB *
+SiScheduleGetResetData (
+ VOID
+ )
+{
+ STATIC SI_SCHEDULE_RESET_HOB *SiScheduleResetHob = NULL;
+ SI_SCHEDULE_RESET_HOB*SiScheduleResetHobTemp;
+ VOID *HobPtr;
+
+ if (SiScheduleResetHob != NULL) {
+return SiScheduleResetHob;
+ }
+
+ HobPtr = GetFirstGuidHob ();
+ if (HobPtr == NULL) {
+SiScheduleResetHobTemp = BuildGuidHob (, sizeof
(SI_SCHEDULE_RESET_HOB));
+if (SiScheduleResetHobTemp == NULL) {
+ ASSERT (FALSE);
+ return SiScheduleResetHobTemp;
+}
+SiScheduleResetHobTemp->ResetType = 0xFF;
+DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : Init SiScheduleResetHob\n"));
+ } else {
+SiScheduleResetHobTemp = (SI_SCHEDULE_RESET_HOB*) GET_GUID_HOB_DATA
(HobPtr);
+ }
+ SiScheduleResetHob = SiScheduleResetHobTemp;
+ return SiScheduleResetHobTemp;
+}
+
+/**
+ This function updates the reset information in SiScheduleResetHob
+ @param[in] ResetTypeUEFI defined reset type.
+ @param[in] ResetDataOptional element used to introduce a platform
specific reset.
+ The exact type of the reset is defined by the
EFI_GUID that follows
+ the Null-terminated Unicode string.
+**/
+VOID
+SiScheduleResetSetType (
+ IN EFI_RESET_TYPE ResetType,
+ IN PCH_RESET_DATA *ResetData OPTIONAL
+ )
+{
+ SI_SCHEDULE_RESET_HOB *SiScheduleResetHob;
+ if (ResetType > EfiResetPlatformSpecific) {
+DEBUG ((DEBUG_INFO, "Unsupported Reset Type Requested\n"));
+return;
+ }
+ SiScheduleResetHob = SiScheduleGetResetData ();
+ if (SiScheduleResetHob == NULL) {
+return;
+ }
+ DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : Current Reset Type = 0x%x\n",
SiScheduleResetHob->ResetType));
+ if (SiScheduleResetHob->ResetType == ResetType) {
+DEBUG ((DEBUG_INFO, "Current Reset Type is same as requested Reset
Type\n"));
+return;
+ }
+ if (SiScheduleResetHob->ResetType == 0xFF) {
+// Init Reset Type to lowest ResetType
+SiScheduleResetHob->ResetType = EfiResetWarm;
+ }
+ //
+ // ResetType Priority set as : ResetPlatformSpecific(3) > ResetShutdown(2) >
ResetCold(0) > ResetWarm(1)
+ //
+ switch (ResetType) {
+case EfiResetWarm:
+ break;
+
+case EfiResetCold:
+ if (SiScheduleResetHob->ResetType == EfiResetWarm) {
+SiScheduleResetHob->ResetType = ResetType;
+ }
+ break;
+
+case EfiResetShutdown:
+ if (SiScheduleResetHob->ResetType < ResetType)
+ SiScheduleResetHob->ResetType = ResetType;
+ break;
+
+case EfiResetPlatformSpecific:
+ SiScheduleResetHob->ResetType = ResetType;
+ SiScheduleResetHob->ResetData = *ResetData;
+ break;
+ }
+ DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : New Reset Type = 0x%x\n",
SiScheduleResetHob->ResetType));
+}
+
+/**
+ This function returns TRUE or FALSE depending on whether a reset is required
based on SiScheduleResetHob
+
+ @retval BOOLEAN The function returns FALSE if no reset is required
+**/
+BOOLEAN
+SiScheduleResetIsRequired (
+ VOID
+ )
+{
+ VOI
[edk2-devel] [PATCH 32/40] TigerlakeSiliconPkg/Pch: Add Pch common library instances
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * Pch/Library/BasePchPciBdfLib * Pch/Library/BaseResetSystemLib * Pch/Library/DxePchPolicyLib * Pch/Library/PeiDxeSmmPchCycleDecodingLib * Pch/Library/PeiDxeSmmPchInfoLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf | 33 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLib.c | 1092 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c | 158 Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf | 38 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.c | 198 Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.inf | 43 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c | 587 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf | 42 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLib.c | 127 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h | 58 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibTgl.c | 715 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibTgl.inf | 43 +++ 12 files changed, 3134 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf new file mode 100644 index 00..4f4096a409 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf @@ -0,0 +1,33 @@ +## @file +# PCH PCIe Bus Device Function Library. +# +# All functions from this library are available in PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent
[edk2-devel] [PATCH 31/40] TigerlakeSiliconPkg/Library: Add package common library instances
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * Library/BasePciSegmentMultiSegLibPci * Library/BaseSiConfigBlockLib * Library/PeiDxeSmmMmPciLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf | 38 +++ Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni | 14 ++ Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/PciSegmentLib.c | 1280 +++ Silicon/Intel/TigerlakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.c | 86 Silicon/Intel/TigerlakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf | 33 +++ Silicon/Intel/TigerlakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c | 35 + Silicon/Intel/TigerlakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf | 43 ++ 7 files changed, 1529 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf new file mode 100644 index 00..b04bce9cf0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf @@ -0,0 +1,38 @@ +## @file +# Instance of PCI Segment Library based on PCI Library. +# +# PCI Segment Library that layers on top of the PCI Library which only +# supports segment 0 and segment 1 PCI configuration access. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION= 0x00010005 + BASE_NAME = BasePciSegmentMultiSegLibPci + MODULE_UNI_FILE= BasePciSegmentMultiSegLibPci.uni + FILE_GUID = AC65B409-DF03-466e-8D2B-6FCE1079F0B2 + MODULE_TYPE= BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciSegmentLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources] + PciSegmentLib.c + +[Packages] + MdePkg/MdePkg.dec + TigerlakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + BaseLib + PciLib + DebugLib + PcdLib diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni new file mode 100644 index 00..09bd0f5cfc --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni @@ -0,0 +1,14 @@ +/** @file + Instance of PCI Segment Library based on PCI Library. + + PCI Segment Library that layers on top of the PCI Library which only + supports segment 0 and segment 1 PCI configuration access. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +#string STR_MODULE_ABSTRACT #language en-US "Instance of PCI Segment Library based on PCI Library." + +#string STR_MODULE_DESCRIPTION #language en-US "PCI Segment Library that layers on top of the PCI Library which only supports segment 0 and segment 1 PCI configuration access." diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/PciSegmentLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/PciSegmentLib.c new file mode 100644 index 00..0d0c64be3f --- /dev/null +++ b/Silicon/Intel/Tigerla
[edk2-devel] [PATCH 30/40] TigerlakeSiliconPkg/IpBlock: Add Vtd component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/Vtd/IncludePrivate * IpBlock/Vtd/Library * IpBlock/Vtd/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdInitLib.h | 62 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdPolicyLib.h | 67 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/VtdDataHob.h | 32 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoLib/PeiDxeSmmVtdInfoLib.inf | 45 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoLib/VtdInfoLib.c | 86 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c | 684 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.inf | 71 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdPolicyLib/DxeVtdPolicyLib.c | 90 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdPolicyLib/DxeVtdPolicyLib.inf | 35 +++ 9 files changed, 1172 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdInitLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdInitLib.h new file mode 100644 index 00..e439cfbac2 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdInitLib.h @@ -0,0 +1,62 @@ +/** @file + Header file for DXE VTD Init Lib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _DXE_VTD_INIT_LIB_H_ +#define _DXE_VTD_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Locate the VT-d ACPI tables data file and read ACPI SSDT tables. + Publish the appropriate SSDT based on current configuration and capabilities. + + @param[in] SaPolicySA DXE Policy protocol + + @retval EFI_SUCCESS - Vtd initialization complete + @retval Other - No Vtd function initiated +**/ +EFI_STATUS +VtdInit ( + IN SA_POLICY_PROTOCOL*SaPolicy + ); + +/** + EndOfPcieEnum routine for update DMAR +**/ +VOID +UpdateDmarEndOfPcieEnum ( + VOID + ); +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdPolicyLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdPolicyLib.h new file mode 100644 index 00..d55cf6bc34 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeVtdPolicyLib.h @@ -0,0 +1,67 @@ +/** @file + Prototype of the DXE VTD Policy Init library. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _DXE_VTD_POLICY_INIT_LIB_H_ +#define _DXE_VTD_POLICY_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern EFI_GUID gVtdDxeConfigGuid; + +/** + This function Load default Vtd DXE policy. + + @param[in] ConfigBlockPointerThe pointer to add VTD config block +**/ +VOID +VtdLoadDefaultDxe ( + IN VOID*ConfigBlockPointer + ); + +/** + This function prints the DXE phase VTD policy. + + @param[in] SaPolicy - Instance of SA_POLICY_PROTOCOL +**/ +VOID +VtdPrintPolicyDxe ( + IN SA_POLICY_PROTOCOL
[edk2-devel] [PATCH 29/40] TigerlakeSiliconPkg/IpBlock: Add Spi component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/Spi/IncludePrivate * IpBlock/Spi/Library * IpBlock/Spi/LibraryPrivate * IpBlock/Spi/Smm Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiAccessPrivateLib.h | 40 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h | 364 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h | 136 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/Library/PeiDxeSmmSpiAccessLib/PeiDxeSmmSpiAccessLib.inf | 33 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/Library/PeiDxeSmmSpiAccessLib/SpiAccessLib.c | 477 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf | 31 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c | 1115 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/PeiDxeSmmSpiAccessPrivateLib/PeiDxeSmmSpiAccessPrivateLib.inf | 40 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/PeiDxeSmmSpiAccessPrivateLib/SpiAccessPrivateLib.c | 133 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c | 296 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf | 47 + 11 files changed, 2712 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiAccessPrivateLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiAccessPrivateLib.h new file mode 100644 index 00..6da88a9047 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiAccessPrivateLib.h @@ -0,0 +1,40 @@ +/** @file + SPI library header for abstraction of SPI HW registers accesses + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SPI_ACCESS_PRIVATE_LIB_H_ +#define _SPI_ACCESS_PRIVATE_LIB_H_ + +/** + Disable EISS (Enable InSMM.STS) +**/ +VOID +SpiDisableEiss ( + VOID + ); + +/** + Configure BiosLockEnable bit and BiosInterfaceLock bit according to policy setting. + + @param[in] BiosLockEnable Policy for BiosLockEnable bit programming + @param[in] BiosInterfaceLock Policy for BiosInterfaceLock bit programming + +**/ +VOID +SpiBiosLockEnableAndBiosInterfaceLockWithS3BootScript ( + IN BOOLEAN BiosLockEnable, + IN BOOLEAN
[edk2-devel] [PATCH 28/40] TigerlakeSiliconPkg/IpBlock: Add Smbus component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/Smbus/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Smbus/IncludePrivate/Register/SmbusRegs.h | 50 ++ 1 file changed, 50 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Smbus/IncludePrivate/Register/SmbusRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Smbus/IncludePrivate/Register/SmbusRegs.h new file mode 100644 index 00..c863615583 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Smbus/IncludePrivate/Register/SmbusRegs.h @@ -0,0 +1,50 @@ +/** @file + Register names for PCH Smbus Device. + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName + - Prefix: +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values within the bits +Definitions beginning with "S_" are register size +Definitions beginning with "N_" are the bit position + - [GenerationName]: +Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). +Register name without GenerationName applies to all generations. + - [ComponentName]: +This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) +Register name without ComponentName applies to all components. +Register that is specific to -LP denoted by "_PCH_LP_" in component name. + - SubsystemName: +This field indicates the subsystem name of the component that the register belongs to +(e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: +MEM - MMIO space register of subsystem. +IO - IO space register of subsystem. +PCR - Private configuration register of subsystem. +CFG - PCI configuration space register of subsystem. + - RegisterName: +Full register name. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_REGS_SMBUS_H_ +#define _PCH_REGS_SMBUS_H_ + +// +// SMBus Controller Registers +// +#define R_SMBUS_CFG_BASE 0x20 +#define B_SMBUS_CFG_BASE_BAR 0xFFE0 + +// +// SMBus I/O Registers +// +#define R_SMBUS_IO_HSTS 0x00 ///< Host Status Register R/W +#define B_SMBUS_IO_SMBALERT_STS 0x20 + +#endif -- 2.24.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70978): https://edk2.groups.io/g/devel/message/70978 Mute This Topic: https://groups.io/mt/80274142/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/SerialIo/IncludePrivate
* IpBlock/SerialIo/Library
* IpBlock/SerialIo/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h
| 377
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Register/SerialIoRegsVer2.h
| 108
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSerialIoAccessLib/PeiDxeSmmSerialIoAccessLib.inf
| 35 +++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSerialIoAccessLib/SerialIoAccessLib.c
| 266
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf
| 34 ++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLib.c
| 156
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibI2c.c
| 122
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibI2cVer2.c
| 70
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibInternal.h
| 20
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibSpi.c
| 122
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibSpiVer2.c
| 82
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibUart.c
| 136
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibUartVer2.c
| 82
++
13 files changed, 1610 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h
new file mode 100644
index 00..47057cd2ef
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h
@@ -0,0 +1,377 @@
+/** @file
+ Header file for Serial IO Private Lib implementation.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_PRIVATE_LIB_H_
+#define _SERIAL_IO_PRIVATE_LIB_H_
+
+#include
+#include
+
+/**
+ Serial Io Pci Device State structure.
+ Used to preserve current information about the device when it is configured
in Pci mode prior to Pch Initialization.
+**/
+typedef struct {
+ UINT64 PciCfgBar0; ///< Pci Config Space Base Address Register
+ UINT8 PciCfgCommand;///< Pci Config Space Command Register
+ UINT8 PciCfgPmeCtrlSts; ///< Pci Config Space Pme Control Status
+ UINT8 PprReset; ///< MMIO Proprietary Reset Register
+} SERIAL_IO_PCI_DEVICE_STATE;
+
+/**
+ Checks if higher functions are enabled.
+ Used for Function 0 Seri
[edk2-devel] [PATCH 23/40] TigerlakeSiliconPkg/IpBlock: Add PcieRp component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/PcieRp/IncludePrivate * IpBlock/PcieRp/Library * IpBlock/PcieRp/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/DxePchPcieRpPolicyLib.h | 55 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/PciExpressHelpersLib.h | 173 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/PcieRpLib.h | 109 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Register/PcieSipRegs.h | 45 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/BasePcieHelperLib/BasePcieHelperLib.c | 315 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/BasePcieHelperLib/BasePcieHelperLib.inf | 37 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLib.c | 69 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h | 20 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c | 128 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf | 39 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c | 179 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.inf | 30 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PciExpressHelpersLibrary/PciExpressHelpersLibrary.c | 1997 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PciExpressHelpersLibrary/PciExpressHelpersLibrary.h | 40 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PciExpressHelpersLibrary/PeiDxeSmmPciExpressHelpersLib.inf | 49 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c | 247 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.inf | 43 +++ 17 files changed, 3575 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/DxePchPcieRpPolicyLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/DxePchPcieRpPolicyLib.h new file mode 100644 index 00..1dea61388e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/IncludePrivate/Library/DxePchPcieRpPolicyLib.h @@ -0,0 +1,55 @@ +/** @file + DXE PcieRp policy library. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _DXE_PCH_PCIERP_POLICY_LIB_H_ +#define _DXE_PCH_PCIERP_POLICY_LIB_H_ + +#include + +/** + Load DXE Config block default for Pch PCIE RP + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadPchPcieRpDxeConfigDefault ( + IN VOID *ConfigBlockPointer
[edk2-devel] [PATCH 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Sata/Library
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
| 32
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
| 138
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLibVer2.c
| 83
+++
3 files changed, 253 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
new file mode 100644
index 00..1c304fed59
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
@@ -0,0 +1,32 @@
+## @file
+# PEI/DXE/SMM PCH SATA library Ver2
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchSataLibVer2
+FILE_GUID = 2519ADE8-D971-4551-8A8E-2EB55DFC555B
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SataLib
+
+[LibraryClasses]
+BaseLib
+PciSegmentLib
+PchInfoLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+TigerlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+SataLib.c
+SataLibVer2.c
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
new file mode 100644
index 00..49cba49910
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/SataLib.c
@@ -0,0 +1,138 @@
+/** @file
+ Pch SATA library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Get SATA controller address that can be passed to the PCI Segment Library
functions.
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller address in PCI Segment Library representation
+**/
+UINT64
+SataRegBase (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+
+ return SataPciCfgBase (SataCtrlIndex);
+}
+
+/**
+ Get SATA controller's Port Present Status
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval Port Present Status
+**/
+UINT8
+GetSataPortPresentStatus (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+
+ return PciSegmentRead8 (SataPciCfgBase (SataCtrlIndex) + R_SATA_CFG_PCS + 2);
+}
+
+/**
+ Get SATA controller Function Disable Status
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval 0 SATA Controller is not Function Disabled
+ @retval 1 SATA Controller is Function Disabled
+**/
+BOOLEAN
+SataControllerFunctionDisableStatus (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ UINT32 SataGc;
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+ SataGc = PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) +
R_SATA_CFG_SATAGC);
+ return !!(SataGc & BIT10);
+}
+
+/**
+ Get SATA controller ABAR size
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller ABAR size
+**/
+UINT32
+GetSataAbarSize (
+ IN UINT32 SataCtrlIndex
+ )
+{
+ UINT32 SataGc;
+ ASSERT (SataCtrlIndex < MaxSataControllerNum ());
+ SataGc = PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) +
R_SATA_CFG_SATAGC);
+
+ switch (SataGc & B_SATA_CFG_SATAGC_ASSEL) {
+case V_SATA_CFG_SATAGC_ASSEL_2K:
+ return SIZE_2KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_16K:
+ return SIZE_16KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_32K:
+ return SIZE_32KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_64K:
+ return SIZE_64KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_128K:
+ return SIZE_128KB;
+ break;
+
+case V_SATA_CFG_SATAGC_ASSEL_512K:
+ return SIZE_256KB;
+ break;
+
+default:
+ return SIZE_2KB;
+ break;
+ }
+}
+
+/**
+ Get SATA controller AHCI base address
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller AHCI base address
+**/
+UIN
[edk2-devel] [PATCH 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Psf/IncludePrivate
* IpBlock/Psf/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h
| 520
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PeiDxeSmmPsfLibVer2.inf
| 40
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLib.c
| 203
+++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibInternal.h
| 470
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibVer2.c
| 115
+++
5 files changed, 1348 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h
new file mode 100644
index 00..f333be48d2
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h
@@ -0,0 +1,520 @@
+/** @file
+ Header file for PchPsfPrivateLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PSF_PRIVATE_LIB_H_
+#define _PCH_PSF_PRIVATE_LIB_H_
+
+#include
+#include
+
+typedef struct {
+ UINT32 Id;
+ PCH_SBI_PID SbPid;
+} PSF_SEGMENT;
+
+/**
+ Get list of supported PSF segments.
+
+ @param[out] PsfTableArray of supported PSF segments
+ @param[out] PsfTableLength Length of PsfTable
+**/
+VOID
+PsfSegments (
+ OUT PSF_SEGMENT **PsfTable,
+ OUT UINT32 *PsfTableLength
+ );
+
+//
+// Structure for storing data on both PSF SideBand Port ID and
+// PSF port register offset for specific device
+//
+typedef struct {
+ PCH_SBI_PID PsfPid;
+ UINT16 RegBase;
+} PSF_PORT;
+
+/**
+ Disable device at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+**/
+VOID
+PsfDisableDevice (
+ IN PSF_PORT PsfPort
+ );
+
+/**
+ Enable device at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+**/
+VOID
+PsfEnableDevice (
+ IN PSF_PORT PsfPort
+ );
+
+/**
+ Hide PciCfgSpace of device at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+**/
+VOID
+PsfHideDevice (
+ IN PSF_PORT PsfPort
+ );
+
+/**
+ Unhide PciCfgSpace of device at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+**/
+VOID
+PsfUnhideDevice (
+ IN PSF_PORT PsfPort
+ );
+
+/**
+ Disable device BARs at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+ @param[in] BarDisMask BIT0-BAR0, BIT1-BAR1,...
+ Mask corresponds to 32bit wide BARs
+**/
+VOID
+PsfDisableDeviceBar (
+ IN PSF_PORT PsfPort,
+ IN UINT32BarDisMask
+ );
+
+/**
+ Enable device BARs at PSF level
+ Method not for bridges (e.g. PCIe Root Port)
+
+ @param[in] PsfPort PSF PORT data structure
+ @param[in] BarEnMask BIT0-BAR0, BIT1-BAR1,...
+ Mask corresponds to 32bit wide BARs
+**/
+VOID
+PsfEnableDeviceBar (
+ IN PSF_PORT PsfPort,
+ IN UINT32BarEnMask
+ );
+
+/**
+ Disable IDER device at PSF level
+**/
+VOID
+PsfDisableIderDevice (
+ VOID
+ );
+
+/**
+ Enable SOL device at PSF level
+**/
+VOID
+PsfEnableSolDevice (
+ VOID
+ );
+
+/**
+ Disable SOL device at PSF level
+**/
+VOID
[edk2-devel] [PATCH 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Pmc/IncludePrivate
* IpBlock/Pmc/Library
* IpBlock/Pmc/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
| 120
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Register/PmcRegsVer2.h
| 52
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
| 42 ++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
| 545
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
| 39 +++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf
| 40
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
| 166
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLibWithS3.c
| 122
++
8 files changed, 1126 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 00..0f2f251d57
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,120 @@
+/** @file
+ Header file for private PmcLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include
+#include "Register/PmcRegs.h"
+
+/**
+ This function checks if GbE device is supported (not disabled by fuse)
+
+ @retval GbE support state
+**/
+BOOLEAN
+PmcIsGbeSupported (
+ VOID
+ );
+
+/**
+ This function checks if LAN wake from DeepSx is enabled
+
+ @retval Lan Wake state
+**/
+BOOLEAN
+PmcIsLanDeepSxWakeEnabled (
+ VOID
+ );
+
+/**
+ This function sets SMI Lock with S3 Boot Script programming
+**/
+VOID
+PmcLockSmiWithS3BootScript (
+ VOID
+ );
+
+/**
+ This function sets eSPI SMI Lock
+ @attention This function must be called after eSPI SMI generation has been
enabled.
+This setting is required in all boot modes and before EndOfDxe.
+If set value will be restored upon S3 resume by bootscript.
+**/
+VOID
+PmcLockEspiSmiWithS3BootScript (
+ VOID
+ );
+
+/**
+ This function checks if eSPI SMI Lock is set
+
+ @retval eSPI SMI Lock state
+**/
+BOOLEAN
+PmcIsEspiSmiLockSet (
+ VOID
+ );
+
+typedef enum {
+ PmcSwSmiRate1p5ms = 0,
+ PmcSwSmiRate16ms,
+ PmcSwSmiRate32ms,
+ PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRateRefer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ );
+
+typedef enum {
+ PmcPeriodicSmiRate8s = 0,
+ PmcPeriodicSmiRate16s,
+ PmcPeriodicSmiRate32s,
+ PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRateRefer to PMC_PERIODIC_SMI_RATE for
possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATEPeriodicSmiRate
+ );
+
+/**
+ This function reads Power Button Level
+
+ @retval State of PWRBTN# signal (0: Low, 1: High)
+**/
+UINT8
+PmcGetPwrBtnLevel (
+ VOID
+ );
+
+/**
+ This function gets Group to GPE0 configuration
+
+ @param[out] GpeDw0Value GPIO Group to GPE_DW0 assignment
+ @param[out] GpeDw1Value GPIO Group to GPE_DW1 assignment
[edk2-devel] [PATCH 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/PchDmi/IncludePrivate * IpBlock/PchDmi/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h | 175 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c | 50 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h | 34 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c | 269 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiWithS3Lib.c | 73 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf | 42 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf | 41 + 7 files changed, 684 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h new file mode 100644 index 00..77db69c75a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h @@ -0,0 +1,175 @@ +/** @file + Header file for PchDmiLib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_DMI_LIB_H_ +#define _PCH_DMI_LIB_H_ + +/** + This function checks if DMI Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmiLocked ( + VOID + ); + +/** + Get PCH TCO base address. + + @retval Address Address of TCO base address. +**/ +UINT16 +PchDmiGetTcoBase ( + VOID + ); + +/** + Set PCH LPC/eSPI generic IO range decoding in DMI + + @param[in] AddressAddress for generic IO range base address. + @param[in] Length Length of generic IO range. + @param[in] RangeIndex Index of choosen range + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcGenIoRange ( + IN UINT32Address, + IN UINT32Length, + IN UINT32RangeIndex + ); + +/** + Set PCH eSPI eSPI CS1# generic IO range decoding in DMI + + @param[in] AddressAddress for generic IO range base address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetEspiCs1GenIoRange ( + IN UINT32Address, + IN UINT32Length + ); + +/** + Set PCH LPC/eSPI memory range decoding in DMI + + @param[in] AddressAddress for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcMemRange ( + IN UINT32Address + ); + +/** + Set PCH eSPI CS1# memory range decoding in DMI + + @param[in] AddressAddress for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetEspiCs1MemRange ( + IN UINT32Address + ); + +/** + Check if Boot BIOS Strap is set for SPI. + + @retval TRUEBoot BIOS Strap set for SPI + @retval FALSE Boot BIOS Strap set for LPC/eSPI +**/ +BOOLEAN +PchDmiIsBootBiosStrapSetForSpi ( + VOID + ); + +/** + Set PCH BIOS range decoding in DMI + Please check EDS for detail of BiosDecodeEnable bit definition. +bit 15: F8-FF Enable +bit 14: F0-F8 Enable +bit 13: E8-EF Enable +bit 12: E0-E8 Enable +bit 11: D8-DF Enable +bit 10: D0-D7 Enable +bit 9: C8-CF
[edk2-devel] [PATCH 20/40] TigerlakeSiliconPkg/IpBlock: Add HostBridge component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/HostBridge/IncludePrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
| 25 +
1 file changed, 25 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
new file mode 100644
index 00..41e92da4df
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
@@ -0,0 +1,25 @@
+/** @file
+ The GUID definition for Host Bridge Data Hob
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _HOST_BRIDGE_DATA_HOB_H_
+#define _HOST_BRIDGE_DATA_HOB_H_
+
+#include
+
+extern EFI_GUID gHostBridgeDataHobGuid;
+#pragma pack (push,1)
+
+///
+/// Host Bridge Data Hob
+///
+typedef struct {
+ EFI_HOB_GUID_TYPEEfiHobGuidType; ///< GUID Hob
type structure for gSaDataHobGuid
+ UINT8EnableAbove4GBMmio; ///<
0=Disable above 4GB MMIO resource support, 1=Enable above 4GB MMIO resource
support
+ BOOLEAN SkipPamLock; ///< 0=All
PAM registers will be locked in System Agent code, 1=Do not lock PAM registers
in System Agent code.
+ UINT8Rsvd1[2]; ///< Reserved
for future use
+} HOST_BRIDGE_DATA_HOB;
+#pragma pack (pop)
+#endif
--
2.24.0.windows.2
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[edk2-devel] [PATCH 21/40] TigerlakeSiliconPkg/IpBlock: Add P2sb component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/P2sb/IncludePrivate
* IpBlock/P2sb/Library
* IpBlock/P2sb/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
| 112
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
| 65
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuRegbarAccessLib/CpuRegbarAccessLib.c
| 494
++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuRegbarAccessLib/PeiDxeSmmCpuRegbarAccessLib.inf
| 35 +++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
| 313
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
| 35 +++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
| 253
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
| 36
8 files changed, 1343 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
new file mode 100644
index 00..3fab933bbd
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
@@ -0,0 +1,112 @@
+/** @file
+ Header file for PchSbiAccessLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SBI_ACCESS_LIB_H_
+#define _PCH_SBI_ACCESS_LIB_H_
+
+#include
+
+/**
+ PCH SBI opcode definitions
+**/
+typedef enum {
+ MemoryRead = 0x0,
+ MemoryWrite= 0x1,
+ PciConfigRead = 0x4,
+ PciConfigWrite = 0x5,
+ PrivateControlRead = 0x6,
+ PrivateControlWrite= 0x7,
+ GpioLockUnlock = 0x13
+} PCH_SBI_OPCODE;
+
+/**
+ PCH SBI response status definitions
+**/
+typedef enum {
+ SBI_SUCCESSFUL = 0,
+ SBI_UNSUCCESSFUL= 1,
+ SBI_POWERDOWN = 2,
+ SBI_MIXED = 3,
+ SBI_INVALID_RESPONSE
+} PCH_SBI_RESPONSE;
+
+/**
+ Execute PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in
both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If
more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after
done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be
checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would
provide additional information
+ when needed.
+
+ @param[in] PidPort ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in, out] Data32Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully complete
[edk2-devel] [PATCH 19/40] TigerlakeSiliconPkg/IpBlock: Add Hda component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/Hda/IncludePrivate * IpBlock/Hda/Library * IpBlock/Hda/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Library/DxeHdaPolicyLib.h | 55 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Register/HdaRegs.h | 46 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/Library/DxeHdaNhltLib/DxeHdaNhltLib.c | 383 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/Library/DxeHdaNhltLib/DxeHdaNhltLib.inf | 31 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/LibraryPrivate/DxeHdaPolicyLib/DxeHdaPolicyLib.c | 92 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/LibraryPrivate/DxeHdaPolicyLib/DxeHdaPolicyLib.inf | 31 +++ 6 files changed, 638 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Library/DxeHdaPolicyLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Library/DxeHdaPolicyLib.h new file mode 100644 index 00..9c42bf5611 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Library/DxeHdaPolicyLib.h @@ -0,0 +1,55 @@ +/** @file + DXE Hda policy library. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _DXE_HDA_POLICY_LIB_H_ +#define _DXE_HDA_POLICY_LIB_H_ + +#include + +/** + Print HDAUDIO_DXE_CONFIG and serial out. + + @param[in] PchPolicyPointer to a PCH_POLICY_PROTOCOL +**/ +VOID +HdaDxePrintConfig ( + IN PCH_POLICY_PROTOCOL*PchPolicy + ); + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +HdaDxeLoadConfigDefault ( + IN VOID *ConfigBlockPointer + ); + +/** + Get Hda config block table size. + + @retval Size of config block +**/ +UINT16 +HdaDxeGetConfigBlockTotalSize ( + VOID + ); + +/** + Add Hda ConfigBlock. + + @param[in] ConfigBlockTableAddressThe pointer to config block table + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +HdaDxeAddConfigBlock ( + IN VOID *ConfigBlockTableAddress + ); + +#endif // _DXE_HDA_POLICY_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Register/HdaRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Register/HdaRegs.h new file mode 100644 index 00..b165e7bb22 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Hda/IncludePrivate/Register/HdaRegs.h @@ -0,0 +1,46 @@ +/** @file + Register names for High Definition Audio device. + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName + - Prefix: +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values within the bits +Definitions beginning with "S_" are register size +Definitions beginning with "N_" are the bit position + - [GenerationName]: +Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). +Register name without GenerationName applies to all generations. + - [ComponentName]: +This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) +Register name without ComponentName applies to all components. +Register that is specific to -LP denoted by "_PCH_LP_" in component name. + - SubsystemName: +This field indicates the subsystem name of the component that the register belongs to +(e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: +MEM - MMIO space register of subsystem. +IO - IO space register of subsystem. +PCR - Private configuration register of subsystem. +CFG - PCI configuration space register of subsystem. + - RegisterName: +Full register name. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _HDA_REGS_
[edk2-devel] [PATCH 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/Gbe/IncludePrivate * IpBlock/Gbe/Library * IpBlock/Gbe/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h | 324 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Register/GbeRegs.h | 68 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/GbeLib.c | 121 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/PeiDxeSmmGbeLib.inf | 43 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGbeMdiLib/GbeMdiLib.c | 388 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGbeMdiLib/PeiDxeSmmGbeMdiLib.inf | 34 ++ 6 files changed, 978 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h new file mode 100644 index 00..b8274ed3dc --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h @@ -0,0 +1,324 @@ +/** @file + Header file for GbeMdiLib. + + Conventions: + + - Prefixes: +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values within the bits +Definitions beginning with "S_" are register sizes +Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by +"_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. +Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. +e.g., "_PCH_LP_" +Registers / bits names without or _LP_ apply for LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" +at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named +as "_PCH_" without [generation_name] inserted. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GBE_MDI_LIB_H_ +#define _GBE_MDI_LIB_H_ + +// +// Maximum loop time for GbE status check +// 4000 * 50 = 200 mSec in total +// +#define GBE_MAX_LOOP_TIME 4000 +#define GBE_ACQUIRE_MDIO_DELAY 50 +#define GBE_MDI_SET_PAGE_DELAY 4000 // 4 mSec delay after setting page + +// +// LAN PHY MDI settings +// +// MDI Control Register Bits +// 31:30 Reserved +// This field is reserved and returns 0. +// 29Interrupt Enable. +// When this bit is set to 1 by software, it causes the device to assert +// an interrupt indicating the end of an MDI cycle. +// 28Ready. +// Set to 1 by the device at the end of MDI transaction (i.e., indicates a Read or +// Write has been completed. It should be reset to 0 by software at the same time the +// command is written. +// 27:26 Opcode +// For an MDI write, the opcode equals 01b, and for MDI read, 10b. 00b and +// 11b are reserved and should not be used. +// 25:21 PHYAdd +// PHY Address +// 20:16 RegAdd +// PHY Register Address +// 15:0 Data + +#define B_PHY_MDI_READYBIT28 +#define B_PHY_MDI_READ BIT27 +#define B_PHY_MDI_WRITEBIT26 +// +// PHY SPECIFIC registers +// +#define B_PHY_MDI_PHY_ADDRESS_02 BIT22 +// +// PHY GENERAL registers +// Regi
[edk2-devel] [PATCH 15/40] TigerlakeSiliconPkg/IpBlock: Add Espi component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Espi/Library
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
| 469
+
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
| 38 ++
2 files changed, 507 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
new file mode 100644
index 00..2d1928ce18
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
@@ -0,0 +1,469 @@
+/** @file
+ This file contains routines for eSPI
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CHANNEL_RESET_TIMEOUT 100 ///< Channel reset timeout in us after
which to report error
+#define SLAVE_CHANNELS_MAX7 ///< Max number of channels
+
+//
+// eSPI Slave registers
+//
+#define R_ESPI_SLAVE_GENCAP 0x08 ///< General Capabilities
and Configurations
+#define B_ESPI_SLAVE_GENCAP_SUPPCHAN 0xFF ///< Channels supported
bit mask
+#define R_ESPI_SLAVE_CHACAP_BASE 0x10 ///< Base address from
which channel Cap and Conf registers start on slave
+#define S_ESPI_SLAVE_CHACAP_OFFSET0x10 ///< Offset for each
channel from base
+#define B_ESPI_SLAVE_CHACAP_CHEN BIT0 ///< Slave Channel enable
bit
+#define B_ESPI_SLAVE_CHACAP_CHRDY BIT1 ///< Slave Channel ready
bit
+
+/**
+ Checks if second slave capability is enabled
+
+ @retval TRUE There's second slave
+ @retval FALSE There's no second slave
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+/**
+ Checks in slave General Capabilities register if it supports channel with
requested number
+
+ @param[in] SlaveId Id of slave to check
+ @param[in] ChannelNumber Number of channel of which to check
+
+ @retval TRUE Channel with requested number is supported by slave device
+ @retval FALSE Channel with requested number is not supported by slave
device
+**/
+BOOLEAN
+IsEspiSlaveChannelSupported (
+ UINT8 SlaveId,
+ UINT8 ChannelNumber
+ )
+{
+ UINT32 Data32;
+ UINT8 SupportedChannels;
+
+ PchEspiSlaveGetConfig (SlaveId, R_ESPI_SLAVE_GENCAP, );
+ SupportedChannels = (UINT8) (Data32 & B_ESPI_SLAVE_GENCAP_SUPPCHAN);
+
+ DEBUG ((DEBUG_INFO, "Slave %d supported channels 0x%4X\n", SlaveId,
SupportedChannels));
+
+ if (ChannelNumber > SLAVE_CHANNELS_MAX || !(SupportedChannels & (BIT0 <<
ChannelNumber))) {
+// Incorrect channel number was specified. Either exceeded max or Slave
doesn't support that channel.
+return FALSE;
+ }
+
+ return TRUE;
+}
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ )
+{
+ return (PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_CFG_VAL) &
B_ESPI_PCR_CFG_VAL_ESPI_EN) != 0;
+}
+
+/**
+ eSPI helper function to clear slave configuration register status
+
+ @retval EFI_SUCCESS Write to private config space succeed
+ @retval others Read / Write failed
+**/
+STATIC
+VOID
+EspiClearScrs (
+ VOID
+ )
+{
+ PchPcrAndThenOr32 (
+PID_ESPISPI,
+R_ESPI_PCR_SLV_CFG_REG_CTL,
+(UINT32) ~0,
+ B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS
+ );
+}
+
+/**
+ eSPI helper function to poll slave configuration register enable for 0
+ and to check for slave configuration register status
+
+ @retval EFI_SUCCESS Enable bit is zero and no error in status bits
+ @retval EFI_DEVICE_ERROR Error in SCRS
+ @retval othersRead / Write to private config space failed
+**/
+STATIC
+EFI_STATUS
+EspiPollScreAndCheckScrs (
+ VOID
+ )
+{
+ UINT32 ScrStat;
+
+ do {
+ScrStat = PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_SLV_CFG_REG_CTL);
+ } while ((ScrStat & B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE) != 0);
+
+ ScrStat = (ScrStat & B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS) >>
N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS;
[edk2-devel] [PATCH 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following files: * IpBlock/CpuPcieRp/Include * IpBlock/CpuPcieRp/IncludePrivate * IpBlock/CpuPcieRp/Library * IpBlock/CpuPcieRp/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h | 31 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h | 353 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieRpLib.h | 47 +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Library/DxeCpuPcieRpLib.h | 18 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/CpuPcieInitCommon.c | 445 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf | 33 + Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/CpuPcieRpLib.c | 48 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf | 32 Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.c | 62 ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf | 40 10 files changed, 1109 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h new file mode 100644 index 00..15eeab0ecf --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h @@ -0,0 +1,31 @@ +/** @file + This file contains definitions of PCIe controller information + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_PCIE_INFO_H_ +#define _CPU_PCIE_INFO_H_ + +#define PCIE_HWEQ_COEFFS_MAX5 + +// +// Device 1 Memory Mapped IO Register Offset Equates +// +#define SA_PEG_DEV_NUM 0x01 +#define SA_PEG0_DEV_NUMSA_PEG_DEV_NUM +#define SA_PEG3_DEV_NUM0x06 + +// +// SA PCI Express* Port configuration +// + +#define CPU_PCIE_MAX_ROOT_PORTS4 + +#define SA_PEG_MAX_FUN 0x04 +#define SA_PEG_MAX_LANE 0x14 +#define SA_PEG_MAX_FUN_GEN3 0x03 +#define SA_PEG_MAX_LANE_GEN3 0x10 +#define SA_PEG_MAX_BUNDLE_GEN3 0x08 + +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h new file mode 100644 index 00..79b255c273 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h @@ -0,0 +1,353 @@ +/** @file +Header file for CpuPcieInitCommonLib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_PCIE_INIT_COMMON_H_ +#define _CPU_PCIE_INIT_COMMON_H_ + +#include + +/** + Print registers value + + @param[in] PrintMmioBase Mmio base address + @param[in] PrintSize Number of registers + @param[in] OffsetFromBase Offset from mmio base address + + @retval None +**/ +VOID +SaPrintRegisters ( + IN UINTNPrintMmioBase, + IN UINT32 PrintSize, + IN UINT32 OffsetFromBase + ); + +/** + Print registers value + + @param[in] PrintPciSegmentBase Pci segment base address + @param[in] PrintSize Number of registers
[edk2-devel] [PATCH 13/40] TigerlakeSiliconPkg/IpBlock: Add Cnvi component
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/Cnvi/IncludePrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Cnvi/IncludePrivate/CnviConfigHob.h
| 27 +++
1 file changed, 27 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Cnvi/IncludePrivate/CnviConfigHob.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Cnvi/IncludePrivate/CnviConfigHob.h
new file mode 100644
index 00..e881e49d62
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Cnvi/IncludePrivate/CnviConfigHob.h
@@ -0,0 +1,27 @@
+/** @file
+ This file defines the CNVi CONFIG HOB
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CNVI_CONFIG_HOB_H_
+#define _CNVI_CONFIG_HOB_H_
+
+#include
+
+extern EFI_GUID gCnviConfigHobGuid;
+#pragma pack (push,1)
+
+/**
+ This HOB is used to pass CNVi related private information to DXE phase
+**/
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID HOB type structure for
gCnviConfigHobGuid
+ UINT32 Mode : 1; ///< 0: Disabled, 1: Auto
+ UINT32 BtCore : 1; ///< 0: Disabled, 1: Enabled
+ UINT32 BtAudioOffload : 1; ///< 0: Disabled, 1: Enabled
+ UINT32 RsvdBits0 : 29; ///< Reserved bits
+} CNVI_CONFIG_HOB;
+#pragma pack (pop)
+
+#endif // _CNVI_CONFIG_HOB_H_
--
2.24.0.windows.2
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[edk2-devel] [PATCH 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Fru/TglPch/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h | 66 ++ 1 file changed, 66 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h new file mode 100644 index 00..4987d21f09 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h @@ -0,0 +1,66 @@ +/** @file + Register names for PCH private chipset register + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName + - Prefix: +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values within the bits +Definitions beginning with "S_" are register size +Definitions beginning with "N_" are the bit position + - [GenerationName]: +Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). +Register name without GenerationName applies to all generations. + - [ComponentName]: +This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) +Register name without ComponentName applies to all components. +Register that is specific to -LP denoted by "_PCH_LP_" in component name. + - SubsystemName: +This field indicates the subsystem name of the component that the register belongs to +(e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: +MEM - MMIO space register of subsystem. +IO - IO space register of subsystem. +PCR - Private configuration register of subsystem. +CFG - PCI configuration space register of subsystem. + - RegisterName: +Full register name. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_REGS_PCR_H_ +#define _PCH_REGS_PCR_H_ + +/** + Definition for SBI PID + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well. +**/ +#define PID_CNVI 0x73 +#define PID_ICLK 0xAD +#define PID_DMI0x88 +#define PID_PSTH 0x89 +#define PID_ESPISPI0x72 +#define PID_SPF0x85 +#define PID_SPE0x84 +#define PID_SPD0x83 +#define PID_SPC0x82 +#define PID_SPB0x81 +#define PID_SPA0x80 +#define PID_PSF6 0x7F +#define PID_PSF4 0xBD +#define PID_PSF3 0xBC +#define PID_PSF2 0xBB +#define PID_PSF1 0xBA +#define PID_GPIOCOM0 0x6E +#define PID_GPIOCOM1 0x6D +#define PID_GPIOCOM2 0x6C +#define PID_GPIOCOM3 0x6B +#define PID_GPIOCOM4 0x6A +#define PID_GPIOCOM5 0x69 +#define PID_CSME_PSF 0x8F + +#endif -- 2.24.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70962): https://edk2.groups.io/g/devel/message/70962 Mute This Topic: https://groups.io/mt/80274123/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Fru/TglPch/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h | 326 ++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.h| 16 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResources.h | 55 +++ 3 files changed, 397 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h new file mode 100644 index 00..0d00f25d5e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h @@ -0,0 +1,326 @@ +/** @file + Header file for TigerLake PCH devices PCI Bus Device Function map. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_BDF_ASSIGNMENT_H_ +#define _PCH_BDF_ASSIGNMENT_H_ + +#define NOT_PRESENT 0xFF + +#define MAX_SATA_CONTROLLER 1 + +// +// PCH PCIe Controllers +// +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 NOT_PRESENT + +// +// USB3 (XHCI) Controller PCI config +// +#define PCI_DEVICE_NUMBER_PCH_XHCI20 +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 + +// +// xDCI (OTG) USB Device Controller +// +#define PCI_DEVICE_NUMBER_PCH_XDCI20 +#define PCI_FUNCTION_NUMBER_PCH_XDCI 1 + +// +// Thermal Device +// +#define PCI_DEVICE_NUMBER_PCH_THERMAL NOT_PRESENT +#define PCI_FUNCTION_NUMBER_PCH_THERMAL NOT_PRESENT + +// +// CSME HECI #1 +// +#define PCI_DEVICE_NUMBER_PCH_HECI1 22 +#define PCI_FUNCTION_NUMBER_PCH_HECI1 0 + +// +// CSME HECI #2 +// +#define PCI_DEVICE_NUMBER_PCH_HECI2 22 +#define PCI_FUNCTION_NUMBER_PCH_HECI2 1 + +// +// CSME IDE-Redirection (IDE-R) +// +#define PCI_DEVICE_NUMBER_PCH_IDER22 +#define PCI_FUNCTION_NUMBER_PCH_IDER 2 + +// +// CSME Keyboard and Text (KT) Redirection +// +#define PCI_DEVICE_NUMBER_PCH_KTR 22 +#define PCI_FUNCTION_NUMBER_PCH_KTR 3 + +// +// CSME HECI #3 +// +#define PCI_DEVICE_NUMBER_PCH_HECI3 22 +#define PCI_FUNCTION_NUMBER_PCH_HECI3 4 + +// +// CSME HECI #4 +// +#define PCI_DEVICE_NUMBER_PCH_HECI4 22 +#define PCI_FUNCTION_NUMBER_PCH_HECI4 5 + +// +// CSME MROM +// +#define PCI_DEVICE_NUMBER_PCH_MROMNOT_PRESENT +#define PCI_FUNCTION_NUMBER_PCH_MROM NOT_PRESENT + +// +// CSME WLAN +// +#define PCI_DEVICE_NUMBER_PCH_WLAN22 +#define PCI_FUNCTION_NUMBER_PCH_WLAN 7 + +// +// SATA
[edk2-devel] [PATCH 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Fru/TglCpu/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFruLib.h | 18 ++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPcieRegs.h | 24 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs.h | 42 ++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuRegs.h | 31 +++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/VtdRegs.h | 22 ++ 5 files changed, 137 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFruLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFruLib.h new file mode 100644 index 00..a46b29cbbe --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFruLib.h @@ -0,0 +1,18 @@ +/** @file + Vtd Initialization Fru Library header file + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _VTD_INIT_FRU_LIB_H_ +#define _VTD_INIT_FRU_LIB_H_ + +/// +/// TCSS DMA controller RMRR buffer 4MB for each DMA controller +/// +#define RMRR_TCSS_DMA_SIZE 0x40 + +extern UINT16 mDevEnMap[][2]; +extern UINTN mDevEnMapSize; + +#endif // _VTD_INIT_FRU_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPcieRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPcieRegs.h new file mode 100644 index 00..a571381202 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPcieRegs.h @@ -0,0 +1,24 @@ +/** @file + This file contains definitions of PCIe Configuration + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PCIE_REGS_H_ +#define _CPU_PCIE_REGS_H_ + +#define R_PCIE_LCAP 0x4C +#define R_PCIE_LCTL 0x50 +#define R_PCIE_LSTS 0x52 +#define R_PCIE_SLCAP 0x54 +#define R_PCIE_SLSTS 0x5A +#define R_PCIE_LCTL2 0x70 +#define R_PCIE_MPC 0xD8 +#define B_PCIE_MPC_HPME BIT1 +#define R_PCIE_PGTHRES 0x5C0 +#define B_PCIE_PGTHRES_L1PGLTREN BIT0 +#define R_PCIE_LCTL3 0xA34 +#define B_PCIE_LCTL3_PE BIT0 + +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs.h new file mode 100644 index 00..f0b30107f4 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs.h @@ -0,0 +1,42 @@ +/** @file + Register names for IGD block + Conventions: + - Prefixes: +- Definitions beginning with "R_" are registers +- Definitions beginning with "B_" are bits within registers +- Definitions beginning with "V_" are meaningful values of bits within the registers +- Definitions beginning with "S_" are register sizes +- Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted by +"_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" +at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be just named +as "_SA_" without [generation_name] inserted. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _IGD_REGS_H_ +#define _IGD_REGS_H_ + +/// +/// Device 2 Register Equates +/// +// +// The following equates must be reviewed and revised when the specification is ready. +// +#define IGD_BUS_NUM 0x00 +#define IGD_DEV_NUM 0x02 +#define IGD_FUN_NUM 0x00 + +/// +/// GTTMMADR aligned to 16MB (Base address = [38:24]) +/// +#define R_SA_IGD_GTTMMADR 0x10 + +#define R_SA_IGD_SWSCI_OFFSET 0x00E8 +#define R_SA_IGD_ASLS_OFFSET 0x00FC ///< ASL Storage + +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuRegs.h b/Silicon/Intel/TigerlakeSi
[edk2-devel] [PATCH 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Fru/TglCpu/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruLib.h | 57 + Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBridge.h | 145 + Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h | 12 3 files changed, 214 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruLib.h new file mode 100644 index 00..89cf952717 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruLib.h @@ -0,0 +1,57 @@ +/** @file + Header file for CpuPcieInfoFruLib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_PCIE_INFO_FRU_LIB_H_ +#define _CPU_PCIE_INFO_FRU_LIB_H_ + +#include + +#define CPU_PCIE_MAX_ROOT_PORTS 4 + +#define CPU_PCIE_ULT_ULX_MAX_ROOT_PORT 1 + +#include + +/** + Get CPU Maximum Pcie Root Port Number + + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number +**/ +UINT8 +GetMaxCpuPciePortNum ( + VOID + ); + +/** + Get CPU Pcie Root Port Device and Function Number by Root Port physical Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device number. + @param[out] RpFun Return corresponding root port function number. + + @retval EFI_SUCCESS Root port device and function is retrieved + @retval EFI_INVALID_PARAMETER RpNumber is invalid +**/ +EFI_STATUS +EFIAPI +GetCpuPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ); + +/** + Gets pci segment base address of PCIe root port. + + @param RpIndexRoot Port Index (0 based) + @return PCIe port base address. +**/ +UINT64 +CpuPcieBase ( + IN UINT32 RpIndex + ); + +#endif // _CPU_PCIE_INFO_FRU_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBridge.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBridge.h new file mode 100644 index 00..32e38fa072 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBridge.h @@ -0,0 +1,145 @@ +/** @file + Register names for Host Bridge block + Conventions: + - Prefixes: +- Definitions beginning with "R_" are registers +- Definitions beginning with "B_" are bits within registers +- Definitions beginning with "V_" are meaningful values of bits within the registers +- Definitions beginning with "S_" are register sizes +- Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted by +"_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" +at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be just named +as "_SA_" without [generation_name] inserted. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SA_REGS_HOST_BRIDGE_H_ +#define _SA_REGS_HOST_BRIDGE_H_ + +#define SA_SEG_NUM 0x00 +#define V_SA_DEVICE_ID_INVALID 0x +// +// DEVICE 0 (Memory Controller Hub) +// +#define SA_MC_BUS 0x00 +#define SA_MC_DEV 0x00 +#define SA_MC_FUN 0x00 +#define V_SA_MC_VID0x8086 +#define R_SA_MC_DEVICE_ID 0x02 +#define R_SA_MC_CAPID0_B 0xE8 + +// +// SA DMI configuration +// + +// +// Maximum DMI lanes and bundles supported (x8 and 4 lanes) +// +#define SA_DMI_MAX_LANE 0x08 +#define SA_DMI_MAX_BUNDLE0x04 +#define SA_DMI_MAX_LANE_VER1 0x04 +#define SA_DMI_MAX_BUNDLE_VER1 0x02 + + +// +// TigerLake Mobile SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_MB_ULT_1 0x9A14 ///< TigerLake Ult (TGL-U 4+2) +#define V_SA_DEVICE_ID_MB_ULT_2 0x9A04 ///< TigerLake Ult (TGL-U 2+2) + +#define V_SA_DEVICE_ID_MB_ULX_1 0x9A12 ///< TigerLake Ulx (TGL-Y 4+2) +#define V_SA_DEVICE_ID_MB_ULX_2 0x9A02 ///< TigerLake Ulx (TGL-Y 2+2) + +/** + Description: + - This is the base addres
[edk2-devel] [PATCH 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivate headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following header files:
* SystemAgent/IncludePrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h
| 42 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
| 30 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h
| 50 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvsAreaDef.h
| 222
++
4 files changed, 344 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h
new file mode 100644
index 00..2e86d497f9
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h
@@ -0,0 +1,42 @@
+/** @file
+ This file defines the SA Iotrap SMI Protocol to provide the
+ I/O address for registered Iotrap SMI.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SA_IOTRAP_SMI_PROTOCOL_H_
+#define _SA_IOTRAP_SMI_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gSaIotrapSmiProtocolGuid;
+
+#define SA_IOTRAP_SMI_PROTOCOL_REVISION_1 1
+
+//
+// SA IO Trap SMI Protocol definition (Private protocol for RC internal use
only)
+//
+typedef struct {
+/*
+ Protocol revision number
+ Any backwards compatible changes to this protocol will result in an update in
the revision number
+ Major changes will require publication of a new protocol
+
+ Revision 1:
+- First version
+*/
+ UINT8 Revision;
+ UINT16 SaIotrapSmiAddress;
+} SA_IOTRAP_SMI_PROTOCOL;
+
+///
+/// Pcie Trap valid types
+///
+typedef enum {
+ CpuPciePmTrap,
+ CpuPcieTrapTypeMaximum
+} CPU_PCIE_TRAP_TYPE;
+
+#endif
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
new file mode 100644
index 00..785a808cf4
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
@@ -0,0 +1,30 @@
+/** @file
+ Definition of the System Agent global NVS area protocol.
+ This protocol publishes the address and format of a global ACPI NVS buffer
+ used as a communications buffer between SMM/DXE/PEI code and ASL code.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SYSTEM_AGENT_NVS_AREA_H_
+#define _SYSTEM_AGENT_NVS_AREA_H_
+
+//
+// SA NVS Area definition
+//
+#include
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gSaNvsAreaProtocolGuid;
+
+///
+/// System Agent Global NVS Area Protocol
+///
+typedef struct {
+ SYSTEM_AGENT_NVS_AREA *Area;///< System Agent Global NVS Area
Structure
+} SYSTEM_AGENT_NVS_AREA_PROTOCOL;
+
+#endif // _SYSTEM_AGENT_NVS_AREA_H_
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h
new file mode 100644
index 00..65622069e6
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h
@@ -0,0 +1,50 @@
+/** @file
+ The GUID definition for SaConfigHob
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SA_CONFIG_HOB_H_
+#define _SA_CONFIG_HOB_H_
+
+#include
+#include
+#include "CpuPcieInfo.h"
+#include
+
+extern EFI_GUID gSaConfigHobGuid;
+#define SA_VTD_ENGINE_NUMBER3
+
+#pragma pack (push,1)
+///
+/// DPR Directory Types
+///
+typedef enum {
+ EnumDprDirectoryTxt = 0,
+} DPR_DIRECTORY_ELEMENT;
+
+#define DPR_DIRECTORY_TYPE_TXT 0x01 ///< DPR directory type - TXT
+#define DPR_DIRECTORY_TYPE_BIOSGUARD0x02 ///< DPR directory type -
BIOS Guard
+#define DPR_DIRECTORY_MAX 1 ///< DPR Maximum Size
+
+///
+/// DPR directory entry definition
+///
+typedef struct {
+ UINT8 Type; ///< DPR Directory Type
+ UINT8 Size; ///< DPR Size in MB
+ UINT32 PhysBase; ///< Must be 4K aligned (bits 11..0 must be clear)
+ UINT16 Reserved; ///< Must be 0
+} DPR_DIRECTORY_ENTRY;
+
+///
+/// System Agent Config Hob
+///
+typedef struct {
+ EFI_HOB_GUID_TYPEEfiHobGuidType;
[edk2-devel] [PATCH 06/40] TigerlakeSiliconPkg/Pch: Add IncludePrivate headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Pch/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h | 47 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h | 26 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h | 269 + Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchHybridStorageHob.h | 21 + Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchNvsAreaDef.h | 319 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchRstHob.h | 58 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PchNvsArea.h | 30 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PcieIoTrap.h | 35 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/SiScheduleResetHob.h | 21 + 9 files changed, 826 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h new file mode 100644 index 00..2ad80a0269 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h @@ -0,0 +1,47 @@ +/** @file + Reset scheduling library services + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_SCHEDULE_RESET_LIB_H_ +#define _SI_SCHEDULE_RESET_LIB_H_ + +#include +#include + +/** + This function updates the reset information in SiScheduleResetHob + @param[in] ResetTypeUEFI defined reset type. + @param[in] ResetDataOptional element used to introduce a platform specific reset. + The exact type of the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. +**/ +VOID +SiScheduleResetSetType ( + IN EFI_RESET_TYPE ResetType, + IN PCH_RESET_DATA *ResetData OPTIONAL + ); + +/** + This function returns TRUE or FALSE depending on whether a reset is required based on SiScheduleResetHob + + @retval BOOLEAN The function returns FALSE if no reset is required +**/ +BOOLEAN +SiScheduleResetIsRequired ( + VOID + ); + +/** + This function performs reset based on SiScheduleResetHob + + @retval BOOLEAN The function returns FALSE if no reset is required +**/ +BOOLEAN +SiScheduleResetPerformReset ( + VOID + ); + +#endif //_SI_SCHEDULE_RESET_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h new file mode 100644 index 00..955dac5a82 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h @@ -0,0 +1,26 @@ +/** @file + Header file for private PCH SMM Lib. + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SMM_PCH_PRIVATE_LIB_H_ +#define _SMM_PCH_PRIVATE_LIB_H_ + +/** + Set InSmm.Sts bit +**/ +VOID +PchSetInSmmSts ( + VOID + ); + +/** + Clear InSmm.Sts bit +**/ +VOID +PchClearInSmmSts ( + VOID + ); + +#endif // _SMM_PCH_PRIVATE_LIB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h new file mode 100644 index 00..13a41f8d04 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h @@ -0,0 +1,269 @@ +/** @file + The GUID definition for PchConfigHob + + Copyright (c) 2021, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_CONFIG_HOB_H_ +#define _PCH_CONFIG_HOB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +extern EFI_GUID gPchConfigHobGuid; + +#pragma pack (push,1
[edk2-devel] [PATCH 05/40] TigerlakeSiliconPkg/Pch: Add include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 Adds the following header files: * Pch/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h | 55 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h | 57 + Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h | 58 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h | 64 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h | 61 + Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h | 38 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h | 72 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h | 258 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h | 590 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h | 552 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h | 70 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h | 67 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h | 55 +++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h | 56 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h | 21 + Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.h | 184 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h | 134 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h | 144 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h | 166 ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h | 40 Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h | 132
[edk2-devel] [PATCH 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds header files common to CPU modules.
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
| 83
+++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
| 148
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfig.h
| 52
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtBasicConfig.h
| 226
++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtCustomConfig.h
| 76
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtPsysConfig.h
| 36
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtTestConfig.h
| 150
++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPreMemConfig.h
| 63 +++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h
| 51 +++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h
| 12
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h
| 21 +
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h
| 23 +++
Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h
| 18 ++
13 files changed, 959 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
new file mode 100644
index 00..d837500a38
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
@@ -0,0 +1,83 @@
+/** @file
+ CPU Config Block.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_CONFIG_H_
+#define _CPU_CONFIG_H_
+
+#define CPU_CONFIG_REVISION 3
+
+extern EFI_GUID gCpuConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ CPU Configuration Structure.
+
+ Revision 1:
+ - Initial version.
+ Revision 2:
+ - Add SmbiosType4MaxSpeedOverride.
+ Revision 3:
+ - Add AvxDisable & Avx3Disable.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32MicrocodePatchRegionSize;
+ EFI_PHYSICAL_ADDRESS MicrocodePatchAddress;///< Pointer to microcode
patch that is suitable for this processor.
+ /**
+Enable or Disable Advanced Encryption Standard (AES) feature.
+For some countries, this should be disabled for legal reasons.
+-0: Disable
+- 1: Enable
+ **/
+ UINT32 AesEnable : 1;
+ /**
+Enable or Disable Trusted Execution Technology (TXT) feature.
+-0: Disable
+- 1: Enable
+ **/
+ UINT32 TxtEnable : 1;
+ UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon
Initialization will skip MP Initialization (including BSP) if enabled. For
non-FSP, this should always be 0.
+ /**
+Enable or Disable or Auto for PPIN Support to view Protected Processor
Inventory Number.
+- 0: Disable
+-1: Enable
+-2: Auto : Feature is based on End Of Manufacturing (EOM) flag. If EOM
is set, it is disabled.
+ **/
+ UINT32 PpinSupport : 2;
+ /**
+Enable or Disable #AC machine check on split lock.
+- 0: Disable
+-1: Enable
+ **/
+ UINT32 AcSplitLock : 1;
+ /**
+ Enable or Disable Avx.
+ - 1: Disable
+ - 0: Enable
+ **/
+ UINT32 AvxDisable : 1;
+ /**
+ Enable or Disable Avx3.
+ - 1: Disable
+ - 0: Enable
+ **/
+ UINT32 Avx3Disable : 1;
+ UINT32 RsvdBits: 24;///< Reserved for future use
+ /**
+Provide the option for platform to override the MaxSpeed field of Smbios
Type 4.
+Value 4000 means 4000MHz.
+If this value is not zero, it dominates the field.
+If this value is zero, CPU RC will
[edk2-devel] [PATCH 07/40] TigerlakeSiliconPkg/SystemAgent: Add include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following header files:
* SystemAgent/Include
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
| 123
+++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieDxeConfig.h
| 114
++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PramPreMemConfig.h
| 34 ++
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiConfig.h
| 24
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h
| 104
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/SaPlatformLib.h
| 48
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h
| 264
Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h
| 61 +
8 files changed, 772 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
new file mode 100644
index 00..451e295b49
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
@@ -0,0 +1,123 @@
+/** @file
+ Memory DXE Policy definitions
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MEMORY_DXE_CONFIG_H_
+#define _MEMORY_DXE_CONFIG_H_
+
+#pragma pack(push, 1)
+
+#define MEMORY_DXE_CONFIG_REVISION 1
+
+typedef struct _MEMORY_DXE_CONFIG MEMORY_DXE_CONFIG;
+
+/**
+ Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator
field.
+ Implementation of this function is optional, if this function pointer is
NULL then
+ the reference implementation of DeviceLocator will be used.
+
+ @param[in] This A pointer to this instance of
MEMORY_DXE_CONFIG.
+ @param[in] ControllerDesired Controller to get a
DeviceLocator string for.
+ @param[in] Dimm Desired DIMM to get a
DeviceLocator string for.
+ @param[in] MdSocket 0 = Memory Down, 1 = Socketed.
+
+ @retval The DeviceLocator string
+ @retval NULL If the return value is NULL, the
default value will be used.
+**/
+typedef
+CHAR8*
+(EFIAPI *MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING)(
+ IN CONSTMEMORY_DXE_CONFIG *This,
+ IN UINT8 Controller,
+ IN UINT8 Dimm,
+ IN UINT8 MdSocket
+ );
+
+/**
+ Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator
field.
+ Implementation of this function is optional, if this function pointer is
NULL then
+ the reference implementation of DeviceLocator will be used.
+
+ @param[in] This A pointer to this instance of
MEMORY_DXE_CONFIG.
+ @param[in] ControllerDesired Controller to get a
BankLocator string for.
+ @param[in] Dimm Desired DIMM to get a BankLocator
string for.
+ @param[in] MdSocket 0 = Memory Down, 1 = Socketed.
+
+ @retval The BankLocator string
+ @retval NULL If the return value is NULL, the
default value will be used.
+**/
+typedef
+CHAR8*
+(EFIAPI *MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING)(
+ IN CONSTMEMORY_DXE_CONFIG *This,
+ IN UINT8 Controller,
+ IN UINT8 Dimm,
+ IN UINT8 MdSocket
+ );
+
+/**
+ The Memory Configuration includes DIMM SPD address Map and DIMM Slot
Mechanical present bit map.
+ The data elements should be initialized by a Platform Module.\n
+ Revision 1:
+ - Initial version.
+**/
+struct _MEMORY_DXE_CONFIG {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config
Block Header
+/**
+ Offset 28:
+ Dimm SPD address
+ Only Server support 2 channels
[edk2-devel] [PATCH 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register and other include headers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following header files:
* Include/Pins
* Include/Register
* Include/*.h
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Heng Luo
---
Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h| 53
+
Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h | 38
++
Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h | 75
+++
Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h | 138
++
Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h| 57
+
Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h | 24
Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h | 155
+++
Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h| 110
++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h | 72
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h | 121
+
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h | 226
++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h | 16
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h| 36
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h | 93
+
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h | 258
++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h | 45
+
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h | 56
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h | 47
+++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h | 51
+++
Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h| 213
+
Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h| 17
+
Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h | 64
22 files changed, 1965 insertions(+)
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 00..ad34e4ea42
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include
+#include
+#include
+#include
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+ EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID
extension HOB header
+ UINT8 Revision; ///< Offset 24Revision
of this config block
+ UINT8 Attributes; ///< Offset 25The main
revision for config block
+ UINT8 Reserved[2]; ///< Offset 26-27 Reserved
for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+
Re: [edk2-devel] [PATCH 1/2] Features/Intel/AdvancedFeaturePkg: Remove temporary build workaround
Dear all, I combined 2 patches into one following Eric's suggestion, new patch have been sent out, please help to review. Thanks, Heng > -Original Message- > From: Ni, Ray > Sent: Friday, April 24, 2020 1:03 PM > To: Luo, Heng ; devel@edk2.groups.io > Cc: Michael Kubacki ; Gao, Liming > ; Dong, Eric > Subject: RE: [PATCH 1/2] Features/Intel/AdvancedFeaturePkg: Remove > temporary build workaround > > Thanks for the explanation. Make sense to me. > > > > -Original Message- > > From: Luo, Heng > > Sent: Friday, April 24, 2020 9:06 AM > > To: Ni, Ray ; devel@edk2.groups.io > > Cc: Michael Kubacki ; Gao, Liming > > ; Dong, Eric > > Subject: RE: [PATCH 1/2] Features/Intel/AdvancedFeaturePkg: Remove > > temporary build workaround > > > > Hi Ray, > > Option 1, In current implement, the usage of AdvancedFeaturePkg in board > DSC is: > > > > !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc # invoke > > section "[Packages]", define default Feature PCD > > #option: [PcdsFeatureFlag], board can override default Feature PCD here, > enable specific feature. > > !include Include/AdvancedFeatures.dsc > > > > Option 2, if there is no AdvancedFeaturesPcd.dsc, we can move section > > "[Packages]" to AdvancedFeatures.dsc, there is 2 concerns here: > > 1. there is no default Feature PCD now, we need to add > > [PcdsFeatureFlag] below in every OpenBoardPkg.dsc. if we add a new > > feature, we have to change all OpenBoardPkg.dsc files, but in option > > 1, we just need to change AdvancedFeaturesPcd.dsc [PcdsFeatureFlag] > > gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable > |FALSE > > gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable > |FALSE > > . > > > > 2. we define FeaturePCDs before section "[Packages]", it does work, but it > looks strange. > > > > So I would like option 1, but I also agree option2 if you think it is > > better. > > > > Thanks, > > Heng > > > -Original Message- > > > From: Ni, Ray > > > Sent: Thursday, April 23, 2020 7:43 PM > > > To: Luo, Heng ; devel@edk2.groups.io > > > Cc: Michael Kubacki ; Gao, Liming > > > ; Dong, Eric > > > Subject: RE: [PATCH 1/2] Features/Intel/AdvancedFeaturePkg: Remove > > > temporary build workaround > > > > > > Heng, > > > Any reason to create a separate Pcd.dsc file? > > > > > > > -Original Message- > > > > From: Luo, Heng > > > > Sent: Thursday, April 23, 2020 4:43 PM > > > > To: devel@edk2.groups.io > > > > Cc: Michael Kubacki ; Gao, Liming > > > > ; Dong, Eric ; Ni, Ray > > > > > > > > Subject: [PATCH 1/2] Features/Intel/AdvancedFeaturePkg: Remove > > > > temporary build workaround > > > > > > > > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2688 > > > > > > > > Remove > Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround, > > > > Add > > > Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc > > > > to support Feature PCDs. > > > > > > > > Cc: Michael Kubacki > > > > Cc: Liming Gao > > > > Cc: Eric Dong > > > > Cc: Ray Ni > > > > Signed-off-by: Heng Luo > > > > --- > > > > Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc > > > | 2 +- > > > > Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc > > > | 41 > > > > + > > > > > > > > Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/Temporar > > > yBuildWorkaround.c | 31 --- > > > > > > > > > > > > > > > > Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/Temporar > > > yBu > > > > ildWorkaround.dsc | 76 -- > > > > -- > > > > > > > > > > > > Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/Temporar > > > yBu > > > > ildWorkaround.inf | 60 --- > > > > - > > > > 5 files changed, 42 insertions(+), 168 deletions(-) > > > > > > > > diff --git > > > > a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc > > > > b/Featur
[edk2-devel] [PATCH] Remove temporary build workaround in Features/Intel/AdvancedFeaturePkg
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2688 Remove Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround, Add Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc to support Feature PCDs. Use AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc instead of AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.dsc Cc: Liming Gao Cc: Eric Dong Cc: Ray Ni Signed-off-by: Heng Luo --- Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc | 2 +- Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc | 41 + Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.c | 31 --- Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.dsc | 76 Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.inf | 60 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc | 2 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 2 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 2 +- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc | 2 +- 11 files changed, 48 insertions(+), 174 deletions(-) diff --git a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc index ea879680ba..e509ef3e1b 100644 --- a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc +++ b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc @@ -30,7 +30,7 @@ PEI_ARCH= IA32 DXE_ARCH= X64 -!include AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.dsc +!include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc # diff --git a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc new file mode 100644 index 00..2eacec18a0 --- /dev/null +++ b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc @@ -0,0 +1,41 @@ +## @file +# DSC file for defining Pcd of advanced features. +# +# This file is intended to be included into another package so advanced features +# can be conditionally built by enabling the respective feature via its FeaturePCD. +# +# Copyright (c) 2020, Intel Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# The section references the package DEC files, +# it allow a FeaturePCD to be used in a conditional statement +# +[Packages] + MdePkg/MdePkg.dec + AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.dec + Usb3DebugFeaturePkg/Usb3DebugFeaturePkg.dec + NetworkFeaturePkg/NetworkFeaturePkg.dec + IpmiFeaturePkg/IpmiFeaturePkg.dec + S3FeaturePkg/S3FeaturePkg.dec + SmbiosFeaturePkg/SmbiosFeaturePkg.dec + UserAuthFeaturePkg/UserAuthFeaturePkg.dec + LogoFeaturePkg/LogoFeaturePkg.dec + +# +# The section below sets all PCDs to FALSE in this DSC file so the feature is not enabled by default. +# Board can set PCDs to TRUE in its DSC file to enable a subset of advanced features +# +[PcdsFeatureFlag] + gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable |FALSE + gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |FALSE + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |FALSE + gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable |FALSE + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable |FALSE + gUsb3DebugFeaturePkgTokenSpaceGuid.PcdUsb3DebugFeatureEnable |FALSE + gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable |FALSE + gLogoFeaturePkgTokenSpaceGuid.PcdLogoFeatureEnable |FALSE + gLogoFeaturePkgTokenSpaceGuid.PcdJpgEnable |FALSE diff --git a/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.c b/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.c deleted file mode 100644 index 2cd91b06f0..00 --- a/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @file - Source code file for a temporary build workaround. - - The purpose of this workaround is described
Re: [edk2-devel] [PATCH 2/2] Platform/Intel: Cleanup temporary build workaround related code
Hi Eric, OK, I will combine them into one patch. Thanks, Heng > -Original Message- > From: Dong, Eric > Sent: Friday, April 24, 2020 8:52 AM > To: Luo, Heng ; devel@edk2.groups.io > Cc: Michael Kubacki ; Gao, Liming > ; Ni, Ray > Subject: RE: [PATCH 2/2] Platform/Intel: Cleanup temporary build > workaround related code > > Hi Heng, > > You can't separate these two patches like this. Because in this case, the > first > patch will cause all platforms which use > AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaro > und.dsc file build error. > Please reorg the patches to make all patches can pass build for all platforms. > > Thanks, > Eric > > -Original Message- > > From: Luo, Heng > > Sent: Thursday, April 23, 2020 4:43 PM > > To: devel@edk2.groups.io > > Cc: Michael Kubacki ; Gao, Liming > > ; Dong, Eric ; Ni, Ray > > > > Subject: [PATCH 2/2] Platform/Intel: Cleanup temporary build > > workaround related code > > > > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2688 > > > > Use AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc instead of > > > AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaro > > und.dsc > > > > Cc: Michael Kubacki > > Cc: Liming Gao > > Cc: Eric Dong > > Cc: Ray Ni > > Signed-off-by: Heng Luo > > --- > > > > Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.d > > sc | 2 +- > > Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc > > | 2 +- > > Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc > > | 2 +- > > Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc > > | 2 +- > > Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc > > | 2 +- > > > > > Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPk > > g.dsc | 2 +- > > 6 files changed, 6 insertions(+), 6 deletions(-) > > > > diff --git > > > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg > > .dsc > > > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg > > .dsc > > index 14e82ba34d..8e04ca8a4f 100644 > > --- > > > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg > > .dsc > > +++ > > > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg > > .ds > > +++ c > > @@ -39,7 +39,7 @@ > ># # Include PCD configuration for this board. #- !include > > > AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaro > > und.dsc+ !include > > AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc !include > > OpenBoardPkgPcd.dsc !include > > AdvancedFeaturePkg/Include/AdvancedFeatures.dsc diff --git > > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc > > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc > > index bf63d53bef..7bb8cd5279 100644 > > --- > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc > > +++ > > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc > > @@ -38,7 +38,7 @@ > ># # Include PCD configuration for this board. #- !include > > > AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaro > > und.dsc+ !include > > AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc !include > > OpenBoardPkgPcd.dsc !include > > AdvancedFeaturePkg/Include/AdvancedFeatures.dsc diff --git > > > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc > > > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc > > index 044688ba4e..ef82f8b716 100644 > > --- > > > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc > > +++ > > > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc > > @@ -37,7 +37,7 @@ > ># # Include PCD configuration for this board. #- !include > > > AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaro > > und.dsc+ !include > > AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc !include > > OpenBoardPkgPcd.dsc !include > > AdvancedFeaturePkg/Include/AdvancedFeatures.dsc diff --git > > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc > > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc > > index 350a75a313..3bafc1ff0a 100644 > > --- > > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc > > +++ > > b/Platform/Intel/SimicsOpenBoardPkg/B
Re: [edk2-devel] [PATCH 1/2] Features/Intel/AdvancedFeaturePkg: Remove temporary build workaround
Hi Ray, Option 1, In current implement, the usage of AdvancedFeaturePkg in board DSC is: !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc # invoke section "[Packages]", define default Feature PCD #option: [PcdsFeatureFlag], board can override default Feature PCD here, enable specific feature. !include Include/AdvancedFeatures.dsc Option 2, if there is no AdvancedFeaturesPcd.dsc, we can move section "[Packages]" to AdvancedFeatures.dsc, there is 2 concerns here: 1. there is no default Feature PCD now, we need to add [PcdsFeatureFlag] below in every OpenBoardPkg.dsc. if we add a new feature, we have to change all OpenBoardPkg.dsc files, but in option 1, we just need to change AdvancedFeaturesPcd.dsc [PcdsFeatureFlag] gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable|FALSE gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |FALSE . 2. we define FeaturePCDs before section "[Packages]", it does work, but it looks strange. So I would like option 1, but I also agree option2 if you think it is better. Thanks, Heng > -Original Message- > From: Ni, Ray > Sent: Thursday, April 23, 2020 7:43 PM > To: Luo, Heng ; devel@edk2.groups.io > Cc: Michael Kubacki ; Gao, Liming > ; Dong, Eric > Subject: RE: [PATCH 1/2] Features/Intel/AdvancedFeaturePkg: Remove > temporary build workaround > > Heng, > Any reason to create a separate Pcd.dsc file? > > > -Original Message- > > From: Luo, Heng > > Sent: Thursday, April 23, 2020 4:43 PM > > To: devel@edk2.groups.io > > Cc: Michael Kubacki ; Gao, Liming > > ; Dong, Eric ; Ni, Ray > > > > Subject: [PATCH 1/2] Features/Intel/AdvancedFeaturePkg: Remove > > temporary build workaround > > > > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2688 > > > > Remove Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround, > > Add > Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc > > to support Feature PCDs. > > > > Cc: Michael Kubacki > > Cc: Liming Gao > > Cc: Eric Dong > > Cc: Ray Ni > > Signed-off-by: Heng Luo > > --- > > Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc > | 2 +- > > Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc > | 41 > > + > > > Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/Temporar > yBuildWorkaround.c | 31 --- > > > > > > > Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/Temporar > yBu > > ildWorkaround.dsc | 76 -- > > -- > > > > > Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/Temporar > yBu > > ildWorkaround.inf | 60 --- > > - > > 5 files changed, 42 insertions(+), 168 deletions(-) > > > > diff --git a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc > > b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc > > index ea879680ba..e509ef3e1b 100644 > > --- a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc > > +++ b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc > > @@ -30,7 +30,7 @@ > >PEI_ARCH= IA32 > > > >DXE_ARCH= X64 > > > > > > > > -!include > > > AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaro > und.d > > sc > > > > +!include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc > > > > > > > > > > > > ## > > ## > > > > # > > > > diff --git > > a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc > > b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc > > new file mode 100644 > > index 00..2eacec18a0 > > --- /dev/null > > +++ > b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.ds > > +++ c > > @@ -0,0 +1,41 @@ > > +## @file > > > > +# DSC file for defining Pcd of advanced features. > > > > +# > > > > +# This file is intended to be included into another package so > > +advanced features > > > > +# can be conditionally built by enabling the respective feature via its > FeaturePCD. > > > > +# > > > > +# Copyright (c) 2020, Intel Corporation. All rights reserved. > > > > +# > > > > +#
[edk2-devel] [PATCH 1/2] Features/Intel/AdvancedFeaturePkg: Remove temporary build workaround
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2688
Remove Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround,
Add Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
to support Feature PCDs.
Cc: Michael Kubacki
Cc: Liming Gao
Cc: Eric Dong
Cc: Ray Ni
Signed-off-by: Heng Luo
---
Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc
| 2 +-
Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
| 41 +
Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.c
| 31 ---
Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.dsc
| 76
Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.inf
| 60
5 files changed, 42 insertions(+), 168 deletions(-)
diff --git a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc
b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc
index ea879680ba..e509ef3e1b 100644
--- a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc
+++ b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc
@@ -30,7 +30,7 @@
PEI_ARCH= IA32
DXE_ARCH= X64
-!include
AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.dsc
+!include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
#
diff --git a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
new file mode 100644
index 00..2eacec18a0
--- /dev/null
+++ b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
@@ -0,0 +1,41 @@
+## @file
+# DSC file for defining Pcd of advanced features.
+#
+# This file is intended to be included into another package so advanced
features
+# can be conditionally built by enabling the respective feature via its
FeaturePCD.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+#
+# The section references the package DEC files,
+# it allow a FeaturePCD to be used in a conditional statement
+#
+[Packages]
+ MdePkg/MdePkg.dec
+ AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.dec
+ Usb3DebugFeaturePkg/Usb3DebugFeaturePkg.dec
+ NetworkFeaturePkg/NetworkFeaturePkg.dec
+ IpmiFeaturePkg/IpmiFeaturePkg.dec
+ S3FeaturePkg/S3FeaturePkg.dec
+ SmbiosFeaturePkg/SmbiosFeaturePkg.dec
+ UserAuthFeaturePkg/UserAuthFeaturePkg.dec
+ LogoFeaturePkg/LogoFeaturePkg.dec
+
+#
+# The section below sets all PCDs to FALSE in this DSC file so the feature is
not enabled by default.
+# Board can set PCDs to TRUE in its DSC file to enable a subset of advanced
features
+#
+[PcdsFeatureFlag]
+ gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable
|FALSE
+ gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable
|FALSE
+ gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable
|FALSE
+ gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable
|FALSE
+ gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable
|FALSE
+ gUsb3DebugFeaturePkgTokenSpaceGuid.PcdUsb3DebugFeatureEnable
|FALSE
+ gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable
|FALSE
+ gLogoFeaturePkgTokenSpaceGuid.PcdLogoFeatureEnable
|FALSE
+ gLogoFeaturePkgTokenSpaceGuid.PcdJpgEnable
|FALSE
diff --git
a/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.c
b/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.c
deleted file mode 100644
index 2cd91b06f0..00
---
a/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @file
- Source code file for a temporary build workaround.
-
- The purpose of this workaround is described in the module INF file.
-
-Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include
-#include
-
-/**
- An empty entry point function.
-
- @param FileHandle Handle of the file being invoked.
- @param PeiServices Describes the list of possible PEI Services.
-
- @retval EFI_SUCCESS This function always returns EFI_SUCCESS.
-
-**/
-EFI_STATUS
-EFIAPI
-TemporaryBuildWorkaroundEntry (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- return EFI_SUCCESS;
-}
diff --git
a/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.dsc
b/Features/Intel
[edk2-devel] [PATCH 0/2] Remove AdvancedFeaturePkg/TemporaryBuildWorkaround
*** BLURB HERE *** Heng Luo (2): Features/Intel/AdvancedFeaturePkg: Remove temporary build workaround Platform/Intel: Cleanup temporary build workaround related code Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc | 2 +- Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc | 41 + Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.c | 31 --- Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.dsc | 76 Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.inf | 60 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc | 2 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 2 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 2 +- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc | 2 +- 11 files changed, 48 insertions(+), 174 deletions(-) create mode 100644 Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc delete mode 100644 Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.c delete mode 100644 Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.dsc delete mode 100644 Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.inf -- 2.24.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57918): https://edk2.groups.io/g/devel/message/57918 Mute This Topic: https://groups.io/mt/73214614/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
