Re: [edk2-devel] [edk2-platforms][PATCH 2/3] Platform/AMD: Update Readme.md

[Zhai, MingXin (Duke) via groups.io]

[AMD Official Use Only - AMD Internal Distribution Only]

Thanks Abner for the up-stream.

Looks good to me.

-Original Message-
From: Chang, Abner 
Sent: Thursday, May 23, 2024 12:12 PM
To: devel@edk2.groups.io
Cc: Grimes, Paul ; Attar, AbdulLateef (Abdul Lateef) 
; Fu, Igniculus ; Yao, Ken 
; Xing, Eric ; Zhai, MingXin (Duke) 

Subject: [edk2-platforms][PATCH 2/3] Platform/AMD: Update Readme.md

From: Abner Chang 

Cc: Paul Grimes 
Cc: Abdul Lateef Attar 
Cc: Igniculus Fu 
Cc: Ken Yao 
Cc: Eric Xing 
Cc: Duke Zhai 
Signed-off-by: Abner Chang 
---
 Platform/AMD/Readme.md | 64 --
 1 file changed, 49 insertions(+), 15 deletions(-)

diff --git a/Platform/AMD/Readme.md b/Platform/AMD/Readme.md index 
99d2b990c7..3297c6ba59 100644
--- a/Platform/AMD/Readme.md
+++ b/Platform/AMD/Readme.md
@@ -7,18 +7,25 @@ booting certain AMD platforms. The definition of sub-folders 
is described in bel

 ## Term and Definitions

+* **AGESA**
+
+  AMD Generic Encapsulated Software Architecture that are executed as
+ part of a  host platform BIOS.
+
 * **AMD Platform** (platform in short)

-  AMD platform refers to a platform that supports the particular AMD SoC 
(processor), such as AMD EPYC Milan and Genoa processors.
+  AMD platform refers to a platform that supports the particular AMD
+ SoC (processor), such as  AMD EPYC Milan and Genoa processors.

 * **AMD Board** (board in short)

   AMD board is a generic terminology refers to a board that is designed based 
on a
   specific AMD SoC architecture (also referred as AMD platform). More than one 
boards
-  are possibly designed to support an AMD platform with different 
configuration, such as 1-processor socket or 2-processor sockets board.
+  are possibly designed to support an AMD platform with different
+ configuration, such as  1-processor socket or 2-processor sockets board.

 * **AMD edk2 Platform Package** (platform package in short)
-
+
   The folder has the AMD edk2 platform common modules.

 * **AMD edk2 Board Package** (board package in short) @@ -28,29 +35,52 @@ 
booting certain AMD platforms. The definition of sub-folders is described in bel

 ## Package Definition

+* **AgesaModulePkg**
+
+  This package contains all of the private interfaces and build
+ configuration files for the  AGESA support.
+
+* **AgesaPkg**
+
+  This package contains all of the public interfaces and build
+ configuration files  for the AGESA support.
+
+* **AmdCbsPkg**
+
+  AMD Configurable BIOS Setting. Provides the edk2 formset following
+ the UEFI HII  spec to configure BIOS settings.
+
+* **AmdCpmPkg**
+
+  AMD Common Platform Module software is a BIOS procedure library
+ designed to aid  AMD customers to quickly implement AMD platform technology 
into their products.
+
 * **AmdPlatformPkg**

-  AMD platform edk2 package under this folder provides the common edk2 modules 
those
-  are leverage by platforms. Usually those modules have no dependencies with
-  particular platforms. The module under this scope can provides a common 
implementation
-  for all platforms, or it may just provide a framework but the differences of 
implementation could be configured through the PCDs declared in 
AmdPlatformPkg.dec, or
-  the board level library provided in the \Pkg.
+  AMD platform edk2 package under this folder provides the common edk2
+ modules that are leveraged by platforms. Usually those modules have no
+ dependencies with  particular platforms. Modules under this scope can
+ provide a common implementation  for all platforms, or may just
+ provide a framework but the differences of implementation  could be
+ configured through the PCDs declared in AmdPlatformPkg.dec, or the board 
level  library provided in the \Pkg.

 * **AmdMinBoardPkg**

-  This package provides the common edk2 modules those can be leverage across 
AMD boards those use MinPlatformPkg framework.
+  This package provides the common edk2 modules that can be leveraged
+ across AMD boards using  the MinPlatform framework.

 * **\Board**

-  This is the folder named by SoC and accommodate one or multiple board 
packages those
-  are designed base on the same SoC platform. Board folder may 
contain edk2
-  package meta files directly or the sub-folders named by \Pkg 
for a
-  variety configurations of a platform.
+  This is the folder named by SoC and accommodates one or multiple
+ board packages  that are designed based on the same SoC platform. Board folder may  contain edk2 package meta files directly or the
+ sub-folders named by \Pkg for  a variety configurations of a 
platform.

 * **Pkg**

-  This is the folder that contains edk2 package meta files for a board which 
is designed base on a platform. Besides the edk2 meta files, Pkg 
may also provides
-  edk2 modules which are specifically to a board.
+  This is the folder that contains edk2 package meta files for a board
+ which is designed base  on a platform. Besides the edk2 meta files,
+ Pkg may also provides edk2 

Re: [edk2-devel] [PATCH 1/2] Platform/AMD: Add AmdSvsmLib to required DSC files

[Zhai, MingXin (Duke) via groups.io]

[AMD Official Use Only - General]

Hi Thomas,

Yes, I agree with your opinion,  edk2-platforms should be able to build against 
the latest edk2 repo. That is why we plan to update VanGoghBoard to support 
latest EDK2, In fact we are doing QA testing.
I think every change on VanGoghBoard need ensure system can works properly. But 
if I apply this patch and use the latest EDK2 version to build, it will 
encounter error because it requires other code changes(Such as including new 
libraries).
So my point is, Let me upload VanGoghBoard related changes after passing full 
QA testing.


Thanks!

-Original Message-
From: Lendacky, Thomas 
Sent: Friday, April 19, 2024 12:03 AM
To: Zhai, MingXin (Duke) ; Xing, Eric ; 
Chang, Abner ; Yao, Ken 
Cc: Roth, Michael ; Attar, AbdulLateef (Abdul Lateef) 

Subject: Re: [PATCH 1/2] Platform/AMD: Add AmdSvsmLib to required DSC files

On 4/18/24 05:02, Zhai, MingXin (Duke) wrote:
> [AMD Official Use Only - General]
>
> Hi Thomas,
>
> this patch looks like for newer EDK2 codebase, but VanGoghBoard is based on 
> EDK2_202208 now, and will encounter build issues if this patch is applied.
> We have plans to update the EDK2 codebase to EDK2_202402. So I thought
> it would be better to add this change when we update the EDK2 code
> base

I thought the latest edk2-platforms repo was supposed to be able to build 
against the latest edk2 repo. If your VanGoghBoard is based on a particular 
edk2 tag, then you should probably have a tag in edk2-platforms so that you can 
have a version of the edk2-platform code that works with a version of the edk2 
code, no?

Why is this a private email? This discussion should be on the list so that the 
maintainer(s) can decide what to do based on the discussion.

Thanks,
Tom

>
>
> Thanks!
>
> -Original Message-
> From: Xing, Eric 
> Sent: Thursday, April 18, 2024 9:54 AM
> To: Chang, Abner ; Lendacky, Thomas
> ; devel@edk2.groups.io; Zhai, MingXin (Duke)
> ; Yao, Ken 
> Cc: Ard Biesheuvel ; Gerd Hoffmann
> ; Roth, Michael ; Min Xu
> ; Leif Lindholm ;
> Michael D Kinney ; Attar, AbdulLateef
> (Abdul Lateef) 
> Subject: RE: [PATCH 1/2] Platform/AMD: Add AmdSvsmLib to required DSC
> files
>
> [AMD Official Use Only - General]
>
> Thanks Thomas and Abner.
> Reviewed-by: 
>
> For up-stream, please let us verify it first:
> @Zhai, MingXin (Duke), Duke, please help verify this change on Chachani Board 
> and feedback.
>
> Thanks,
> Eric
>
>> -Original Message-
>> From: Chang, Abner 
>> Sent: Thursday, April 18, 2024 8:59 AM
>> To: Lendacky, Thomas ; devel@edk2.groups.io
>> Cc: Ard Biesheuvel ; Gerd Hoffmann
>> ; Roth, Michael ; Min Xu
>> ; Leif Lindholm ;
>> Michael D Kinney ; Attar, AbdulLateef
>> (Abdul
>> Lateef) ; Xing, Eric 
>> Subject: RE: [PATCH 1/2] Platform/AMD: Add AmdSvsmLib to required DSC
>> files
>>
>> [AMD Official Use Only - General]
>>
>> Reviewed-by: 
>>
>> Thanks
>>
>>> -Original Message-
>>> From: Lendacky, Thomas 
>>> Sent: Monday, April 15, 2024 11:01 PM
>>> To: devel@edk2.groups.io
>>> Cc: Ard Biesheuvel ; Gerd Hoffmann
>>> ; Roth, Michael ; Min Xu
>>> ; Leif Lindholm ;
>>> Michael D Kinney ; Chang, Abner
>>> ; Attar, AbdulLateef (Abdul Lateef)
>>> ; Xing, Eric 
>>> Subject: [PATCH 1/2] Platform/AMD: Add AmdSvsmLib to required DSC
>>> files
>>>
>>> Any DSC file that uses the UefiCpuPkg MpInitLib library now requires
>>> the AmdSvsmLib library. Update the DSC files to include the
>>> AmdSvsmLib NULL library implementation. Also, fix the specification
>>> of VmgExitLib as it was renamed to CcExitLib.
>>>
>>> Cc: Abner Chang 
>>> Cc: Abdul Lateef Attar 
>>> Cc: Eric Xing 
>>> Signed-off-by: Tom Lendacky 
>>> ---
>>>   Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc | 3 ++-
>>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
>>> b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
>>> index 20f06dd851..e478e0b0c2 100644
>>> --- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
>>> +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
>>> @@ -371,7 +371,8 @@
>>>
>>>   [LibraryClasses.common]
>>>
>>> RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilte
>>> RegisterFilterLib|rL
>>> RegisterFilterLib|ibNull.inf
>>> -  VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
>>> +  CcExitLib|UefiCpuPkg/Library/CcExitLibNull/CcExitLibNull.inf
>>> +  AmdSvsmLib|UefiCpuPkg/Library/AmdSvsmLibNull/AmdSvsmLibNull.inf
>>>
>>>   [PcdsFixedAtBuild]
>>>
>> gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemBeforePciRestoreSwSmi|0xEA
>>> --
>>> 2.43.2
>>
>
>


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[edk2-devel] [PATCH] AMD/AmdPlatformPkg: Update AMD Vangogh platform reference code

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4728

1.Use HPET timer to replace 8254 timer
2.Fix Bug Microcode version cannot show correctly at BIOS setup
3.Enable capsule at linux build
4.Update FspWrapper UPD table for BIOS setup options

Cc: Ken Yao 
Cc: Igniculus Fu 
Reviewed-by: Abner Chang 
Reviewed-by: Eric Xing 
Signed-off-by: Duke Zhai 
---
 .../BIOSImageDirectory32M.xml |  2 +-
 .../ChachaniBoardPkg/GenCapsule.bat   |  2 +-
 .../VanGoghBoard/ChachaniBoardPkg/Project.dsc |  2 -
 .../VanGoghBoard/ChachaniBoardPkg/Project.fdf |  3 +-
 .../VanGoghBoard/ChachaniBoardPkg/build.sh| 22 +-
 .../edk2/Fsp2WrapperPkg/Include/FspmUpd.h | 71 ++-
 .../FspWrapperPlatformLibSample.c | 29 
 7 files changed, 59 insertions(+), 72 deletions(-)

diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml
index 22af6623e2..585e12d487 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml
@@ -57,7 +57,7 @@
 
 
 
-
+
 
   
 
diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat
index 7dca22a4e3..c55f561772 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat
@@ -36,7 +36,7 @@ if not exist %WORKSPACE%\%BIOS_FILE_NAME% (
   goto ERROR
 )
 
- Setup OpenSSL Command Line Environment
+echo Setup OpenSSL Command Line Environment
 if not "%OPENSSL_PATH%" == "" (
   set OPENSSL_PATH_TEMP=%OPENSSL_PATH%
 )
diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
index 510ce10c0c..20f06dd851 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
@@ -745,8 +745,6 @@
   MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
   FatPkg/EnhancedFatDxe/Fat.inf
   PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
-  OvmfPkg/8259InterruptControllerDxe/8259.inf
-  OvmfPkg/8254TimerDxe/8254Timer.inf
   
MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf
   
MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf
 
diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf
index 5194a8c10d..0d844689b3 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf
@@ -416,8 +416,7 @@ NumBlocks = 0x100
   # Platform
   #
   INF  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
-  INF  OvmfPkg/8259InterruptControllerDxe/8259.inf
-  INF  OvmfPkg/8254TimerDxe/8254Timer.inf
+  INF  PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
 
   #
   # ACPI
diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh
index f4652e91c6..0984876ef2 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh
@@ -1,3 +1,4 @@
+#!/bin/bash
 ## @file
 # Linux build script file to launch Chachani Board BIOS build
 #
@@ -22,6 +23,7 @@ export OemBoard=Chachani
 export PLATFORM_PATH=edk2-platforms/Platform/AMD/VanGoghBoard
 export BUILD_TYPE=RELEASE
 export TOOLCHAIN_TAG=CLANGPDB
+export OTA_CAPSULE_NAME=OTACAPSULE # You need to keep this name sync with 
PlatformCapsule.fdf
 #TRUE / FALSE
 export COMPRESS_FSP_REGION=TRUE
 export KEY_MODE=TK
@@ -35,16 +37,25 @@ export NASM_PREFIX=
 export GCC5_BIN=
 #CLANG_BIN shall end with a slash.
 export CLANG_BIN=
+#OPENSSL_PATH shall end with a slash.
+export OPENSSL_PATH=
 
 echo "Building for ${OemBoard} board, ${BUILD_TYPE} mode with 
${TOOLCHAIN_TAG}."
-echo "IASL: ${IASL_PREFIX}iasl, NASM: ${NASM_PREFIX}nasm, GCC: ${GCC5_BIN}gcc, 
CLANG:${CLANG_BIN}clang."
+echo "IASL: ${IASL_PREFIX}iasl, NASM: ${NASM_PREFIX}nasm, GCC: ${GCC5_BIN}gcc, 
CLANG:${CLANG_BIN}clang, OPENSSL:${OPENSSL_PATH}openssl."
 [[ ${COMPRESS_FSP_REGION} == "TRUE" ]] && echo "FSP will be built with 
compress support."
 # Env check
 echo_section "Checking compilation environment"
 [[ "${IASL_PREFIX}" == "" ]] && export IASL_PREFIX=$(dirname $(which iasl))/
 [[ "${NASM_PREFIX}" == "" ]] && export NASM_PREFIX=$(dirname $(which nasm))/
+[[ "${OPENSSL_PATH}" == "" ]] && export OPENSSL_PATH=$(dirname $(which 
openssl))/
 [[ -f ${IASL_PREFIX}iasl ]] || (echo "IASL not found! Please specify 
IASL_PREFIX!";exit -1)
-[[ -f ${IASL_PREFIX}nasm ]] || (echo "NASM not found! Please specify 
NASM_PREFIX!";exit -1)
+[[ -f ${NASM_PREFIX}nasm ]] || (echo "NASM not found! Please specify 
NASM_PREFIX!";exit -1)
+[[ -f ${OPENSSL_PATH}openssl ]] || (echo "OpenSSL not found! Please specify 
OPENSSL_PATH!";exit -1)
+

[edk2-devel] [PATCH 4/4] AMD/AmdPlatformPkg: Update FspWrapper UPD table for BIOS setup options

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4728
1.Remove useless options like I2C enable
2.Add new option:SocVoltage

Cc: Abner Chang 
Cc: Igniculus Fu 
Reviewed-by: Ken Yao 
Reviewed-by: Eric Xing 
Signed-off-by: Duke Zhai 
---
 .../edk2/Fsp2WrapperPkg/Include/FspmUpd.h | 71 ++-
 .../FspWrapperPlatformLibSample.c | 29 
 2 files changed, 36 insertions(+), 64 deletions(-)

diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUpd.h 
b/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUpd.h
index 8cadbe430a..875461a58a 100644
--- a/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUpd.h
+++ b/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUpd.h
@@ -16,41 +16,42 @@
 /** Fsp M Configuration
 **/
 typedef struct {
-  /** Offset 0x0040**/ UINT32bert_size;
-  /** Offset 0x0044**/ UINT32tseg_size;
-  /** Offset 0x0048**/ UINT32dxio_descriptor_table_pointer;
-  /** Offset 0x004C**/ UINT32pcie_reset_function_pointer;
-  /** Offset 0x0050**/ UINT32ddi_descriptor_table_pointer;
-  /** Offset 0x0054**/ UINT32temp_memory_base_addr;
-  /** Offset 0x0058**/ UINT32temp_memory_size;
-  /** Offset 0x005C**/ UINT32fsp_o_pei_volume_address;
-  /** Offset 0x0060**/ UINT32fsp_o_pei_upd_address;
-  /** Offset 0x0064**/ UINT32pei_reset_ppi_addr;
-  /** Offset 0x0068**/ UINT32resource_size_for_each_rb_ptr;
-  /** Offset 0x006C**/ UINT32resource_size_for_each_rb_size;
-  /** Offset 0x0070**/ UINT32total_number_of_root_bridges_ptr;
-  /** Offset 0x0074**/ UINT32total_number_of_root_bridges_size;
-  /** Offset 0x0078**/ UINT32amd_pbs_setup_ptr;
-  /** Offset 0x007C**/ UINT32amd_pbs_setup_size;
-  /** Offset 0x0080**/ UINT32ap_sync_flag_nv_ptr;
-  /** Offset 0x0084**/ UINT32ap_sync_flag_nv_size;
-  /** Offset 0x0088**/ UINT8 DbgFchUsbUsb0DrdMode;
-  /** Offset 0x0089**/ UINT8 DbgFchUsbUsb2DrdMode;
-  /** Offset 0x008A**/ UINT32CmnGnbGfxUmaFrameBufferSize;
-  /** Offset 0x008E**/ UINT8 CmnGnbNbIOMMU;
-  /** Offset 0x008F**/ UINT32DbgFastPPTLimit;
-  /** Offset 0x0093**/ UINT32DbgSlowPPTLimit;
-  /** Offset 0x0097**/ UINT32CmnCpuVoltageOffset;
-  /** Offset 0x009B**/ UINT32CmnGpuVoltageOffset;
-  /** Offset 0x009F**/ UINT32CmnSocVoltageOffset;
-  /** Offset 0x00A3**/ UINT8 CmnGnbGfxUmaMode;
-  /** Offset 0x00A4**/ UINT8 CmnFchI2C0Config;
-  /** Offset 0x00A5**/ UINT8 CmnFchI2C1Config;
-  /** Offset 0x00A6**/ UINT8 CmnFchI2C2Config;
-  /** Offset 0x00A7**/ UINT8 CmnFchI2C3Config;
-  /** Offset 0x00A8**/ UINT32ids_nv_table_address;
-  /** Offset 0x00AC**/ UINT32ids_nv_table_size;
-  /** Offset 0x00B0**/ UINT16UpdTerminator;
+   /** Offset 0x0040**/UINT32  bert_size;
+   /** Offset 0x0044**/UINT32  tseg_size;
+   /** Offset 0x0048**/UINT32  
dxio_descriptor_table_pointer;
+   /** Offset 0x004C**/UINT32  
pcie_reset_function_pointer;
+   /** Offset 0x0050**/UINT32  
ddi_descriptor_table_pointer;
+   /** Offset 0x0054**/UINT32  
temp_memory_base_addr;
+   /** Offset 0x0058**/UINT32  temp_memory_size;
+   /** Offset 0x005C**/UINT32  
fsp_o_pei_volume_address;
+   /** Offset 0x0060**/UINT32  
fsp_o_pei_upd_address;
+   /** Offset 0x0064**/UINT32  pei_reset_ppi_addr;
+   /** Offset 0x0068**/UINT32  
resource_size_for_each_rb_ptr;
+   /** Offset 0x006C**/UINT32  
resource_size_for_each_rb_size;
+   /** Offset 0x0070**/UINT32  
total_number_of_root_bridges_ptr;
+   /** Offset 0x0074**/UINT32  
total_number_of_root_bridges_size;
+   /** Offset 0x0078**/UINT32  amd_pbs_setup_ptr;
+   /** Offset 0x007C**/UINT32  amd_pbs_setup_size;
+   /** Offset 0x0080**/UINT32  ap_sync_flag_nv_ptr;
+   /** Offset 0x0084**/UINT32  
ap_sync_flag_nv_size;
+   /** Offset 0x0088**/UINT8   FchUsbUsb0DrdMode;
+   /** Offset 0x0089**/UINT8   FchUsbUsb2DrdMode;
+   /** Offset 0x008A**/UINT8   CmnGnbGfxUmaMode;
+   /** Offset 0x008B**/UINT32  
CmnGnbGfxUmaFrameBufferSize;
+   /** Offset 0x008F**/UINT8   CmnGnbNbIOMMU;
+   /** Offset 0x0090**/UINT8   PPTCtl;
+   /** Offset 0x0091**/UINT32  FastPPTLimit;
+   /** Offset 0x0095**/UINT32  SlowPPTLimit;
+   /** Offset 0x0099**/UINT8   

[edk2-devel] [PATCH 3/4] AMD/AmdPlatformPkg: Enable capsule at linux build

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4720
Linux build script include capsule build.
Fix winodws capsule build issue.

Cc: Abner Chang 
Cc: Igniculus Fu 
Reviewed-by: Ken Yao 
Reviewed-by: Eric Xing 
Signed-off-by: Duke Zhai 
---
 .../ChachaniBoardPkg/GenCapsule.bat   |  2 +-
 .../VanGoghBoard/ChachaniBoardPkg/build.sh| 22 +--
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat
index 7dca22a4e3..c55f561772 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat
@@ -36,7 +36,7 @@ if not exist %WORKSPACE%\%BIOS_FILE_NAME% (
   goto ERROR
 )

- Setup OpenSSL Command Line Environment
+echo Setup OpenSSL Command Line Environment
 if not "%OPENSSL_PATH%" == "" (
   set OPENSSL_PATH_TEMP=%OPENSSL_PATH%
 )
diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh
index f4652e91c6..0984876ef2 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh
@@ -1,3 +1,4 @@
+#!/bin/bash
 ## @file
 # Linux build script file to launch Chachani Board BIOS build
 #
@@ -22,6 +23,7 @@ export OemBoard=Chachani
 export PLATFORM_PATH=edk2-platforms/Platform/AMD/VanGoghBoard
 export BUILD_TYPE=RELEASE
 export TOOLCHAIN_TAG=CLANGPDB
+export OTA_CAPSULE_NAME=OTACAPSULE # You need to keep this name sync with 
PlatformCapsule.fdf
 #TRUE / FALSE
 export COMPRESS_FSP_REGION=TRUE
 export KEY_MODE=TK
@@ -35,16 +37,25 @@ export NASM_PREFIX=
 export GCC5_BIN=
 #CLANG_BIN shall end with a slash.
 export CLANG_BIN=
+#OPENSSL_PATH shall end with a slash.
+export OPENSSL_PATH=

 echo "Building for ${OemBoard} board, ${BUILD_TYPE} mode with 
${TOOLCHAIN_TAG}."
-echo "IASL: ${IASL_PREFIX}iasl, NASM: ${NASM_PREFIX}nasm, GCC: ${GCC5_BIN}gcc, 
CLANG:${CLANG_BIN}clang."
+echo "IASL: ${IASL_PREFIX}iasl, NASM: ${NASM_PREFIX}nasm, GCC: ${GCC5_BIN}gcc, 
CLANG:${CLANG_BIN}clang, OPENSSL:${OPENSSL_PATH}openssl."
 [[ ${COMPRESS_FSP_REGION} == "TRUE" ]] && echo "FSP will be built with 
compress support."
 # Env check
 echo_section "Checking compilation environment"
 [[ "${IASL_PREFIX}" == "" ]] && export IASL_PREFIX=$(dirname $(which iasl))/
 [[ "${NASM_PREFIX}" == "" ]] && export NASM_PREFIX=$(dirname $(which nasm))/
+[[ "${OPENSSL_PATH}" == "" ]] && export OPENSSL_PATH=$(dirname $(which 
openssl))/
 [[ -f ${IASL_PREFIX}iasl ]] || (echo "IASL not found! Please specify 
IASL_PREFIX!";exit -1)
-[[ -f ${IASL_PREFIX}nasm ]] || (echo "NASM not found! Please specify 
NASM_PREFIX!";exit -1)
+[[ -f ${NASM_PREFIX}nasm ]] || (echo "NASM not found! Please specify 
NASM_PREFIX!";exit -1)
+[[ -f ${OPENSSL_PATH}openssl ]] || (echo "OpenSSL not found! Please specify 
OPENSSL_PATH!";exit -1)
+
+echo "IASL version $(LC_ALL=C ${IASL_PREFIX}iasl -v | sed -n '3,3p' | cut -d' 
' -f5) detected."
+echo "NASM version $(LC_ALL=C ${NASM_PREFIX}nasm --version | head -n1 | cut 
-d' ' -f3) detected."
+echo "OpenSSL version $(LC_ALL=C ${OPENSSL_PATH}openssl version | head -n1 | 
cut -d' ' -f2) detected."
+
 if [ ${TOOLCHAIN_TAG} != "CLANGPDB" ]
 then
 [[ "${GCC5_BIN}" == "" ]]   && export GCC5_BIN=$(dirname $(which gcc))/
@@ -174,4 +185,11 @@ python3 FlashABImage32M.py ${F1_ECSIG} ${F2_EC} ${F3_EFS} 
${F4_PSP_L1_DIRECTORY}
 ${F6_SLOT_HEADER_1} ${F7_SLOT_HEADER_2} ${F8_SLOT_A} ${F9_SLOT_B} 
${F10_OUT_IMAGE}
 popd

+echo_section "Generating Capsule image"
+rm -r 
${WORKSPACE}/Build/ChachaniBoardPkg/${BUILD_TYPE}_${TOOLCHAIN_TAG}/FV/SYSTEMFIRMWAREUPDATECARGO*
+touch 
${WORKSPACE}/Build/ChachaniBoardPkg/${BUILD_TYPE}_${TOOLCHAIN_TAG}/FV/SYSTEMFIRMWAREUPDATECARGO.Fv
+build -p ${PROJECT_PKG}/PlatformCapsule.dsc -t ${TOOLCHAIN_TAG} -b 
${BUILD_TYPE} -D BIOS_FILE=${BIOSNAME}UDK.FD
+[[ $? -ne 0 ]] && exit -1
+cp 
${WORKSPACE}/Build/ChachaniBoardPkg/${BUILD_TYPE}_${TOOLCHAIN_TAG}/FV/${OTA_CAPSULE_NAME}.Cap
 .
+
 echo_section "Build success @ $(date)"
--
2.31.1



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[edk2-devel] [PATCH 1/4] AMD/AmdPlatformPkg: Use HpetTimerDxe to replace 8254Timer.

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4718
As the new EDK2 no supports 8254 timer, so used HpetTimer to replace it.

Cc: Abner Chang 
Cc: Igniculus Fu 
Reviewed-by: Ken Yao 
Reviewed-by: Eric Xing 
Signed-off-by: Duke Zhai 
---
 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc | 2 --
 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf | 3 +--
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
index 510ce10c0c..20f06dd851 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
@@ -745,8 +745,6 @@
   MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
   FatPkg/EnhancedFatDxe/Fat.inf
   PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
-  OvmfPkg/8259InterruptControllerDxe/8259.inf
-  OvmfPkg/8254TimerDxe/8254Timer.inf
   
MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf
   
MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf

diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf
index 5194a8c10d..0d844689b3 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf
@@ -416,8 +416,7 @@ NumBlocks = 0x100
   # Platform
   #
   INF  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
-  INF  OvmfPkg/8259InterruptControllerDxe/8259.inf
-  INF  OvmfPkg/8254TimerDxe/8254Timer.inf
+  INF  PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf

   #
   # ACPI
--
2.31.1



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[edk2-devel] [PATCH 2/4] AMD/AmdPlatformPkg: Fix Bug Microcode version cannot show correctly at BIOS setup

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4719
Microcode not load correct cause BIOS setup not show microcode version, modify 
Microcode binary's instance to fixed this issue.

Cc: Abner Chang 
Cc: Igniculus Fu 
Reviewed-by: Ken Yao 
Reviewed-by: Eric Xing 
Signed-off-by: Duke Zhai 
---
 .../AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml
index 22af6623e2..585e12d487 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml
@@ -57,7 +57,7 @@
 
 
 
-
+
 
   
 
--
2.31.1



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[edk2-devel] [PATCH 0/4] Update Vangogh platform reference code

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

1. Use HPET timer to replace 8254 timer
2.Fix Bug Microcode version cannot show correctly at BIOS setup
3.Enable capsule at linux build
4.Update FspWrapper UPD table for BIOS setup options

Duke Zhai (4):
  AMD/AmdPlatformPkg: Use HpetTimerDxe to replace 8254Timer.
  AMD/AmdPlatformPkg: Fix Bug Microcode version cannot show correctly at
BIOS setup
  AMD/AmdPlatformPkg: Enable capsule at linux build
  AMD/AmdPlatformPkg: Update FspWrapper UPD table for BIOS setup options

 .../BIOSImageDirectory32M.xml |  2 +-
 .../ChachaniBoardPkg/GenCapsule.bat   |  2 +-
 .../VanGoghBoard/ChachaniBoardPkg/Project.dsc |  2 -
 .../VanGoghBoard/ChachaniBoardPkg/Project.fdf |  3 +-
 .../VanGoghBoard/ChachaniBoardPkg/build.sh| 22 +-
 .../edk2/Fsp2WrapperPkg/Include/FspmUpd.h | 71 ++-
 .../FspWrapperPlatformLibSample.c | 29 
 7 files changed, 59 insertions(+), 72 deletions(-)

--
2.31.1



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[edk2-devel] [PATCH V3 32/32] AMD/VanGoghBoard: Check in Chachani board project files and build script

[Zhai, MingXin (Duke) via groups.io]

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[edk2-devel] [PATCH V3 31/32] AMD/VanGoghBoard: Check in AMD SmmControlPei module

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial AMD SmmControlPei module in Silicon folder.
  This module initializes SMM-related registers, and installs gPeiSmmControlPpi.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Smm/SmmControlPei/SmmControlPei.c | 307 ++
 .../Smm/SmmControlPei/SmmControlPei.inf   |  40 +++
 2 files changed, 347 insertions(+)
 create mode 100644 Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c
 create mode 100644 Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.inf

diff --git a/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c 
b/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c
new file mode 100644
index 00..4752aede9c
--- /dev/null
+++ b/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c
@@ -0,0 +1,307 @@
+/** @file
+  Implements SmmControlPei.c
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  This routine generates an SMI
+
+  @param[in]   PeiServices   Describes the list of possible PEI 
Services.
+  @param[in]   This  The pointer to this instance of this 
PPI.
+  @param[in, out]  ArgumentBufferThe buffer of argument
+  @param[in, out]  ArgumentBufferSizeThe size of the argument buffer
+  @param[in]   Periodic  TRUE to indicate a periodical SMI
+  @param[in]   ActivationIntervalInterval of periodic SMI
+
+  @retval  EFI_SUCCESSSMI generated.
+  @retval  EFI_INVALID_PARAMETER  Some parameter value passed is not supported
+**/
+EFI_STATUS
+EFIAPI
+PeiTrigger (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_SMM_CONTROL_PPI  *This,
+  IN OUT INT8 *ArgumentBuffer OPTIONAL,
+  IN OUT UINTN*ArgumentBufferSize OPTIONAL,
+  IN BOOLEAN  Periodic OPTIONAL,
+  IN UINTNActivationInterval OPTIONAL
+  );
+
+/**
+  Clear SMI related chipset status.
+
+  @param[in]  PeiServices   Describes the list of possible PEI 
Services.
+  @param[in]  This  The pointer to this instance of this PPI.
+  @param[in]  Periodic  TRUE to indicate a periodical SMI.
+
+  @return  Return value from ClearSmi()
+**/
+EFI_STATUS
+EFIAPI
+PeiClear (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_SMM_CONTROL_PPI  *This,
+  IN BOOLEAN  Periodic OPTIONAL
+  );
+
+STATIC PEI_SMM_CONTROL_PPI  mSmmControlPpi = {
+  PeiTrigger,
+  PeiClear
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR  mPpiList = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  
+};
+
+/**
+ Init related registers
+
+ @param [in]None
+
+ @retval  EFI_LOAD_ERROR  Get ACPI MMIO base error.
+ @retval  EFI_SUCCESS The function completed successfully..
+*/
+EFI_STATUS
+SmmControlPeiPreInit (
+  VOID
+  )
+{
+  UINT16  SmmControlData16;
+  UINT16  SmmControlMask16;
+  UINT32  SmmControlData32;
+  UINT8   SmmControlIndex;
+  UINT16  AcpiPmBase;
+
+  //
+  // Get ACPI MMIO base and AcpiPm1EvtBlk address
+  //
+  AcpiPmBase = MmioRead16 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60);
+
+  if (0 == AcpiPmBase) {
+return EFI_LOAD_ERROR;
+  }
+
+  //
+  // Clean up all SMI status and enable bits
+  //
+  // Clear all SmiControl registers
+  SmmControlData32 = 0;
+  for (SmmControlIndex = FCH_SMI_REGA0; SmmControlIndex <= FCH_SMI_REGC4; 
SmmControlIndex += 4) {
+MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + SmmControlIndex, 
SmmControlData32);
+  }
+
+  // Clear all SmiStatus registers (SmiStatus0-4)
+  SmmControlData32 = 0x;
+  MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG80, SmmControlData32);
+  MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG84, SmmControlData32);
+  MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG88, SmmControlData32);
+  MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG8C, SmmControlData32);
+  MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG90, SmmControlData32);
+
+  //
+  // If SCI is not enabled, clean up all ACPI PM status/enable registers
+  //
+  SmmControlData16 = IoRead16 (AcpiPmBase + R_FCH_ACPI_PM_CONTROL);
+  if (!(SmmControlData16 & BIT0)) {
+// Clear WAKE_EN, RTC_EN, SLPBTN_EN, GBL_EN and TMR_EN
+SmmControlData16 = 0;
+SmmControlMask16 = (UINT16) ~(BIT15 + BIT10 + BIT9 + BIT5 + BIT0);
+IoAndThenOr16 (AcpiPmBase + R_FCH_ACPI_PM1_ENABLE, SmmControlMask16, 
SmmControlData16);
+
+// Clear WAKE_STS, RTC_STS, SLPBTN_STS, GBL_STS and TMR_STS
+SmmControlData16 = BIT15 + BIT10 + BIT9 + BIT5 + BIT0;
+IoWrite16 

[edk2-devel] [PATCH V3 29/32] AMD/VanGoghBoard: Check in SmramSaveState module

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial SmramSaveState module.
  This module provides services to access SMRAM Save State Map.

Signed-off-by: Ken Yao 
Cc: Eric Xing 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../PiSmmCpuDxeSmm/SmramSaveState.c   | 706 ++
 1 file changed, 706 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c

diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
new file mode 100644
index 00..ca63de9ba6
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -0,0 +1,706 @@
+/** @file
+Provides services to access SMRAM Save State Map
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "PiSmmCpuDxeSmm.h"
+
+typedef struct {
+  UINT64Signature;  // Offset 0x00
+  UINT16Reserved1;  // Offset 0x08
+  UINT16Reserved2;  // Offset 0x0A
+  UINT16Reserved3;  // Offset 0x0C
+  UINT16SmmCs;  // Offset 0x0E
+  UINT16SmmDs;  // Offset 0x10
+  UINT16SmmSs;  // Offset 0x12
+  UINT16SmmOtherSegment;// Offset 0x14
+  UINT16Reserved4;  // Offset 0x16
+  UINT64Reserved5;  // Offset 0x18
+  UINT64Reserved6;  // Offset 0x20
+  UINT64Reserved7;  // Offset 0x28
+  UINT64SmmGdtPtr;  // Offset 0x30
+  UINT32SmmGdtSize; // Offset 0x38
+  UINT32Reserved8;  // Offset 0x3C
+  UINT64Reserved9;  // Offset 0x40
+  UINT64Reserved10; // Offset 0x48
+  UINT16Reserved11; // Offset 0x50
+  UINT16Reserved12; // Offset 0x52
+  UINT32Reserved13; // Offset 0x54
+  UINT64Reserved14; // Offset 0x58
+} PROCESSOR_SMM_DESCRIPTOR;
+
+extern CONST PROCESSOR_SMM_DESCRIPTOR  gcPsd;
+
+//
+// EFER register LMA bit
+//
+#define LMA  BIT10
+
+///
+/// Macro used to simplify the lookup table entries of type 
CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
+///
+#define SMM_CPU_OFFSET(Field)  OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
+
+///
+/// Macro used to simplify the lookup table entries of type 
CPU_SMM_SAVE_STATE_REGISTER_RANGE
+///
+#define SMM_REGISTER_RANGE(Start, End)  { Start, End, End - Start + 1 }
+
+///
+/// Structure used to describe a range of registers
+///
+typedef struct {
+  EFI_SMM_SAVE_STATE_REGISTERStart;
+  EFI_SMM_SAVE_STATE_REGISTEREnd;
+  UINTN  Length;
+} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
+
+///
+/// Structure used to build a lookup table to retrieve the widths and offsets
+/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
+///
+
+#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX   1
+#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2
+#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX  3
+#define SMM_SAVE_STATE_REGISTER_MAX_INDEX4
+
+typedef struct {
+  UINT8  Width32;
+  UINT8  Width64;
+  UINT16 Offset32;
+  UINT16 Offset64Lo;
+  UINT16 Offset64Hi;
+  BOOLEANWriteable;
+} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
+
+///
+/// Structure used to build a lookup table for the IOMisc width information
+///
+typedef struct {
+  UINT8  Width;
+  EFI_SMM_SAVE_STATE_IO_WIDTHIoWidth;
+} CPU_SMM_SAVE_STATE_IO_WIDTH;
+
+///
+/// Variables from SMI Handler
+///
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmbase;
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmiStack;
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmiCr3;
+extern volatile UINT8 gcSmiHandlerTemplate[];
+extern CONST UINT16   gcSmiHandlerSize;
+
+//
+// Variables used by SMI Handler
+//
+IA32_DESCRIPTOR  gSmiHandlerIdtr;
+
+///
+/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
+/// 

[edk2-devel] [PATCH V3 28/32] AMD/VanGoghBoard: Check in SmmCpuFeaturesLibCommon module

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial SmmCpuFeaturesLibCommon module. The CPU specific programming for
  PiSmmCpuDxeSmm module when STM support is not included.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../SmmCpuFeaturesLibCommon.c | 623 ++
 1 file changed, 623 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c

diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
new file mode 100644
index 00..f3615e2d9e
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
@@ -0,0 +1,623 @@
+/** @file
+Implementation shared across all library instances.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) Microsoft Corporation.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "CpuFeaturesLib.h"
+
+//
+// Machine Specific Registers (MSRs)
+//
+#define  SMM_FEATURES_LIB_IA32_MTRR_CAP0x0FE
+#define  SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A
+#define  SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE   0x1F2
+#define  SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK   0x1F3
+#define  SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE  0x0A0
+#define  SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK  0x0A1
+#defineEFI_MSR_SMRR_MASK   0xF000
+#defineEFI_MSR_SMRR_PHYS_MASK_VALIDBIT11
+#define  SMM_FEATURES_LIB_SMM_FEATURE_CONTROL  0x4E0
+
+//
+// MSRs required for configuration of SMM Code Access Check
+//
+#define SMM_FEATURES_LIB_IA32_MCA_CAP  0x17D
+#define   SMM_CODE_ACCESS_CHK_BIT  BIT58
+
+extern UINT8  mSmmSaveStateRegisterLma;
+
+//
+// Set default value to assume SMRR is not supported
+//
+BOOLEAN  mSmrrSupported = FALSE;
+
+//
+// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported
+//
+BOOLEAN  mSmmFeatureControlSupported = FALSE;
+
+//
+// Set default value to assume IA-32 Architectural MSRs are used
+//
+UINT32  mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;
+UINT32  mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;
+
+//
+// Set default value to assume MTRRs need to be configured on each SMI
+//
+BOOLEAN  mNeedConfigureMtrrs = TRUE;
+
+//
+// Array for state of SMRR enable on all CPUs
+//
+BOOLEAN  *mSmrrEnabled;
+
+/**
+  Performs library initialization.
+
+  This initialization function contains common functionality shared betwen all
+  library instance constructors.
+
+**/
+VOID
+CpuFeaturesLibInitialization (
+  VOID
+  )
+{
+  UINT32  RegEax;
+  UINT32  RegEdx;
+  UINTN   FamilyId;
+  UINTN   ModelId;
+
+  //
+  // Retrieve CPU Family and Model
+  //
+  AsmCpuid (CPUID_VERSION_INFO, , NULL, NULL, );
+  FamilyId = (RegEax >> 8) & 0xf;
+  ModelId  = (RegEax >> 4) & 0xf;
+  if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
+ModelId = ModelId | ((RegEax >> 12) & 0xf0);
+  }
+
+  //
+  // Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability
+  //
+  if ((RegEdx & BIT12) != 0) {
+//
+// Check MTRR_CAP MSR bit 11 for SMRR support
+//
+if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {
+  mSmrrSupported = TRUE;
+}
+  }
+
+  //
+  // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+  // Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family
+  //
+  // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then
+  // SMRR Physical Base and SMM Physical Mask MSRs are not available.
+  //
+  if (FamilyId == 0x06) {
+if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) || 
(ModelId == 0x35) || (ModelId == 0x36)) {
+  mSmrrSupported = FALSE;
+}
+  }
+
+  //
+  // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+  // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
+  //
+  // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2
+  // Processor Family MSRs
+  //
+  if (FamilyId == 0x06) {
+if ((ModelId == 0x17) || (ModelId == 0x0f)) {
+  mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;
+  mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;
+}
+  }
+
+  //
+  // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+  // Volume 3C, Section 34.4.2 SMRAM 

[edk2-devel] [PATCH V3 26/32] AMD/VanGoghBoard: Check in Smbios platform dxe drivers

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial Smbios platform DXE drivers. Static SMBIOS Table for Chachani 
platform.
  SmbiosLib provides detailed information of Chachani platform.

Signed-off-by: Eric Xing 
Cc: Ken Yao 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../PlatformSmbiosDxe/PlatformSmbiosDxe.c |  75 
 .../PlatformSmbiosDxe/PlatformSmbiosDxe.inf   |  52 +++
 .../Universal/PlatformSmbiosDxe/SmbiosTable.c | 382 ++
 3 files changed, 509 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/SmbiosTable.c

diff --git 
a/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.c 
b/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.c
new file mode 100644
index 00..c4de6ca133
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.c
@@ -0,0 +1,75 @@
+/** @file
+  Static SMBIOS Table for platform
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2012, Apple Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+extern SMBIOS_TEMPLATE_ENTRY  gSmbiosTemplate[];
+
+/**
+  Main entry for this driver.
+
+  @param ImageHandle Image handle this driver.
+  @param SystemTable Pointer to SystemTable.
+
+  @retval EFI_SUCESS This function always complete successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformSmbiosDriverEntryPoint (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUSStatus;
+  EFI_SMBIOS_HANDLE SmbiosHandle;
+  SMBIOS_STRUCTURE_POINTER  Smbios;
+
+  DEBUG ((DEBUG_INFO, " PlatfomrSmbiosDriverEntryPoint \n"));
+
+  // Phase 0 - Patch table to make SMBIOS 2.7 structures smaller to conform
+  //   to an early version of the specification.
+
+  // Phase 1 - Initialize SMBIOS tables from template
+  Status = SmbiosLibInitializeFromTemplate (gSmbiosTemplate);
+  ASSERT_EFI_ERROR (Status);
+
+  // Phase 2 - Patch SMBIOS table entries
+  Smbios.Hdr = SmbiosLibGetRecord (EFI_SMBIOS_TYPE_BIOS_INFORMATION, 0, 
);
+  if (Smbios.Type0 != NULL) {
+// 64K * (n+1) bytes
+Smbios.Type0->BiosSize = (UINT8)DivU64x32 (FixedPcdGet64 
(PcdFlashAreaSize), 64*1024) - 1;
+
+SmbiosLibUpdateUnicodeString (
+  SmbiosHandle,
+  Smbios.Type0->BiosVersion,
+  (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString)
+  );
+
+DEBUG ((
+  DEBUG_INFO,
+  " Smbios.Type0->BiosSize: %dMB, Smbios.Type0->BiosVersion: %S, Build 
Time: %a,%a\n",
+  (Smbios.Type0->BiosSize +1) * 64 / 1024,
+  (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),
+  __DATE__,
+  __TIME__
+  ));
+  }
+
+  return EFI_SUCCESS;
+}
diff --git 
a/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.inf 
b/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
new file mode 100644
index 00..1f4fefeaa2
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
@@ -0,0 +1,52 @@
+## @file
+# Platform SMBIOS driver that fills in SMBIOS table entries.
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2012, Apple Inc. All rights reserved.
+# Portions copyright (c) 2006 - 2010, Intel Corporation. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = PlatformSmbiosDxe
+  FILE_GUID  = 15EEEB97-709E-91FA-CDA7-44A9C85DDB78
+  MODULE_TYPE= DXE_DRIVER
+  VERSION_STRING = 1.0
+  ENTRY_POINT= PlatformSmbiosDriverEntryPoint
+
+
+[Sources]
+  SmbiosTable.c
+  PlatformSmbiosDxe.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  VanGoghCommonPkg/AmdCommonPkg.dec
+  ChachaniBoardPkg/Project.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  PcdLib
+  MemoryAllocationLib
+  UefiBootServicesTableLib
+  UefiLib
+  HobLib
+  SmbiosLib
+
+[Protocols]
+  gEfiSmbiosProtocolGuid
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString
+  

[edk2-devel] [PATCH V3 25/32] AMD/VanGoghBoard: Check in PlatformInitPei module

[Zhai, MingXin (Duke) via groups.io]

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[edk2-devel] [PATCH V3 24/32] AMD/VanGoghBoard: Check in FchSpi module

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial FchSpi module. FCH SPI Common Driver implements
  the SPI Host Controller Compatibility Interface.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Universal/FchSpi/FchSpiProtect.c  |  67 ++
 .../Universal/FchSpi/FchSpiProtect.h  |  38 +
 .../Universal/FchSpi/FchSpiRuntimeDxe.c   | 163 
 .../Universal/FchSpi/FchSpiRuntimeDxe.h   |  49 ++
 .../Universal/FchSpi/FchSpiRuntimeDxe.inf |  84 ++
 .../VanGoghBoard/Universal/FchSpi/FchSpiSmm.c | 112 +++
 .../VanGoghBoard/Universal/FchSpi/FchSpiSmm.h |  32 +
 .../Universal/FchSpi/FchSpiSmm.inf|  94 +++
 .../VanGoghBoard/Universal/FchSpi/SpiCommon.c | 790 ++
 .../VanGoghBoard/Universal/FchSpi/SpiInfo.h   |  24 +
 10 files changed, 1453 insertions(+)
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.c
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.h
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.h
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.inf
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiSmm.c
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiSmm.h
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiSmm.inf
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/SpiCommon.c
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/SpiInfo.h

diff --git a/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.c 
b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.c
new file mode 100644
index 00..658d9b063d
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.c
@@ -0,0 +1,67 @@
+/** @file
+  Implements FchSpiProtect.c
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "FchSpiProtect.h"
+
+/**
+
+   Fch Spi Protect Lock
+
+   @param SpiMmioBase
+
+**/
+EFI_STATUS
+EFIAPI
+FchSpiProtect_Lock (
+  IN UINTN  SpiMmioBase
+  )
+{
+  if (!(MmioRead8 (SpiMmioBase + 2) & 0xC0)) {
+// Check BIT7+BIT6
+return EFI_SUCCESS;
+  } else {
+MmioWrite8 (SpiMmioBase + 9, 0x6);// 
PrefixOpCode WRITE_ENABLE
+MmioWrite8 (SpiMmioBase + 2, MmioRead8 (SpiMmioBase + 2) & 0x3F); // Clear 
BIT7+BIT6
+if (MmioRead8 (SpiMmioBase + 2) & 0xC0) {
+  return EFI_DEVICE_ERROR;
+}
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+
+   Fch Spi Protect UnLock
+
+   @param SpiMmioBase
+
+**/
+EFI_STATUS
+EFIAPI
+FchSpiProtect_UnLock (
+  IN UINTN  SpiMmioBase
+  )
+{
+  if ((MmioRead8 (SpiMmioBase + 2) & 0xC0) || (6 != MmioRead8 (SpiMmioBase + 
9))) {
+return EFI_SUCCESS;
+  } else {
+MmioWrite8 (SpiMmioBase + 9, 0x0);
+MmioWrite8 (SpiMmioBase + 2, MmioRead8 (SpiMmioBase + 2) | 0xC0); // Set 
BIT7+BIT6
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.h 
b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.h
new file mode 100644
index 00..e46a1a066a
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.h
@@ -0,0 +1,38 @@
+/** @file
+  Implements FchSpiProtect.h
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef FCH_SPI_PROTECT_H_
+#define FCH_SPI_PROTECT_H_
+
+/**
+
+   Fch Spi Protect Lock
+
+   @param UINTN SpiMmioBase
+
+**/
+EFI_STATUS
+EFIAPI
+FchSpiProtect_Lock (
+  IN UINTN  SpiMmioBase
+  );
+
+/**
+
+   Fch Spi Protect UnLock
+
+   @param UINTN SpiMmioBase
+
+**/
+EFI_STATUS
+EFIAPI
+FchSpiProtect_UnLock (
+  IN UINTN  SpiMmioBase
+  );
+
+#endif
diff --git a/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.c 
b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.c
new file mode 100644
index 00..7bb402402c
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.c
@@ -0,0 +1,163 @@
+/** @file
+PCH SPI Runtime Driver implements the SPI Host Controller Compatibility 
Interface.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2015 Intel Corporation.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifdef _MSC_VER
+  

[edk2-devel] [PATCH V3 23/32] AMD/VanGoghBoard: Check in AcpiPlatform

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial Acpi platform dxe drivers. Use firmware volume protocol
  to update global NVS area for ASL and SMM init code.

Signed-off-by: Eric Xing 
Cc: Ken Yao 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Universal/AcpiPlatformDxe/AcpiPlatform.c  | 336 ++
 .../AcpiPlatformDxe/AcpiPlatform.uni  |  15 +
 .../AcpiPlatformDxe/AcpiPlatformDxe.inf   |  59 +++
 .../AcpiPlatformDxe/AcpiPlatformExtra.uni |  13 +
 .../AcpiPlatformDxe/AcpiPlatformHooks.c   | 152 
 .../AcpiPlatformDxe/AcpiPlatformHooks.h   |  48 +++
 6 files changed, 623 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatformDxe.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatformExtra.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatformHooks.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatformHooks.h

diff --git a/Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.c 
b/Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.c
new file mode 100644
index 00..73a022594e
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.c
@@ -0,0 +1,336 @@
+/** @file
+  Sample ACPI Platform Driver
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "AcpiPlatformHooks.h"
+#include 
+
+EFI_GLOBAL_NVS_AREA_PROTOCOL  mGlobalNvsArea;
+
+/**
+  Locate the first instance of a protocol.  If the protocol requested is an
+  FV protocol, then it will return the first FV that contains the ACPI table
+  storage file.
+
+  @param  Instance  Return pointer to the first instance of the protocol
+
+  @return EFI_SUCCESS   The function completed successfully.
+  @return EFI_NOT_FOUND The protocol could not be located.
+  @return EFI_OUT_OF_RESOURCES  There are not enough resources to find the 
protocol.
+
+**/
+EFI_STATUS
+LocateFvInstanceWithTables (
+  OUT EFI_FIRMWARE_VOLUME2_PROTOCOL  **Instance
+  )
+{
+  EFI_STATUS Status;
+  EFI_HANDLE *HandleBuffer;
+  UINTN  NumberOfHandles;
+  EFI_FV_FILETYPEFileType;
+  UINT32 FvStatus;
+  EFI_FV_FILE_ATTRIBUTES Attributes;
+  UINTN  Size;
+  UINTN  Index;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL  *FvInstance;
+
+  FvStatus = 0;
+
+  //
+  // Locate protocol.
+  //
+  Status = gBS->LocateHandleBuffer (
+  ByProtocol,
+  ,
+  NULL,
+  ,
+  
+  );
+  if (EFI_ERROR (Status)) {
+//
+// Defined errors at this time are not found and out of resources.
+//
+return Status;
+  }
+
+  //
+  // Looking for FV with ACPI storage file
+  //
+
+  for (Index = 0; Index < NumberOfHandles; Index++) {
+//
+// Get the protocol on this handle
+// This should not fail because of LocateHandleBuffer
+//
+Status = gBS->HandleProtocol (
+HandleBuffer[Index],
+,
+(VOID **)
+);
+ASSERT_EFI_ERROR (Status);
+
+//
+// See if it has the ACPI storage file
+//
+Status = FvInstance->ReadFile (
+   FvInstance,
+   (EFI_GUID *)PcdGetPtr (PcdAcpiTableStorageFile),
+   NULL,
+   ,
+   ,
+   ,
+   
+   );
+
+//
+// If we found it, then we are done
+//
+if (Status == EFI_SUCCESS) {
+  *Instance = FvInstance;
+  break;
+}
+  }
+
+  //
+  // Our exit status is determined by the success of the previous operations
+  // If the protocol was found, Instance already points to it.
+  //
+
+  //
+  // Free any allocated buffers
+  //
+  gBS->FreePool (HandleBuffer);
+
+  return Status;
+}
+
+/**
+  This function calculates and updates an 

[edk2-devel] [PATCH V3 22/32] AMD/VanGoghBoard: Check in Vtf0

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial Vtf0 module.
  This module includes all assembly code files of reset vector.

Signed-off-by: Eric Xing 
Cc: Ken Yao 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../ResetVector/Vtf0/CommonMacros.inc |  27 +++
 .../ResetVector/Vtf0/DebugDisabled.asm|  21 ++
 .../ResetVector/Vtf0/Ia16/Init16.asm  |  51 +
 .../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm  | 138 +
 .../ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm | 108 ++
 .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm  |  40 
 .../ResetVector/Vtf0/Ia32/PageTables64.asm|  25 +++
 .../Vtf0/Ia32/SearchForBfvBase.asm|  84 
 .../Vtf0/Ia32/SearchForSecEntry.asm   | 195 ++
 .../edk2/UefiCpuPkg/ResetVector/Vtf0/Main.asm | 127 
 .../ResetVector/Vtf0/Port80Debug.asm  |  23 +++
 .../UefiCpuPkg/ResetVector/Vtf0/PostCodes.inc |  20 ++
 .../ResetVector/Vtf0/ResetVector.uni  | Bin 0 -> 780 bytes
 .../ResetVector/Vtf0/ResetVectorExtra.uni | Bin 0 -> 682 bytes
 .../ResetVector/Vtf0/SerialDebug.asm  | 127 
 .../edk2/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf |  37 
 .../UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb|  67 ++
 .../ResetVector/Vtf0/X64/PageTables.asm   |  73 +++
 18 files changed, 1163 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/DebugDisabled.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia16/Init16.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForBfvBase.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForSecEntry.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Main.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Port80Debug.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/PostCodes.inc
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/ResetVector.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/ResetVectorExtra.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/SerialDebug.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm

diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc
 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc
new file mode 100644
index 00..5da472faaa
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc
@@ -0,0 +1,27 @@
+;--
+; @file
+; Common macros used in the ResetVector VTF module.
+;
+; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;--
+
+%define ADDR16_OF(x) (0x1 - fourGigabytes + x)
+%define ADDR_OF(x) (0x1 - fourGigabytes + x)
+%define ADDR_OF_MEM(x) (VIRTUAL4G - fourGigabytes + x)
+%define SMM_RESUME_SIGNATURE 0x55AABB66
+%macro  OneTimeCall 1
+jmp %1
+%1 %+ OneTimerCallReturn:
+%endmacro
+
+%macro  OneTimeCallRet 1
+jmp %1 %+ OneTimerCallReturn
+%endmacro
+
+StartOfResetVectorCode:
+
+%define ADDR_OF_START_OF_RESET_CODE ADDR_OF(StartOfResetVectorCode)
+
diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/DebugDisabled.asm
 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/DebugDisabled.asm
new file mode 

[edk2-devel] [PATCH V3 21/32] AMD/VanGoghBoard: Check in SignedCapsule

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial SignedCapsule module for Signed Capsule.
  Produce FMP instance to update system firmware.

Signed-off-by: Ken Yao 
Cc: Eric Xing 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../BaseTools/Source/Python/GenFds/Capsule.py |  253 +++
 .../SystemFirmwareUpdate/ParseConfigProfile.c |  217 +++
 .../SystemFirmwareCommonDxe.c |  371 +
 .../SystemFirmwareUpdate/SystemFirmwareDxe.h  |  421 +
 .../SystemFirmwareUpdateDxe.c | 1426 +
 .../SystemFirmwareUpdateDxe.inf   |   77 +
 .../SystemFirmwareUpdateDxe.uni   |   15 +
 .../SystemFirmwareUpdateDxeExtra.uni  |   15 +
 8 files changed, 2795 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/BaseTools/Source/Python/GenFds/Capsule.py
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/ParseConfigProfile.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareCommonDxe.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareDxe.h
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxeExtra.uni

diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/BaseTools/Source/Python/GenFds/Capsule.py
 
b/Platform/AMD/VanGoghBoard/Override/edk2/BaseTools/Source/Python/GenFds/Capsule.py
new file mode 100644
index 00..0ec0b3ca43
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/Override/edk2/BaseTools/Source/Python/GenFds/Capsule.py
@@ -0,0 +1,253 @@
+## @file
+# generate capsule
+#
+#  Copyright (C) 2024 Advanced Micro Devices, Inc.
+#  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+##
+# Import Modules
+#
+from __future__ import absolute_import
+from .GenFdsGlobalVariable import GenFdsGlobalVariable, FindExtendTool
+from CommonDataClass.FdfClass import CapsuleClassObject
+import Common.LongFilePathOs as os
+from io import BytesIO
+from Common.Misc import SaveFileOnChange, PackGUID
+import uuid
+from struct import pack
+from Common import EdkLogger
+from Common.BuildToolError import GENFDS_ERROR
+from Common.DataType import TAB_LINE_BREAK
+
+WIN_CERT_REVISION = 0x0200
+WIN_CERT_TYPE_EFI_GUID = 0x0EF1
+EFI_CERT_TYPE_PKCS7_GUID = uuid.UUID('{4aafd29d-68df-49ee-8aa9-347d375665a7}')
+EFI_CERT_TYPE_RSA2048_SHA256_GUID = 
uuid.UUID('{a7717414-c616-4977-9420-844712a735bf}')
+
+## create inf file describes what goes into capsule and call GenFv to generate 
capsule
+#
+#
+class Capsule (CapsuleClassObject):
+## The constructor
+#
+#   @param  selfThe object pointer
+#
+def __init__(self):
+CapsuleClassObject.__init__(self)
+# For GenFv
+self.BlockSize = None
+# For GenFv
+self.BlockNum = None
+self.CapsuleName = None
+
+## Generate FMP capsule
+#
+#   @retval string  Generated Capsule file path
+#
+def GenFmpCapsule(self):
+#
+# Generate capsule header
+# typedef struct {
+# EFI_GUID  CapsuleGuid;
+# UINT32HeaderSize;
+# UINT32Flags;
+# UINT32CapsuleImageSize;
+# } EFI_CAPSULE_HEADER;
+#
+Header = BytesIO()
+#
+# Use FMP capsule GUID: 6DCBD5ED-E82D-4C44-BDA1-7194199AD92A
+#
+
Header.write(PackGUID('6DCBD5ED-E82D-4C44-BDA1-7194199AD92A'.split('-')))
+HdrSize = 0
+if 'CAPSULE_HEADER_SIZE' in self.TokensDict:
+Header.write(pack('=I', 
int(self.TokensDict['CAPSULE_HEADER_SIZE'], 16)))
+HdrSize = int(self.TokensDict['CAPSULE_HEADER_SIZE'], 16)
+else:
+Header.write(pack('=I', 0x20))
+HdrSize = 0x20
+Flags = 0
+if 'CAPSULE_FLAGS' in self.TokensDict:
+for flag in self.TokensDict['CAPSULE_FLAGS'].split(','):
+  

[edk2-devel] [PATCH V3 19/32] AMD/VanGoghBoard: Check in PcatRealTimeClockRuntimeDxe module

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  This driver provides GetTime, SetTime, GetWakeupTime, SetWakeupTime services 
to Runtime Service Table.
  It will install a tagging protocol with gEfiRealTimeClockArchProtocolGuid.

Signed-off-by: Ken Yao 
Cc: Eric Xing 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../PcatRealTimeClockRuntimeDxe/PcRtc.c   | 1341 +
 .../PcatRealTimeClockRuntimeDxe/PcRtc.h   |  374 +
 .../PcatRealTimeClockRuntimeDxe/PcRtc.uni |   17 +
 .../PcatRealTimeClockRuntimeDxe/PcRtcEntry.c  |  171 +++
 .../PcRtcExtra.uni|   15 +
 .../PcatRealTimeClockRuntimeDxe.inf   |   77 +
 6 files changed, 1995 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcExtra.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf

diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
 
b/Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
new file mode 100644
index 00..4e42d9d2ad
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
@@ -0,0 +1,1341 @@
+/** @file
+  RTC Architectural Protocol GUID as defined in DxeCis 0.96.
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PcRtc.h"
+
+//
+// Days of month.
+//
+UINTN  mDayOfMonth[] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+//
+// The name of NV variable to store the timezone and daylight saving 
information.
+//
+CHAR16  mTimeZoneVariableName[] = L"RTC";
+
+/**
+  Compare the Hour, Minute and Second of the From time and the To time.
+
+  Only compare H/M/S in EFI_TIME and ignore other fields here.
+
+  @param From   the first time
+  @param To the second time
+
+  @return  >0   The H/M/S of the From time is later than those of To time
+  @return  ==0  The H/M/S of the From time is same as those of To time
+  @return  <0   The H/M/S of the From time is earlier than those of To time
+**/
+INTN
+CompareHMS (
+  IN EFI_TIME  *From,
+  IN EFI_TIME  *To
+  );
+
+/**
+  To check if second date is later than first date within 24 hours.
+
+  @param  From   the first date
+  @param  To the second date
+
+  @retval TRUE   From is previous to To within 24 hours.
+  @retval FALSE  From is later, or it is previous to To more than 24 hours.
+**/
+BOOLEAN
+IsWithinOneDay (
+  IN EFI_TIME  *From,
+  IN EFI_TIME  *To
+  );
+
+/**
+  Read RTC content through its registers.
+
+  @param  Address  Address offset of RTC. It is recommended to use macros such 
as
+   RTC_ADDRESS_SECONDS.
+
+  @return The data of UINT8 type read from RTC.
+**/
+UINT8
+RtcRead (
+  IN  UINT8  Address
+  )
+{
+  IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, (UINT8)(Address | (UINT8)(IoRead8 
(PCAT_RTC_ADDRESS_REGISTER) & 0x80)));
+  return IoRead8 (PCAT_RTC_DATA_REGISTER);
+}
+
+/**
+  Write RTC through its registers.
+
+  @param  Address  Address offset of RTC. It is recommended to use macros such 
as
+   RTC_ADDRESS_SECONDS.
+  @param  Data The content you want to write into RTC.
+
+**/
+VOID
+RtcWrite (
+  IN  UINT8  Address,
+  IN  UINT8  Data
+  )
+{
+  IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, (UINT8)(Address | (UINT8)(IoRead8 
(PCAT_RTC_ADDRESS_REGISTER) & 0x80)));
+  IoWrite8 (PCAT_RTC_DATA_REGISTER, Data);
+}
+
+/**
+  Initialize RTC.
+
+  @param  GlobalFor global use inside this module.
+
+  @retval EFI_DEVICE_ERROR  Initialization failed due to device error.
+  @retval EFI_SUCCESS   Initialization successful.
+
+**/
+EFI_STATUS
+PcRtcInit (
+  IN PC_RTC_MODULE_GLOBALS  *Global
+  )
+{
+  EFI_STATUS  Status;
+  RTC_REGISTER_B  RegisterB;
+  EFI_TIMETime;
+  UINTN   DataSize;
+  UINT32  TimerVar;
+  BOOLEAN 

[edk2-devel] [PATCH V3 17/32] AMD/VanGoghBoard: Check in Smm access module

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial AMD Smm access module.
  Contains description files for ACPI SMM Platform handler module.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Smm/AcpiSmm/AcpiSmmPlatform.c | 183 
 .../Smm/AcpiSmm/AcpiSmmPlatform.h |  50 ++
 .../Smm/AcpiSmm/AcpiSmmPlatform.inf   |  57 +++
 .../Smm/SmmAccessPei/SmmAccessPei.c   | 436 ++
 .../Smm/SmmAccessPei/SmmAccessPei.inf |  43 ++
 5 files changed, 769 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAccessPei/SmmAccessPei.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAccessPei/SmmAccessPei.inf

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.c 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.c
new file mode 100644
index 00..20a0ed6cb7
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.c
@@ -0,0 +1,183 @@
+/** @file
+ACPISMM Driver implementation file.
+
+This is QNC Smm platform driver
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2019 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+/**
+  Allocate EfiACPIMemoryNVS below 4G memory address.
+
+  This function allocates EfiACPIMemoryNVS below 4G memory address.
+
+  @param[in] Size   Size of memory to allocate.
+
+  @return   Allocated address for output.
+
+**/
+VOID *
+AllocateAcpiNvsMemoryBelow4G (
+  IN UINTN  Size
+  )
+{
+  UINTN Pages;
+  EFI_PHYSICAL_ADDRESS  Address;
+  EFI_STATUSStatus;
+  VOID  *Buffer;
+
+  Pages   = EFI_SIZE_TO_PAGES (Size);
+  Address = 0x;
+
+  Status = gBS->AllocatePages (
+  AllocateMaxAddress,
+  EfiACPIMemoryNVS,
+  Pages,
+  
+  );
+  if (EFI_ERROR (Status)) {
+return NULL;
+  }
+
+  Buffer = (VOID *)(UINTN)Address;
+  ZeroMem (Buffer, Size);
+
+  return Buffer;
+}
+
+/**
+  Reserved S3 memory for InstallS3Memory
+
+  @retval  EFI_OUT_OF_RESOURCES Insufficient resources to complete 
function.
+  @retval  EFI_SUCCESS  Function has completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+ReservedS3Memory (
+  UINTN  SystemMemoryLength
+
+  )
+
+{
+  VOID*GuidHob;
+  EFI_SMRAM_HOB_DESCRIPTOR_BLOCK  *DescriptorBlock;
+  VOID*AcpiReservedBase;
+
+  UINTN   TsegIndex;
+  UINTN   TsegSize;
+  UINTN   TsegBase;
+  RESERVED_ACPI_S3_RANGE  *AcpiS3Range;
+
+  DEBUG ((DEBUG_INFO, "ReservedS3Memory, SystemMemoryLength: 0x%08X\n", 
SystemMemoryLength));
+  //
+  // Get Hob list for SMRAM desc
+  //
+  GuidHob = GetFirstGuidHob ();
+  ASSERT (GuidHob != NULL);
+  DEBUG ((DEBUG_INFO, "gEfiSmmPeiSmramMemoryReserveGuid: 0x%X \n", 
(UINTN)GuidHob));
+  DescriptorBlock = GET_GUID_HOB_DATA (GuidHob);
+  ASSERT (DescriptorBlock != NULL);
+
+  //
+  // Use the hob to get SMRAM capabilities
+  //
+  TsegIndex = DescriptorBlock->NumberOfSmmReservedRegions - 1;
+  DEBUG ((DEBUG_INFO, "DescriptorBlock->NumberOfSmmReservedRegions: 0x%X\n", 
DescriptorBlock->NumberOfSmmReservedRegions));
+  DEBUG ((DEBUG_INFO, "TsegIndex: 0x%X\n", TsegIndex));
+  ASSERT (TsegIndex <= (MAX_SMRAM_RANGES - 1));
+  TsegBase = (UINTN)DescriptorBlock->Descriptor[TsegIndex].PhysicalStart;
+  TsegSize = (UINTN)DescriptorBlock->Descriptor[TsegIndex].PhysicalSize;
+
+  DEBUG ((DEBUG_INFO, "SMM  Base: %08X\n", TsegBase));
+  DEBUG ((DEBUG_INFO, "SMM  Size: %08X\n", TsegSize));
+
+  //
+  // Now find the location of the data structure that is used to store the 
address
+  // of the S3 reserved memory.
+  //
+  AcpiS3Range = (RESERVED_ACPI_S3_RANGE *)(UINTN)(TsegBase + 
RESERVED_ACPI_S3_RANGE_OFFSET);
+  DEBUG ((DEBUG_INFO, "AcpiS3Range: %08X\n", (UINTN)AcpiS3Range));
+  //
+  // Allocate reserved ACPI memory for S3 resume.  Pointer to this region is
+  // stored in SMRAM in the first page of TSEG.
+  //
+  AcpiReservedBase = AllocateAcpiNvsMemoryBelow4G (PcdGet32 
(PcdS3AcpiReservedMemorySize));
+  DEBUG ((DEBUG_INFO, "AcpiReservedBase: %08X\n", (UINTN)AcpiReservedBase));
+  ASSERT (AcpiReservedBase != NULL);
+  if 

[edk2-devel] [PATCH V3 16/32] AMD/VanGoghBoard: Check in BaseTscTimerLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Provides basic TSC timer calibration based on the ACPI timer hardware.
  The performance counter features are provided by the processors time stamp 
counter.

Signed-off-by: Ken Yao 
Cc: Eric Xing 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Library/TscTimerLib/BaseTscTimerLib.c |  23 ++
 .../Library/TscTimerLib/BaseTscTimerLib.inf   |  43 +++
 .../Library/TscTimerLib/DxeTscTimerLib.c  |  80 ++
 .../Library/TscTimerLib/DxeTscTimerLib.inf|  55 
 .../Library/TscTimerLib/PeiTscTimerLib.c  |  53 
 .../Library/TscTimerLib/PeiTscTimerLib.inf|  49 
 .../Library/TscTimerLib/TscTimerLibInternal.h |  53 
 .../Library/TscTimerLib/TscTimerLibShare.c| 255 ++
 8 files changed, 611 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/PeiTscTimerLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/PeiTscTimerLib.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/TscTimerLibInternal.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/TscTimerLibShare.c

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.c
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.c
new file mode 100644
index 00..7dfef490e9
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.c
@@ -0,0 +1,23 @@
+/** @file
+  ACPI Timer implements one instance of Timer Library.
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "TscTimerLibInternal.h"
+
+/**  Get TSC frequency.
+
+  @return The number of TSC counts per second.
+
+**/
+UINT64
+InternalGetTscFrequency (
+  VOID
+  )
+{
+  return InternalCalculateTscFrequency ();
+}
diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.inf
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.inf
new file mode 100644
index 00..d6c4e2e1d6
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.inf
@@ -0,0 +1,43 @@
+## @file
+# BaseTscTimerLib
+#  Provides basic timer support using the ACPI timer hardware.  The performance
+#  counter features are provided by the processors time stamp counter.
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = BaseTscTimerLib
+  FILE_GUID  = D29338B9-50FE-4e4f-B7D4-A150A2C1F4FB
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = TimerLib
+
+
+#
+#  VALID_ARCHITECTURES   = IA32 X64
+#
+
+[Sources.common]
+  TscTimerLibShare.c
+  BaseTscTimerLib.c
+  TscTimerLibInternal.h
+
+
+[Packages]
+  MdePkg/MdePkg.dec
+  AgesaPublic/AgesaPublic.dec
+
+
+[LibraryClasses]
+  PcdLib
+  PciLib
+  IoLib
+  BaseLib
+
+[Pcd.common]
+  gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr
diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.c
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.c
new file mode 100644
index 00..5a374665c3
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.c
@@ -0,0 +1,80 @@
+/** @file
+  ACPI Timer implements one instance of Timer Library.
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) Microsoft Corporation.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 

[edk2-devel] [PATCH V3 15/32] AMD/VanGoghBoard: Check in SpiFlashDeviceLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial AMD SpiFlashDeviceLib for Chachani board flash IC.
  Chachani board use the W25Q256JW as flash IC.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../SpiFlashDeviceLib/SpiFlashDeviceLib.c | 42 +++
 .../SpiFlashDeviceLib/SpiFlashDeviceLib.inf   | 29 +
 2 files changed, 71 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.inf

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.c
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.c
new file mode 100644
index 00..49636f6a89
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.c
@@ -0,0 +1,42 @@
+/** @file
+  Implements SpiFlashDeviceLib.c
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+SPI_INIT_TABLE  mSpiInitTable[] = {
+  { // W25Q256JW/W74M25JW
+SF_VENDOR_ID_WINBOND,
+SF_DEVICE_ID0_W25Q256JW,
+SF_DEVICE_ID1_W25Q256JW,
+{
+  SPI_COMMAND_WRITE_ENABLE,
+  SPI_COMMAND_WRITE_S_EN
+},
+{
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_JEDEC_ID,  
EnumSpiOperationJedecId},
+  { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_WRITE_S,   
EnumSpiOperationWriteStatus},
+  { EnumSpiOpcodeWrite,SPI_COMMAND_WRITE, 
EnumSpiOperationProgramData_1_Byte },
+  { EnumSpiOpcodeRead, SPI_COMMAND_READ,  
EnumSpiOperationReadData   },
+  { EnumSpiOpcodeWrite,SPI_COMMAND_ERASE, 
EnumSpiOperationErase_4K_Byte  },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_READ_S,
EnumSpiOperationReadStatus },
+  { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_CHIP_ERASE,
EnumSpiOperationFullChipErase  },
+  { EnumSpiOpcodeRead, SPI_COMMAND_READ_SFDP, 
EnumSpiOperationReadData   },
+  { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_RPMC_OP1,  
EnumSpiOperationOther  },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_RPMC_OP2,  
EnumSpiOperationReadData   },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_Enter_4Byte_Addr,  
EnumSpiOperationOther  },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_Exit_4Byte_Addr,   
EnumSpiOperationOther  }
+},
+0,
+0x200   // BIOS image size in flash
+  }
+};
+
+//
+// The total number of support flash part
+//
+UINT8  mNumSpiFlashMax = sizeof (mSpiInitTable) / sizeof (mSpiInitTable[0]);
diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.inf
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.inf
new file mode 100644
index 00..951cf6c480
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.inf
@@ -0,0 +1,29 @@
+## @file
+# SpiFlashDeviceLib
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = SpiFlashDeviceLib
+  FILE_GUID  = D5A903A8-4D19-4E4C-AAF4-07C5D10D5939
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = SpiFlashDeviceLib
+
+#
+#  VALID_ARCHITECTURES   = IA32 X64
+#
+
+[Sources]
+  SpiFlashDeviceLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  VanGoghCommonPkg/AmdCommonPkg.dec
+
+[LibraryClasses]
+  SpiFlashDeviceLib
-- 
2.31.1



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[edk2-devel] [PATCH V3 14/32] AMD/VanGoghBoard: Check in SmbiosLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Provides library functions for common SMBIOS operations. Only available to DXE
  and UEFI module types.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Include/Library/SmbiosLib.h   | 171 ++
 .../Library/SmbiosLib/SmbiosLib.c | 322 ++
 .../Library/SmbiosLib/SmbiosLib.inf   |  41 +++
 3 files changed, 534 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SmbiosLib.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SmbiosLib/SmbiosLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SmbiosLib/SmbiosLib.inf

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SmbiosLib.h 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SmbiosLib.h
new file mode 100644
index 00..53e8652686
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SmbiosLib.h
@@ -0,0 +1,171 @@
+/** @file
+  Implements AMD SmbiosLib.h
+  Provides library functions for common SMBIOS operations. Only available to 
DXE
+  and UEFI module types.
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2012, Apple Inc. All rights reserved. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SMBIOS_LIB_H_
+#define SMBIOS_LIB_H_
+
+#include 
+#include 
+
+///
+/// Cache copy of the SMBIOS Protocol pointer
+///
+extern EFI_SMBIOS_PROTOCOL  *gSmbios;
+
+///
+/// Template for SMBIOS table initialization.
+/// The SMBIOS_TABLE_STRING types in the formated area must match the
+/// StringArray sequene.
+///
+typedef struct {
+  //
+  // formatted area of a given SMBIOS record
+  //
+  SMBIOS_STRUCTURE*Entry;
+  //
+  // NULL terminated array of ASCII strings to be added to the SMBIOS record.
+  //
+  CHAR8   **StringArray;
+} SMBIOS_TEMPLATE_ENTRY;
+
+/**
+  Create an initial SMBIOS Table from an array of SMBIOS_TEMPLATE_ENTRY
+  entries. SMBIOS_TEMPLATE_ENTRY.NULL indicates the end of the table.
+
+  @param[in]  Template   Array of SMBIOS_TEMPLATE_ENTRY entries.
+
+  @retval EFI_SUCCESS  New SMBIOS tables were created.
+  @retval EFI_OUT_OF_RESOURCES New SMBIOS tables were not created.
+**/
+EFI_STATUS
+EFIAPI
+SmbiosLibInitializeFromTemplate (
+  IN  SMBIOS_TEMPLATE_ENTRY  *Template
+  );
+
+/**
+  Create SMBIOS record.
+
+  Converts a fixed SMBIOS structure and an array of pointers to strings into
+  an SMBIOS record where the strings are cat'ed on the end of the fixed record
+  and terminated via a double NULL and add to SMBIOS table.
+
+  @param[in]  SmbiosEntry   Fixed SMBIOS structure
+  @param[in]  StringArray   Array of strings to convert to an SMBIOS string 
pack.
+NULL is OK.
+
+  @retval EFI_SUCCESS  New SmbiosEntry was added to SMBIOS table.
+  @retval EFI_OUT_OF_RESOURCES SmbiosEntry was not added.
+**/
+EFI_STATUS
+EFIAPI
+SmbiosLibCreateEntry (
+  IN  SMBIOS_STRUCTURE  *SmbiosEntry,
+  IN  CHAR8 **StringArray
+  );
+
+/**
+  Update the string associated with an existing SMBIOS record.
+
+  This function allows the update of specific SMBIOS strings. The number of 
valid strings for any
+  SMBIOS record is defined by how many strings were present when Add() was 
called.
+
+  @param[in]SmbiosHandleSMBIOS Handle of structure that will have its 
string updated.
+  @param[in]StringNumberThe non-zero string number of the string to 
update.
+  @param[in]String  Update the StringNumber string with String.
+
+  @retval EFI_SUCCESS   SmbiosHandle had its StringNumber String 
updated.
+  @retval EFI_INVALID_PARAMETER SmbiosHandle does not exist. Or String is 
invalid.
+  @retval EFI_UNSUPPORTED   String was not added because it is longer than 
the SMBIOS Table supports.
+  @retval EFI_NOT_FOUND The StringNumber.is not valid for this SMBIOS 
record.
+**/
+EFI_STATUS
+EFIAPI
+SmbiosLibUpdateString (
+  IN  EFI_SMBIOS_HANDLESmbiosHandle,
+  IN  SMBIOS_TABLE_STRING  StringNumber,
+  IN  CHAR8*String
+  );
+
+/**
+  Update the string associated with an existing SMBIOS record.
+
+  This function allows the update of specific SMBIOS strings. The number of 
valid strings for any
+  SMBIOS record is defined by how many strings were present when Add() was 
called.
+
+  @param[in]SmbiosHandleSMBIOS Handle of structure that will have its 
string 

[edk2-devel] [PATCH V3 13/32] AMD/VanGoghBoard: Check in PlatformFlashAccessLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial AMD PlatformFlashAccessLib, It provides flash access protocol for 
other modules.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Include/Library/SpiFlashDeviceLib.h   |  59 ++
 .../VanGoghCommonPkg/Include/Protocol/Spi.h   | 346 
 .../Include/Protocol/SpiCommon.h  | 247 
 .../Include/Protocol/SpiFlashUpdate.h | 152 +
 .../PlatformFlashAccessLib.c  | 528 ++
 .../PlatformFlashAccessLib.inf|  52 ++
 6 files changed, 1384 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SpiFlashDeviceLib.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/Spi.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/SpiCommon.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/SpiFlashUpdate.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.inf

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SpiFlashDeviceLib.h
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SpiFlashDeviceLib.h
new file mode 100644
index 00..391453f512
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SpiFlashDeviceLib.h
@@ -0,0 +1,59 @@
+/** @file
+  Implements SpiFlashDevice.h
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SPI_FLASH_DEVICE_LIB_H_
+#define SPI_FLASH_DEVICE_LIB_H_
+
+#include 
+
+//
+// Provides mSpiInitTable and the total number of flash part in mSpiInitTable 
for other modules.
+//
+extern SPI_INIT_TABLE  mSpiInitTable[];
+extern UINT8   mNumSpiFlashMax;
+
+//
+// Flash Device commands
+//
+// If a supported device uses a command different from the list below, a 
device specific command
+// will be defined just below it's JEDEC id section.
+//
+#define SPI_COMMAND_WRITE 0x02
+#define SPI_COMMAND_WRITE_AAI 0xAD
+#define SPI_COMMAND_READ  0x03
+#define SPI_COMMAND_ERASE 0x20
+#define SPI_COMMAND_WRITE_DISABLE 0x04
+#define SPI_COMMAND_READ_S0x05
+#define SPI_COMMAND_WRITE_ENABLE  0x06
+#define SPI_COMMAND_READ_ID   0xAB
+#define SPI_COMMAND_JEDEC_ID  0x9F
+#define SPI_COMMAND_WRITE_S_EN0x50
+#define SPI_COMMAND_WRITE_S   0x01
+#define SPI_COMMAND_CHIP_ERASE0xC7
+#define SPI_COMMAND_BLOCK_ERASE   0xD8
+#define SPI_COMMAND_READ_SFDP 0x5A
+#define SPI_COMMAND_RPMC_OP1  0x9B
+#define SPI_COMMAND_RPMC_OP2  0x96
+#define SPI_COMMAND_Enter_4Byte_Addr  0xB7
+#define SPI_COMMAND_Exit_4Byte_Addr   0xE9
+
+//
+// Winbond 256Mbit parts
+//
+#define SF_VENDOR_ID_WINBOND 0xEF
+#define SF_DEVICE_ID1_W25Q256JW  0x19  // Capacity 256Mbit
+#define SF_DEVICE_ID0_W25Q256JW  0x60
+
+//
+// index for prefix opcodes
+//
+#define SPI_WREN_INDEX  0 // Prefix Opcode 0: 
SPI_COMMAND_WRITE_ENABLE
+#define SPI_EWSR_INDEX  1 // Prefix Opcode 1: 
SPI_COMMAND_WRITE_S_EN
+#define BIOS_CTRL   0xDC
+
+#endif
diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/Spi.h 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/Spi.h
new file mode 100644
index 00..9702d34f7c
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/Spi.h
@@ -0,0 +1,346 @@
+/** @file
+  Implements AMD Spi
+  This file defines the EFI SPI Protocol which implements the
+  Intel(R) ICH SPI Host Controller Compatibility Interface.
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SPI_H_
+#define SPI_H_
+
+#include 
+
+//
+// Define the SPI protocol GUID
+//
+// EDK and EDKII have different GUID formats
+//
+#if !defined (EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x0002)
+#define EFI_SPI_PROTOCOL_GUID \
+  { \
+0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 
\
+  }
+#define EFI_SMM_SPI_PROTOCOL_GUID \
+  { \
+0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 

[edk2-devel] [PATCH V3 12/32] AMD/VanGoghBoard: Check in AMD BaseSerialPortLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial FCH UART port for Serial log output.
  Chachani board uses this UART for outputting debug log.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../BaseSerialPortLib16550AmdFchUart.c| 463 ++
 .../BaseSerialPortLib16550AmdFchUart.inf  |  40 ++
 2 files changed, 503 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.inf

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.c
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.c
new file mode 100644
index 00..665f47f703
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.c
@@ -0,0 +1,463 @@
+/** @file
+  16550 UART Serial Port library functions
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (C) 2014 Hewlett-Packard Development Company, L.P.
+  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+  Copyright (c) 2020, ARM Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+//
+// 16550 UART register offsets and bitfields
+//
+#define R_UART_RXBUF 0
+#define R_UART_TXBUF 0
+#define R_UART_BAUD_LOW  0
+#define R_UART_BAUD_HIGH 1
+#define R_UART_FCR   2
+#define   B_UART_FCR_FIFOE   BIT0
+#define   B_UART_FCR_FIFO64  BIT5
+#define R_UART_LCR   3
+#define   B_UART_LCR_DLABBIT7
+#define R_UART_MCR   4
+#define   B_UART_MCR_RTS BIT1
+#define R_UART_LSR   5
+#define   B_UART_LSR_RXRDY   BIT0
+#define   B_UART_LSR_TXRDY   BIT5
+#define   B_UART_LSR_TEMTBIT6
+#define R_UART_MSR   6
+#define   B_UART_MSR_CTS BIT4
+#define   B_UART_MSR_DSR BIT5
+
+/**
+  Read an 8-bit 16550 register.  The parameter Offset is added to the base 
address of the
+  16550 registers that is specified by PcdSerialRegisterBase.
+  @param  Offset  The offset of the 16550 register to read.
+  @return The value read from the 16550 register.
+**/
+UINT8
+SerialPortReadRegister (
+  UINTN  Offset
+  )
+{
+  return MmioRead8 ((UINTN)PcdGet64 (PcdSerialRegisterBase) + Offset * 4);
+}
+
+/**
+  Write an 8-bit 16550 register. The parameter Offset is added to the base 
address of the
+  16550 registers that is specified by PcdSerialRegisterBase.
+  @param  Offset  The offset of the 16550 register to write.
+  @param  Value   The value to write to the 16550 register specified by Offset.
+  @return The value written to the 16550 register.
+**/
+UINT8
+SerialPortWriteRegister (
+  UINTN  Offset,
+  UINT8  Value
+  )
+{
+  return MmioWrite8 ((UINTN)PcdGet64 (PcdSerialRegisterBase) + Offset * 4, 
Value);
+}
+
+/**
+  Return whether the hardware flow control signal allows writing.
+
+  @retval TRUE  The serial port is writable.
+  @retval FALSE The serial port is not writable.
+**/
+BOOLEAN
+SerialPortWritable (
+  VOID
+  )
+{
+  if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+if (PcdGetBool (PcdSerialDetectCable)) {
+  //
+  // Wait for both DSR and CTS to be set
+  //   DSR is set if a cable is connected.
+  //   CTS is set if it is ok to transmit data
+  //
+  //   DSR  CTS  Description   Action
+  //   ===  ===    
+  //00   No cable connected.   Wait
+  //01   No cable connected.   Wait
+  //10   Cable connected, but not clear to send.   Wait
+  //11   Cable connected, and clear to send.   Transmit
+  //
+  return (BOOLEAN)((SerialPortReadRegister (R_UART_MSR) & (B_UART_MSR_DSR 
| B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));
+} else {
+  //
+  // Wait for both DSR and CTS to be set OR for DSR to be clear.
+  //   DSR is set if a cable is connected.
+  //   CTS is set if it is ok to transmit data
+  //
+  //   DSR  CTS  Description   Action
+  //   ===  ===    
+  //00   No cable connected.   Transmit
+  //01   No cable connected.   Transmit
+  

[edk2-devel] [PATCH V3 11/32] AMD/VanGoghBoard: Check in FvbServices

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial FvbServices module. It describes platform flash IC information
  for FlashUpdate module to send command correctly.
  Different flash ICs may use the different Opcodes.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../VanGoghCommonPkg/FvbServices/FvbInfo.c|  120 ++
 .../FvbServices/FwBlockService.c  | 1285 +
 .../FvbServices/FwBlockService.h  |  515 +++
 .../FvbServices/PlatformSmmSpi.inf|   68 +
 4 files changed, 1988 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FvbInfo.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/PlatformSmmSpi.inf

diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FvbInfo.c 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FvbInfo.c
new file mode 100644
index 00..c0be635864
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FvbInfo.c
@@ -0,0 +1,120 @@
+/** @file
+Defines data structure that is the volume header found.These data is intent
+to decouple FVB driver with FV header.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#define FVB_MEDIA_BLOCK_SIZE  (0x0001)
+
+#define SYSTEM_NV_BLOCK_NUM  ((FixedPcdGet32(PcdFlashNvStorageVariableSize)+ 
FixedPcdGet32(PcdFlashNvStorageFtwWorkingSize) + 
FixedPcdGet32(PcdFlashNvStorageFtwSpareSize))/ FVB_MEDIA_BLOCK_SIZE)
+
+typedef struct {
+  EFI_PHYSICAL_ADDRESS  BaseAddress;
+  EFI_FIRMWARE_VOLUME_HEADERFvbInfo;
+  //
+  // EFI_FV_BLOCK_MAP_ENTRYExtraBlockMap[n];//n=0
+  //
+  EFI_FV_BLOCK_MAP_ENTRYEnd[1];
+} EFI_FVB2_MEDIA_INFO;
+
+EFI_FVB2_MEDIA_INFO  mPlatformFvbMediaInfo =
+  //
+  // Systen NvStorage FVB
+  //
+{
+  0,
+  {
+{
+  0,
+},// ZeroVector[16]
+EFI_SYSTEM_NV_DATA_FV_GUID,
+FVB_MEDIA_BLOCK_SIZE *SYSTEM_NV_BLOCK_NUM,
+EFI_FVH_SIGNATURE,
+EFI_FVB2_MEMORY_MAPPED |
+EFI_FVB2_READ_ENABLED_CAP |
+EFI_FVB2_READ_STATUS |
+EFI_FVB2_WRITE_ENABLED_CAP |
+EFI_FVB2_WRITE_STATUS |
+EFI_FVB2_ERASE_POLARITY |
+EFI_FVB2_ALIGNMENT_16,
+sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
+0xFBFF,// CheckSum
+0, // ExtHeaderOffset
+{
+  0,
+},// Reserved[1]
+2,// Revision
+{
+  {
+SYSTEM_NV_BLOCK_NUM,
+FVB_MEDIA_BLOCK_SIZE,
+  }
+}
+  },
+  {
+{
+  0,
+  0
+}
+  }
+};
+
+/**
+  Get Fvb information.
+
+  @param[in] BaseAddressThe base address compare with NvStorageVariable 
base address.
+  @param[out] FvbInfoFvb information.
+
+  @retval EFI_SUCCESS   Get Fvb information successfully.
+  @retval EFI_NOT_FOUND Not find Fvb information.
+
+**/
+EFI_STATUS
+EFIAPI
+GetFvbInfo (
+  IN  UINT64  BaseAddress,
+  OUT EFI_FIRMWARE_VOLUME_HEADER  **FvbInfo
+  )
+{
+  mPlatformFvbMediaInfo.BaseAddress = PcdGet32 (PcdFlashNvStorageVariableBase);
+
+  if (mPlatformFvbMediaInfo.BaseAddress == BaseAddress) {
+*FvbInfo = 
+return EFI_SUCCESS;
+  }
+
+  return EFI_NOT_FOUND;
+}
diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.c 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.c
new file mode 100644
index 00..f514ad772a
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.c
@@ -0,0 +1,1285 @@
+/** @file
+  Implements FvbServicesSmm
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2013-2016 Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifdef _MSC_VER
+  #pragma optimize( "", off )
+#endif
+
+#ifdef __GNUC__
+  #ifndef __clang__
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+  #else
+#pragma clang optimize off
+  #endif
+#endif
+
+#include "FwBlockService.h"
+
+#define EFI_FVB2_STATUS  

[edk2-devel] [PATCH V3 10/32] AMD/VanGoghBoard: Check in FlashUpdate

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial FlashUpdate module for Chachani platform flash IC.
  It provides mEfiSpiFlashUpdateProtocol for other module to access flash.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../FlashUpdate/FlashUpdateCommon.h   | 143 +
 .../FlashUpdate/FlashUpdateSmm.c  | 512 ++
 .../FlashUpdate/FlashUpdateSmm.h  | 123 +
 .../FlashUpdate/FlashUpdateSmm.inf|  59 ++
 .../FlashUpdate/FlashUpdateSmmRuntimeDxe.c| 407 ++
 .../FlashUpdate/FlashUpdateSmmRuntimeDxe.inf  |  48 ++
 .../VanGoghCommonPkg/FlashUpdate/PcRtc.h  | 375 +
 7 files changed, 1667 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateCommon.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmm.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmm.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmm.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmmRuntimeDxe.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmmRuntimeDxe.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/PcRtc.h

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateCommon.h 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateCommon.h
new file mode 100644
index 00..77967f1f26
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateCommon.h
@@ -0,0 +1,143 @@
+/** @file
+  Implements AMD FlashUpdateCommon.h
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef FLASH_UPDATE_COMMON_H_
+#define FLASH_UPDATE_COMMON_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+
+#define SPI_SMM_COMM_ID_GET_FLASH_SIZE_BLOCK_SIZE  0x0   // ID for get 
flash size and block size
+#define SPI_SMM_COMM_ID_READ_FLASH 0x1   // ID for Read 
Flash
+#define SPI_SMM_COMM_ID_WRITE_FALSH0x2   // ID for Write 
Flash
+#define SPI_SMM_COMM_ID_ERASE_FALSH0x3   // ID for Erase 
Flash
+
+//
+// SMM communication common buffer
+//
+typedef struct _FLASH_UPDATE_SMM_COMMUNICATION_CMN {
+  UINT32id; // Function ID of smm communication buffer
+} FLASH_UPDATE_SMM_COMMUNICATION_CMN;
+
+#pragma pack(1)
+
+//
+// SMM communication common buffer
+//
+typedef struct _SMM_COMM_RWE_FLASH {
+  UINT32id;  // ID of smm communication buffer
+  UINTN FlashAddress;// Flash devicd physical flash 
address
+  UINTN NumBytes;// Number in byte
+  EFI_STATUSReturnStatus;// Return status
+  UINT8 Buffer[1];   // Buffer start
+} SMM_COMM_RWE_FLASH;
+
+//
+// SMM communication common buffer
+//
+typedef struct _SMM_COMM_GET_FLASH_SIZE_BLOCK_SIZE {
+  UINT32id;   // ID of smm communication buffer
+  UINTN FlashSize;// Flash size
+  UINTN BlockSize;// Block size of flash device
+  EFI_STATUSReturnStatus; // Return status
+} SMM_COMM_GET_FLASH_SIZE_BLOCK_SIZE;
+
+#pragma pack()
+
+#define SMM_COMMUNICATE_HEADER_SIZE  (OFFSET_OF (EFI_SMM_COMMUNICATE_HEADER, 
Data))
+#define SMM_COMM_RWE_FLASH_SIZE  (OFFSET_OF (SMM_COMM_RWE_FLASH, Buffer))
+
+/**
+  Read data from flash device.
+
+  @param[in]  FlashAddressPhysical flash address.
+  @param[in]  NumBytesNumber in Byte.
+  @param[out] Buffer  Buffer contain the read data.
+
+  @retval EFI_SUCCESS Read successfully.
+  @retval EFI_INVALID_PARAMETER   Invalid parameter.
+  @retval others  Some error occurs when executing 
this routine.
+
+**/
+EFI_STATUS
+EFIAPI
+SfuProtocolFlashFdRead (
+  IN  UINTN  FlashAddress,
+  IN  UINTN  NumBytes,
+  OUT VOID   *Buffer
+  );
+
+/**
+  Erase flash region according to input in a block size.
+
+  @param[in] FlashAddress Physical flash address.
+  @param[in] NumBytes Number in Byte, a block size in 
flash device.

[edk2-devel] [PATCH V3 09/32] AMD/VanGoghBoard: Check in Flash_AB

[Zhai, MingXin (Duke) via groups.io]

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[edk2-devel] [PATCH V3 08/32] AMD/VanGoghBoard: Check in UDKFlashUpdate

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  UDKFlashUpdate is a uefi tool for BIOS binary updating. It depends on EDK2's 
flash access protocol.
  UDKFlashUpdate needs to run under EDK2 BIOS.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../UDKFlashUpdate/SpiFlashDevice.c   |  37 +
 .../UDKFlashUpdate/SpiFlashDevice.h   |  62 ++
 .../UDKFlashUpdate/UDKFlashUpdate.c   | 671 ++
 .../UDKFlashUpdate/UDKFlashUpdate.h   |  48 ++
 .../UDKFlashUpdate/UDKFlashUpdate.inf |  51 ++
 5 files changed, 869 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/UDKFlashUpdate.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/UDKFlashUpdate.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/UDKFlashUpdate.inf

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.c
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.c
new file mode 100644
index 00..d4f5b12f41
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.c
@@ -0,0 +1,37 @@
+/** @file
+  Implements SpiFlashDevice.c
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SpiFlashDevice.h"
+
+SPI_INIT_TABLE  mSpiInitTable[] = {
+  { // W25Q256JW/W74M25JW
+SF_VENDOR_ID_WINBOND,
+SF_DEVICE_ID0_W25Q256JW,
+SF_DEVICE_ID1_W25Q256JW,
+{
+  SPI_COMMAND_WRITE_ENABLE,
+  SPI_COMMAND_WRITE_S_EN
+},
+{
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_JEDEC_ID,  
EnumSpiOperationJedecId},
+  { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_WRITE_S,   
EnumSpiOperationWriteStatus},
+  { EnumSpiOpcodeWrite,SPI_COMMAND_WRITE, 
EnumSpiOperationProgramData_1_Byte },
+  { EnumSpiOpcodeRead, SPI_COMMAND_READ,  
EnumSpiOperationReadData   },
+  { EnumSpiOpcodeWrite,SPI_COMMAND_ERASE, 
EnumSpiOperationErase_4K_Byte  },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_READ_S,
EnumSpiOperationReadStatus },
+  { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_CHIP_ERASE,
EnumSpiOperationFullChipErase  },
+  { EnumSpiOpcodeRead, SPI_COMMAND_READ_SFDP, 
EnumSpiOperationReadData   },
+  { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_RPMC_OP1,  
EnumSpiOperationOther  },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_RPMC_OP2,  
EnumSpiOperationReadData   },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_Enter_4Byte_Addr,  
EnumSpiOperationOther  },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_Exit_4Byte_Addr,   
EnumSpiOperationOther  }
+},
+0,
+0x200   // BIOS image size in flash
+  }
+};
diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.h
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.h
new file mode 100644
index 00..fa7a7fec27
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.h
@@ -0,0 +1,62 @@
+/** @file
+  Implements SpiFlashDevice.h
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SPI_FLASH_DEVICE_H_
+#define SPI_FLASH_DEVICE_H_
+
+#include 
+#include 
+#include 
+
+//
+// Supported SPI Flash Devices
+//
+typedef enum {
+  EnumSpiFlashW25Q256JW,
+  EnumSpiFlashMax
+} SPI_FLASH_TYPES_SUPPORTED;
+
+// Flash Device commands
+//
+// If a supported device uses a command different from the list below, a 
device specific command
+// will be defined just below it's JEDEC id section.
+//
+#define SPI_COMMAND_WRITE 0x02
+#define SPI_COMMAND_WRITE_AAI 0xAD
+#define SPI_COMMAND_READ  0x03
+#define SPI_COMMAND_ERASE 0x20
+#define SPI_COMMAND_WRITE_DISABLE 0x04
+#define SPI_COMMAND_READ_S0x05
+#define SPI_COMMAND_WRITE_ENABLE  0x06
+#define SPI_COMMAND_READ_ID   0xAB
+#define 

[edk2-devel] [PATCH V3 07/32] AMD/VanGoghBoard: Check in PciPlatform

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  BIOS detects current IGPU device ID and install corresponding VBIOS.
  Inital PciPlatform module to load VBIOS and to provide interface for
  other option ROMs if necessary.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Include/Protocol/GlobalNvsArea.h  |  63 ++
 .../PciPlatform/CommonHeader.h|  27 +++
 .../PciPlatform/PciPlatform.c | 183 ++
 .../PciPlatform/PciPlatform.h |  89 +
 .../PciPlatform/PciPlatform.inf   |  51 +
 5 files changed, 413 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvsArea.h
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.h
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.inf

diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvsArea.h 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvsArea.h
new file mode 100644
index 00..36d4f43ebd
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvsArea.h
@@ -0,0 +1,63 @@
+/** @file
+Definition of the global NVS area protocol.  This protocol
+publishes the address and format of a global ACPI NVS buffer
+used as a communications buffer between SMM code and ASL code.
+The format is derived from the ACPI reference code, version 0.95.
+Note:  Data structures defined in this protocol are not naturally aligned.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef GLOBAL_NVS_AREA_H_
+#define GLOBAL_NVS_AREA_H_
+
+//
+// Includes
+//
+#define GLOBAL_NVS_DEVICE_ENABLE   1
+#define GLOBAL_NVS_DEVICE_DISABLE  0
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+{ 0x74e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc} }
+
+//
+// Revision id - Added TPM related fields
+//
+#define GLOBAL_NVS_AREA_RIVISION_1  1
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID  gEfiGlobalNvsAreaProtocolGuid;
+
+//
+// Global NVS Area definition
+//
+#pragma pack (1)
+typedef struct {
+  //
+  // Miscellaneous Dynamic Values, the definitions below need to be matched
+  // GNVS definitions in Platform.ASL
+  //
+  UINT32TopOfMem;   // TOPM
+  UINT8 NbIoApic;   // NAPC
+  UINT32PcieBaseAddress;// PCBA
+  UINT32PcieBaseLimit;  // PCBL
+} EFI_GLOBAL_NVS_AREA;
+#pragma pack ()
+
+//
+// Global NVS Area Protocol
+//
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+  EFI_GLOBAL_NVS_AREA*Area;
+} EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif
diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h
new file mode 100644
index 00..1297de6369
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h
@@ -0,0 +1,27 @@
+/** @file
+  Implements CommonHeader.h
+  This file includes package header files, library classes and protocol, PPI & 
GUID definitions.
+
+  Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef COMMON_HEADER_H_
+#define COMMON_HEADER_H_
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#endif
diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c
new file mode 100644
index 00..aa0a133b1f
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c
@@ -0,0 +1,183 @@
+/** @file
+  Implements PciPlatform.c
+  Registers onboard PCI ROMs with PCI.IO
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CommonHeader.h"
+
+#include "PciPlatform.h"
+

[edk2-devel] [PATCH V3 03/32] AMD/VanGoghBoard: Check in Capsule update

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Chachani board supports "Capsule on Disk (CoD)" feature defined in UEFI
  Spec chapter 8.5.5 "Delivery of Capsules via file on Mass Storage Device".
  The BIOS capsule image is saved in hard disk as default setting.

Signed-off-by: Ken Yao 
Cc: Duke Zhai 
Cc: Eric Xing 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../SystemFirmwareDescriptor.aslc |   85 ++
 .../SystemFirmwareDescriptor.inf  |   39 +
 .../SystemFirmwareDescriptorPei.c |   64 +
 .../Include/Library/CapsuleHookLib.h  |   40 +
 .../Capsule/CapsuleHookLib/CapsuleHookLib.c   | 1153 +
 .../Capsule/CapsuleHookLib/CapsuleHookLib.inf |   56 +
 .../PlatformBootManager.c |  794 
 .../PlatformBootManager.h |  150 +++
 .../PlatformBootManagerLib.inf|   89 ++
 .../PlatformBootManagerLib/PlatformConsole.c  |  495 +++
 .../PlatformBootManagerLib/PlatformConsole.h  |   69 +
 .../PlatformBootManagerLib/PlatformData.c |   39 +
 .../CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf   |  115 ++
 .../CapsuleRuntimeDxe/CapsuleService.c|  461 +++
 .../CapsuleRuntimeDxe/CapsuleService.h|   73 ++
 15 files changed, 3722 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Library/CapsuleHookLib.h
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/CapsuleHookLib/CapsuleHookLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/CapsuleHookLib/CapsuleHookLib.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformBootManager.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformBootManager.h
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformBootManagerLib.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformConsole.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformConsole.h
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformData.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleService.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleService.h

diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
new file mode 100644
index 00..2e05a523c7
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
@@ -0,0 +1,85 @@
+/** @file
+  System firmware Descriptor file
+  System Firmware descriptor.
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+
+#define PACKAGE_VERSION 0x
+#define PACKAGE_VERSION_STRING  L"Unknown"
+
+#define CURRENT_FIRMWARE_VERSION0x3818
+#define CURRENT_FIRMWARE_VERSION_STRING L"3818"
+#define LOWEST_SUPPORTED_FIRMWARE_VERSION   0x0001
+
+#define IMAGE_IDSIGNATURE_64('C', 'H', 'A', 'C', 
'H', 'A','N','I')
+#define IMAGE_ID_STRING L"ChachaniFD"
+
+// PcdSystemFmpCapsuleImageTypeIdGuid
+#define IMAGE_TYPE_ID_GUID  { 0x38663fe6, 0x934f, 0x42a1, { 
0xbc, 0xb0, 0xf7, 0x9e, 0x62, 0xec, 0xbe, 0x80 } }
+
+typedef struct {
+  EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR  Descriptor;
+  // real string data
+  CHAR16  

[edk2-devel] [PATCH V3 05/32] AMD/VanGoghBoard: Check in PlatformSecLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Chachani board jump to PlatformSec function after x86 releasing.
  This module provides the SEC entry function, which does platform-related
  early initialization.

Signed-off-by: Ken Yao 
Cc: Duke Zhai 
Cc: Eric Xing 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Library/PlatformSecLib/Ia32/Flat32.nasm   | 534 ++
 .../Library/PlatformSecLib/Ia32/Platform.inc  |  53 ++
 .../Library/PlatformSecLib/PlatformSecLib.c   | 196 +++
 .../Library/PlatformSecLib/PlatformSecLib.inf |  61 ++
 .../PlatformSecLib/PlatformSecLibModStrs.uni  |  19 +
 5 files changed, 863 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Platform.inc
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni

diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm
 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm
new file mode 100644
index 00..5638c411e3
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm
@@ -0,0 +1,534 @@
+;/** @file
+; AMD VanGoghBoard PlatformSecLib
+;  This is the code that goes from real-mode to protected mode.
+;  It consumes the reset vector, configures the stack.
+;
+; Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;**/
+
+;
+; Include processor definitions
+;
+%use masm
+
+
+%include "Platform.inc"
+
+;
+; CR0 cache control bit definition
+;
+CR0_CACHE_DISABLE   EQU 04000h
+CR0_NO_WRITEEQU 02000h
+BSP_STACK_BASE_ADDR EQU FixedPcdGet32 
(PcdPeiCorePeiPreMemoryStackBaseAddress) ; Base address for core 0 stack
+PRE_MEM_STACK_SIZE  EQU FixedPcdGet32 (PcdPeiCorePeiPreMemoryStackSize)
+PCIEX_LENGTH_BIT_SETTING EQU 011000b
+
+MSR_IA32_EFER   EQU  0c080h   ; Extended Feature Enable 
Register
+MSR_IA32_EFER_LME   EQU  8; Long Mode Enable
+
+MSR_SMM_BASEEQU  0c0010111h   ; SMBASE Register
+
+SMM_BASE_DEFAULTEQU  3h   ; reset value of MSR MSR_SMM_BASE
+
+SMMMASK_ADDRESS EQU  0c0010113h   ; SMM TSeg Base Address
+SMMMASK_ADDRESS_AE  EQU  0; Aseg Address Range Enable
+SMMMASK_ADDRESS_TE  EQU  1; Tseg Address Range Enable
+
+;
+; In Modified Conventional Resume S3 Design:
+;   With Modified Conventional Resume path, the x86 resumes from sleep,
+; begins executing code from a predefined SMM resume vector and then
+; jump to ROM code to continue conventional resume.
+; EDX is filled with special signature "0x55AABB66" when jump to Sec,
+; this signature can be used to identify if resume back from SMM resume.
+;
+SMM_RESUME_SIGNATUREEQU  055AABB66h
+
+PCAT_RTC_ADDRESS_REGISTER  EQU  0x70
+PCAT_RTC_DATA_REGISTER EQU  0x71
+
+NMI_DISABLE_BIT EQU  0x80
+
+RTC_ADDRESS_REGISTER_A  EQU  0x0A  ; R/W[0..6]  R0[7]
+RTC_ADDRESS_REGISTER_B  EQU  0x0B  ; R/W
+RTC_ADDRESS_REGISTER_C  EQU  0x0C  ; RO
+RTC_ADDRESS_REGISTER_D  EQU  0x0D  ; R/W
+
+;
+; External and public declarations
+;  TopOfStack is used by C code
+;  SecStartup is the entry point to the C code
+; Neither of these names can be modified without
+; updating the C code.
+;
+extern   ASM_PFX(SecStartup)
+
+SECTION .text
+;
+; Protected mode portion initializes stack, configures cache, and calls C 
entry point
+;
+
+;
+;
+; Procedure:ProtectedModeEntryPoint
+;
+; Input:Executing in 32 Bit Protected (flat) mode
+;cs: 0-4GB
+;ds: 0-4GB
+;es: 0-4GB
+;fs: 0-4GB
+;gs: 0-4GB
+;ss: 0-4GB
+;
+; Output:   This function never returns
+;
+; Destroys:
+;   ecx
+;   edi
+;esi
+;esp
+;
+; Description:
+;Perform any essential early platform initilaisation
+;   Setup a stack
+;   Call the main EDKII Sec C code
+;
+;
+
+global ASM_PFX(_ModuleEntryPoint)

[edk2-devel] [PATCH V3 06/32] AMD/VanGoghBoard: Check in AmdIdsExtLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  A small part of Chachani platform code and FSPWrapperPkg needs IdsHookExtLib.
  Initial AmdIdsHookExtLibNull for ChachaniBoardPkg module.

Signed-off-by: Ken Yao 
Cc: Duke Zhai 
Cc: Eric Xing 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../AmdIdsExtLibNull/AmdIdsHookExtLibNull.c   | 33 
 .../AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf | 39 +++
 2 files changed, 72 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf

diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.c
 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.c
new file mode 100644
index 00..f59b5beea1
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.c
@@ -0,0 +1,33 @@
+/** @file
+  Implements AmdIdsHookExtLibNull.c
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+
+typedef enum {
+  IDS_HOOK_UNSUPPORTED = 1
+} IDS_HOOK_STATUS;
+
+IDS_HOOK_STATUS
+IdsHookExtEntry (
+  UINT32  HookId,
+  VOID*Handle,
+  VOID*Data
+  )
+{
+  return IDS_HOOK_UNSUPPORTED;
+}
+
+IDS_HOOK_STATUS
+GetIdsNvTable (
+  IN OUT   VOID*IdsNvTable,
+  IN OUT   UINT32  *IdsNvTableSize
+  )
+{
+  return IDS_HOOK_UNSUPPORTED;
+}
diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf
 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf
new file mode 100644
index 00..354c19dd19
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf
@@ -0,0 +1,39 @@
+## @file
+#  Amd Ids Hook Ext Lib Module INF file
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010006
+  BASE_NAME  = AmdIdsHookExtLibNull.inf
+  FILE_GUID  = CB364A1C-793D-46CE-B80A-0AB5FCB16D76
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = AmdIdsHookExtLib
+
+[Sources.common]
+  AmdIdsHookExtLibNull.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+
+[Guids]
+
+[Protocols]
+
+[Ppis]
+
+[FeaturePcd]
+
+[Pcd]
+
+[Depex]
+  TRUE
+
+[BuildOptions]
+
-- 
2.31.1



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[edk2-devel] [PATCH V3 04/32] AMD/VanGoghBoard: Check in AgesaPublicPkg

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Chachani board platform code depends on some AGESA-related PCDs/GUIDs.
  Add AgesaPublicPkg for AGESA-related PCDs/GUIDs to support platfrom build.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../VanGoghBoard/AgesaPublic/AgesaPublic.dec  |  61 +
 .../VanGoghBoard/AgesaPublic/Include/AGESA.h  |  35 +++
 .../VanGoghBoard/AgesaPublic/Include/AMD.h| 189 +
 .../AgesaPublic/Include/AmdPspDirectory.h |  55 
 .../AgesaPublic/Include/FchRegistersCommon.h  |  23 ++
 .../Include/Guid/AmdMemoryInfoHob.h   |  51 
 .../Include/Library/AmdPspBaseLibV2.h | 248 ++
 .../Include/Library/AmdPspCommonLib.h |  29 ++
 .../Include/Library/AmdPspFtpmLib.h   |  94 +++
 .../AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h   |  80 ++
 .../Include/Protocol/AmdPspFtpmProtocol.h | 112 
 11 files changed, 977 insertions(+)
 create mode 100644 Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
 create mode 100644 Platform/AMD/VanGoghBoard/AgesaPublic/Include/AGESA.h
 create mode 100644 Platform/AMD/VanGoghBoard/AgesaPublic/Include/AMD.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/AmdPspDirectory.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/FchRegistersCommon.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Guid/AmdMemoryInfoHob.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspBaseLibV2.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspCommonLib.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspFtpmLib.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Protocol/AmdPspFtpmProtocol.h

diff --git a/Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec 
b/Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
new file mode 100644
index 00..e987b9b603
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
@@ -0,0 +1,61 @@
+## @file
+# EDK II AgesaPublic.dec file
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+  DEC_SPECIFICATION  = 0x00010005
+  PACKAGE_NAME   = AgesaPublic
+  PACKAGE_GUID   = EA54B0FA-908C-43DE-95A5-5E821A893CA4
+  PACKAGE_VERSION= 0.1
+
+[Includes]
+  Include
+
+[Guids]
+  gEfiAmdAgesaModulePkgTokenSpaceGuid  = { 0x7788adf0, 0x9788, 0x4a3f, { 
0x83, 0xfa, 0xcb, 0x51, 0x2e, 0x7c, 0xf8, 0xdd } }
+  gEfiAmdAgesaPkgTokenSpaceGuid= { 0xd4d8435f, 0xfffb, 0x4acb, { 
0xa0, 0x4d, 0xff, 0x0f, 0xad, 0x67, 0x7f, 0xe9 } }
+  gAmdCpmPkgTokenSpaceGuid = { 0x916e0ddd, 0x2bd2, 0x4704, { 
0x93, 0xb9, 0x59, 0x4b, 0x01, 0xa5, 0xfa, 0x9f } }
+  gAmdResourceSizeForEachRbGuid= { 0x542b8f2f, 0xbd52, 0x4233, { 
0x8c, 0x3d, 0x66, 0x53, 0x0d, 0xe8, 0xa3, 0x69 } }
+  gAmdPbsSystemConfigurationGuid   = { 0xa339d746, 0xf678, 0x49b3, { 
0x9f, 0xc7, 0x54, 0xce, 0x0f, 0x9d, 0xf2, 0x26 } }
+  gAmdTotalNumberOfRootBridgesGuid = { 0xfb5703f5, 0xf8a7, 0xf401, { 
0x18, 0xb4, 0x3f, 0x10, 0x8d, 0xeb, 0x26, 0x12 } }
+  gApSyncFlagNvVariableGuid= { 0xad3f6761, 0xf0a3, 0x46c8, { 
0xa4, 0xcb, 0x19, 0xb7, 0x0f, 0xfd, 0xb3, 0x05 } }
+  gAmdMemoryInfoHobGuid= { 0x1bce3d14, 0xa5fe, 0x4a0b, { 
0x9a, 0x8d, 0x69, 0xca, 0x5d, 0x98, 0x38, 0xd3 } }
+  gAmdPspApobHobGuid   = { 0x30b174f3, 0x7712, 0x4cca, { 
0xbd, 0x13, 0xd0, 0xb8, 0xa8, 0x80, 0x19, 0x97 } }
+
+[Protocols]
+  gPspFlashAccSmmCommReadyProtocolGuid = { 0x9f373486, 0xda76, 0x4c9f, { 
0x81, 0x55, 0x6c, 0xcd, 0xdb, 0x0b, 0x0b, 0x04 } }
+  gAmdPspFtpmProtocolGuid  = { 0xac234e04, 0xb036, 0x476c, { 
0x91, 0x66, 0xbe, 0x47, 0x52, 0xa0, 0x95, 0x09 } }
+  gFchInitDonePolicyProtocolGuid   = { 0xc63c0c73, 0xf612, 0x4c02, { 
0x84, 0xa3, 0xc6, 0x40, 0xad, 0x0b, 0xa6, 0x22 } }
+  gAmdCapsuleSmmHookProtocolGuid   = { 0x4fc43bbe, 0x1433, 0x4951, { 
0xac, 0x2d, 0x0d, 0x01, 0xfe, 0xc0, 0x0e, 0xb1 } }
+  gAmdCpmAllPciIoProtocolsInstalledProtocolGuid = { 0x676D7012, 0x139B, 
0x485A, { 0x96, 0xF1, 0x98, 0x6F, 0xC4, 0x8A, 0x86, 0x4B } }
+  gAmdFspSetupTableInitDoneGuid= { 0xef5394c6, 0x566d, 0x440f, { 
0x9d, 0x05, 0xc0, 0xa3, 0x2c, 0xb9, 0x33, 

[edk2-devel] [PATCH V3 02/32] AMD/VanGoghBoard: Check in ACPI tables

[Zhai, MingXin (Duke) via groups.io]

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[edk2-devel] [PATCH V3 01/32] AMD/AmdPlatformPkg: Check in AMD S3 logo

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  LogoDxe module displays boot logo.
  S3LogoDxe module is based on EDK2 LogoDxe module and update AMD S3 logo.

Signed-off-by: Eric Xing 
Cc: Duke Zhai 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../AmdPlatformPkg/Universal/LogoDxe/Logo.c   | 198 ++
 .../Universal/LogoDxe/S3Logo.bmp  | Bin 0 -> 964114 bytes
 .../Universal/LogoDxe/S3Logo.idf  |   9 +
 .../Universal/LogoDxe/S3LogoDxe.inf   |  55 +
 4 files changed, 262 insertions(+)
 create mode 100644 Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c
 create mode 100644 Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3Logo.bmp
 create mode 100644 Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3Logo.idf
 create mode 100644 Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3LogoDxe.inf

diff --git a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c 
b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c
new file mode 100644
index 00..4463ba58eb
--- /dev/null
+++ b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c
@@ -0,0 +1,198 @@
+/**
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+**/
+
+/** @file
+  Logo DXE Driver, install Edk2 Platform Logo protocol.
+
+  Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "Logo.h"
+
+EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+EFI_HII_HANDLE mHiiHandle;
+LOGO_ENTRY mLogos[] = {
+  {
+IMAGE_TOKEN (IMG_LOGO),
+EdkiiPlatformLogoDisplayAttributeCenter,
+0,
+0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param[in]  This  The pointer to this protocol instance.
+  @param[in, out] Instance  The visible image instance is found.
+  @param[out] Image Points to the image.
+  @param[out] Attribute The display attributes of the image 
returned.
+  @param[out] OffsetX   The X offset of the image regarding the 
Attribute.
+  @param[out] OffsetY   The Y offset of the image regarding the 
Attribute.
+
+  @retval EFI_SUCCESSThe image was fetched successfully.
+  @retval EFI_NOT_FOUND  The specified image could not be found.
+  @retval EFI_INVALID_PARAMETER  One of the given input parameters are 
incorrect
+**/
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN EDKII_PLATFORM_LOGO_PROTOCOL*This,
+  IN OUT UINT32  *Instance,
+  OUT EFI_IMAGE_INPUT*Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN   *OffsetX,
+  OUT INTN   *OffsetY
+  )
+{
+  UINT32  Current;
+
+  if ((Instance == NULL) || (Image == NULL) ||
+  (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
+return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++; // Advance to next logo.
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, 
mLogos[Current].ImageId, Image);
+}
+
+EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
+  GetImage
+};
+
+// AMD_EDKII_OVERRIDE START
+
+/**
+  After console ready before boot option event callback
+
+  @param[in] Event  The Event this notify function registered to.
+  @param[in] ContextPointer to the context data registered to the Event.
+**/
+VOID
+EFIAPI
+LogoDxeDisplayEventCallback (
+  IN EFI_EVENT  Event,
+  IN VOID   *Context
+  )
+{
+  DEBUG ((DEBUG_INFO, "AMD logo is displaying.\n"));
+
+  BootLogoEnableLogo ();
+  gBS->CloseEvent (Event);
+}
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle   The firmware allocated handle for the EFI image.
+  @param  SystemTable   A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS   The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL*HiiDatabase;
+  EFI_HANDLE   Handle;
+  EFI_EVENTAfterConsoleReadyBeforeBootOptionEvent;
+
+  Status = 

[edk2-devel] [PATCH V3 00/32] Introduce AMD Vangogh platform reference code

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

In V3: Improve coding style follow edk2 C coding standard.
  1.Remove macro definition extra underscores.
  2.Putting some AMD copyright in the right place.

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  This AMD reference platform BIOS supports AMD Vangogh B0 SOC and Chachani 
board.

Duke Zhai (32):
  AMD/AmdPlatformPkg: Check in AMD S3 logo
  AMD/VanGoghBoard: Check in ACPI tables
  AMD/VanGoghBoard: Check in Capsule update
  AMD/VanGoghBoard: Check in AgesaPublic pkg
  AMD/VanGoghBoard: Check in PlatformSecLib
  AMD/VanGoghBoard: Check in AmdIdsExtLib
  AMD/VanGoghBoard: Check in PciPlatform
  AMD/VanGoghBoard: Check in UDKFlashUpdate
  AMD/VanGoghBoard: Check in Flash_AB
  AMD/VanGoghBoard: Check in FlashUpdate
  AMD/VanGoghBoard: Check in FvbServices
  AMD/VanGoghBoard: Check in AMD BaseSerialPortLib
  AMD/VanGoghBoard: Check in PlatformFlashAccessLib
  AMD/VanGoghBoard: Check in SmbiosLib
  AMD/VanGoghBoard: Check in SpiFlashDeviceLib
  AMD/VanGoghBoard: Check in BaseTscTimerLib
  AMD/VanGoghBoard: Check in Smm access module
  AMD/VanGoghBoard: Check in PciHostBridge module
  AMD/VanGoghBoard: Check in PcatRealTimeClockRuntimeDxe  module
  AMD/VanGoghBoard: Check in FTPM module
  AMD/VanGoghBoard: Check in SignedCapsule
  AMD/VanGoghBoard: Check in Vtf0
  AMD/VanGoghBoard: Check in AcpiPlatform
  AMD/VanGoghBoard: Check in FchSpi module
  AMD/VanGoghBoard: Check in PlatformInitPei module
  AMD/VanGoghBoard: Check in Smbios platform dxe drivers
  AMD/VanGoghBoard: Check in Fsp2WrapperPkg
  AMD/VanGoghBoard: Check in SmmCpuFeaturesLibCommon module
  AMD/VanGoghBoard: Check in SmramSaveState module
  AMD/VanGoghBoard: Check in EDK2 override files
  AMD/VanGoghBoard: Check in AMD SmmControlPei module
  AMD/VanGoghBoard: Check in Chachani board project files and build
script

 .../AmdPlatformPkg/Universal/LogoDxe/Logo.c   |  198 +
 .../Universal/LogoDxe/S3Logo.bmp  |  Bin 0 -> 964114 bytes
 .../Universal/LogoDxe/S3Logo.idf  |9 +
 .../Universal/LogoDxe/S3LogoDxe.inf   |   55 +
 .../VanGoghBoard/AgesaPublic/AgesaPublic.dec  |   61 +
 .../VanGoghBoard/AgesaPublic/Include/AGESA.h  |   35 +
 .../VanGoghBoard/AgesaPublic/Include/AMD.h|  189 +
 .../AgesaPublic/Include/AmdPspDirectory.h |   55 +
 .../AgesaPublic/Include/FchRegistersCommon.h  |   23 +
 .../Include/Guid/AmdMemoryInfoHob.h   |   51 +
 .../Include/Library/AmdPspBaseLibV2.h |  248 +
 .../Include/Library/AmdPspCommonLib.h |   29 +
 .../Include/Library/AmdPspFtpmLib.h   |   94 +
 .../AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h   |   80 +
 .../Include/Protocol/AmdPspFtpmProtocol.h |  112 +
 .../Acpi/AcpiTables/AcpiTables.inf|   33 +
 .../Acpi/AcpiTables/Dsdt/CPU.asl  |   22 +
 .../Acpi/AcpiTables/Dsdt/Dsdt.asl |   36 +
 .../Acpi/AcpiTables/Dsdt/FchShang.asi |  927 ++
 .../Acpi/AcpiTables/Dsdt/GloblNvs.asl |   17 +
 .../Acpi/AcpiTables/Dsdt/HOST_BUS.ASL |  209 +
 .../Acpi/AcpiTables/Dsdt/LINK.ASL |  481 ++
 .../Acpi/AcpiTables/Dsdt/Lpc0.asl |  168 +
 .../Acpi/AcpiTables/Dsdt/PciTree.asl  |  776 ++
 .../Acpi/AcpiTables/Dsdt/Platform.asl |  135 +
 .../Acpi/AcpiTables/Dsdt/_PR.asl  |   36 +
 .../Acpi/AcpiTables/Facs/Facs.h   |   31 +
 .../Acpi/AcpiTables/Facs/Facs50.aslc  |   68 +
 .../Acpi/AcpiTables/Fadt/Fadt.h   |   64 +
 .../Acpi/AcpiTables/Fadt/Fadt50.aslc  |  159 +
 .../Acpi/AcpiTables/Hpet/Hpet.h   |   70 +
 .../Acpi/AcpiTables/Hpet/Hpet50.aslc  |   58 +
 .../Acpi/AcpiTables/Madt/Madt.h   |  114 +
 .../Acpi/AcpiTables/Madt/Madt50.aslc  |  327 +
 .../Acpi/AcpiTables/Mcfg/Mcfg.h   |   61 +
 .../Acpi/AcpiTables/Mcfg/Mcfg50.aslc  |   61 +
 .../BIOSImageDirectory32M.xml |   63 +
 .../VanGoghBoard/ChachaniBoardPkg/Board.env   |   23 +
 .../ChachaniBoardPkg/BuildPspImage.bat|  126 +
 .../SystemFirmwareDescriptor.aslc |   85 +
 .../SystemFirmwareDescriptor.inf  |   39 +
 .../SystemFirmwareDescriptorPei.c |   64 +
 .../ChachaniBoardPkg/Conf/ReadMe.txt  |   14 +
 .../ChachaniBoardPkg/Conf/build_rule.txt  |  654 ++
 .../ChachaniBoardPkg/Conf/target.txt  |   73 +
 .../ChachaniBoardPkg/Conf/tools_def.txt   | 7571 +
 .../ChachaniBoardPkg/FlashABImage32M.py   |  102 +
 .../ChachaniBoardPkg/GenCapsule.bat   |   81 +
 .../ChachaniBoardPkg/GenFlashABImage.bat  |   39 +
 .../ChachaniBoardPkg/GoZ_ChachaniExt.bat  |   81 +
 .../Include/Library/CapsuleHookLib.h  |   40 +
 .../Include/Protocol/GlobalNvsArea.h  |   63 

[edk2-devel] [PATCH V2 32/32] AMD/VanGoghBoard: Check in Chachani board project files and build script

[Zhai, MingXin (Duke) via groups.io]

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[edk2-devel] [PATCH V2 31/32] AMD/VanGoghBoard: Check in AMD SmmControlPei module

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial AMD SmmControlPei module in Silicon folder.
  This module initializes SMM-related registers, and installs gPeiSmmControlPpi.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Smm/SmmControlPei/SmmControlPei.c | 307 ++
 .../Smm/SmmControlPei/SmmControlPei.inf   |  40 +++
 2 files changed, 347 insertions(+)
 create mode 100644 Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c
 create mode 100644 Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.inf

diff --git a/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c 
b/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c
new file mode 100644
index 00..4752aede9c
--- /dev/null
+++ b/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c
@@ -0,0 +1,307 @@
+/** @file
+  Implements SmmControlPei.c
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  This routine generates an SMI
+
+  @param[in]   PeiServices   Describes the list of possible PEI 
Services.
+  @param[in]   This  The pointer to this instance of this 
PPI.
+  @param[in, out]  ArgumentBufferThe buffer of argument
+  @param[in, out]  ArgumentBufferSizeThe size of the argument buffer
+  @param[in]   Periodic  TRUE to indicate a periodical SMI
+  @param[in]   ActivationIntervalInterval of periodic SMI
+
+  @retval  EFI_SUCCESSSMI generated.
+  @retval  EFI_INVALID_PARAMETER  Some parameter value passed is not supported
+**/
+EFI_STATUS
+EFIAPI
+PeiTrigger (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_SMM_CONTROL_PPI  *This,
+  IN OUT INT8 *ArgumentBuffer OPTIONAL,
+  IN OUT UINTN*ArgumentBufferSize OPTIONAL,
+  IN BOOLEAN  Periodic OPTIONAL,
+  IN UINTNActivationInterval OPTIONAL
+  );
+
+/**
+  Clear SMI related chipset status.
+
+  @param[in]  PeiServices   Describes the list of possible PEI 
Services.
+  @param[in]  This  The pointer to this instance of this PPI.
+  @param[in]  Periodic  TRUE to indicate a periodical SMI.
+
+  @return  Return value from ClearSmi()
+**/
+EFI_STATUS
+EFIAPI
+PeiClear (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_SMM_CONTROL_PPI  *This,
+  IN BOOLEAN  Periodic OPTIONAL
+  );
+
+STATIC PEI_SMM_CONTROL_PPI  mSmmControlPpi = {
+  PeiTrigger,
+  PeiClear
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR  mPpiList = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  
+};
+
+/**
+ Init related registers
+
+ @param [in]None
+
+ @retval  EFI_LOAD_ERROR  Get ACPI MMIO base error.
+ @retval  EFI_SUCCESS The function completed successfully..
+*/
+EFI_STATUS
+SmmControlPeiPreInit (
+  VOID
+  )
+{
+  UINT16  SmmControlData16;
+  UINT16  SmmControlMask16;
+  UINT32  SmmControlData32;
+  UINT8   SmmControlIndex;
+  UINT16  AcpiPmBase;
+
+  //
+  // Get ACPI MMIO base and AcpiPm1EvtBlk address
+  //
+  AcpiPmBase = MmioRead16 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60);
+
+  if (0 == AcpiPmBase) {
+return EFI_LOAD_ERROR;
+  }
+
+  //
+  // Clean up all SMI status and enable bits
+  //
+  // Clear all SmiControl registers
+  SmmControlData32 = 0;
+  for (SmmControlIndex = FCH_SMI_REGA0; SmmControlIndex <= FCH_SMI_REGC4; 
SmmControlIndex += 4) {
+MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + SmmControlIndex, 
SmmControlData32);
+  }
+
+  // Clear all SmiStatus registers (SmiStatus0-4)
+  SmmControlData32 = 0x;
+  MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG80, SmmControlData32);
+  MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG84, SmmControlData32);
+  MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG88, SmmControlData32);
+  MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG8C, SmmControlData32);
+  MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG90, SmmControlData32);
+
+  //
+  // If SCI is not enabled, clean up all ACPI PM status/enable registers
+  //
+  SmmControlData16 = IoRead16 (AcpiPmBase + R_FCH_ACPI_PM_CONTROL);
+  if (!(SmmControlData16 & BIT0)) {
+// Clear WAKE_EN, RTC_EN, SLPBTN_EN, GBL_EN and TMR_EN
+SmmControlData16 = 0;
+SmmControlMask16 = (UINT16) ~(BIT15 + BIT10 + BIT9 + BIT5 + BIT0);
+IoAndThenOr16 (AcpiPmBase + R_FCH_ACPI_PM1_ENABLE, SmmControlMask16, 
SmmControlData16);
+
+// Clear WAKE_STS, RTC_STS, SLPBTN_STS, GBL_STS and TMR_STS
+SmmControlData16 = BIT15 + BIT10 + BIT9 + BIT5 + BIT0;
+IoWrite16 

[edk2-devel] [PATCH V2 28/32] AMD/VanGoghBoard: Check in SmmCpuFeaturesLibCommon module.

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial SmmCpuFeaturesLibCommon module. The CPU specific programming for
  PiSmmCpuDxeSmm module when STM support is not included.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../SmmCpuFeaturesLibCommon.c | 623 ++
 1 file changed, 623 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c

diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
new file mode 100644
index 00..f3615e2d9e
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
@@ -0,0 +1,623 @@
+/** @file
+Implementation shared across all library instances.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) Microsoft Corporation.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "CpuFeaturesLib.h"
+
+//
+// Machine Specific Registers (MSRs)
+//
+#define  SMM_FEATURES_LIB_IA32_MTRR_CAP0x0FE
+#define  SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A
+#define  SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE   0x1F2
+#define  SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK   0x1F3
+#define  SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE  0x0A0
+#define  SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK  0x0A1
+#defineEFI_MSR_SMRR_MASK   0xF000
+#defineEFI_MSR_SMRR_PHYS_MASK_VALIDBIT11
+#define  SMM_FEATURES_LIB_SMM_FEATURE_CONTROL  0x4E0
+
+//
+// MSRs required for configuration of SMM Code Access Check
+//
+#define SMM_FEATURES_LIB_IA32_MCA_CAP  0x17D
+#define   SMM_CODE_ACCESS_CHK_BIT  BIT58
+
+extern UINT8  mSmmSaveStateRegisterLma;
+
+//
+// Set default value to assume SMRR is not supported
+//
+BOOLEAN  mSmrrSupported = FALSE;
+
+//
+// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported
+//
+BOOLEAN  mSmmFeatureControlSupported = FALSE;
+
+//
+// Set default value to assume IA-32 Architectural MSRs are used
+//
+UINT32  mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;
+UINT32  mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;
+
+//
+// Set default value to assume MTRRs need to be configured on each SMI
+//
+BOOLEAN  mNeedConfigureMtrrs = TRUE;
+
+//
+// Array for state of SMRR enable on all CPUs
+//
+BOOLEAN  *mSmrrEnabled;
+
+/**
+  Performs library initialization.
+
+  This initialization function contains common functionality shared betwen all
+  library instance constructors.
+
+**/
+VOID
+CpuFeaturesLibInitialization (
+  VOID
+  )
+{
+  UINT32  RegEax;
+  UINT32  RegEdx;
+  UINTN   FamilyId;
+  UINTN   ModelId;
+
+  //
+  // Retrieve CPU Family and Model
+  //
+  AsmCpuid (CPUID_VERSION_INFO, , NULL, NULL, );
+  FamilyId = (RegEax >> 8) & 0xf;
+  ModelId  = (RegEax >> 4) & 0xf;
+  if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
+ModelId = ModelId | ((RegEax >> 12) & 0xf0);
+  }
+
+  //
+  // Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability
+  //
+  if ((RegEdx & BIT12) != 0) {
+//
+// Check MTRR_CAP MSR bit 11 for SMRR support
+//
+if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {
+  mSmrrSupported = TRUE;
+}
+  }
+
+  //
+  // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+  // Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family
+  //
+  // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then
+  // SMRR Physical Base and SMM Physical Mask MSRs are not available.
+  //
+  if (FamilyId == 0x06) {
+if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) || 
(ModelId == 0x35) || (ModelId == 0x36)) {
+  mSmrrSupported = FALSE;
+}
+  }
+
+  //
+  // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+  // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
+  //
+  // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2
+  // Processor Family MSRs
+  //
+  if (FamilyId == 0x06) {
+if ((ModelId == 0x17) || (ModelId == 0x0f)) {
+  mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;
+  mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;
+}
+  }
+
+  //
+  // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+  // Volume 3C, Section 34.4.2 SMRAM 

[edk2-devel] [PATCH V2 29/32] AMD/VanGoghBoard: Check in SmramSaveState module

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial SmramSaveState module.
  This module provides services to access SMRAM Save State Map.

Signed-off-by: Ken Yao 
Cc: Eric Xing 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../PiSmmCpuDxeSmm/SmramSaveState.c   | 706 ++
 1 file changed, 706 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c

diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
new file mode 100644
index 00..ca63de9ba6
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -0,0 +1,706 @@
+/** @file
+Provides services to access SMRAM Save State Map
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "PiSmmCpuDxeSmm.h"
+
+typedef struct {
+  UINT64Signature;  // Offset 0x00
+  UINT16Reserved1;  // Offset 0x08
+  UINT16Reserved2;  // Offset 0x0A
+  UINT16Reserved3;  // Offset 0x0C
+  UINT16SmmCs;  // Offset 0x0E
+  UINT16SmmDs;  // Offset 0x10
+  UINT16SmmSs;  // Offset 0x12
+  UINT16SmmOtherSegment;// Offset 0x14
+  UINT16Reserved4;  // Offset 0x16
+  UINT64Reserved5;  // Offset 0x18
+  UINT64Reserved6;  // Offset 0x20
+  UINT64Reserved7;  // Offset 0x28
+  UINT64SmmGdtPtr;  // Offset 0x30
+  UINT32SmmGdtSize; // Offset 0x38
+  UINT32Reserved8;  // Offset 0x3C
+  UINT64Reserved9;  // Offset 0x40
+  UINT64Reserved10; // Offset 0x48
+  UINT16Reserved11; // Offset 0x50
+  UINT16Reserved12; // Offset 0x52
+  UINT32Reserved13; // Offset 0x54
+  UINT64Reserved14; // Offset 0x58
+} PROCESSOR_SMM_DESCRIPTOR;
+
+extern CONST PROCESSOR_SMM_DESCRIPTOR  gcPsd;
+
+//
+// EFER register LMA bit
+//
+#define LMA  BIT10
+
+///
+/// Macro used to simplify the lookup table entries of type 
CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
+///
+#define SMM_CPU_OFFSET(Field)  OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
+
+///
+/// Macro used to simplify the lookup table entries of type 
CPU_SMM_SAVE_STATE_REGISTER_RANGE
+///
+#define SMM_REGISTER_RANGE(Start, End)  { Start, End, End - Start + 1 }
+
+///
+/// Structure used to describe a range of registers
+///
+typedef struct {
+  EFI_SMM_SAVE_STATE_REGISTERStart;
+  EFI_SMM_SAVE_STATE_REGISTEREnd;
+  UINTN  Length;
+} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
+
+///
+/// Structure used to build a lookup table to retrieve the widths and offsets
+/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
+///
+
+#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX   1
+#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2
+#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX  3
+#define SMM_SAVE_STATE_REGISTER_MAX_INDEX4
+
+typedef struct {
+  UINT8  Width32;
+  UINT8  Width64;
+  UINT16 Offset32;
+  UINT16 Offset64Lo;
+  UINT16 Offset64Hi;
+  BOOLEANWriteable;
+} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
+
+///
+/// Structure used to build a lookup table for the IOMisc width information
+///
+typedef struct {
+  UINT8  Width;
+  EFI_SMM_SAVE_STATE_IO_WIDTHIoWidth;
+} CPU_SMM_SAVE_STATE_IO_WIDTH;
+
+///
+/// Variables from SMI Handler
+///
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmbase;
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmiStack;
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmiCr3;
+extern volatile UINT8 gcSmiHandlerTemplate[];
+extern CONST UINT16   gcSmiHandlerSize;
+
+//
+// Variables used by SMI Handler
+//
+IA32_DESCRIPTOR  gSmiHandlerIdtr;
+
+///
+/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
+/// 

[edk2-devel] [PATCH V2 26/32] AMD/VanGoghBoard: Check in Smbios platform dxe drivers

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial Smbios platform DXE drivers. Static SMBIOS Table for Chachani 
platform.
  SmbiosLib provides detailed information of Chachani platform.

Signed-off-by: Eric Xing 
Cc: Ken Yao 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../PlatformSmbiosDxe/PlatformSmbiosDxe.c |  75 
 .../PlatformSmbiosDxe/PlatformSmbiosDxe.inf   |  53 +++
 .../Universal/PlatformSmbiosDxe/SmbiosTable.c | 382 ++
 3 files changed, 510 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/SmbiosTable.c

diff --git 
a/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.c 
b/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.c
new file mode 100644
index 00..c4de6ca133
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.c
@@ -0,0 +1,75 @@
+/** @file
+  Static SMBIOS Table for platform
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2012, Apple Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+extern SMBIOS_TEMPLATE_ENTRY  gSmbiosTemplate[];
+
+/**
+  Main entry for this driver.
+
+  @param ImageHandle Image handle this driver.
+  @param SystemTable Pointer to SystemTable.
+
+  @retval EFI_SUCESS This function always complete successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformSmbiosDriverEntryPoint (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUSStatus;
+  EFI_SMBIOS_HANDLE SmbiosHandle;
+  SMBIOS_STRUCTURE_POINTER  Smbios;
+
+  DEBUG ((DEBUG_INFO, " PlatfomrSmbiosDriverEntryPoint \n"));
+
+  // Phase 0 - Patch table to make SMBIOS 2.7 structures smaller to conform
+  //   to an early version of the specification.
+
+  // Phase 1 - Initialize SMBIOS tables from template
+  Status = SmbiosLibInitializeFromTemplate (gSmbiosTemplate);
+  ASSERT_EFI_ERROR (Status);
+
+  // Phase 2 - Patch SMBIOS table entries
+  Smbios.Hdr = SmbiosLibGetRecord (EFI_SMBIOS_TYPE_BIOS_INFORMATION, 0, 
);
+  if (Smbios.Type0 != NULL) {
+// 64K * (n+1) bytes
+Smbios.Type0->BiosSize = (UINT8)DivU64x32 (FixedPcdGet64 
(PcdFlashAreaSize), 64*1024) - 1;
+
+SmbiosLibUpdateUnicodeString (
+  SmbiosHandle,
+  Smbios.Type0->BiosVersion,
+  (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString)
+  );
+
+DEBUG ((
+  DEBUG_INFO,
+  " Smbios.Type0->BiosSize: %dMB, Smbios.Type0->BiosVersion: %S, Build 
Time: %a,%a\n",
+  (Smbios.Type0->BiosSize +1) * 64 / 1024,
+  (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),
+  __DATE__,
+  __TIME__
+  ));
+  }
+
+  return EFI_SUCCESS;
+}
diff --git 
a/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.inf 
b/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
new file mode 100644
index 00..e16a448d7a
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
@@ -0,0 +1,53 @@
+## @file
+# Platform SMBIOS driver that fills in SMBIOS table entries.
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2012, Apple Inc. All rights reserved.
+# Portions copyright (c) 2006 - 2010, Intel Corporation. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = PlatformSmbiosDxe
+  FILE_GUID  = 15EEEB97-709E-91FA-CDA7-44A9C85DDB78
+  MODULE_TYPE= DXE_DRIVER
+  VERSION_STRING = 1.0
+  ENTRY_POINT= PlatformSmbiosDriverEntryPoint
+
+
+[Sources]
+  SmbiosTable.c
+  PlatformSmbiosDxe.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  VanGoghCommonPkg/AmdCommonPkg.dec
+  ChachaniBoardPkg/Project.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  PcdLib
+  MemoryAllocationLib
+  UefiBootServicesTableLib
+  UefiLib
+  HobLib
+  SmbiosLib
+
+[Protocols]
+  gEfiSmbiosProtocolGuid
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+  gPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
+
+[Depex]
+  gEfiSmbiosProtocolGuid
diff --git 

[edk2-devel] [PATCH V2 25/32] AMD/VanGoghBoard: Check in PlatformInitPei module

[Zhai, MingXin (Duke) via groups.io]

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[edk2-devel] [PATCH V2 24/32] AMD/VanGoghBoard: Check in FchSpi module

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial FchSpi module. FCH SPI Common Driver implements
  the SPI Host Controller Compatibility Interface.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Universal/FchSpi/FchSpiProtect.c  |  67 ++
 .../Universal/FchSpi/FchSpiProtect.h  |  38 +
 .../Universal/FchSpi/FchSpiRuntimeDxe.c   | 163 
 .../Universal/FchSpi/FchSpiRuntimeDxe.h   |  49 ++
 .../Universal/FchSpi/FchSpiRuntimeDxe.inf |  84 ++
 .../VanGoghBoard/Universal/FchSpi/FchSpiSmm.c | 112 +++
 .../VanGoghBoard/Universal/FchSpi/FchSpiSmm.h |  32 +
 .../Universal/FchSpi/FchSpiSmm.inf|  94 +++
 .../VanGoghBoard/Universal/FchSpi/SpiCommon.c | 790 ++
 .../VanGoghBoard/Universal/FchSpi/SpiInfo.h   |  24 +
 10 files changed, 1453 insertions(+)
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.c
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.h
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.h
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.inf
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiSmm.c
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiSmm.h
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiSmm.inf
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/SpiCommon.c
 create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/SpiInfo.h

diff --git a/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.c 
b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.c
new file mode 100644
index 00..658d9b063d
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.c
@@ -0,0 +1,67 @@
+/** @file
+  Implements FchSpiProtect.c
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "FchSpiProtect.h"
+
+/**
+
+   Fch Spi Protect Lock
+
+   @param SpiMmioBase
+
+**/
+EFI_STATUS
+EFIAPI
+FchSpiProtect_Lock (
+  IN UINTN  SpiMmioBase
+  )
+{
+  if (!(MmioRead8 (SpiMmioBase + 2) & 0xC0)) {
+// Check BIT7+BIT6
+return EFI_SUCCESS;
+  } else {
+MmioWrite8 (SpiMmioBase + 9, 0x6);// 
PrefixOpCode WRITE_ENABLE
+MmioWrite8 (SpiMmioBase + 2, MmioRead8 (SpiMmioBase + 2) & 0x3F); // Clear 
BIT7+BIT6
+if (MmioRead8 (SpiMmioBase + 2) & 0xC0) {
+  return EFI_DEVICE_ERROR;
+}
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+
+   Fch Spi Protect UnLock
+
+   @param SpiMmioBase
+
+**/
+EFI_STATUS
+EFIAPI
+FchSpiProtect_UnLock (
+  IN UINTN  SpiMmioBase
+  )
+{
+  if ((MmioRead8 (SpiMmioBase + 2) & 0xC0) || (6 != MmioRead8 (SpiMmioBase + 
9))) {
+return EFI_SUCCESS;
+  } else {
+MmioWrite8 (SpiMmioBase + 9, 0x0);
+MmioWrite8 (SpiMmioBase + 2, MmioRead8 (SpiMmioBase + 2) | 0xC0); // Set 
BIT7+BIT6
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.h 
b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.h
new file mode 100644
index 00..1dd57c6f52
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.h
@@ -0,0 +1,38 @@
+/** @file
+  Implements FchSpiProtect.h
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef FCH_SPI_PROTECT_H__
+#define FCH_SPI_PROTECT_H__
+
+/**
+
+   Fch Spi Protect Lock
+
+   @param UINTN SpiMmioBase
+
+**/
+EFI_STATUS
+EFIAPI
+FchSpiProtect_Lock (
+  IN UINTN  SpiMmioBase
+  );
+
+/**
+
+   Fch Spi Protect UnLock
+
+   @param UINTN SpiMmioBase
+
+**/
+EFI_STATUS
+EFIAPI
+FchSpiProtect_UnLock (
+  IN UINTN  SpiMmioBase
+  );
+
+#endif
diff --git a/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.c 
b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.c
new file mode 100644
index 00..7bb402402c
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.c
@@ -0,0 +1,163 @@
+/** @file
+PCH SPI Runtime Driver implements the SPI Host Controller Compatibility 
Interface.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2015 Intel Corporation.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifdef _MSC_VER
+  #pragma optimize( "", off )
+#endif
+
+#ifdef __GNUC__
+  #ifndef __clang__
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+  #else
+

[edk2-devel] [PATCH V2 23/32] AMD/VanGoghBoard: Check in AcpiPlatform

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial Acpi platform dxe drivers. Use firmware volume protocol
  to update global NVS area for ASL and SMM init code.

Signed-off-by: Eric Xing 
Cc: Ken Yao 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Universal/AcpiPlatformDxe/AcpiPlatform.c  | 336 ++
 .../AcpiPlatformDxe/AcpiPlatform.uni  |  15 +
 .../AcpiPlatformDxe/AcpiPlatformDxe.inf   |  59 +++
 .../AcpiPlatformDxe/AcpiPlatformExtra.uni |  13 +
 .../AcpiPlatformDxe/AcpiPlatformHooks.c   | 152 
 .../AcpiPlatformDxe/AcpiPlatformHooks.h   |  48 +++
 6 files changed, 623 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatformDxe.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatformExtra.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatformHooks.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatformHooks.h

diff --git a/Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.c 
b/Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.c
new file mode 100644
index 00..73a022594e
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.c
@@ -0,0 +1,336 @@
+/** @file
+  Sample ACPI Platform Driver
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "AcpiPlatformHooks.h"
+#include 
+
+EFI_GLOBAL_NVS_AREA_PROTOCOL  mGlobalNvsArea;
+
+/**
+  Locate the first instance of a protocol.  If the protocol requested is an
+  FV protocol, then it will return the first FV that contains the ACPI table
+  storage file.
+
+  @param  Instance  Return pointer to the first instance of the protocol
+
+  @return EFI_SUCCESS   The function completed successfully.
+  @return EFI_NOT_FOUND The protocol could not be located.
+  @return EFI_OUT_OF_RESOURCES  There are not enough resources to find the 
protocol.
+
+**/
+EFI_STATUS
+LocateFvInstanceWithTables (
+  OUT EFI_FIRMWARE_VOLUME2_PROTOCOL  **Instance
+  )
+{
+  EFI_STATUS Status;
+  EFI_HANDLE *HandleBuffer;
+  UINTN  NumberOfHandles;
+  EFI_FV_FILETYPEFileType;
+  UINT32 FvStatus;
+  EFI_FV_FILE_ATTRIBUTES Attributes;
+  UINTN  Size;
+  UINTN  Index;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL  *FvInstance;
+
+  FvStatus = 0;
+
+  //
+  // Locate protocol.
+  //
+  Status = gBS->LocateHandleBuffer (
+  ByProtocol,
+  ,
+  NULL,
+  ,
+  
+  );
+  if (EFI_ERROR (Status)) {
+//
+// Defined errors at this time are not found and out of resources.
+//
+return Status;
+  }
+
+  //
+  // Looking for FV with ACPI storage file
+  //
+
+  for (Index = 0; Index < NumberOfHandles; Index++) {
+//
+// Get the protocol on this handle
+// This should not fail because of LocateHandleBuffer
+//
+Status = gBS->HandleProtocol (
+HandleBuffer[Index],
+,
+(VOID **)
+);
+ASSERT_EFI_ERROR (Status);
+
+//
+// See if it has the ACPI storage file
+//
+Status = FvInstance->ReadFile (
+   FvInstance,
+   (EFI_GUID *)PcdGetPtr (PcdAcpiTableStorageFile),
+   NULL,
+   ,
+   ,
+   ,
+   
+   );
+
+//
+// If we found it, then we are done
+//
+if (Status == EFI_SUCCESS) {
+  *Instance = FvInstance;
+  break;
+}
+  }
+
+  //
+  // Our exit status is determined by the success of the previous operations
+  // If the protocol was found, Instance already points to it.
+  //
+
+  //
+  // Free any allocated buffers
+  //
+  gBS->FreePool (HandleBuffer);
+
+  return Status;
+}
+
+/**
+  This function calculates and updates an UINT8 checksum.
+
+  @param  Buffer  Pointer to buffer to checksum
+  @param  SizeNumber of bytes to checksum
+
+**/
+VOID

[edk2-devel] [PATCH V2 21/32] AMD/VanGoghBoard: Check in SignedCapsule

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial SignedCapsule module for Signed Capsule.
  Produce FMP instance to update system firmware.

Signed-off-by: Ken Yao 
Cc: Eric Xing 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../BaseTools/Source/Python/GenFds/Capsule.py |  253 +++
 .../SystemFirmwareUpdate/ParseConfigProfile.c |  231 +++
 .../SystemFirmwareCommonDxe.c |  371 +
 .../SystemFirmwareUpdate/SystemFirmwareDxe.h  |  421 +
 .../SystemFirmwareUpdateDxe.c | 1426 +
 .../SystemFirmwareUpdateDxe.inf   |   91 ++
 .../SystemFirmwareUpdateDxe.uni   |   15 +
 .../SystemFirmwareUpdateDxeExtra.uni  |   15 +
 8 files changed, 2823 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/BaseTools/Source/Python/GenFds/Capsule.py
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/ParseConfigProfile.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareCommonDxe.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareDxe.h
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxeExtra.uni

diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/BaseTools/Source/Python/GenFds/Capsule.py
 
b/Platform/AMD/VanGoghBoard/Override/edk2/BaseTools/Source/Python/GenFds/Capsule.py
new file mode 100644
index 00..0ec0b3ca43
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/Override/edk2/BaseTools/Source/Python/GenFds/Capsule.py
@@ -0,0 +1,253 @@
+## @file
+# generate capsule
+#
+#  Copyright (C) 2024 Advanced Micro Devices, Inc.
+#  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+##
+# Import Modules
+#
+from __future__ import absolute_import
+from .GenFdsGlobalVariable import GenFdsGlobalVariable, FindExtendTool
+from CommonDataClass.FdfClass import CapsuleClassObject
+import Common.LongFilePathOs as os
+from io import BytesIO
+from Common.Misc import SaveFileOnChange, PackGUID
+import uuid
+from struct import pack
+from Common import EdkLogger
+from Common.BuildToolError import GENFDS_ERROR
+from Common.DataType import TAB_LINE_BREAK
+
+WIN_CERT_REVISION = 0x0200
+WIN_CERT_TYPE_EFI_GUID = 0x0EF1
+EFI_CERT_TYPE_PKCS7_GUID = uuid.UUID('{4aafd29d-68df-49ee-8aa9-347d375665a7}')
+EFI_CERT_TYPE_RSA2048_SHA256_GUID = 
uuid.UUID('{a7717414-c616-4977-9420-844712a735bf}')
+
+## create inf file describes what goes into capsule and call GenFv to generate 
capsule
+#
+#
+class Capsule (CapsuleClassObject):
+## The constructor
+#
+#   @param  selfThe object pointer
+#
+def __init__(self):
+CapsuleClassObject.__init__(self)
+# For GenFv
+self.BlockSize = None
+# For GenFv
+self.BlockNum = None
+self.CapsuleName = None
+
+## Generate FMP capsule
+#
+#   @retval string  Generated Capsule file path
+#
+def GenFmpCapsule(self):
+#
+# Generate capsule header
+# typedef struct {
+# EFI_GUID  CapsuleGuid;
+# UINT32HeaderSize;
+# UINT32Flags;
+# UINT32CapsuleImageSize;
+# } EFI_CAPSULE_HEADER;
+#
+Header = BytesIO()
+#
+# Use FMP capsule GUID: 6DCBD5ED-E82D-4C44-BDA1-7194199AD92A
+#
+
Header.write(PackGUID('6DCBD5ED-E82D-4C44-BDA1-7194199AD92A'.split('-')))
+HdrSize = 0
+if 'CAPSULE_HEADER_SIZE' in self.TokensDict:
+Header.write(pack('=I', 
int(self.TokensDict['CAPSULE_HEADER_SIZE'], 16)))
+HdrSize = int(self.TokensDict['CAPSULE_HEADER_SIZE'], 16)
+else:
+Header.write(pack('=I', 0x20))
+HdrSize = 0x20
+Flags = 0
+if 'CAPSULE_FLAGS' in self.TokensDict:
+for flag in self.TokensDict['CAPSULE_FLAGS'].split(','):
+flag = flag.strip()
+if flag == 'PopulateSystemTable':
+Flags |= 0x0001 | 0x0002
+elif 

[edk2-devel] [PATCH V2 22/32] AMD/VanGoghBoard: Check in Vtf0

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial Vtf0 module.
  This module includes all assembly code files of reset vector.

Signed-off-by: Eric Xing 
Cc: Ken Yao 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../ResetVector/Vtf0/CommonMacros.inc |  27 +++
 .../ResetVector/Vtf0/DebugDisabled.asm|  21 ++
 .../ResetVector/Vtf0/Ia16/Init16.asm  |  51 +
 .../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm  | 138 +
 .../ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm | 108 ++
 .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm  |  40 
 .../ResetVector/Vtf0/Ia32/PageTables64.asm|  25 +++
 .../Vtf0/Ia32/SearchForBfvBase.asm|  84 
 .../Vtf0/Ia32/SearchForSecEntry.asm   | 195 ++
 .../edk2/UefiCpuPkg/ResetVector/Vtf0/Main.asm | 127 
 .../ResetVector/Vtf0/Port80Debug.asm  |  23 +++
 .../UefiCpuPkg/ResetVector/Vtf0/PostCodes.inc |  20 ++
 .../ResetVector/Vtf0/ResetVector.uni  | Bin 0 -> 780 bytes
 .../ResetVector/Vtf0/ResetVectorExtra.uni | Bin 0 -> 682 bytes
 .../ResetVector/Vtf0/SerialDebug.asm  | 127 
 .../edk2/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf |  37 
 .../UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb|  67 ++
 .../ResetVector/Vtf0/X64/PageTables.asm   |  73 +++
 18 files changed, 1163 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/DebugDisabled.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia16/Init16.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForBfvBase.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForSecEntry.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Main.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Port80Debug.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/PostCodes.inc
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/ResetVector.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/ResetVectorExtra.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/SerialDebug.asm
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm

diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc
 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc
new file mode 100644
index 00..5da472faaa
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc
@@ -0,0 +1,27 @@
+;--
+; @file
+; Common macros used in the ResetVector VTF module.
+;
+; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;--
+
+%define ADDR16_OF(x) (0x1 - fourGigabytes + x)
+%define ADDR_OF(x) (0x1 - fourGigabytes + x)
+%define ADDR_OF_MEM(x) (VIRTUAL4G - fourGigabytes + x)
+%define SMM_RESUME_SIGNATURE 0x55AABB66
+%macro  OneTimeCall 1
+jmp %1
+%1 %+ OneTimerCallReturn:
+%endmacro
+
+%macro  OneTimeCallRet 1
+jmp %1 %+ OneTimerCallReturn
+%endmacro
+
+StartOfResetVectorCode:
+
+%define ADDR_OF_START_OF_RESET_CODE ADDR_OF(StartOfResetVectorCode)
+
diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/DebugDisabled.asm
 
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/DebugDisabled.asm
new file mode 

[edk2-devel] [PATCH V2 19/32] AMD/VanGoghBoard: Check in PcatRealTimeClockRuntimeDxe module

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  This driver provides GetTime, SetTime, GetWakeupTime, SetWakeupTime services 
to Runtime Service Table.
  It will install a tagging protocol with gEfiRealTimeClockArchProtocolGuid.

Signed-off-by: Ken Yao 
Cc: Eric Xing 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../PcatRealTimeClockRuntimeDxe/PcRtc.c   | 1341 +
 .../PcatRealTimeClockRuntimeDxe/PcRtc.h   |  374 +
 .../PcatRealTimeClockRuntimeDxe/PcRtc.uni |   17 +
 .../PcatRealTimeClockRuntimeDxe/PcRtcEntry.c  |  171 +++
 .../PcRtcExtra.uni|   15 +
 .../PcatRealTimeClockRuntimeDxe.inf   |   77 +
 6 files changed, 1995 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcExtra.uni
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf

diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
 
b/Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
new file mode 100644
index 00..4e42d9d2ad
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
@@ -0,0 +1,1341 @@
+/** @file
+  RTC Architectural Protocol GUID as defined in DxeCis 0.96.
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PcRtc.h"
+
+//
+// Days of month.
+//
+UINTN  mDayOfMonth[] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+//
+// The name of NV variable to store the timezone and daylight saving 
information.
+//
+CHAR16  mTimeZoneVariableName[] = L"RTC";
+
+/**
+  Compare the Hour, Minute and Second of the From time and the To time.
+
+  Only compare H/M/S in EFI_TIME and ignore other fields here.
+
+  @param From   the first time
+  @param To the second time
+
+  @return  >0   The H/M/S of the From time is later than those of To time
+  @return  ==0  The H/M/S of the From time is same as those of To time
+  @return  <0   The H/M/S of the From time is earlier than those of To time
+**/
+INTN
+CompareHMS (
+  IN EFI_TIME  *From,
+  IN EFI_TIME  *To
+  );
+
+/**
+  To check if second date is later than first date within 24 hours.
+
+  @param  From   the first date
+  @param  To the second date
+
+  @retval TRUE   From is previous to To within 24 hours.
+  @retval FALSE  From is later, or it is previous to To more than 24 hours.
+**/
+BOOLEAN
+IsWithinOneDay (
+  IN EFI_TIME  *From,
+  IN EFI_TIME  *To
+  );
+
+/**
+  Read RTC content through its registers.
+
+  @param  Address  Address offset of RTC. It is recommended to use macros such 
as
+   RTC_ADDRESS_SECONDS.
+
+  @return The data of UINT8 type read from RTC.
+**/
+UINT8
+RtcRead (
+  IN  UINT8  Address
+  )
+{
+  IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, (UINT8)(Address | (UINT8)(IoRead8 
(PCAT_RTC_ADDRESS_REGISTER) & 0x80)));
+  return IoRead8 (PCAT_RTC_DATA_REGISTER);
+}
+
+/**
+  Write RTC through its registers.
+
+  @param  Address  Address offset of RTC. It is recommended to use macros such 
as
+   RTC_ADDRESS_SECONDS.
+  @param  Data The content you want to write into RTC.
+
+**/
+VOID
+RtcWrite (
+  IN  UINT8  Address,
+  IN  UINT8  Data
+  )
+{
+  IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, (UINT8)(Address | (UINT8)(IoRead8 
(PCAT_RTC_ADDRESS_REGISTER) & 0x80)));
+  IoWrite8 (PCAT_RTC_DATA_REGISTER, Data);
+}
+
+/**
+  Initialize RTC.
+
+  @param  GlobalFor global use inside this module.
+
+  @retval EFI_DEVICE_ERROR  Initialization failed due to device error.
+  @retval EFI_SUCCESS   Initialization successful.
+
+**/
+EFI_STATUS
+PcRtcInit (
+  IN PC_RTC_MODULE_GLOBALS  *Global
+  )
+{
+  EFI_STATUS  Status;
+  RTC_REGISTER_B  RegisterB;
+  EFI_TIMETime;
+  UINTN   DataSize;
+  UINT32  TimerVar;
+  BOOLEAN Enabled;
+  BOOLEAN Pending;
+
+  //
+  // Acquire RTC Lock to make access to RTC atomic
+  //
+  if (!EfiAtRuntime ()) {
+EfiAcquireLock (>RtcLock);

[edk2-devel] [PATCH V2 17/32] AMD/VanGoghBoard: Check in Smm access module

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial AMD Smm access module.
  Contains description files for ACPI SMM Platform handler module.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Smm/AcpiSmm/AcpiSmmPlatform.c | 183 
 .../Smm/AcpiSmm/AcpiSmmPlatform.h |  50 ++
 .../Smm/AcpiSmm/AcpiSmmPlatform.inf   |  57 +++
 .../Smm/SmmAccessPei/SmmAccessPei.c   | 436 ++
 .../Smm/SmmAccessPei/SmmAccessPei.inf |  43 ++
 5 files changed, 769 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAccessPei/SmmAccessPei.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAccessPei/SmmAccessPei.inf

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.c 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.c
new file mode 100644
index 00..20a0ed6cb7
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.c
@@ -0,0 +1,183 @@
+/** @file
+ACPISMM Driver implementation file.
+
+This is QNC Smm platform driver
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2019 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+/**
+  Allocate EfiACPIMemoryNVS below 4G memory address.
+
+  This function allocates EfiACPIMemoryNVS below 4G memory address.
+
+  @param[in] Size   Size of memory to allocate.
+
+  @return   Allocated address for output.
+
+**/
+VOID *
+AllocateAcpiNvsMemoryBelow4G (
+  IN UINTN  Size
+  )
+{
+  UINTN Pages;
+  EFI_PHYSICAL_ADDRESS  Address;
+  EFI_STATUSStatus;
+  VOID  *Buffer;
+
+  Pages   = EFI_SIZE_TO_PAGES (Size);
+  Address = 0x;
+
+  Status = gBS->AllocatePages (
+  AllocateMaxAddress,
+  EfiACPIMemoryNVS,
+  Pages,
+  
+  );
+  if (EFI_ERROR (Status)) {
+return NULL;
+  }
+
+  Buffer = (VOID *)(UINTN)Address;
+  ZeroMem (Buffer, Size);
+
+  return Buffer;
+}
+
+/**
+  Reserved S3 memory for InstallS3Memory
+
+  @retval  EFI_OUT_OF_RESOURCES Insufficient resources to complete 
function.
+  @retval  EFI_SUCCESS  Function has completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+ReservedS3Memory (
+  UINTN  SystemMemoryLength
+
+  )
+
+{
+  VOID*GuidHob;
+  EFI_SMRAM_HOB_DESCRIPTOR_BLOCK  *DescriptorBlock;
+  VOID*AcpiReservedBase;
+
+  UINTN   TsegIndex;
+  UINTN   TsegSize;
+  UINTN   TsegBase;
+  RESERVED_ACPI_S3_RANGE  *AcpiS3Range;
+
+  DEBUG ((DEBUG_INFO, "ReservedS3Memory, SystemMemoryLength: 0x%08X\n", 
SystemMemoryLength));
+  //
+  // Get Hob list for SMRAM desc
+  //
+  GuidHob = GetFirstGuidHob ();
+  ASSERT (GuidHob != NULL);
+  DEBUG ((DEBUG_INFO, "gEfiSmmPeiSmramMemoryReserveGuid: 0x%X \n", 
(UINTN)GuidHob));
+  DescriptorBlock = GET_GUID_HOB_DATA (GuidHob);
+  ASSERT (DescriptorBlock != NULL);
+
+  //
+  // Use the hob to get SMRAM capabilities
+  //
+  TsegIndex = DescriptorBlock->NumberOfSmmReservedRegions - 1;
+  DEBUG ((DEBUG_INFO, "DescriptorBlock->NumberOfSmmReservedRegions: 0x%X\n", 
DescriptorBlock->NumberOfSmmReservedRegions));
+  DEBUG ((DEBUG_INFO, "TsegIndex: 0x%X\n", TsegIndex));
+  ASSERT (TsegIndex <= (MAX_SMRAM_RANGES - 1));
+  TsegBase = (UINTN)DescriptorBlock->Descriptor[TsegIndex].PhysicalStart;
+  TsegSize = (UINTN)DescriptorBlock->Descriptor[TsegIndex].PhysicalSize;
+
+  DEBUG ((DEBUG_INFO, "SMM  Base: %08X\n", TsegBase));
+  DEBUG ((DEBUG_INFO, "SMM  Size: %08X\n", TsegSize));
+
+  //
+  // Now find the location of the data structure that is used to store the 
address
+  // of the S3 reserved memory.
+  //
+  AcpiS3Range = (RESERVED_ACPI_S3_RANGE *)(UINTN)(TsegBase + 
RESERVED_ACPI_S3_RANGE_OFFSET);
+  DEBUG ((DEBUG_INFO, "AcpiS3Range: %08X\n", (UINTN)AcpiS3Range));
+  //
+  // Allocate reserved ACPI memory for S3 resume.  Pointer to this region is
+  // stored in SMRAM in the first page of TSEG.
+  //
+  AcpiReservedBase = AllocateAcpiNvsMemoryBelow4G (PcdGet32 
(PcdS3AcpiReservedMemorySize));
+  DEBUG ((DEBUG_INFO, "AcpiReservedBase: %08X\n", (UINTN)AcpiReservedBase));
+  ASSERT (AcpiReservedBase != NULL);
+  if 

[edk2-devel] [PATCH V2 15/32] AMD/VanGoghBoard: Check in SpiFlashDeviceLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial AMD SpiFlashDeviceLib for Chachani board flash IC.
  Chachani board use the W25Q256JW as flash IC.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../SpiFlashDeviceLib/SpiFlashDeviceLib.c | 42 +++
 .../SpiFlashDeviceLib/SpiFlashDeviceLib.inf   | 29 +
 2 files changed, 71 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.inf

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.c
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.c
new file mode 100644
index 00..49636f6a89
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.c
@@ -0,0 +1,42 @@
+/** @file
+  Implements SpiFlashDeviceLib.c
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+SPI_INIT_TABLE  mSpiInitTable[] = {
+  { // W25Q256JW/W74M25JW
+SF_VENDOR_ID_WINBOND,
+SF_DEVICE_ID0_W25Q256JW,
+SF_DEVICE_ID1_W25Q256JW,
+{
+  SPI_COMMAND_WRITE_ENABLE,
+  SPI_COMMAND_WRITE_S_EN
+},
+{
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_JEDEC_ID,  
EnumSpiOperationJedecId},
+  { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_WRITE_S,   
EnumSpiOperationWriteStatus},
+  { EnumSpiOpcodeWrite,SPI_COMMAND_WRITE, 
EnumSpiOperationProgramData_1_Byte },
+  { EnumSpiOpcodeRead, SPI_COMMAND_READ,  
EnumSpiOperationReadData   },
+  { EnumSpiOpcodeWrite,SPI_COMMAND_ERASE, 
EnumSpiOperationErase_4K_Byte  },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_READ_S,
EnumSpiOperationReadStatus },
+  { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_CHIP_ERASE,
EnumSpiOperationFullChipErase  },
+  { EnumSpiOpcodeRead, SPI_COMMAND_READ_SFDP, 
EnumSpiOperationReadData   },
+  { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_RPMC_OP1,  
EnumSpiOperationOther  },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_RPMC_OP2,  
EnumSpiOperationReadData   },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_Enter_4Byte_Addr,  
EnumSpiOperationOther  },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_Exit_4Byte_Addr,   
EnumSpiOperationOther  }
+},
+0,
+0x200   // BIOS image size in flash
+  }
+};
+
+//
+// The total number of support flash part
+//
+UINT8  mNumSpiFlashMax = sizeof (mSpiInitTable) / sizeof (mSpiInitTable[0]);
diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.inf
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.inf
new file mode 100644
index 00..951cf6c480
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.inf
@@ -0,0 +1,29 @@
+## @file
+# SpiFlashDeviceLib
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = SpiFlashDeviceLib
+  FILE_GUID  = D5A903A8-4D19-4E4C-AAF4-07C5D10D5939
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = SpiFlashDeviceLib
+
+#
+#  VALID_ARCHITECTURES   = IA32 X64
+#
+
+[Sources]
+  SpiFlashDeviceLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  VanGoghCommonPkg/AmdCommonPkg.dec
+
+[LibraryClasses]
+  SpiFlashDeviceLib
--
2.31.1



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[edk2-devel] [PATCH V2 16/32] AMD/VanGoghBoard: Check in BaseTscTimerLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Provides basic TSC timer calibration based on the ACPI timer hardware.
  The performance counter features are provided by the processors time stamp 
counter.

Signed-off-by: Ken Yao 
Cc: Eric Xing 
Cc: Duke Zhai 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Library/TscTimerLib/BaseTscTimerLib.c |  23 ++
 .../Library/TscTimerLib/BaseTscTimerLib.inf   |  43 +++
 .../Library/TscTimerLib/DxeTscTimerLib.c  |  80 ++
 .../Library/TscTimerLib/DxeTscTimerLib.inf|  62 +
 .../Library/TscTimerLib/PeiTscTimerLib.c  |  53 
 .../Library/TscTimerLib/PeiTscTimerLib.inf|  56 
 .../Library/TscTimerLib/TscTimerLibInternal.h |  53 
 .../Library/TscTimerLib/TscTimerLibShare.c| 255 ++
 8 files changed, 625 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/PeiTscTimerLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/PeiTscTimerLib.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/TscTimerLibInternal.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/TscTimerLibShare.c

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.c
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.c
new file mode 100644
index 00..7dfef490e9
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.c
@@ -0,0 +1,23 @@
+/** @file
+  ACPI Timer implements one instance of Timer Library.
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "TscTimerLibInternal.h"
+
+/**  Get TSC frequency.
+
+  @return The number of TSC counts per second.
+
+**/
+UINT64
+InternalGetTscFrequency (
+  VOID
+  )
+{
+  return InternalCalculateTscFrequency ();
+}
diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.inf
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.inf
new file mode 100644
index 00..d6c4e2e1d6
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.inf
@@ -0,0 +1,43 @@
+## @file
+# BaseTscTimerLib
+#  Provides basic timer support using the ACPI timer hardware.  The performance
+#  counter features are provided by the processors time stamp counter.
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = BaseTscTimerLib
+  FILE_GUID  = D29338B9-50FE-4e4f-B7D4-A150A2C1F4FB
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = TimerLib
+
+
+#
+#  VALID_ARCHITECTURES   = IA32 X64
+#
+
+[Sources.common]
+  TscTimerLibShare.c
+  BaseTscTimerLib.c
+  TscTimerLibInternal.h
+
+
+[Packages]
+  MdePkg/MdePkg.dec
+  AgesaPublic/AgesaPublic.dec
+
+
+[LibraryClasses]
+  PcdLib
+  PciLib
+  IoLib
+  BaseLib
+
+[Pcd.common]
+  gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr
diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.c
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.c
new file mode 100644
index 00..5a374665c3
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.c
@@ -0,0 +1,80 @@
+/** @file
+  ACPI Timer implements one instance of Timer Library.
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) Microsoft Corporation.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include "TscTimerLibInternal.h"
+
+UINT64  mTscFrequency;
+
+/** The constructor function determines the actual TSC frequency.
+
+  First, Get TSC frequency from system 

[edk2-devel] [PATCH V2 14/32] AMD/VanGoghBoard: Check in SmbiosLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Provides library functions for common SMBIOS operations. Only available to DXE
  and UEFI module types.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Include/Library/SmbiosLib.h   | 171 ++
 .../Library/SmbiosLib/SmbiosLib.c | 322 ++
 .../Library/SmbiosLib/SmbiosLib.inf   |  41 +++
 3 files changed, 534 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SmbiosLib.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SmbiosLib/SmbiosLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SmbiosLib/SmbiosLib.inf

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SmbiosLib.h 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SmbiosLib.h
new file mode 100644
index 00..314f0448fd
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SmbiosLib.h
@@ -0,0 +1,171 @@
+/** @file
+  Implements AMD SmbiosLib.h
+  Provides library functions for common SMBIOS operations. Only available to 
DXE
+  and UEFI module types.
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2012, Apple Inc. All rights reserved. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SMBIOS_LIB_H___
+#define SMBIOS_LIB_H___
+
+#include 
+#include 
+
+///
+/// Cache copy of the SMBIOS Protocol pointer
+///
+extern EFI_SMBIOS_PROTOCOL  *gSmbios;
+
+///
+/// Template for SMBIOS table initialization.
+/// The SMBIOS_TABLE_STRING types in the formated area must match the
+/// StringArray sequene.
+///
+typedef struct {
+  //
+  // formatted area of a given SMBIOS record
+  //
+  SMBIOS_STRUCTURE*Entry;
+  //
+  // NULL terminated array of ASCII strings to be added to the SMBIOS record.
+  //
+  CHAR8   **StringArray;
+} SMBIOS_TEMPLATE_ENTRY;
+
+/**
+  Create an initial SMBIOS Table from an array of SMBIOS_TEMPLATE_ENTRY
+  entries. SMBIOS_TEMPLATE_ENTRY.NULL indicates the end of the table.
+
+  @param[in]  Template   Array of SMBIOS_TEMPLATE_ENTRY entries.
+
+  @retval EFI_SUCCESS  New SMBIOS tables were created.
+  @retval EFI_OUT_OF_RESOURCES New SMBIOS tables were not created.
+**/
+EFI_STATUS
+EFIAPI
+SmbiosLibInitializeFromTemplate (
+  IN  SMBIOS_TEMPLATE_ENTRY  *Template
+  );
+
+/**
+  Create SMBIOS record.
+
+  Converts a fixed SMBIOS structure and an array of pointers to strings into
+  an SMBIOS record where the strings are cat'ed on the end of the fixed record
+  and terminated via a double NULL and add to SMBIOS table.
+
+  @param[in]  SmbiosEntry   Fixed SMBIOS structure
+  @param[in]  StringArray   Array of strings to convert to an SMBIOS string 
pack.
+NULL is OK.
+
+  @retval EFI_SUCCESS  New SmbiosEntry was added to SMBIOS table.
+  @retval EFI_OUT_OF_RESOURCES SmbiosEntry was not added.
+**/
+EFI_STATUS
+EFIAPI
+SmbiosLibCreateEntry (
+  IN  SMBIOS_STRUCTURE  *SmbiosEntry,
+  IN  CHAR8 **StringArray
+  );
+
+/**
+  Update the string associated with an existing SMBIOS record.
+
+  This function allows the update of specific SMBIOS strings. The number of 
valid strings for any
+  SMBIOS record is defined by how many strings were present when Add() was 
called.
+
+  @param[in]SmbiosHandleSMBIOS Handle of structure that will have its 
string updated.
+  @param[in]StringNumberThe non-zero string number of the string to 
update.
+  @param[in]String  Update the StringNumber string with String.
+
+  @retval EFI_SUCCESS   SmbiosHandle had its StringNumber String 
updated.
+  @retval EFI_INVALID_PARAMETER SmbiosHandle does not exist. Or String is 
invalid.
+  @retval EFI_UNSUPPORTED   String was not added because it is longer than 
the SMBIOS Table supports.
+  @retval EFI_NOT_FOUND The StringNumber.is not valid for this SMBIOS 
record.
+**/
+EFI_STATUS
+EFIAPI
+SmbiosLibUpdateString (
+  IN  EFI_SMBIOS_HANDLESmbiosHandle,
+  IN  SMBIOS_TABLE_STRING  StringNumber,
+  IN  CHAR8*String
+  );
+
+/**
+  Update the string associated with an existing SMBIOS record.
+
+  This function allows the update of specific SMBIOS strings. The number of 
valid strings for any
+  SMBIOS record is defined by how many strings were present when Add() was 
called.
+
+  @param[in]SmbiosHandleSMBIOS Handle of structure that will have its 
string updated.
+  @param[in]StringNumberThe non-zero string number of the string to 
update.
+  @param[in]String  Update the StringNumber string 

[edk2-devel] [PATCH V2 13/32] AMD/VanGoghBoard: Check in PlatformFlashAccessLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial AMD PlatformFlashAccessLib, It provides flash access protocol for 
other modules.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Include/Library/SpiFlashDeviceLib.h   |  59 ++
 .../VanGoghCommonPkg/Include/Protocol/Spi.h   | 346 
 .../Include/Protocol/SpiCommon.h  | 247 
 .../Include/Protocol/SpiFlashUpdate.h | 152 +
 .../PlatformFlashAccessLib.c  | 528 ++
 .../PlatformFlashAccessLib.inf|  64 +++
 6 files changed, 1396 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SpiFlashDeviceLib.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/Spi.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/SpiCommon.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/SpiFlashUpdate.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.inf

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SpiFlashDeviceLib.h
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SpiFlashDeviceLib.h
new file mode 100644
index 00..a6ec077f05
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SpiFlashDeviceLib.h
@@ -0,0 +1,59 @@
+/** @file
+  Implements SpiFlashDevice.h
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SPI_FLASH_DEVICE_LIB_H__
+#define SPI_FLASH_DEVICE_LIB_H__
+
+#include 
+
+//
+// Provides mSpiInitTable and the total number of flash part in mSpiInitTable 
for other modules.
+//
+extern SPI_INIT_TABLE  mSpiInitTable[];
+extern UINT8   mNumSpiFlashMax;
+
+//
+// Flash Device commands
+//
+// If a supported device uses a command different from the list below, a 
device specific command
+// will be defined just below it's JEDEC id section.
+//
+#define SPI_COMMAND_WRITE 0x02
+#define SPI_COMMAND_WRITE_AAI 0xAD
+#define SPI_COMMAND_READ  0x03
+#define SPI_COMMAND_ERASE 0x20
+#define SPI_COMMAND_WRITE_DISABLE 0x04
+#define SPI_COMMAND_READ_S0x05
+#define SPI_COMMAND_WRITE_ENABLE  0x06
+#define SPI_COMMAND_READ_ID   0xAB
+#define SPI_COMMAND_JEDEC_ID  0x9F
+#define SPI_COMMAND_WRITE_S_EN0x50
+#define SPI_COMMAND_WRITE_S   0x01
+#define SPI_COMMAND_CHIP_ERASE0xC7
+#define SPI_COMMAND_BLOCK_ERASE   0xD8
+#define SPI_COMMAND_READ_SFDP 0x5A
+#define SPI_COMMAND_RPMC_OP1  0x9B
+#define SPI_COMMAND_RPMC_OP2  0x96
+#define SPI_COMMAND_Enter_4Byte_Addr  0xB7
+#define SPI_COMMAND_Exit_4Byte_Addr   0xE9
+
+//
+// Winbond 256Mbit parts
+//
+#define SF_VENDOR_ID_WINBOND 0xEF
+#define SF_DEVICE_ID1_W25Q256JW  0x19  // Capacity 256Mbit
+#define SF_DEVICE_ID0_W25Q256JW  0x60
+
+//
+// index for prefix opcodes
+//
+#define SPI_WREN_INDEX  0 // Prefix Opcode 0: 
SPI_COMMAND_WRITE_ENABLE
+#define SPI_EWSR_INDEX  1 // Prefix Opcode 1: 
SPI_COMMAND_WRITE_S_EN
+#define BIOS_CTRL   0xDC
+
+#endif
diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/Spi.h 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/Spi.h
new file mode 100644
index 00..c7c3591479
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/Spi.h
@@ -0,0 +1,346 @@
+/** @file
+  Implements AMD Spi
+  This file defines the EFI SPI Protocol which implements the
+  Intel(R) ICH SPI Host Controller Compatibility Interface.
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SPI_H__
+#define SPI_H__
+
+#include 
+
+//
+// Define the SPI protocol GUID
+//
+// EDK and EDKII have different GUID formats
+//
+#if !defined (EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x0002)
+#define EFI_SPI_PROTOCOL_GUID \
+  { \
+0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 
\
+  }
+#define EFI_SMM_SPI_PROTOCOL_GUID \
+  { \
+0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 
\
+  }
+#else
+#define EFI_SPI_PROTOCOL_GUID \
+  { \
+0x1156efc6, 0xea32, 0x4396, \
+{ \
+  0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 

[edk2-devel] [PATCH V2 12/32] AMD/VanGoghBoard: Check in AMD BaseSerialPortLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial FCH UART port for Serial log output.
  Chachani board uses this UART for outputting debug log.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../BaseSerialPortLib16550AmdFchUart.c| 463 ++
 .../BaseSerialPortLib16550AmdFchUart.inf  |  40 ++
 2 files changed, 503 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.inf

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.c
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.c
new file mode 100644
index 00..665f47f703
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.c
@@ -0,0 +1,463 @@
+/** @file
+  16550 UART Serial Port library functions
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (C) 2014 Hewlett-Packard Development Company, L.P.
+  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+  Copyright (c) 2020, ARM Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+//
+// 16550 UART register offsets and bitfields
+//
+#define R_UART_RXBUF 0
+#define R_UART_TXBUF 0
+#define R_UART_BAUD_LOW  0
+#define R_UART_BAUD_HIGH 1
+#define R_UART_FCR   2
+#define   B_UART_FCR_FIFOE   BIT0
+#define   B_UART_FCR_FIFO64  BIT5
+#define R_UART_LCR   3
+#define   B_UART_LCR_DLABBIT7
+#define R_UART_MCR   4
+#define   B_UART_MCR_RTS BIT1
+#define R_UART_LSR   5
+#define   B_UART_LSR_RXRDY   BIT0
+#define   B_UART_LSR_TXRDY   BIT5
+#define   B_UART_LSR_TEMTBIT6
+#define R_UART_MSR   6
+#define   B_UART_MSR_CTS BIT4
+#define   B_UART_MSR_DSR BIT5
+
+/**
+  Read an 8-bit 16550 register.  The parameter Offset is added to the base 
address of the
+  16550 registers that is specified by PcdSerialRegisterBase.
+  @param  Offset  The offset of the 16550 register to read.
+  @return The value read from the 16550 register.
+**/
+UINT8
+SerialPortReadRegister (
+  UINTN  Offset
+  )
+{
+  return MmioRead8 ((UINTN)PcdGet64 (PcdSerialRegisterBase) + Offset * 4);
+}
+
+/**
+  Write an 8-bit 16550 register. The parameter Offset is added to the base 
address of the
+  16550 registers that is specified by PcdSerialRegisterBase.
+  @param  Offset  The offset of the 16550 register to write.
+  @param  Value   The value to write to the 16550 register specified by Offset.
+  @return The value written to the 16550 register.
+**/
+UINT8
+SerialPortWriteRegister (
+  UINTN  Offset,
+  UINT8  Value
+  )
+{
+  return MmioWrite8 ((UINTN)PcdGet64 (PcdSerialRegisterBase) + Offset * 4, 
Value);
+}
+
+/**
+  Return whether the hardware flow control signal allows writing.
+
+  @retval TRUE  The serial port is writable.
+  @retval FALSE The serial port is not writable.
+**/
+BOOLEAN
+SerialPortWritable (
+  VOID
+  )
+{
+  if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+if (PcdGetBool (PcdSerialDetectCable)) {
+  //
+  // Wait for both DSR and CTS to be set
+  //   DSR is set if a cable is connected.
+  //   CTS is set if it is ok to transmit data
+  //
+  //   DSR  CTS  Description   Action
+  //   ===  ===    
+  //00   No cable connected.   Wait
+  //01   No cable connected.   Wait
+  //10   Cable connected, but not clear to send.   Wait
+  //11   Cable connected, and clear to send.   Transmit
+  //
+  return (BOOLEAN)((SerialPortReadRegister (R_UART_MSR) & (B_UART_MSR_DSR 
| B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));
+} else {
+  //
+  // Wait for both DSR and CTS to be set OR for DSR to be clear.
+  //   DSR is set if a cable is connected.
+  //   CTS is set if it is ok to transmit data
+  //
+  //   DSR  CTS  Description   Action
+  //   ===  ===    
+  //00   No cable connected.   Transmit
+  //01   No cable connected.   Transmit
+  

[edk2-devel] [PATCH V2 11/32] AMD/VanGoghBoard: Check in FvbServices

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial FvbServices module. It describes platform flash IC information
  for FlashUpdate module to send command correctly.
  Different flash ICs may use the different Opcodes.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../VanGoghCommonPkg/FvbServices/FvbInfo.c|  120 ++
 .../FvbServices/FwBlockService.c  | 1285 +
 .../FvbServices/FwBlockService.h  |  515 +++
 .../FvbServices/PlatformSmmSpi.inf|   68 +
 4 files changed, 1988 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FvbInfo.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/PlatformSmmSpi.inf

diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FvbInfo.c 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FvbInfo.c
new file mode 100644
index 00..c0be635864
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FvbInfo.c
@@ -0,0 +1,120 @@
+/** @file
+Defines data structure that is the volume header found.These data is intent
+to decouple FVB driver with FV header.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#define FVB_MEDIA_BLOCK_SIZE  (0x0001)
+
+#define SYSTEM_NV_BLOCK_NUM  ((FixedPcdGet32(PcdFlashNvStorageVariableSize)+ 
FixedPcdGet32(PcdFlashNvStorageFtwWorkingSize) + 
FixedPcdGet32(PcdFlashNvStorageFtwSpareSize))/ FVB_MEDIA_BLOCK_SIZE)
+
+typedef struct {
+  EFI_PHYSICAL_ADDRESS  BaseAddress;
+  EFI_FIRMWARE_VOLUME_HEADERFvbInfo;
+  //
+  // EFI_FV_BLOCK_MAP_ENTRYExtraBlockMap[n];//n=0
+  //
+  EFI_FV_BLOCK_MAP_ENTRYEnd[1];
+} EFI_FVB2_MEDIA_INFO;
+
+EFI_FVB2_MEDIA_INFO  mPlatformFvbMediaInfo =
+  //
+  // Systen NvStorage FVB
+  //
+{
+  0,
+  {
+{
+  0,
+},// ZeroVector[16]
+EFI_SYSTEM_NV_DATA_FV_GUID,
+FVB_MEDIA_BLOCK_SIZE *SYSTEM_NV_BLOCK_NUM,
+EFI_FVH_SIGNATURE,
+EFI_FVB2_MEMORY_MAPPED |
+EFI_FVB2_READ_ENABLED_CAP |
+EFI_FVB2_READ_STATUS |
+EFI_FVB2_WRITE_ENABLED_CAP |
+EFI_FVB2_WRITE_STATUS |
+EFI_FVB2_ERASE_POLARITY |
+EFI_FVB2_ALIGNMENT_16,
+sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
+0xFBFF,// CheckSum
+0, // ExtHeaderOffset
+{
+  0,
+},// Reserved[1]
+2,// Revision
+{
+  {
+SYSTEM_NV_BLOCK_NUM,
+FVB_MEDIA_BLOCK_SIZE,
+  }
+}
+  },
+  {
+{
+  0,
+  0
+}
+  }
+};
+
+/**
+  Get Fvb information.
+
+  @param[in] BaseAddressThe base address compare with NvStorageVariable 
base address.
+  @param[out] FvbInfoFvb information.
+
+  @retval EFI_SUCCESS   Get Fvb information successfully.
+  @retval EFI_NOT_FOUND Not find Fvb information.
+
+**/
+EFI_STATUS
+EFIAPI
+GetFvbInfo (
+  IN  UINT64  BaseAddress,
+  OUT EFI_FIRMWARE_VOLUME_HEADER  **FvbInfo
+  )
+{
+  mPlatformFvbMediaInfo.BaseAddress = PcdGet32 (PcdFlashNvStorageVariableBase);
+
+  if (mPlatformFvbMediaInfo.BaseAddress == BaseAddress) {
+*FvbInfo = 
+return EFI_SUCCESS;
+  }
+
+  return EFI_NOT_FOUND;
+}
diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.c 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.c
new file mode 100644
index 00..f514ad772a
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.c
@@ -0,0 +1,1285 @@
+/** @file
+  Implements FvbServicesSmm
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2013-2016 Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifdef _MSC_VER
+  #pragma optimize( "", off )
+#endif
+
+#ifdef __GNUC__
+  #ifndef __clang__
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+  #else
+#pragma clang optimize off
+  #endif
+#endif
+
+#include "FwBlockService.h"
+
+#define EFI_FVB2_STATUS  

[edk2-devel] [PATCH V2 10/32] AMD/VanGoghBoard: Check in FlashUpdate

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Initial FlashUpdate module for Chachani platform flash IC.
  It provides mEfiSpiFlashUpdateProtocol for other module to access flash.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../FlashUpdate/FlashUpdateCommon.h   | 143 +
 .../FlashUpdate/FlashUpdateSmm.c  | 512 ++
 .../FlashUpdate/FlashUpdateSmm.h  | 123 +
 .../FlashUpdate/FlashUpdateSmm.inf|  59 ++
 .../FlashUpdate/FlashUpdateSmmRuntimeDxe.c| 407 ++
 .../FlashUpdate/FlashUpdateSmmRuntimeDxe.inf  |  48 ++
 .../VanGoghCommonPkg/FlashUpdate/PcRtc.h  | 375 +
 7 files changed, 1667 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateCommon.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmm.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmm.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmm.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmmRuntimeDxe.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmmRuntimeDxe.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/PcRtc.h

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateCommon.h 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateCommon.h
new file mode 100644
index 00..616035b82d
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateCommon.h
@@ -0,0 +1,143 @@
+/** @file
+  Implements AMD FlashUpdateCommon.h
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef FLASH_UPDATE_COMMON_H__
+#define FLASH_UPDATE_COMMON_H__
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+
+#define SPI_SMM_COMM_ID_GET_FLASH_SIZE_BLOCK_SIZE  0x0   // ID for get 
flash size and block size
+#define SPI_SMM_COMM_ID_READ_FLASH 0x1   // ID for Read 
Flash
+#define SPI_SMM_COMM_ID_WRITE_FALSH0x2   // ID for Write 
Flash
+#define SPI_SMM_COMM_ID_ERASE_FALSH0x3   // ID for Erase 
Flash
+
+//
+// SMM communication common buffer
+//
+typedef struct _FLASH_UPDATE_SMM_COMMUNICATION_CMN {
+  UINT32id; // Function ID of smm communication buffer
+} FLASH_UPDATE_SMM_COMMUNICATION_CMN;
+
+#pragma pack(1)
+
+//
+// SMM communication common buffer
+//
+typedef struct _SMM_COMM_RWE_FLASH {
+  UINT32id;  // ID of smm communication buffer
+  UINTN FlashAddress;// Flash devicd physical flash 
address
+  UINTN NumBytes;// Number in byte
+  EFI_STATUSReturnStatus;// Return status
+  UINT8 Buffer[1];   // Buffer start
+} SMM_COMM_RWE_FLASH;
+
+//
+// SMM communication common buffer
+//
+typedef struct _SMM_COMM_GET_FLASH_SIZE_BLOCK_SIZE {
+  UINT32id;   // ID of smm communication buffer
+  UINTN FlashSize;// Flash size
+  UINTN BlockSize;// Block size of flash device
+  EFI_STATUSReturnStatus; // Return status
+} SMM_COMM_GET_FLASH_SIZE_BLOCK_SIZE;
+
+#pragma pack()
+
+#define SMM_COMMUNICATE_HEADER_SIZE  (OFFSET_OF (EFI_SMM_COMMUNICATE_HEADER, 
Data))
+#define SMM_COMM_RWE_FLASH_SIZE  (OFFSET_OF (SMM_COMM_RWE_FLASH, Buffer))
+
+/**
+  Read data from flash device.
+
+  @param[in]  FlashAddressPhysical flash address.
+  @param[in]  NumBytesNumber in Byte.
+  @param[out] Buffer  Buffer contain the read data.
+
+  @retval EFI_SUCCESS Read successfully.
+  @retval EFI_INVALID_PARAMETER   Invalid parameter.
+  @retval others  Some error occurs when executing 
this routine.
+
+**/
+EFI_STATUS
+EFIAPI
+SfuProtocolFlashFdRead (
+  IN  UINTN  FlashAddress,
+  IN  UINTN  NumBytes,
+  OUT VOID   *Buffer
+  );
+
+/**
+  Erase flash region according to input in a block size.
+
+  @param[in] FlashAddress Physical flash address.
+  @param[in] NumBytes Number in Byte, a block size in 
flash device.
+
+  @retval EFI_SUCCESS Erase successfully.
+  @retval EFI_INVALID_PARAMETER   Invalid parameter.
+  @retval others 

[edk2-devel] [PATCH V2 09/32] AMD/VanGoghBoard: Check in Flash_AB

[Zhai, MingXin (Duke) via groups.io]

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[edk2-devel] [PATCH V2 08/32] AMD/VanGoghBoard: Check in UDKFlashUpdate

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  UDKFlashUpdate is a uefi tool for BIOS binary updating. It depends on EDK2's 
flash access protocol.
  UDKFlashUpdate needs to run under EDK2 BIOS.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../UDKFlashUpdate/SpiFlashDevice.c   |  37 +
 .../UDKFlashUpdate/SpiFlashDevice.h   |  62 ++
 .../UDKFlashUpdate/UDKFlashUpdate.c   | 671 ++
 .../UDKFlashUpdate/UDKFlashUpdate.h   |  48 ++
 .../UDKFlashUpdate/UDKFlashUpdate.inf |  51 ++
 5 files changed, 869 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/UDKFlashUpdate.c
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/UDKFlashUpdate.h
 create mode 100644 
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/UDKFlashUpdate.inf

diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.c
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.c
new file mode 100644
index 00..d4f5b12f41
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.c
@@ -0,0 +1,37 @@
+/** @file
+  Implements SpiFlashDevice.c
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SpiFlashDevice.h"
+
+SPI_INIT_TABLE  mSpiInitTable[] = {
+  { // W25Q256JW/W74M25JW
+SF_VENDOR_ID_WINBOND,
+SF_DEVICE_ID0_W25Q256JW,
+SF_DEVICE_ID1_W25Q256JW,
+{
+  SPI_COMMAND_WRITE_ENABLE,
+  SPI_COMMAND_WRITE_S_EN
+},
+{
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_JEDEC_ID,  
EnumSpiOperationJedecId},
+  { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_WRITE_S,   
EnumSpiOperationWriteStatus},
+  { EnumSpiOpcodeWrite,SPI_COMMAND_WRITE, 
EnumSpiOperationProgramData_1_Byte },
+  { EnumSpiOpcodeRead, SPI_COMMAND_READ,  
EnumSpiOperationReadData   },
+  { EnumSpiOpcodeWrite,SPI_COMMAND_ERASE, 
EnumSpiOperationErase_4K_Byte  },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_READ_S,
EnumSpiOperationReadStatus },
+  { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_CHIP_ERASE,
EnumSpiOperationFullChipErase  },
+  { EnumSpiOpcodeRead, SPI_COMMAND_READ_SFDP, 
EnumSpiOperationReadData   },
+  { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_RPMC_OP1,  
EnumSpiOperationOther  },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_RPMC_OP2,  
EnumSpiOperationReadData   },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_Enter_4Byte_Addr,  
EnumSpiOperationOther  },
+  { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_Exit_4Byte_Addr,   
EnumSpiOperationOther  }
+},
+0,
+0x200   // BIOS image size in flash
+  }
+};
diff --git 
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.h
 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.h
new file mode 100644
index 00..fe4d99e82c
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.h
@@ -0,0 +1,62 @@
+/** @file
+  Implements SpiFlashDevice.h
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SPI_FLASH_DEVICE_H__
+#define SPI_FLASH_DEVICE_H__
+
+#include 
+#include 
+#include 
+
+//
+// Supported SPI Flash Devices
+//
+typedef enum {
+  EnumSpiFlashW25Q256JW,
+  EnumSpiFlashMax
+} SPI_FLASH_TYPES_SUPPORTED;
+
+// Flash Device commands
+//
+// If a supported device uses a command different from the list below, a 
device specific command
+// will be defined just below it's JEDEC id section.
+//
+#define SPI_COMMAND_WRITE 0x02
+#define SPI_COMMAND_WRITE_AAI 0xAD
+#define SPI_COMMAND_READ  0x03
+#define SPI_COMMAND_ERASE 0x20
+#define SPI_COMMAND_WRITE_DISABLE 0x04
+#define SPI_COMMAND_READ_S0x05
+#define SPI_COMMAND_WRITE_ENABLE  0x06
+#define SPI_COMMAND_READ_ID   0xAB
+#define SPI_COMMAND_JEDEC_ID  0x9F
+#define SPI_COMMAND_WRITE_S_EN0x50
+#define SPI_COMMAND_WRITE_S   0x01
+#define SPI_COMMAND_CHIP_ERASE

[edk2-devel] [PATCH V2 06/32] AMD/VanGoghBoard: Check in AmdIdsExtLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  A small part of Chachani platform code and FSPWrapperPkg needs IdsHookExtLib.
  Initial AmdIdsHookExtLibNull for ChachaniBoardPkg module.

Signed-off-by: Ken Yao 
Cc: Duke Zhai 
Cc: Eric Xing 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../AmdIdsExtLibNull/AmdIdsHookExtLibNull.c   | 33 
 .../AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf | 39 +++
 2 files changed, 72 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf

diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.c
 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.c
new file mode 100644
index 00..f59b5beea1
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.c
@@ -0,0 +1,33 @@
+/** @file
+  Implements AmdIdsHookExtLibNull.c
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+
+typedef enum {
+  IDS_HOOK_UNSUPPORTED = 1
+} IDS_HOOK_STATUS;
+
+IDS_HOOK_STATUS
+IdsHookExtEntry (
+  UINT32  HookId,
+  VOID*Handle,
+  VOID*Data
+  )
+{
+  return IDS_HOOK_UNSUPPORTED;
+}
+
+IDS_HOOK_STATUS
+GetIdsNvTable (
+  IN OUT   VOID*IdsNvTable,
+  IN OUT   UINT32  *IdsNvTableSize
+  )
+{
+  return IDS_HOOK_UNSUPPORTED;
+}
diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf
 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf
new file mode 100644
index 00..354c19dd19
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf
@@ -0,0 +1,39 @@
+## @file
+#  Amd Ids Hook Ext Lib Module INF file
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010006
+  BASE_NAME  = AmdIdsHookExtLibNull.inf
+  FILE_GUID  = CB364A1C-793D-46CE-B80A-0AB5FCB16D76
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = AmdIdsHookExtLib
+
+[Sources.common]
+  AmdIdsHookExtLibNull.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+
+[Guids]
+
+[Protocols]
+
+[Ppis]
+
+[FeaturePcd]
+
+[Pcd]
+
+[Depex]
+  TRUE
+
+[BuildOptions]
+
--
2.31.1



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[edk2-devel] [PATCH V2 07/32] AMD/VanGoghBoard: Check in PciPlatform

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  BIOS detects current IGPU device ID and install corresponding VBIOS.
  Inital PciPlatform module to load VBIOS and to provide interface for
  other option ROMs if necessary.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Include/Protocol/GlobalNvsArea.h  |  63 ++
 .../PciPlatform/CommonHeader.h|  27 +++
 .../PciPlatform/PciPlatform.c | 183 ++
 .../PciPlatform/PciPlatform.h |  89 +
 .../PciPlatform/PciPlatform.inf   |  51 +
 5 files changed, 413 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvsArea.h
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.h
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.inf

diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvsArea.h 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvsArea.h
new file mode 100644
index 00..e844932cc0
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvsArea.h
@@ -0,0 +1,63 @@
+/** @file
+Definition of the global NVS area protocol.  This protocol
+publishes the address and format of a global ACPI NVS buffer
+used as a communications buffer between SMM code and ASL code.
+The format is derived from the ACPI reference code, version 0.95.
+Note:  Data structures defined in this protocol are not naturally aligned.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef GLOBAL_NVS_AREA_H__
+#define GLOBAL_NVS_AREA_H__
+
+//
+// Includes
+//
+#define GLOBAL_NVS_DEVICE_ENABLE   1
+#define GLOBAL_NVS_DEVICE_DISABLE  0
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+{ 0x74e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc} }
+
+//
+// Revision id - Added TPM related fields
+//
+#define GLOBAL_NVS_AREA_RIVISION_1  1
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID  gEfiGlobalNvsAreaProtocolGuid;
+
+//
+// Global NVS Area definition
+//
+#pragma pack (1)
+typedef struct {
+  //
+  // Miscellaneous Dynamic Values, the definitions below need to be matched
+  // GNVS definitions in Platform.ASL
+  //
+  UINT32TopOfMem;   // TOPM
+  UINT8 NbIoApic;   // NAPC
+  UINT32PcieBaseAddress;// PCBA
+  UINT32PcieBaseLimit;  // PCBL
+} EFI_GLOBAL_NVS_AREA;
+#pragma pack ()
+
+//
+// Global NVS Area Protocol
+//
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+  EFI_GLOBAL_NVS_AREA*Area;
+} EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif
diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h
new file mode 100644
index 00..f4e6461206
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h
@@ -0,0 +1,27 @@
+/** @file
+  Implements CommonHeader.h
+  This file includes package header files, library classes and protocol, PPI & 
GUID definitions.
+
+  Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef COMMON_HEADER_H___
+#define COMMON_HEADER_H___
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#endif
diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c
new file mode 100644
index 00..aa0a133b1f
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c
@@ -0,0 +1,183 @@
+/** @file
+  Implements PciPlatform.c
+  Registers onboard PCI ROMs with PCI.IO
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CommonHeader.h"
+
+#include "PciPlatform.h"
+
+PCI_OPTION_ROM_TABLE  mPciOptionRomTable[] = {
+  { ONBOARD_SPH_VIDEO_OPTION_ROM_FILE_GUID, 0x1002, 0x1435 },
+  { NULL_ROM_FILE_GUID, 0x, 0x 

[edk2-devel] [PATCH V2 03/32] AMD/VanGoghBoard: Check in Capsule update

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Chachani board supports "Capsule on Disk (CoD)" feature defined in UEFI
  Spec chapter 8.5.5 "Delivery of Capsules via file on Mass Storage Device".
  The BIOS capsule image is saved in hard disk as default setting.

Signed-off-by: Ken Yao 
Cc: Duke Zhai 
Cc: Eric Xing 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../SystemFirmwareDescriptor.aslc |   85 ++
 .../SystemFirmwareDescriptor.inf  |   39 +
 .../SystemFirmwareDescriptorPei.c |   64 +
 .../Include/Library/CapsuleHookLib.h  |   40 +
 .../Capsule/CapsuleHookLib/CapsuleHookLib.c   | 1153 +
 .../Capsule/CapsuleHookLib/CapsuleHookLib.inf |   56 +
 .../PlatformBootManager.c |  794 
 .../PlatformBootManager.h |  150 +++
 .../PlatformBootManagerLib.inf|   89 ++
 .../PlatformBootManagerLib/PlatformConsole.c  |  495 +++
 .../PlatformBootManagerLib/PlatformConsole.h  |   69 +
 .../PlatformBootManagerLib/PlatformData.c |   39 +
 .../CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf   |  122 ++
 .../CapsuleRuntimeDxe/CapsuleService.c|  461 +++
 .../CapsuleRuntimeDxe/CapsuleService.h|   73 ++
 15 files changed, 3729 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Library/CapsuleHookLib.h
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/CapsuleHookLib/CapsuleHookLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/CapsuleHookLib/CapsuleHookLib.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformBootManager.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformBootManager.h
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformBootManagerLib.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformConsole.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformConsole.h
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformData.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleService.c
 create mode 100644 
Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleService.h

diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
new file mode 100644
index 00..2e05a523c7
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
@@ -0,0 +1,85 @@
+/** @file
+  System firmware Descriptor file
+  System Firmware descriptor.
+
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+
+#define PACKAGE_VERSION 0x
+#define PACKAGE_VERSION_STRING  L"Unknown"
+
+#define CURRENT_FIRMWARE_VERSION0x3818
+#define CURRENT_FIRMWARE_VERSION_STRING L"3818"
+#define LOWEST_SUPPORTED_FIRMWARE_VERSION   0x0001
+
+#define IMAGE_IDSIGNATURE_64('C', 'H', 'A', 'C', 
'H', 'A','N','I')
+#define IMAGE_ID_STRING L"ChachaniFD"
+
+// PcdSystemFmpCapsuleImageTypeIdGuid
+#define IMAGE_TYPE_ID_GUID  { 0x38663fe6, 0x934f, 0x42a1, { 
0xbc, 0xb0, 0xf7, 0x9e, 0x62, 0xec, 0xbe, 0x80 } }
+
+typedef struct {
+  EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR  Descriptor;
+  // real string data
+  CHAR16  
ImageIdNameStr[sizeof(IMAGE_ID_STRING)/sizeof(CHAR16)];
+  CHAR16  
VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING)/sizeof(CHAR16)];
+  

[edk2-devel] [PATCH V2 05/32]AMD/VanGoghBoard: Check in PlatformSecLib

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Chachani board jump to PlatformSec function after x86 releasing.
  This module provides the SEC entry function, which does platform-related
  early initialization.

Signed-off-by: Ken Yao 
Cc: Duke Zhai 
Cc: Eric Xing 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../Library/PlatformSecLib/Ia32/Flat32.nasm   | 534 ++
 .../Library/PlatformSecLib/Ia32/Platform.inc  |  53 ++
 .../Library/PlatformSecLib/PlatformSecLib.c   | 196 +++
 .../Library/PlatformSecLib/PlatformSecLib.inf |  61 ++
 .../PlatformSecLib/PlatformSecLibModStrs.uni  |  19 +
 5 files changed, 863 insertions(+)
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Platform.inc
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.c
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf
 create mode 100644 
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni

diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm
 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm
new file mode 100644
index 00..5638c411e3
--- /dev/null
+++ 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm
@@ -0,0 +1,534 @@
+;/** @file
+; AMD VanGoghBoard PlatformSecLib
+;  This is the code that goes from real-mode to protected mode.
+;  It consumes the reset vector, configures the stack.
+;
+; Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;**/
+
+;
+; Include processor definitions
+;
+%use masm
+
+
+%include "Platform.inc"
+
+;
+; CR0 cache control bit definition
+;
+CR0_CACHE_DISABLE   EQU 04000h
+CR0_NO_WRITEEQU 02000h
+BSP_STACK_BASE_ADDR EQU FixedPcdGet32 
(PcdPeiCorePeiPreMemoryStackBaseAddress) ; Base address for core 0 stack
+PRE_MEM_STACK_SIZE  EQU FixedPcdGet32 (PcdPeiCorePeiPreMemoryStackSize)
+PCIEX_LENGTH_BIT_SETTING EQU 011000b
+
+MSR_IA32_EFER   EQU  0c080h   ; Extended Feature Enable 
Register
+MSR_IA32_EFER_LME   EQU  8; Long Mode Enable
+
+MSR_SMM_BASEEQU  0c0010111h   ; SMBASE Register
+
+SMM_BASE_DEFAULTEQU  3h   ; reset value of MSR MSR_SMM_BASE
+
+SMMMASK_ADDRESS EQU  0c0010113h   ; SMM TSeg Base Address
+SMMMASK_ADDRESS_AE  EQU  0; Aseg Address Range Enable
+SMMMASK_ADDRESS_TE  EQU  1; Tseg Address Range Enable
+
+;
+; In Modified Conventional Resume S3 Design:
+;   With Modified Conventional Resume path, the x86 resumes from sleep,
+; begins executing code from a predefined SMM resume vector and then
+; jump to ROM code to continue conventional resume.
+; EDX is filled with special signature "0x55AABB66" when jump to Sec,
+; this signature can be used to identify if resume back from SMM resume.
+;
+SMM_RESUME_SIGNATUREEQU  055AABB66h
+
+PCAT_RTC_ADDRESS_REGISTER  EQU  0x70
+PCAT_RTC_DATA_REGISTER EQU  0x71
+
+NMI_DISABLE_BIT EQU  0x80
+
+RTC_ADDRESS_REGISTER_A  EQU  0x0A  ; R/W[0..6]  R0[7]
+RTC_ADDRESS_REGISTER_B  EQU  0x0B  ; R/W
+RTC_ADDRESS_REGISTER_C  EQU  0x0C  ; RO
+RTC_ADDRESS_REGISTER_D  EQU  0x0D  ; R/W
+
+;
+; External and public declarations
+;  TopOfStack is used by C code
+;  SecStartup is the entry point to the C code
+; Neither of these names can be modified without
+; updating the C code.
+;
+extern   ASM_PFX(SecStartup)
+
+SECTION .text
+;
+; Protected mode portion initializes stack, configures cache, and calls C 
entry point
+;
+
+;
+;
+; Procedure:ProtectedModeEntryPoint
+;
+; Input:Executing in 32 Bit Protected (flat) mode
+;cs: 0-4GB
+;ds: 0-4GB
+;es: 0-4GB
+;fs: 0-4GB
+;gs: 0-4GB
+;ss: 0-4GB
+;
+; Output:   This function never returns
+;
+; Destroys:
+;   ecx
+;   edi
+;esi
+;esp
+;
+; Description:
+;Perform any essential early platform initilaisation
+;   Setup a stack
+;   Call the main EDKII Sec C code
+;
+;
+
+global ASM_PFX(_ModuleEntryPoint)

[edk2-devel] [PATCH V2 02/32] AMD/VanGoghBoard: Check in ACPI tables

[Zhai, MingXin (Duke) via groups.io]

-=-=-=-=-=-=-=-=-=-=-=-
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[edk2-devel] [PATCH V2 04/32] AMD/VanGoghBoard: Check in AgesaPublic pkg

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  Chachani board platform code depends on some AGESA-related PCDs/GUIDs.
  Add AgesaPublicPkg for AGESA-related PCDs/GUIDs to support platfrom build.

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../VanGoghBoard/AgesaPublic/AgesaPublic.dec  |  61 +
 .../VanGoghBoard/AgesaPublic/Include/AGESA.h  |  35 +++
 .../VanGoghBoard/AgesaPublic/Include/AMD.h| 189 +
 .../AgesaPublic/Include/AmdPspDirectory.h |  55 
 .../AgesaPublic/Include/FchRegistersCommon.h  |  23 ++
 .../Include/Guid/AmdMemoryInfoHob.h   |  51 
 .../Include/Library/AmdPspBaseLibV2.h | 248 ++
 .../Include/Library/AmdPspCommonLib.h |  29 ++
 .../Include/Library/AmdPspFtpmLib.h   |  94 +++
 .../AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h   |  80 ++
 .../Include/Protocol/AmdPspFtpmProtocol.h | 112 
 11 files changed, 977 insertions(+)
 create mode 100644 Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
 create mode 100644 Platform/AMD/VanGoghBoard/AgesaPublic/Include/AGESA.h
 create mode 100644 Platform/AMD/VanGoghBoard/AgesaPublic/Include/AMD.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/AmdPspDirectory.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/FchRegistersCommon.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Guid/AmdMemoryInfoHob.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspBaseLibV2.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspCommonLib.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspFtpmLib.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h
 create mode 100644 
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Protocol/AmdPspFtpmProtocol.h

diff --git a/Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec 
b/Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
new file mode 100644
index 00..e987b9b603
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
@@ -0,0 +1,61 @@
+## @file
+# EDK II AgesaPublic.dec file
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+  DEC_SPECIFICATION  = 0x00010005
+  PACKAGE_NAME   = AgesaPublic
+  PACKAGE_GUID   = EA54B0FA-908C-43DE-95A5-5E821A893CA4
+  PACKAGE_VERSION= 0.1
+
+[Includes]
+  Include
+
+[Guids]
+  gEfiAmdAgesaModulePkgTokenSpaceGuid  = { 0x7788adf0, 0x9788, 0x4a3f, { 
0x83, 0xfa, 0xcb, 0x51, 0x2e, 0x7c, 0xf8, 0xdd } }
+  gEfiAmdAgesaPkgTokenSpaceGuid= { 0xd4d8435f, 0xfffb, 0x4acb, { 
0xa0, 0x4d, 0xff, 0x0f, 0xad, 0x67, 0x7f, 0xe9 } }
+  gAmdCpmPkgTokenSpaceGuid = { 0x916e0ddd, 0x2bd2, 0x4704, { 
0x93, 0xb9, 0x59, 0x4b, 0x01, 0xa5, 0xfa, 0x9f } }
+  gAmdResourceSizeForEachRbGuid= { 0x542b8f2f, 0xbd52, 0x4233, { 
0x8c, 0x3d, 0x66, 0x53, 0x0d, 0xe8, 0xa3, 0x69 } }
+  gAmdPbsSystemConfigurationGuid   = { 0xa339d746, 0xf678, 0x49b3, { 
0x9f, 0xc7, 0x54, 0xce, 0x0f, 0x9d, 0xf2, 0x26 } }
+  gAmdTotalNumberOfRootBridgesGuid = { 0xfb5703f5, 0xf8a7, 0xf401, { 
0x18, 0xb4, 0x3f, 0x10, 0x8d, 0xeb, 0x26, 0x12 } }
+  gApSyncFlagNvVariableGuid= { 0xad3f6761, 0xf0a3, 0x46c8, { 
0xa4, 0xcb, 0x19, 0xb7, 0x0f, 0xfd, 0xb3, 0x05 } }
+  gAmdMemoryInfoHobGuid= { 0x1bce3d14, 0xa5fe, 0x4a0b, { 
0x9a, 0x8d, 0x69, 0xca, 0x5d, 0x98, 0x38, 0xd3 } }
+  gAmdPspApobHobGuid   = { 0x30b174f3, 0x7712, 0x4cca, { 
0xbd, 0x13, 0xd0, 0xb8, 0xa8, 0x80, 0x19, 0x97 } }
+
+[Protocols]
+  gPspFlashAccSmmCommReadyProtocolGuid = { 0x9f373486, 0xda76, 0x4c9f, { 
0x81, 0x55, 0x6c, 0xcd, 0xdb, 0x0b, 0x0b, 0x04 } }
+  gAmdPspFtpmProtocolGuid  = { 0xac234e04, 0xb036, 0x476c, { 
0x91, 0x66, 0xbe, 0x47, 0x52, 0xa0, 0x95, 0x09 } }
+  gFchInitDonePolicyProtocolGuid   = { 0xc63c0c73, 0xf612, 0x4c02, { 
0x84, 0xa3, 0xc6, 0x40, 0xad, 0x0b, 0xa6, 0x22 } }
+  gAmdCapsuleSmmHookProtocolGuid   = { 0x4fc43bbe, 0x1433, 0x4951, { 
0xac, 0x2d, 0x0d, 0x01, 0xfe, 0xc0, 0x0e, 0xb1 } }
+  gAmdCpmAllPciIoProtocolsInstalledProtocolGuid = { 0x676D7012, 0x139B, 
0x485A, { 0x96, 0xF1, 0x98, 0x6F, 0xC4, 0x8A, 0x86, 0x4B } }
+  gAmdFspSetupTableInitDoneGuid= { 0xef5394c6, 0x566d, 0x440f, { 
0x9d, 0x05, 0xc0, 0xa3, 0x2c, 0xb9, 0x33, 0x58 } }
+
+[Ppis]
+  gAmdMemoryInfoHobPpiGuid = { 0xba16e587, 0x1d66, 0x41b7, { 
0x9b, 0x52, 0xca, 0x4f, 0x2c, 0xad, 0x0d, 0xc8 } }
+  

[edk2-devel] [PATCH V2 01/32] AMD/AmdPlatformPkg: Check in AMD S3 logo

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

BZ #:4640
In V2: Improve coding style
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  LogoDxe module displays boot logo.
  S3LogoDxe module is based on EDK2 LogoDxe module and update AMD S3 logo.

Signed-off-by: Eric Xing 
Cc: Duke Zhai 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 .../AmdPlatformPkg/Universal/LogoDxe/Logo.c   | 198 ++
 .../Universal/LogoDxe/S3Logo.bmp  | Bin 0 -> 964114 bytes
 .../Universal/LogoDxe/S3Logo.idf  |   9 +
 .../Universal/LogoDxe/S3LogoDxe.inf   |  55 +
 4 files changed, 262 insertions(+)
 create mode 100644 Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c
 create mode 100644 Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3Logo.bmp
 create mode 100644 Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3Logo.idf
 create mode 100644 Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3LogoDxe.inf

diff --git a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c 
b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c
new file mode 100644
index 00..4463ba58eb
--- /dev/null
+++ b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c
@@ -0,0 +1,198 @@
+/**
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+**/
+
+/** @file
+  Logo DXE Driver, install Edk2 Platform Logo protocol.
+
+  Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "Logo.h"
+
+EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+EFI_HII_HANDLE mHiiHandle;
+LOGO_ENTRY mLogos[] = {
+  {
+IMAGE_TOKEN (IMG_LOGO),
+EdkiiPlatformLogoDisplayAttributeCenter,
+0,
+0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param[in]  This  The pointer to this protocol instance.
+  @param[in, out] Instance  The visible image instance is found.
+  @param[out] Image Points to the image.
+  @param[out] Attribute The display attributes of the image 
returned.
+  @param[out] OffsetX   The X offset of the image regarding the 
Attribute.
+  @param[out] OffsetY   The Y offset of the image regarding the 
Attribute.
+
+  @retval EFI_SUCCESSThe image was fetched successfully.
+  @retval EFI_NOT_FOUND  The specified image could not be found.
+  @retval EFI_INVALID_PARAMETER  One of the given input parameters are 
incorrect
+**/
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN EDKII_PLATFORM_LOGO_PROTOCOL*This,
+  IN OUT UINT32  *Instance,
+  OUT EFI_IMAGE_INPUT*Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN   *OffsetX,
+  OUT INTN   *OffsetY
+  )
+{
+  UINT32  Current;
+
+  if ((Instance == NULL) || (Image == NULL) ||
+  (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
+return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++; // Advance to next logo.
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, 
mLogos[Current].ImageId, Image);
+}
+
+EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
+  GetImage
+};
+
+// AMD_EDKII_OVERRIDE START
+
+/**
+  After console ready before boot option event callback
+
+  @param[in] Event  The Event this notify function registered to.
+  @param[in] ContextPointer to the context data registered to the Event.
+**/
+VOID
+EFIAPI
+LogoDxeDisplayEventCallback (
+  IN EFI_EVENT  Event,
+  IN VOID   *Context
+  )
+{
+  DEBUG ((DEBUG_INFO, "AMD logo is displaying.\n"));
+
+  BootLogoEnableLogo ();
+  gBS->CloseEvent (Event);
+}
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle   The firmware allocated handle for the EFI image.
+  @param  SystemTable   A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS   The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL*HiiDatabase;
+  EFI_HANDLE   Handle;
+  EFI_EVENTAfterConsoleReadyBeforeBootOptionEvent;
+
+  Status = 

[edk2-devel] [PATCH V2 00/32] Introduce AMD Vangogh platform reference code

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

In V2: Improve coding style.
  1.Remove the leading underscore and use double underscore at trailing in C 
header files.
  2.Remove old tianocore licenses and redundant license description.
  3.Improve coding style. For example: remove space between @param.

In V1:
  This AMD reference platform BIOS supports AMD Vangogh B0 SOC and Chachani 
board.

Duke Zhai (32):
  AMD/AmdPlatformPkg: Check in AMD S3 logo
  AMD/VanGoghBoard: Check in ACPI tables
  AMD/VanGoghBoard: Check in Capsule update
  AMD/VanGoghBoard: Check in AgesaPublic pkg
  AMD/VanGoghBoard: Check in PlatformSecLib
  AMD/VanGoghBoard: Check in AmdIdsExtLib
  AMD/VanGoghBoard: Check in PciPlatform
  AMD/VanGoghBoard: Check in UDKFlashUpdate
  AMD/VanGoghBoard: Check in Flash_AB
  AMD/VanGoghBoard: Check in FlashUpdate
  AMD/VanGoghBoard: Check in FvbServices
  AMD/VanGoghBoard: Check in AMD BaseSerialPortLib
  AMD/VanGoghBoard: Check in PlatformFlashAccessLib
  AMD/VanGoghBoard: Check in SmbiosLib
  AMD/VanGoghBoard: Check in SpiFlashDeviceLib
  AMD/VanGoghBoard: Check in BaseTscTimerLib
  AMD/VanGoghBoard: Check in Smm access module
  AMD/VanGoghBoard: Check in PciHostBridge module
  AMD/VanGoghBoard: Check in PcatRealTimeClockRuntimeDxe  module
  AMD/VanGoghBoard: Check in FTPM module
  AMD/VanGoghBoard: Check in SignedCapsule
  AMD/VanGoghBoard: Check in Vtf0
  AMD/VanGoghBoard: Check in AcpiPlatform
  AMD/VanGoghBoard: Check in FchSpi module
  AMD/VanGoghBoard: Check in PlatformInitPei module
  AMD/VanGoghBoard: Check in Smbios platform dxe drivers
  AMD/VanGoghBoard: Check in Fsp2WrapperPkg
  AMD/VanGoghBoard: Check in SmmCpuFeaturesLibCommon  module
  AMD/VanGoghBoard: Check in SmramSaveState module
  AMD/VanGoghBoard: Check in EDK2 override files
  AMD/VanGoghBoard: Check in AMD SmmControlPei module
  AMD/VanGoghBoard: Check in Chachani board project files  and build
script

 .../AmdPlatformPkg/Universal/LogoDxe/Logo.c   |  198 +
 .../Universal/LogoDxe/S3Logo.bmp  |  Bin 0 -> 964114 bytes
 .../Universal/LogoDxe/S3Logo.idf  |9 +
 .../Universal/LogoDxe/S3LogoDxe.inf   |   55 +
 .../VanGoghBoard/AgesaPublic/AgesaPublic.dec  |   61 +
 .../VanGoghBoard/AgesaPublic/Include/AGESA.h  |   35 +
 .../VanGoghBoard/AgesaPublic/Include/AMD.h|  189 +
 .../AgesaPublic/Include/AmdPspDirectory.h |   55 +
 .../AgesaPublic/Include/FchRegistersCommon.h  |   23 +
 .../Include/Guid/AmdMemoryInfoHob.h   |   51 +
 .../Include/Library/AmdPspBaseLibV2.h |  248 +
 .../Include/Library/AmdPspCommonLib.h |   29 +
 .../Include/Library/AmdPspFtpmLib.h   |   94 +
 .../AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h   |   80 +
 .../Include/Protocol/AmdPspFtpmProtocol.h |  112 +
 .../Acpi/AcpiTables/AcpiTables.inf|   33 +
 .../Acpi/AcpiTables/Dsdt/CPU.asl  |   22 +
 .../Acpi/AcpiTables/Dsdt/Dsdt.asl |   36 +
 .../Acpi/AcpiTables/Dsdt/FchShang.asi |  927 ++
 .../Acpi/AcpiTables/Dsdt/GloblNvs.asl |   17 +
 .../Acpi/AcpiTables/Dsdt/HOST_BUS.ASL |  209 +
 .../Acpi/AcpiTables/Dsdt/LINK.ASL |  481 ++
 .../Acpi/AcpiTables/Dsdt/Lpc0.asl |  168 +
 .../Acpi/AcpiTables/Dsdt/PciTree.asl  |  776 ++
 .../Acpi/AcpiTables/Dsdt/Platform.asl |  135 +
 .../Acpi/AcpiTables/Dsdt/_PR.asl  |   36 +
 .../Acpi/AcpiTables/Facs/Facs.h   |   31 +
 .../Acpi/AcpiTables/Facs/Facs50.aslc  |   68 +
 .../Acpi/AcpiTables/Fadt/Fadt.h   |   64 +
 .../Acpi/AcpiTables/Fadt/Fadt50.aslc  |  159 +
 .../Acpi/AcpiTables/Hpet/Hpet.h   |   70 +
 .../Acpi/AcpiTables/Hpet/Hpet50.aslc  |   58 +
 .../Acpi/AcpiTables/Madt/Madt.h   |  114 +
 .../Acpi/AcpiTables/Madt/Madt50.aslc  |  327 +
 .../Acpi/AcpiTables/Mcfg/Mcfg.h   |   61 +
 .../Acpi/AcpiTables/Mcfg/Mcfg50.aslc  |   61 +
 .../BIOSImageDirectory32M.xml |   63 +
 .../VanGoghBoard/ChachaniBoardPkg/Board.env   |   23 +
 .../ChachaniBoardPkg/BuildPspImage.bat|  126 +
 .../SystemFirmwareDescriptor.aslc |   85 +
 .../SystemFirmwareDescriptor.inf  |   39 +
 .../SystemFirmwareDescriptorPei.c |   64 +
 .../ChachaniBoardPkg/Conf/ReadMe.txt  |   14 +
 .../ChachaniBoardPkg/Conf/build_rule.txt  |  654 ++
 .../ChachaniBoardPkg/Conf/target.txt  |   73 +
 .../ChachaniBoardPkg/Conf/tools_def.txt   | 7571 +
 .../ChachaniBoardPkg/FlashABImage32M.py   |  102 +
 .../ChachaniBoardPkg/GenCapsule.bat   |   81 +
 .../ChachaniBoardPkg/GenFlashABImage.bat  |   39 +
 .../ChachaniBoardPkg/GoZ_ChachaniExt.bat  |   81 +
 .../Include/Library/CapsuleHookLib.h  |   40 +
 .../Include/Protocol/GlobalNvsArea.h  |   63 +
 .../AmdIdsExtLibNull/AmdIdsHookExtLibNull.c   |   33 +
 .../AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf |   39 +
 

[edk2-devel] [PATCH] AMD/VanGogh: Update VanGogh firmware binaries to UCC4126.3B30 Update firmware binaries for VanGogh B0 processors to UCC4126.3B30

[Zhai, MingXin (Duke) via groups.io]

From: Duke Zhai 

Signed-off-by: Duke Zhai 
Cc: Eric Xing 
Cc: Ken Yao 
Cc: Igniculus Fu 
Cc: Abner Chang 
---
 Silicon/AMD/VanGogh/Firmwares/TypeId0x08.sbin | Bin 262656 -> 262656 bytes
 Silicon/AMD/VanGogh/Firmwares/TypeId0x12.sbin | Bin 262656 -> 262656 bytes
 .../AMD/VanGogh/Firmwares/TypeId0x30.csbin| Bin 440144 -> 441216 bytes
 Silicon/AMD/VanGogh/Firmwares/TypeId0x66.bin  | Bin 3200 -> 3200 bytes
 .../AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3.bin | Bin 10796 -> 10796 bytes
 .../Apcb/ApcbSet1Ff3DefaultRecovery.bin   | Bin 10796 -> 10796 bytes
 .../FspBlobs/Apcb/ApcbSet1Ff3Updatable.bin| Bin 488 -> 488 bytes
 .../AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3.bin | Bin 10796 -> 10796 bytes
 .../Apcb/ApcbSet2Ff3DefaultRecovery.bin   | Bin 10796 -> 10796 bytes
 .../FspBlobs/Apcb/ApcbSet2Ff3Updatable.bin| Bin 504 -> 504 bytes
 .../Fsp/VangoghSet1ExternalReleaseM.fd| Bin 786432 -> 786432 bytes
 .../Fsp/VangoghSet1ExternalReleaseS.fd| Bin 524288 -> 524288 bytes
 .../Fsp/VangoghSet2ExternalReleaseM.fd| Bin 786432 -> 786432 bytes
 .../Fsp/VangoghSet2ExternalReleaseS.fd| Bin 524288 -> 524288 bytes
 Silicon/AMD/VanGogh/ReleaseNote.txt   |  13 +
 15 files changed, 13 insertions(+)

diff --git a/Silicon/AMD/VanGogh/Firmwares/TypeId0x08.sbin 
b/Silicon/AMD/VanGogh/Firmwares/TypeId0x08.sbin
index c35c0ca..0dc2605 100644
Binary files a/Silicon/AMD/VanGogh/Firmwares/TypeId0x08.sbin and 
b/Silicon/AMD/VanGogh/Firmwares/TypeId0x08.sbin differ
diff --git a/Silicon/AMD/VanGogh/Firmwares/TypeId0x12.sbin 
b/Silicon/AMD/VanGogh/Firmwares/TypeId0x12.sbin
index 3332cac..a38714a 100644
Binary files a/Silicon/AMD/VanGogh/Firmwares/TypeId0x12.sbin and 
b/Silicon/AMD/VanGogh/Firmwares/TypeId0x12.sbin differ
diff --git a/Silicon/AMD/VanGogh/Firmwares/TypeId0x30.csbin 
b/Silicon/AMD/VanGogh/Firmwares/TypeId0x30.csbin
index 8c6fcfd..2c15c9c 100644
Binary files a/Silicon/AMD/VanGogh/Firmwares/TypeId0x30.csbin and 
b/Silicon/AMD/VanGogh/Firmwares/TypeId0x30.csbin differ
diff --git a/Silicon/AMD/VanGogh/Firmwares/TypeId0x66.bin 
b/Silicon/AMD/VanGogh/Firmwares/TypeId0x66.bin
index 3119039..e59c3fe 100644
Binary files a/Silicon/AMD/VanGogh/Firmwares/TypeId0x66.bin and 
b/Silicon/AMD/VanGogh/Firmwares/TypeId0x66.bin differ
diff --git a/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3.bin 
b/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3.bin
index b8b3f08..10a246e 100644
Binary files a/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3.bin and 
b/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3.bin differ
diff --git a/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3DefaultRecovery.bin 
b/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3DefaultRecovery.bin
index b8b3f08..10a246e 100644
Binary files a/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3DefaultRecovery.bin 
and b/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3DefaultRecovery.bin differ
diff --git a/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3Updatable.bin 
b/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3Updatable.bin
index 3570f9b..4c01863 100644
Binary files a/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3Updatable.bin and 
b/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet1Ff3Updatable.bin differ
diff --git a/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3.bin 
b/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3.bin
index d476d2d..ab2186f 100644
Binary files a/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3.bin and 
b/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3.bin differ
diff --git a/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3DefaultRecovery.bin 
b/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3DefaultRecovery.bin
index d476d2d..ab2186f 100644
Binary files a/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3DefaultRecovery.bin 
and b/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3DefaultRecovery.bin differ
diff --git a/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3Updatable.bin 
b/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3Updatable.bin
index 819ebb2..678eba6 100644
Binary files a/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3Updatable.bin and 
b/Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3Updatable.bin differ
diff --git a/Silicon/AMD/VanGogh/FspBlobs/Fsp/VangoghSet1ExternalReleaseM.fd 
b/Silicon/AMD/VanGogh/FspBlobs/Fsp/VangoghSet1ExternalReleaseM.fd
index 3b09a23..b0d27f2 100644
Binary files a/Silicon/AMD/VanGogh/FspBlobs/Fsp/VangoghSet1ExternalReleaseM.fd 
and b/Silicon/AMD/VanGogh/FspBlobs/Fsp/VangoghSet1ExternalReleaseM.fd differ
diff --git a/Silicon/AMD/VanGogh/FspBlobs/Fsp/VangoghSet1ExternalReleaseS.fd 
b/Silicon/AMD/VanGogh/FspBlobs/Fsp/VangoghSet1ExternalReleaseS.fd
index 6ac95d1..82459ac 100644
Binary files a/Silicon/AMD/VanGogh/FspBlobs/Fsp/VangoghSet1ExternalReleaseS.fd 
and b/Silicon/AMD/VanGogh/FspBlobs/Fsp/VangoghSet1ExternalReleaseS.fd differ
diff --git a/Silicon/AMD/VanGogh/FspBlobs/Fsp/VangoghSet2ExternalReleaseM.fd 
b/Silicon/AMD/VanGogh/FspBlobs/Fsp/VangoghSet2ExternalReleaseM.fd
index cd5e337..87f554f 100644
Binary files 

[edk2-devel] [PATCH V2 33/33] AMD/VanGoghBoard: Improvement coding style

[Zhai, MingXin (Duke) via groups.io]

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Re: [edk2-devel] [edk2-non-osi][Silicon/AMD/VanGogh][PATCH] Silicon/AMD/VanGogh: Update VanGogh firmware binaries

[Zhai, MingXin (Duke) via groups.io]

[AMD Official Use Only - General]

It looks good to me.

Reviewed-by:  Zhai MingXin

Thanks!
Duke Zhai

-Original Message-
From: Xing, Eric 
Sent: Wednesday, November 29, 2023 4:37 PM
To: devel@edk2.groups.io
Cc: Zhai, MingXin (Duke) ; Attar, AbdulLateef (Abdul Lateef) 
; Chang, Abner 
Subject: [edk2-devel][edk2-non-osi][Silicon/AMD/VanGogh][PATCH] 
Silicon/AMD/VanGogh: Update VanGogh firmware binaries

From: Eric Xing 

Update firmware binaries for VanGogh B0 processors to UCC3B16.3824

Cc: Duke Zhai 
Cc: Abdul Lateef Attar 
Cc: Abner Chang 
Signed-off-by: Eric Xing 
---
 .../VanGogh/Firmwares/AmdSjGenericVbios.bin   | Bin 45056 -> 45056 bytes
 Silicon/AMD/VanGogh/Firmwares/TypeId0x01.sbin | Bin 9024 -> 9024 bytes
 Silicon/AMD/VanGogh/Firmwares/TypeId0x02.sbin | Bin 86864 -> 86864 bytes
 Silicon/AMD/VanGogh/Firmwares/TypeId0x08.sbin | Bin 262656 -> 262656 bytes
 Silicon/AMD/VanGogh/Firmwares/TypeId0x12.sbin | Bin 262656 -> 262656 bytes
 Silicon/AMD/VanGogh/Firmwares/TypeId0x13.sbin | Bin 8640 -> 8704 bytes
 Silicon/AMD/VanGogh/Firmwares/TypeId0x28.sbin | Bin 120720 -> 120720 bytes
 .../AMD/VanGogh/Firmwares/TypeId0x30.csbin| Bin 438592 -> 440144 bytes
 Silicon/AMD/VanGogh/Firmwares/TypeId0x73.sbin | Bin 68864 -> 68864 bytes
 .../AmdTools/CompressBios/CompressBios.lnx64  | Bin 0 -> 827088 bytes
 .../PspDirectoryTool/BuildPspDirectory.lnx64  | Bin 0 -> 7232552 bytes
 .../Apcb/{ApcbFf3.bin => ApcbSet1Ff3.bin} | Bin 8828 -> 10796 bytes
 ...ery.bin => ApcbSet1Ff3DefaultRecovery.bin} | Bin 8828 -> 10796 bytes
 ...Updatable.bin => ApcbSet1Ff3Updatable.bin} | Bin 488 -> 488 bytes
 .../AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3.bin | Bin 0 -> 10796 bytes
 .../Apcb/ApcbSet2Ff3DefaultRecovery.bin   | Bin 0 -> 10796 bytes
 .../FspBlobs/Apcb/ApcbSet2Ff3Updatable.bin| Bin 0 -> 504 bytes
 .../Fsp/VangoghSet1ExternalReleaseM.fd| Bin 720896 -> 786432 bytes
 .../Fsp/VangoghSet1ExternalReleaseS.fd| Bin 589824 -> 524288 bytes
 .../Fsp/VangoghSet2ExternalReleaseM.fd| Bin 720896 -> 786432 bytes
 .../Fsp/VangoghSet2ExternalReleaseS.fd| Bin 589824 -> 524288 bytes
 Silicon/AMD/VanGogh/License.txt   | 136 --
 Silicon/AMD/VanGogh/ReleaseNote.txt   |  31 +++-
 23 files changed, 125 insertions(+), 42 deletions(-)
 create mode 100644 
Silicon/AMD/VanGogh/FspBlobs/AmdTools/CompressBios/CompressBios.lnx64
 create mode 100644 
Silicon/AMD/VanGogh/FspBlobs/AmdTools/PspDirectoryTool/BuildPspDirectory.lnx64
 rename Silicon/AMD/VanGogh/FspBlobs/Apcb/{ApcbFf3.bin => ApcbSet1Ff3.bin} (65%)
 rename Silicon/AMD/VanGogh/FspBlobs/Apcb/{ApcbFf3DefaultRecovery.bin => 
ApcbSet1Ff3DefaultRecovery.bin} (65%)
 rename Silicon/AMD/VanGogh/FspBlobs/Apcb/{ApcbFf3Updatable.bin => 
ApcbSet1Ff3Updatable.bin} (85%)
 create mode 100644 Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3.bin
 create mode 100644 
Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3DefaultRecovery.bin
 create mode 100644 Silicon/AMD/VanGogh/FspBlobs/Apcb/ApcbSet2Ff3Updatable.bin

diff --git a/Silicon/AMD/VanGogh/Firmwares/AmdSjGenericVbios.bin 
b/Silicon/AMD/VanGogh/Firmwares/AmdSjGenericVbios.bin
index 
7065afc8fcfe3cdfd03e49b2cc55637ffd9794bc..5e3ca43cca6280c9125272cad3c7891c21eefd40
 100644
GIT binary patch
delta 3244
zcmZ`*3s_S}7M{8HCWOZq15E`{6JA~{NDL7W-7H0l;SnB@V0hV}Qd3=gP@AmZrWB)C
zG`WEl##TV^MLxBDw96W|3T_cLD*e`V(e7?PZMW5`Yopi}?bbfl$DSKN>+aVX{xdWG
zIdjgLbMKvCyF%HnP|=GIm)`u<4D^5PIOeIGjQoG3H%HG%cKVhGB`RmbpK8u5W%B%_
z#QDk;FuJ*iMK|AOVOE0@6Xzr>$j{W*tjw)3H*cEmr`Kgi-(Jvso@u^SIp3!-
zWaJd;6-bqosGOUa7=cm}Q}mA|g=4cthZ%(y*W)t1v6O5`0vG57LN3BiFN;_*2}9
zuJiE_C7~q8vGah0;#Yj5$q;6l%(mH6$Q?Xyt}A*8wL0blDvU1n=hZd-wf=i!27Ghr
z<73a9(GiW%Z81V&0ld|1_cCgEGSF3Uhe!lRgO@_2UzP$SV(OOmmWV**F|W
zF0os28(9|n67F}Oi9JB$XWeV!8A@nLP<(gnRriL3*8(t2zL|R~q-tLM57-=hvU=X8
zA22qHPQL2?I`xK7-;KFna<2z@`eBm9nUx-ySblPh6xR(!$)=XtbaJqgZEz-IUJ*(a#rQfiWX)1t=SJyKe!tAc+OtHgy(9qmgeQCo@gxj8}ch-ElZg
zWKUlB6pf2Jn(bmE3mGv1)I7bb*)DwIlOSg2os=<{#~j$eat)nhA(t8;4ryd@ht8k
z-(Rb>5=4Y<~QYe_7|$t1)$4+oJvW7t%Q(Q)dl?u@T;AD+7UZQsZA?OrMB8=zI!
z`=_`!8s}hPYL|iy{7j^&1>rb?61^rET4RBkFWmHNp!3Y8d#5g3;YLdpk9HWA
zdbTg!+t%CmQCt18OWOmR>zZ-PZwVnCZ>`xmy0fJ9Zd-BtgN}}>%zc?lpLFT|(1z-*
z{PBou>1rHBf|seWl@u(KVXJ%1vOtW>$#0gg6#R2}|AXb^#`07=g~+Ssq*~c~!mW(W
zl2f0S#~^dY-W;YEMJTv58_V9ynu9H382qtiDo}Ooh*T}C3xsJcaa7F!~FlO9U
zEBu6P`HHcdjlbRaX03jD9gae}&;VTB(lD7ootRhKL(i<{{$`Y$Fa9PjXR->mVB
zTe?OvB{JFK3H-!N-_+m|)c|b&=5XZ+s*ANxXPx?BI|0tF8wOm~lF5Ul^-!
zZ2iQ!g0_V2<0S;Gh--(4*R#7kBLLxXjt|f;#m)ldBlppM-Lc@ArZjosqD`
z=8T+F$L^IdF-o=4EKoEFZKTKf4z>|vV>9qZ}Y$Fe`qj>?UM{_{H%YOg{s%guY-C-^V433;F+
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zEu0wsdje1Z8o@@K)fhz*~X00^b9C5AZ#}_W<9c14R!gs=;{^AP-KS2PZ!S
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Re: [edk2-devel] [[edk2-non-osi][Silicon/AMD][PATCH] VanGogh Silicon initialization firmware binaries 1/2] Maintainers.txt: Add maintainer for Silicon/AMD and Silicon/AMD/Vangogh

[Zhai, MingXin (Duke) via groups.io]

[AMD Official Use Only - General]

It looks good to me.

Reviewed-by:  Zhai MingXin

Thanks!
Duke Zhai

-Original Message-
From: Chang, Abner 
Sent: Saturday, September 30, 2023 12:18 AM
To: Leif Lindholm ; devel@edk2.groups.io
Cc: Xing, Eric ; Michael D Kinney 
; Attar, AbdulLateef (Abdul Lateef) 
; Zhai, MingXin (Duke) 
Subject: RE: [edk2-devel] [[edk2-non-osi][Silicon/AMD][PATCH] VanGogh Silicon 
initialization firmware binaries 1/2] Maintainers.txt: Add maintainer for 
Silicon/AMD and Silicon/AMD/Vangogh

[AMD Official Use Only - General]

> -Original Message-
> From: Leif Lindholm 
> Sent: Friday, September 29, 2023 11:31 PM
> To: devel@edk2.groups.io; Chang, Abner 
> Cc: Xing, Eric ; Michael D Kinney
> ; Attar, AbdulLateef (Abdul Lateef)
> ; Zhai, MingXin (Duke) 
> Subject: Re: [edk2-devel] [[edk2-non-osi][Silicon/AMD][PATCH] VanGogh
> Silicon initialization firmware binaries 1/2] Maintainers.txt: Add
> maintainer for Silicon/AMD and Silicon/AMD/Vangogh
>
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
>
>
> On Fri, Sep 29, 2023 at 14:52:23 +, Chang, Abner via groups.io wrote:
> > > -Original Message-
> > > From: Leif Lindholm 
> > > Sent: Friday, September 29, 2023 6:49 PM
> > > To: Chang, Abner 
> > > Cc: Xing, Eric ; devel@edk2.groups.io; Michael
> > > D
> Kinney
> > > ; Attar, AbdulLateef (Abdul Lateef)
> > > 
> > > Subject: Re: [[edk2-non-osi][Silicon/AMD][PATCH] VanGogh Silicon
> > > initialization firmware binaries 1/2] Maintainers.txt: Add
> > > maintainer for Silicon/AMD and Silicon/AMD/Vangogh
> > >
> > > Caution: This message originated from an External Source. Use
> > > proper
> caution
> > > when opening attachments, clicking links, or responding.
> > >
> > >
> > > Hi Abner,
> > >
> > > On Fri, Sep 29, 2023 at 09:09:25 +, Chang, Abner wrote:
> > > > We have done the review on these patches.
> > >
> > > Still waiting for an R-b from Duke. Hmm, who doesn't seem to have
> > > been cc:d.
> >
> > Hmm... he is not in CCed. I add him in CC. Lets just wait for his
> > RB, it  may take a while as China is in a long holiday. I will that
> > him know as well.
>
> Thanks.
>
> > > > Are you the steward of this repo and able to grant AMD folks the
> > > > merge privilege? To Eric, Abdul and me.
> > >
> > > I'm not a github admin - Mike?
> >
> > I thought you can do anything!! :-D
>
> Haha, thankfully not.
>
> > > But that reminds me, we should start adding github IDs in []
> > > brackets after email, like we do for edk2/edk2-platforms.
> >
> > I don’t quite understand. Any example?
>
> Ah, I'm getting ahead of myself - we haven't done that for
> edk2-platform yet, but:
>
> https://github.com/tianocore/edk2/blob/master/Maintainers.txt#L196
Ah, I got your point.

>
> > > > Btw, do we have to create a PR against non OSI repo for merging
> > > > or we can just push it?
> > >
> > > Just push. But send out for review first.
> >
> > Ok.
> >
> > >
> > > Are any of you attending the plugfest?
> > > If more maintainers are joining edk2-non-osi, maybe we should have
> > > a proper chat about it.
> >
> > I am checking now, I am not able to join this time though. But I
> > prefer you come to Taipei if there is an UEFI Plugfest in Taipei. 
>
> But will there be kaoliang? ;)
Absolutely, I will prepare one bottle for you if you come,  58% one for you. 

Abner

>
> Regards,
>
> Leif
>
> >
> > Abner
> >
> > >
> > > Regards,
> > >
> > > Leif
> > >
> > > > Get Outlook for Android
> > > > 
> > > > From: Leif Lindholm 
> > > > Sent: Friday, September 29, 2023 1:39:07 AM
> > > > To: Xing, Eric 
> > > > Cc: devel@edk2.groups.io ; Michael D
> > > > Kinney
> > > ; Attar, AbdulLateef (Abdul Lateef)
> > > ; Chang, Abner 
> > > > Subject: Re: [[edk2-non-osi][Silicon/AMD][PATCH] VanGogh Silicon
> > > initialization firmware binaries 1/2] Maintainers.txt: Add
> > > maintainer for Silicon/AMD and Silicon/AMD/Vangogh
> > > >
> > > > Caution: This message originated from an External Source. Use
> > > > proper
> > > caution when opening attachments, clicking links, or responding.
> > > >
> > > >
> > > > Hi Eric,
> > > >
> > > > Thanks.
> > > > You didn't really need to rework the patch, but I do want to see
> > > > the Reviewed-by's from the other added people before merging.
> > > >
> > > > Best Regards,
> > > >
> > > > Leif
> > > >
> > > > On Thu, Sep 28, 2023 at 17:13:36 +, Xing, Eric wrote:
> > > > > [AMD Official Use Only - General]
> > > > >
> > > > > Thanks Leif for your quick response and reminder. I added
> > > > > Abner as CC
> in
> > > PATCH v2.
> > > > > Sorry troubling you, would you help review it again so I can
> > > > > get your
> > > approved with v2 patch? Thanks again.
> > > > >
> > > > > Eric
> > > > >
> > > > > -Original Message-
> > > > > From: Leif Lindholm 
> > > > > Sent: Friday, September 29, 2023 12:15 AM
> > > > > To: