from:"cbduggap"

[edk2-devel] [PATCH] IntelFsp2Pkg/PatchFv.py: FIX for GCC 32BIT build error

2024-04-22 Thread cbduggap

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4762

Map file generating 8 byte address offset is not matched
with the pattern defined in patchFv tool resulting build
error.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Duggapu Chinni B 
Cc: Ashraf Ali S 
Cc: Ted Kuo 

Signed-off-by: Duggapu Chinni B 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index bd9aa71e3c..d35aa1dc9f 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -432,7 +432,7 @@ class Symbols:
 if reportLine.strip().find("Archive member included") != -1:
 #GCC
 #0x1d55IoRead8
-patchMapFileMatchString = 
r"\s+(0x[0-9a-fA-F]{16})\s+([^\s][^0x][_a-zA-Z0-9\-]+)\s"
+patchMapFileMatchString = 
r"\s+(0x[0-9a-fA-F]{8,16})\s+([^\s][^0x][_a-zA-Z0-9\-]+)\s"
 matchKeyGroupIndex = 2
 matchSymbolGroupIndex  = 1
 prefix = '_'
-- 
2.44.0.windows.1



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[edk2-devel] [PATCH v6 3/3] IntelFsp2WrapperPkg: Fix UPD structure Reserved bytes

2024-04-05 Thread cbduggap

Changes to update SecRamInitData UPD structure reserved
bytes as par the latest spec.


Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Chiu Chasel 
Cc: Duggapu Chinni B 


Signed-off-by: Duggapu Chinni B 
---
 .../SecFspWrapperPlatformSecLibSample/SecRamInitData.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git 
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
 
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
index f4ed658674..dabcd83eef 100644
--- 
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
+++ 
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
@@ -34,8 +34,11 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA  
FsptUpdDataPtr = {
 // UPD header revision must be equal or greater than 2 when the structure 
is compliant with FSP spec 2.2.
 //
 0x02,
-{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+{
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00
+}
   },
   //
   // If FSP spec version < 2.2, remove FSPT_ARCH_UPD structure.
-- 
2.39.1.windows.1



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[edk2-devel] [PATCH v6 2/3] IntelFsp2WrapperPkg: Fsp T new ARCH UPD Support

2024-04-05 Thread cbduggap

Changes to update SecRamInitData as per New Spec


Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Chiu Chasel 
Cc: Duggapu Chinni B 


Signed-off-by: Duggapu Chinni B 
---
 .../SecFspWrapperPlatformSecLibSample/SecRamInitData.c   | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git 
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
 
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
index fb0d9a8683..f4ed658674 100644
--- 
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
+++ 
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
@@ -43,14 +43,15 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA  
FsptUpdDataPtr = {
   // Else, use FSPT_ARCH2_UPD structure.
   //
   {
-0x02,
+0x03,
 {
   0x00, 0x00, 0x00
 },
 0x0020,
 0x,
+0x,
 {
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 }
   },
-- 
2.39.1.windows.1



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[edk2-devel] [PATCH v6 1/3] IntelFsp2Pkg: Fsp T new ARCH UPD Support

2024-04-05 Thread cbduggap

Changes to support spec changes

1. Remove usage of Pcd.
2. Change code to validate the Temporary Ram size input.
3. Consume the input saved in YMM Register

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Chiu Chasel 
Cc: Duggapu Chinni B 


Signed-off-by: Duggapu Chinni B 
---
 IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf |  1 +
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf   |  1 +
 .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm   |  1 -
 .../FspSecCore/Ia32/FspApiEntryM.nasm |  1 -
 .../FspSecCore/Ia32/FspApiEntryT.nasm | 60 +---
 .../FspSecCore/Ia32/SaveRestoreSseNasm.inc| 11 +++
 IntelFsp2Pkg/FspSecCore/SecFsp.c  |  9 +++
 IntelFsp2Pkg/FspSecCore/SecFsp.h  |  1 +
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 68 +++
 IntelFsp2Pkg/Include/FspEas/FspApi.h  | 12 +++-
 IntelFsp2Pkg/Include/Library/FspPlatformLib.h | 13 
 .../Include/SaveRestoreSseAvxNasm.inc | 21 ++
 .../BaseFspPlatformLib/FspPlatformMemory.c| 38 +++
 13 files changed, 211 insertions(+), 26 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
index cb011f99f9..8cb0e6411f 100644
--- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
@@ -60,6 +60,7 @@
   FspSecPlatformLib
   CpuLib
   FspMultiPhaseLib
+  FspPlatformLib
 
 [Pcd]
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index 8029832235..ef19c6ae78 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -59,6 +59,7 @@
   FspCommonLib
   FspSecPlatformLib
   CpuLib
+  FspPlatformLib
 
 [Pcd]
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
index 15f8ecea83..5fa5c03569 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
 
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index 61ab4612a3..861cce4d01 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
 
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 900126b93b..088bd7ee7f 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -109,7 +109,8 @@ struc LoadMicrocodeParamsFsp24
 .FsptArchReserved:resb3
 .FsptArchLength:  resd1
 .FspDebugHandler  resq1
-.FsptArchUpd: resd4
+.FspTemporaryRamSize: resd1  ; Supported only if ArchRevison is >= 
3
+.FsptArchUpd: resd3
 ; }
 ; FSPT_CORE_UPD {
 .MicrocodeCodeAddr:   resq1
@@ -267,7 +268,7 @@ ASM_PFX(LoadMicrocodeDefault):
cmpbyte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jb Fsp20UpdHeader
cmpbyte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
-   je Fsp24UpdHeader
+   jaeFsp24UpdHeader
jmpFsp22UpdHeader
 
 Fsp20UpdHeader:
@@ -405,7 +406,7 @@ CheckAddress:
cmp   byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jb Fsp20UpdHeader1
cmpbyte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
-   je Fsp24UpdHeader1;
+   jaeFsp24UpdHeader1;
jmpFsp22UpdHeader1
 
 Fsp20UpdHeader1:
@@ -497,7 +498,8 @@ ASM_PFX(EstablishStackFsp):
   ; Enable FSP STACK
   ;
   mov   esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
-  add   esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
+  LOAD_TEMPORARY_RAM_SIZE ecx
+  add   esp, ecx
 
   push  DATA_LEN_OF_MCUD ; Size of the data region
   push  4455434Dh; Signature of the  data region 'MCUD'
@@ -506,7 +508,7 @@ ASM_PFX(EstablishStackFsp):
   cmp   byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
   jbFsp20UpdHeader2
   cmp   byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
-  jeFsp24UpdHeader2
+  jae   Fsp24UpdHeader2
   jmp   Fsp22UpdHeader2
 
 Fsp20UpdHeader2:
@@ -554,12 +556,13 @@ ContinueAfterUpdPush:
   ;
   ; Set ECX/EDX to the

[edk2-devel] [PATCH v6 0/3] IntelFsp2Pkg: Fsp T new ARCH UPD Support

2024-04-05 Thread cbduggap

This Patch will add changes to support FSP T new ARCH UPD
and Fix Bug in IntelFsp2WrapperPkg

cbduggap (3):
  IntelFsp2Pkg: Fsp T new ARCH UPD Support
  IntelFsp2WrapperPkg: Fsp T new ARCH UPD Support
  IntelFsp2WrapperPkg: Fix UPD structure Reserved bytes

 IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf |  1 +
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf   |  1 +
 .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm   |  1 -
 .../FspSecCore/Ia32/FspApiEntryM.nasm |  1 -
 .../FspSecCore/Ia32/FspApiEntryT.nasm | 60 +---
 .../FspSecCore/Ia32/SaveRestoreSseNasm.inc| 11 +++
 IntelFsp2Pkg/FspSecCore/SecFsp.c  |  9 +++
 IntelFsp2Pkg/FspSecCore/SecFsp.h  |  1 +
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 68 +++
 IntelFsp2Pkg/Include/FspEas/FspApi.h  | 12 +++-
 IntelFsp2Pkg/Include/Library/FspPlatformLib.h | 13 
 .../Include/SaveRestoreSseAvxNasm.inc | 21 ++
 .../BaseFspPlatformLib/FspPlatformMemory.c| 38 +++
 .../SecRamInitData.c  | 12 ++--
 14 files changed, 219 insertions(+), 30 deletions(-)

-- 
2.39.1.windows.1



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[edk2-devel] [PATCH v5] IntelFsp2Pkg: Fsp T new ARCH UPD Support

2024-03-21 Thread cbduggap

Changes to support spec changes

1. Remove usage of Pcd.
2. Change code to validate the Temporary Ram size input.
3. Consume the input saved in YMM Register

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Chiu Chasel 
Cc: Duggapu Chinni B 


Signed-off-by: Duggapu Chinni B 
---
 IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf |  1 +
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf   |  1 +
 .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm   |  1 -
 .../FspSecCore/Ia32/FspApiEntryM.nasm |  1 -
 .../FspSecCore/Ia32/FspApiEntryT.nasm | 62 ++---
 .../FspSecCore/Ia32/SaveRestoreSseNasm.inc| 11 +++
 IntelFsp2Pkg/FspSecCore/SecFsp.c  |  9 +++
 IntelFsp2Pkg/FspSecCore/SecFsp.h  |  1 +
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 69 +++
 IntelFsp2Pkg/Include/FspEas/FspApi.h  |  5 +-
 IntelFsp2Pkg/Include/Library/FspPlatformLib.h | 13 
 .../Include/SaveRestoreSseAvxNasm.inc | 21 ++
 .../BaseFspPlatformLib/FspPlatformMemory.c| 38 ++
 .../SecRamInitData.c  |  3 +-
 14 files changed, 209 insertions(+), 27 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
index cb011f99f9..8cb0e6411f 100644
--- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
@@ -60,6 +60,7 @@
   FspSecPlatformLib
   CpuLib
   FspMultiPhaseLib
+  FspPlatformLib
 
 [Pcd]
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index 8029832235..ef19c6ae78 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -59,6 +59,7 @@
   FspCommonLib
   FspSecPlatformLib
   CpuLib
+  FspPlatformLib
 
 [Pcd]
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
index 15f8ecea83..5fa5c03569 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
 
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index 61ab4612a3..861cce4d01 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
 
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 900126b93b..f72da0d5a9 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -109,7 +109,8 @@ struc LoadMicrocodeParamsFsp24
 .FsptArchReserved:resb3
 .FsptArchLength:  resd1
 .FspDebugHandler  resq1
-.FsptArchUpd: resd4
+.FspTemporaryRamSize: resd1  ; Supported only if ArchRevison is >= 
3
+.FsptArchUpd: resd3
 ; }
 ; FSPT_CORE_UPD {
 .MicrocodeCodeAddr:   resq1
@@ -267,7 +268,7 @@ ASM_PFX(LoadMicrocodeDefault):
cmpbyte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jb Fsp20UpdHeader
cmpbyte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
-   je Fsp24UpdHeader
+   jaeFsp24UpdHeader
jmpFsp22UpdHeader
 
 Fsp20UpdHeader:
@@ -405,7 +406,7 @@ CheckAddress:
cmp   byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jb Fsp20UpdHeader1
cmpbyte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
-   je Fsp24UpdHeader1;
+   jaeFsp24UpdHeader1;
jmpFsp22UpdHeader1
 
 Fsp20UpdHeader1:
@@ -497,7 +498,8 @@ ASM_PFX(EstablishStackFsp):
   ; Enable FSP STACK
   ;
   mov   esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
-  add   esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
+  LOAD_TEMPORARY_RAM_SIZE ecx
+  add   esp, ecx
 
   push  DATA_LEN_OF_MCUD ; Size of the data region
   push  4455434Dh; Signature of the  data region 'MCUD'
@@ -506,7 +508,7 @@ ASM_PFX(EstablishStackFsp):
   cmp   byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
   jbFsp20UpdHeader2
   cmp   byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
-  jeFsp24UpdHeader2
+  jae   Fsp24UpdHeader2
   jmp   Fsp22UpdHeader2
 
 Fsp20UpdHeader2:
@@ -554,12 +556,13 @@

[edk2-devel] [PATCH v4] IntelFsp2Pkg: Fsp 2.x Changes

2024-02-28 Thread cbduggap

Changes to support spec changes

1. Remove usage of Pcd.
2. Change code to validate the Temporary Ram size input.
3. Consume the input saved in YMM Register

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Chiu Chasel 
Cc: Duggapu Chinni B 


Signed-off-by: Duggapu Chinni B 
---
 IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf |  2 +-
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf   |  2 +-
 IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf   |  1 +
 .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm   |  1 -
 .../FspSecCore/Ia32/FspApiEntryM.nasm |  1 -
 .../FspSecCore/Ia32/FspApiEntryT.nasm | 70 ++---
 .../FspSecCore/Ia32/SaveRestoreSseNasm.inc| 11 +++
 IntelFsp2Pkg/FspSecCore/SecFsp.c  | 17 +++-
 IntelFsp2Pkg/FspSecCore/SecFspApiChk.c|  4 +-
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 78 +++
 IntelFsp2Pkg/Include/FspEas/FspApi.h  |  5 +-
 .../Include/SaveRestoreSseAvxNasm.inc | 21 +
 IntelFsp2Pkg/IntelFsp2Pkg.dec |  5 ++
 .../SecRamInitData.c  |  3 +-
 14 files changed, 185 insertions(+), 36 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
index cb011f99f9..cf8cb2eda9 100644
--- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
@@ -63,11 +63,11 @@
 
 [Pcd]
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
-  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize   ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index 8029832235..717941c33f 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -62,11 +62,11 @@
 
 [Pcd]
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
-  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize   ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
index e5a6eaa164..05c0d5f48b 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
@@ -51,6 +51,7 @@
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
index 15f8ecea83..5fa5c03569 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
 
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index 61ab4612a3..861cce4d01 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
 
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 900126b93b..020599ba89 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -16,6 +16,7 @@
 extern   ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
 extern   ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
+extern   ASM_PFX(PcdGet32

[edk2-devel] [PATCH v3] IntelFsp2Pkg: Fsp 2.x Changes

2024-02-26 Thread cbduggap

Changes to support spec changes

1. Remove usage of Pcd.
2. Change code to validate the Temporary Ram size input.
3. Consume the input saved in YMM Register

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Chiu Chasel 
Cc: Duggapu Chinni B 


Signed-off-by: Duggapu Chinni B 
---
 IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf |  2 +-
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf   |  2 +-
 IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf   |  1 +
 .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm   |  1 -
 .../FspSecCore/Ia32/FspApiEntryM.nasm |  1 -
 .../FspSecCore/Ia32/FspApiEntryT.nasm | 71 ++---
 .../FspSecCore/Ia32/SaveRestoreSseNasm.inc| 11 +++
 IntelFsp2Pkg/FspSecCore/SecFsp.c  | 23 --
 IntelFsp2Pkg/FspSecCore/SecFspApiChk.c|  4 +-
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 78 +++
 IntelFsp2Pkg/Include/FspEas/FspApi.h  |  5 +-
 .../Include/SaveRestoreSseAvxNasm.inc | 21 +
 IntelFsp2Pkg/IntelFsp2Pkg.dec |  4 +
 .../SecRamInitData.c  |  3 +-
 14 files changed, 186 insertions(+), 41 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
index cb011f99f9..cf8cb2eda9 100644
--- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
@@ -63,11 +63,11 @@
 
 [Pcd]
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
-  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize   ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index 8029832235..717941c33f 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -62,11 +62,11 @@
 
 [Pcd]
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
-  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize   ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
index e5a6eaa164..05c0d5f48b 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
@@ -51,6 +51,7 @@
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
index 15f8ecea83..5fa5c03569 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
 
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index 61ab4612a3..861cce4d01 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
 
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 900126b93b..fd08b01839 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -16,6 +16,7 @@
 extern   ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
 extern   ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
+extern   ASM_PFX(PcdGet32

Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fsp 2.x Changes

2024-02-25 Thread cbduggap

Corrected #3 in background.

Thanks,
Chinni.

-Original Message-
From: devel@edk2.groups.io  On Behalf Of cbduggap
Sent: Monday, February 26, 2024 10:45 AM
To: Desimone, Nathaniel L ; devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 

Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fsp 2.x Changes

Thanks, Nate, for taking some time to review the patch.
I agree that GlobalDatapointer usage to pass Top of CAR from FSP-T to FSP-M is 
an ugly hack where I only convinced 90% (with my approach ) but ended up in 
adding that logic as we covered all corner cases.  

Here is the background why:
1.  FSP-M Sec Core function SecGetPlatformData is using Top of CAR to retrieve 
"FSP T Core UPD information" and "Time Stamp for FSP T entry and exit". This 
code is FSP API Mode only code. 
2.  Both are invalid if some Boot loader not calling FSP-T. 
3. Further in the changes, we are safely returning from FSP-M 
SecGetPlatformData Function when the value of the Register is 0 or if signature 
is not found.

Few Options that are explored before adding this logic:
1. Initially was thinking to stop using SecGetPlatformData function in FSP-M 
Sec because we don’t have any use case where we need to save the details of FSP 
T Core UPD information for later stages. But we would need Top of CAR to 
capture FSP-T entry & exit time (which still can be retrieved in Bootloader 
code as we pass Start & end range of TempRam in ECX and EDX as a output).
2. Further thought of using some YMM register to save the value (inside FSP-T ) 
for later consumption but there is no guarantee that Bootloaders will preserve 
that value until they call FSP-M.

I agree that we need to add the same logic inside IA32 implementation also 
which was missed (to find during Unit testing ) as we haven’t seen any Boot 
failures with these changes on another intel program where we are still using 
FSP 32 BIT (This is because we don’t use FSP T Core UPDs in FSP-M But might not 
be able to capture the FSP-T entry & exit time in FPDT for API Mode).

I will take care of other feedback and re-send Patch V3 But need some inputs on 
"How we can avoid the GlobalDatapointer hack".

Other feedback :
1. What is the reason for removing the LoadUpdPointerToECX function and putting 
the equivalent logic inline? 
 Initially I thought that we need changes to this logic and cannot keep 
this as a separate function, but I agree we can reuse the same function now.

Thanks,
Chinni.

-Original Message-
From: Desimone, Nathaniel L 
Sent: Saturday, February 24, 2024 4:22 AM
To: Duggapu, Chinni B ; devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 

Subject: RE: [PATCH v2] IntelFsp2Pkg: Fsp 2.x Changes

Hi Chinni,

Using the FspGlobalDataPointer as a scratchpad for your top of CAR early and 
then putting the real global data into it later is an ugly hack. If you are 
going to initialize the FspGlobalDataPointer in FSP-T, then FSP-T needs to 
actually initialize that FSP global data structure fully.

Moreover, you have added the assumption that FspGlobalDataPointer is 
initialized to top of CAR to SecFsp.c but you don't actually write top of CAR 
to that location in the IA32 version of TempRamInit(), only the X64 version has 
that addition. Since SecFsp.c is used on both, you have effectively broken all 
32-bit FSP builds. For obvious reasons, your patch will not be merged without 
additional work.

Additional feedback below inline.

Thanks,
Nate

> -Original Message-
> From: Duggapu, Chinni B 
> Sent: Thursday, February 15, 2024 9:07 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Desimone, 
> Nathaniel L ; Chiu, Chasel 
> ; Duggapu, Chinni B 
> 
> Subject: [PATCH v2] IntelFsp2Pkg: Fsp 2.x Changes
> 
> Changes to support spec changes
> 
> 1. Remove usage of Pcd.
> 2. Change code to validate the Temporary Ram size input.
> 3. Consume the input saved in YMM Register
> 
> Cc: Sai Chaganty 
> Cc: Nate DeSimone 
> Cc: Chiu Chasel 
> Cc: Duggapu Chinni B 
> 
> 
> Signed-off-by: Duggapu Chinni B 
> ---
>  IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf |   2 +-
>  IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf   |   2 +-
>  IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf   |   1 +
>  .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm   |   1 -
>  .../FspSecCore/Ia32/FspApiEntryM.nasm |   1 -
>  .../FspSecCore/Ia32/FspApiEntryT.nasm | 110 --
>  .../FspSecCore/Ia32/SaveRestoreSseNasm.inc|  11 ++
>  IntelFsp2Pkg/FspSecCore/SecFsp.c  |  23 ++--
>  IntelFsp2Pkg/FspSecCore/SecFspApiChk.c|   4 +-
>  IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm |  79 +++--
>  IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm|   6 +-
>  IntelFsp2Pkg/Include/FspEas/FspApi.h  |   5 +-
>  .../Include/SaveRestoreSseAvxNasm.inc |  21 
>

Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fsp 2.x Changes

2024-02-25 Thread cbduggap

Thanks, Nate, for taking some time to review the patch.
I agree that GlobalDatapointer usage to pass Top of CAR from FSP-T to FSP-M is 
an ugly hack where I only convinced 90% (with my approach ) but ended up in 
adding that logic as we covered all corner cases.  

Here is the background why:
1.  FSP-M Sec Core function SecGetPlatformData is using Top of CAR to retrieve 
"FSP T Core UPD information" and "Time Stamp for FSP T entry and exit". This 
code is FSP API Mode only code. 
2.  Both are invalid if some Boot loader not calling FSP-T. 
3. Further in the changes, we are safely returning from FSP-M 
SecGetPlatformData Function when the value of the Register is all F's.

Few Options that are explored before adding this logic:
1. Initially was thinking to stop using SecGetPlatformData function in FSP-M 
Sec because we don’t have any use case where we need to save the details of FSP 
T Core UPD information for later stages. But we would need Top of CAR to 
capture FSP-T entry & exit time (which still can be retrieved in Bootloader 
code as we pass Start & end range of TempRam in ECX and EDX as a output).
2. Further thought of using some YMM register to save the value (inside FSP-T ) 
for later consumption but there is no guarantee that Bootloaders will preserve 
that value until they call FSP-M.

I agree that we need to add the same logic inside IA32 implementation also 
which was missed (to find during Unit testing ) as we haven’t seen any Boot 
failures with these changes on another intel program where we are still using 
FSP 32 BIT (This is because we don’t use FSP T Core UPDs in FSP-M But might not 
be able to capture the FSP-T entry & exit time in FPDT for API Mode).

I will take care of other feedback and re-send Patch V3 But need some inputs on 
"How we can avoid the GlobalDatapointer hack".


Other feedback :
1. What is the reason for removing the LoadUpdPointerToECX function and putting 
the equivalent logic inline? 
 Initially I thought that we need changes to this logic and cannot keep 
this as a separate function, but I agree we can reuse the same function now.

Thanks,
Chinni.

-Original Message-
From: Desimone, Nathaniel L  
Sent: Saturday, February 24, 2024 4:22 AM
To: Duggapu, Chinni B ; devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 

Subject: RE: [PATCH v2] IntelFsp2Pkg: Fsp 2.x Changes

Hi Chinni,

Using the FspGlobalDataPointer as a scratchpad for your top of CAR early and 
then putting the real global data into it later is an ugly hack. If you are 
going to initialize the FspGlobalDataPointer in FSP-T, then FSP-T needs to 
actually initialize that FSP global data structure fully.

Moreover, you have added the assumption that FspGlobalDataPointer is 
initialized to top of CAR to SecFsp.c but you don't actually write top of CAR 
to that location in the IA32 version of TempRamInit(), only the X64 version has 
that addition. Since SecFsp.c is used on both, you have effectively broken all 
32-bit FSP builds. For obvious reasons, your patch will not be merged without 
additional work.

Additional feedback below inline.

Thanks,
Nate

> -Original Message-
> From: Duggapu, Chinni B 
> Sent: Thursday, February 15, 2024 9:07 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Desimone, 
> Nathaniel L ; Chiu, Chasel 
> ; Duggapu, Chinni B 
> 
> Subject: [PATCH v2] IntelFsp2Pkg: Fsp 2.x Changes
> 
> Changes to support spec changes
> 
> 1. Remove usage of Pcd.
> 2. Change code to validate the Temporary Ram size input.
> 3. Consume the input saved in YMM Register
> 
> Cc: Sai Chaganty 
> Cc: Nate DeSimone 
> Cc: Chiu Chasel 
> Cc: Duggapu Chinni B 
> 
> 
> Signed-off-by: Duggapu Chinni B 
> ---
>  IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf |   2 +-
>  IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf   |   2 +-
>  IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf   |   1 +
>  .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm   |   1 -
>  .../FspSecCore/Ia32/FspApiEntryM.nasm |   1 -
>  .../FspSecCore/Ia32/FspApiEntryT.nasm | 110 --
>  .../FspSecCore/Ia32/SaveRestoreSseNasm.inc|  11 ++
>  IntelFsp2Pkg/FspSecCore/SecFsp.c  |  23 ++--
>  IntelFsp2Pkg/FspSecCore/SecFspApiChk.c|   4 +-
>  IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm |  79 +++--
>  IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm|   6 +-
>  IntelFsp2Pkg/Include/FspEas/FspApi.h  |   5 +-
>  .../Include/SaveRestoreSseAvxNasm.inc |  21 
>  IntelFsp2Pkg/IntelFsp2Pkg.dec |   4 +
>  .../SecRamInitData.c  |   3 +-
>  15 files changed, 206 insertions(+), 67 deletions(-)
> 
> diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf 
> b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
> index cb011f99f9..cf8cb2eda9 100644
> --- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
> +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
> @@ -63,11 +63,11 @@
>  
>  [Pcd]
>gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase

[edk2-devel] [PATCH v2] IntelFsp2Pkg: Fsp 2.x Changes

2024-02-15 Thread cbduggap

Changes to support spec changes

1. Remove usage of Pcd.
2. Change code to validate the Temporary Ram size input.
3. Consume the input saved in YMM Register

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Chiu Chasel 
Cc: Duggapu Chinni B 


Signed-off-by: Duggapu Chinni B 
---
 IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf |   2 +-
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf   |   2 +-
 IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf   |   1 +
 .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm   |   1 -
 .../FspSecCore/Ia32/FspApiEntryM.nasm |   1 -
 .../FspSecCore/Ia32/FspApiEntryT.nasm | 110 --
 .../FspSecCore/Ia32/SaveRestoreSseNasm.inc|  11 ++
 IntelFsp2Pkg/FspSecCore/SecFsp.c  |  23 ++--
 IntelFsp2Pkg/FspSecCore/SecFspApiChk.c|   4 +-
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm |  79 +++--
 IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm|   6 +-
 IntelFsp2Pkg/Include/FspEas/FspApi.h  |   5 +-
 .../Include/SaveRestoreSseAvxNasm.inc |  21 
 IntelFsp2Pkg/IntelFsp2Pkg.dec |   4 +
 .../SecRamInitData.c  |   3 +-
 15 files changed, 206 insertions(+), 67 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
index cb011f99f9..cf8cb2eda9 100644
--- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
@@ -63,11 +63,11 @@
 
 [Pcd]
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
-  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize   ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index 8029832235..717941c33f 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -62,11 +62,11 @@
 
 [Pcd]
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
-  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize   ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
index e5a6eaa164..05c0d5f48b 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
@@ -51,6 +51,7 @@
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
index 15f8ecea83..5fa5c03569 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
 
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index 61ab4612a3..861cce4d01 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
 
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 900126b93b..2f8465df3d 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -109,7 +109,8 @@ struc LoadMicrocodeParamsFsp24
 .FsptArchReserved:resb3
 .FsptArchLength:  resd1

[edk2-devel] [PATCH] IntelFsp2Pkg: Fsp 2.x Changes

2024-02-15 Thread cbduggap

Changes to support spec changes

1. Remove usage of Pcd.
2. Change code to validate the Temporary Ram size input.
3. Consume the input saved in YMM Register

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Chiu Chasel 


Signed-off-by: cbduggap 
---
 .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm   |   1 -
 .../FspSecCore/Ia32/FspApiEntryM.nasm |   1 -
 .../FspSecCore/Ia32/FspApiEntryT.nasm | 110 --
 .../FspSecCore/Ia32/SaveRestoreSseNasm.inc|  11 ++
 IntelFsp2Pkg/FspSecCore/SecFsp.c  |   1 -
 IntelFsp2Pkg/FspSecCore/SecFspApiChk.c|   4 +-
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm |  69 +--
 IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm|   6 +-
 IntelFsp2Pkg/Include/FspEas/FspApi.h  |   5 +-
 .../Include/SaveRestoreSseAvxNasm.inc |  21 
 .../SecRamInitData.c  |   3 +-
 11 files changed, 175 insertions(+), 57 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
index 15f8ecea83..5fa5c03569 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
 
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index 61ab4612a3..861cce4d01 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
 
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 900126b93b..5fca46ca7a 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -109,7 +109,8 @@ struc LoadMicrocodeParamsFsp24
 .FsptArchReserved:resb3
 .FsptArchLength:  resd1
 .FspDebugHandler  resq1
-.FsptArchUpd: resd4
+.FspTemporaryRamSize: resd1  ; Supported only if ArchRevison is >= 
3
+.FsptArchUpd: resd3
 ; }
 ; FSPT_CORE_UPD {
 .MicrocodeCodeAddr:   resq1
@@ -178,29 +179,6 @@ endstruc
   jmp ebp   ; restore EIP from EBP
 %endmacro
 
-;
-; Load UPD region pointer in ECX
-;
-global ASM_PFX(LoadUpdPointerToECX)
-ASM_PFX(LoadUpdPointerToECX):
-  ;
-  ; esp + 4 is input UPD parameter
-  ; If esp + 4 is NULL the default UPD should be used
-  ; ecx will be the UPD region that should be used
-  ;
-  mov   ecx, dword [esp + 4]
-  cmp   ecx, 0
-  jnz   ParamValid
-
-  ;
-  ; Fall back to default UPD region
-  ;
-  CALL_EDI  ASM_PFX(AsmGetFspInfoHeaderNoStack)
-  mov   ecx, DWORD [eax + 01Ch]  ; Read FsptImageBaseAddress
-  add   ecx, DWORD [eax + 024h]  ; Get Cfg Region base address = 
FsptImageBaseAddress + CfgRegionOffset
-ParamValid:
-  RET_EBP
-
 ;
 ; @todo: The strong/weak implementation does not work.
 ;This needs to be reviewed later.
@@ -267,7 +245,7 @@ ASM_PFX(LoadMicrocodeDefault):
cmpbyte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jb Fsp20UpdHeader
cmpbyte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
-   je Fsp24UpdHeader
+   jae Fsp24UpdHeader
jmpFsp22UpdHeader
 
 Fsp20UpdHeader:
@@ -405,7 +383,7 @@ CheckAddress:
cmp   byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jb Fsp20UpdHeader1
cmpbyte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
-   je Fsp24UpdHeader1;
+   jae Fsp24UpdHeader1;
jmpFsp22UpdHeader1
 
 Fsp20UpdHeader1:
@@ -497,7 +475,8 @@ ASM_PFX(EstablishStackFsp):
   ; Enable FSP STACK
   ;
   mov   esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
-  add   esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
+  LOAD_TEMPORARY_RAM_SIZE eax
+  add   esp, eax
 
   push  DATA_LEN_OF_MCUD ; Size of the data region
   push  4455434Dh; Signature of the  data region 'MCUD'
@@ -506,7 +485,7 @@ ASM_PFX(EstablishStackFsp):
   cmp   byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
   jbFsp20UpdHeader2
   cmp   byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
-  jeFsp24UpdHeader2
+  jaeFsp24UpdHeader2
   jmp   Fsp22UpdHeader2
 
 Fsp20UpdHeader2:
@@ -554,12 +533,13 @@ ContinueAfterUpdPush:
   ;
   ; Set ECX/EDX to the BootLoader temporary memory range
   ;
-  mov   ecx,  [ASM_PFX(PcdGet32 (PcdTemporaryRamB

Re: [edk2-devel] Need help to add me to the edk-ii-maintainers and edk-ii-reviewers team

2023-06-25 Thread cbduggap



Thanks,
Chinni.

From: Duggapu, Chinni B
Sent: Monday, June 19, 2023 10:58 AM
To: devel@edk2.groups.io
Subject: Need help to add me to the edk-ii-maintainers and edk-ii-reviewers team


HI All
I signed up to work as Maintainer for InteFsp2Pkg and IntelFsp2WrapperPkg and 
part of https://github.com/tianocore/edk2/blob/master/Maintainers.txt
Need help to add me to the edk-ii-maintainers and edk-ii-reviewers team.

Maintainer: https://github.com/orgs/tianocore/teams/edk-ii-maintainers

Reviewer: https://github.com/orgs/tianocore/teams/edk-ii-reviewers

Thanks,
Chinni.



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[edk2-devel] Need help to add me to the edk-ii-maintainers and edk-ii-reviewers team

2023-06-18 Thread cbduggap


HI All
I signed up to work as Maintainer for InteFsp2Pkg and IntelFsp2WrapperPkg and 
part of https://github.com/tianocore/edk2/blob/master/Maintainers.txt
Need help to add me to the edk-ii-maintainers and edk-ii-reviewers team.

Maintainer: https://github.com/orgs/tianocore/teams/edk-ii-maintainers

Reviewer: https://github.com/orgs/tianocore/teams/edk-ii-reviewers

Thanks,
Chinni.



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Re: [edk2-devel] [PATCH] Maintainers.txt: Update for IntelFsp2Pkg and IntelFsp2WrapperPkg.

2023-05-03 Thread cbduggap

Reviewed-by:  Duggapu Chinni B 

Thanks,
Chinni.

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Chiu, Chasel
Sent: Monday, April 24, 2023 11:51 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Duggapu, Chinni B 
; Ng, Ray Han Lim ; Chen, 
Gang C ; Zeng, Star ; Kuo, Ted 
; S, Ashraf Ali ; Mohapatra, Susovan 

Subject: [edk2-devel] [PATCH] Maintainers.txt: Update for IntelFsp2Pkg and 
IntelFsp2WrapperPkg.

Add more maintainers and reviewers for these 2 packages.

Cc: Nate DeSimone 
Cc: Duggapu Chinni B 
Cc: Ray Han Lim Ng 
Cc: Chen Gang C 
Cc: Star Zeng 
Cc: Ted Kuo 
Cc: Ashraf Ali S 
Cc: Susovan Mohapatra 
Signed-off-by: Chasel Chiu 
---
 Maintainers.txt | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt index 455afdbc69..09d04af27a 
100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -237,14 +237,24 @@ F: IntelFsp2Pkg/
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg M: 
Chasel Chiu  [ChaselChiu] M: Nate DeSimone 
 [nate-desimone]+M: Duggapu Chinni B 
 [cbduggap]+M: Ray Han Lim Ng 
 [rayhanlimng] R: Star Zeng  
[lzeng14]+R: Ted Kuo  [tedkuo1]+R: Ashraf Ali S 
 [AshrafAliS]+R: Susovan Mohapatra 
 [susovanmohapatra]  IntelFsp2WrapperPkg F: 
IntelFsp2WrapperPkg/ W: 
https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPkg M: 
Chasel Chiu  [ChaselChiu] M: Nate DeSimone 
 [nate-desimone]+M: Duggapu Chinni B 
 [cbduggap]+M: Chen Gang C  
[chengangc] R: Star Zeng  [lzeng14]+R: Ted Kuo 
 [tedkuo1]+R: Ashraf Ali S  
[AshrafAliS]+R: Susovan Mohapatra  
[susovanmohapatra]  MdeModulePkg F: MdeModulePkg/--
2.35.0.windows.1



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[edk2-devel] [PATCH v3] IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file directly

2023-04-16 Thread cbduggap

From: "Duggapu, Chinni B" 

https://bugzilla.tianocore.org/show_bug.cgi?id=4412

After shrinking the FSP (FV) component using FMMT, Image size
in FSP info header is not in sync with the FV length in FV header.
This enhancement helps to patch the FSP image size offset with
correct length & can be used to patch any offset directly on
the FSP Component Fd.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Ted Kuo 
Signed-off-by: Duggapu Chinni B 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 14 -
 .../Tools/UserManuals/PatchFvUserManual.md| 20 +++
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index eb130049b5..73ab877c71 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -165,6 +165,17 @@ class Symbols:
 if not os.path.isdir(fvDir):
 raise Exception ("'%s' is not a valid directory!" % fvDir)
 
+#
+# if user provided fd name as a input, skip rest of the flow to
+# patch fd directly
+#
+fdFile =  os.path.join(fvDir,fvNames + ".fd")
+if os.path.exists(fdFile):
+print("Tool identified Fd file as a input to patch '%s'" %fdFile)
+self.fdFile = fdFile
+self.fdSize = os.path.getsize(fdFile)
+return 0
+
 #
 # If the Guid.xref is not existing in fvDir, then raise an exception
 #
@@ -848,8 +859,9 @@ class Symbols:
 #  Print out the usage
 #
 def Usage():
-print ("PatchFv Version 0.50")
+print ("PatchFv Version 0.60")
 print ("Usage: \n\tPatchFv FvBuildDir 
[FvFileBaseNames:]FdFileBaseNameToPatch \"Offset, Value\"")
+print ("\tPatchFv FdFileDir FdFileName \"Offset, Value\"")
 
 def main():
 #
diff --git a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md 
b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
index 5f1031e729..f28eedf625 100644
--- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
+++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
@@ -1,6 +1,7 @@
 #Name
 **_PatchFv.py_** - The python script that patches the firmware volumes (**FV**)
 with in the flash device (**FD**) file post FSP build.
+From version 0.60, script is capable of patching flash device (**FD**) 
directly.
 
 #Synopsis
 
@@ -10,6 +11,12 @@ PatchFv FvBuildDir [FvFileBaseNames:]FdFileBaseNameToPatch 
["Offset, Value"]+
   | ["Offset, Value, $Command"]+
   | ["Offset, Value, $Command, @Comment"]+
 ```
+```
+PatchFv FdFileDir FdFileName ["Offset, Value"]+
+  | ["Offset, Value, @Comment"]+
+  | ["Offset, Value, $Command"]+
+  | ["Offset, Value, $Command, @Comment"]+
+```
 
 #Description
 The **_PatchFv.py_** tool allows the developer to fix up FD images to follow 
the
@@ -102,6 +109,19 @@ ModuleGuid:Offset
   < > Convert absolute address  into an image offset (expr & FSP_SIZE)
 
 ```
+From version 0.60 tool allows to pass flash device file path as Argument 1 and
+flash device name as Argument 2 and rules for passing offset & value are same
+as explained in the previous sections.
+
+Example usage:
+Argument 1
+```
+ YouPlatformFspBinPkg\
+```
+Argument 2
+```
+ Fsp_Rebased_T
+```
 
 ###Special Commands:
 Special commands must use the **$** symbol as a prefix to the command itself.
-- 
2.39.1.windows.1



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[edk2-devel] [PATCH v2] IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file directly https://bugzilla.tianocore.org/show_bug.cgi?id=4412

2023-04-14 Thread cbduggap

After shrinking the FSP (FV) component using FMMT, Image size
in FSP info header is not in sync with the FV length in FV header.
This enhancement helps to patch the FSP image size offset with
correct length & can be used to patch any offset directly on
the FSP Component Fd .

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Ted Kuo 
Signed-off-by: Duggapu Chinni B 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 14 -
 .../Tools/UserManuals/PatchFvUserManual.md| 20 +++
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index eb130049b5..156c937abe 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -165,6 +165,17 @@ class Symbols:
 if not os.path.isdir(fvDir):
 raise Exception ("'%s' is not a valid directory!" % fvDir)
 
+#
+# if user provided fd name as a input, skip rest of the flow to
+# patch fd directly
+# 
+fdFile =  os.path.join(fvDir,fvNames + ".fd")
+if os.path.exists(fdFile):
+print("Tool identified Fd file as a input to patch '%s'" %fdFile)
+self.fdFile = fdFile
+self.fdSize = os.path.getsize(fdFile)
+return 0
+
 #
 # If the Guid.xref is not existing in fvDir, then raise an exception
 #
@@ -848,8 +859,9 @@ class Symbols:
 #  Print out the usage
 #
 def Usage():
-print ("PatchFv Version 0.50")
+print ("PatchFv Version 0.60")
 print ("Usage: \n\tPatchFv FvBuildDir 
[FvFileBaseNames:]FdFileBaseNameToPatch \"Offset, Value\"")
+print ("\tPatchFv FdFileDir FdFileName \"Offset, Value\"")
 
 def main():
 #
diff --git a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md 
b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
index 5f1031e729..33bba38a3f 100644
--- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
+++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
@@ -1,6 +1,7 @@
 #Name
 **_PatchFv.py_** - The python script that patches the firmware volumes (**FV**)
 with in the flash device (**FD**) file post FSP build.
+From version 0.60, script is capable of patching flash device (**FD**) 
directly.
 
 #Synopsis
 
@@ -10,6 +11,12 @@ PatchFv FvBuildDir [FvFileBaseNames:]FdFileBaseNameToPatch 
["Offset, Value"]+
   | ["Offset, Value, $Command"]+
   | ["Offset, Value, $Command, @Comment"]+
 ```
+```
+PatchFv FdFileDir FdFileName ["Offset, Value"]+
+  | ["Offset, Value, @Comment"]+
+  | ["Offset, Value, $Command"]+
+  | ["Offset, Value, $Command, @Comment"]+
+```
 
 #Description
 The **_PatchFv.py_** tool allows the developer to fix up FD images to follow 
the
@@ -102,6 +109,19 @@ ModuleGuid:Offset
   < > Convert absolute address  into an image offset (expr & FSP_SIZE)
 
 ```
+From version 0.60 tool allows to pass flash device file path as Argument 1 and 
+flash device name as Argument 2 and rules for passing offset & value are same
+as explained in the previous sections.
+
+Example usage:
+Argument 1
+```
+ YouPlatformFspBinPkg\
+```
+Argument 2
+```
+ Fsp_Rebased_T
+```
 
 ###Special Commands:
 Special commands must use the **$** symbol as a prefix to the command itself.
-- 
2.39.1.windows.1



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[edk2-devel] [PATCH] IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file directly https://bugzilla.tianocore.org/show_bug.cgi?id=4412

2023-04-14 Thread cbduggap

After shrinking the FSP (FV) component using FMMT, Image size
in FSP info header is not in sync with the FV length in FV header.
This enhancement helps to patch the FSP image size offset with
correct length & can be used to patch any offset directly on
the FSP Component Fd .

Signed-off-by: Duggapu Chinni B 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 14 -
 .../Tools/UserManuals/PatchFvUserManual.md| 20 +++
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index eb130049b5..156c937abe 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -165,6 +165,17 @@ class Symbols:
 if not os.path.isdir(fvDir):
 raise Exception ("'%s' is not a valid directory!" % fvDir)
 
+#
+# if user provided fd name as a input, skip rest of the flow to
+# patch fd directly
+# 
+fdFile =  os.path.join(fvDir,fvNames + ".fd")
+if os.path.exists(fdFile):
+print("Tool identified Fd file as a input to patch '%s'" %fdFile)
+self.fdFile = fdFile
+self.fdSize = os.path.getsize(fdFile)
+return 0
+
 #
 # If the Guid.xref is not existing in fvDir, then raise an exception
 #
@@ -848,8 +859,9 @@ class Symbols:
 #  Print out the usage
 #
 def Usage():
-print ("PatchFv Version 0.50")
+print ("PatchFv Version 0.60")
 print ("Usage: \n\tPatchFv FvBuildDir 
[FvFileBaseNames:]FdFileBaseNameToPatch \"Offset, Value\"")
+print ("\tPatchFv FdFileDir FdFileName \"Offset, Value\"")
 
 def main():
 #
diff --git a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md 
b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
index 5f1031e729..33bba38a3f 100644
--- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
+++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
@@ -1,6 +1,7 @@
 #Name
 **_PatchFv.py_** - The python script that patches the firmware volumes (**FV**)
 with in the flash device (**FD**) file post FSP build.
+From version 0.60, script is capable of patching flash device (**FD**) 
directly.
 
 #Synopsis
 
@@ -10,6 +11,12 @@ PatchFv FvBuildDir [FvFileBaseNames:]FdFileBaseNameToPatch 
["Offset, Value"]+
   | ["Offset, Value, $Command"]+
   | ["Offset, Value, $Command, @Comment"]+
 ```
+```
+PatchFv FdFileDir FdFileName ["Offset, Value"]+
+  | ["Offset, Value, @Comment"]+
+  | ["Offset, Value, $Command"]+
+  | ["Offset, Value, $Command, @Comment"]+
+```
 
 #Description
 The **_PatchFv.py_** tool allows the developer to fix up FD images to follow 
the
@@ -102,6 +109,19 @@ ModuleGuid:Offset
   < > Convert absolute address  into an image offset (expr & FSP_SIZE)
 
 ```
+From version 0.60 tool allows to pass flash device file path as Argument 1 and 
+flash device name as Argument 2 and rules for passing offset & value are same
+as explained in the previous sections.
+
+Example usage:
+Argument 1
+```
+ YouPlatformFspBinPkg\
+```
+Argument 2
+```
+ Fsp_Rebased_T
+```
 
 ###Special Commands:
 Special commands must use the **$** symbol as a prefix to the command itself.
-- 
2.39.1.windows.1



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[edk2-devel] [PATCH] UefiCpuPkg/ResetVector:Add Option to reserve 4K region at 4GB

2022-11-06 Thread cbduggap

From: "Duggapu, Chinni B" 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4140

Some implementations may need to keep the initial Reset code to be
separated out from rest of the code.This request is to add padding at
lower 4K region below 4 GB which will result having only few jmp
instructions and data at that region.

Cc: Ray Ni 
Signed-off-by: Duggapu Chinni B 
---
 UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm 
b/UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm
index 7538192876..fe5bbea803 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm
@@ -21,7 +21,15 @@ ALIGN   16
 ; located just below 0x1 (4GB) in the firmware device.
 ;
 %ifdef ALIGN_TOP_TO_4K_FOR_PAGING
-TIMES (0x1000 - ($ - EndOfPageTables) - 0x20) DB 0
+TIMES (0x1000 - ($ - EndOfPageTables)) DB 0
+;
+; Pad the VTF0 Reset code for Bsp & Ap to 4k aligned block.
+; Some implementations may need to keep the initial Reset code
+; to be separated out from rest of the code.
+; This padding will make sure lower 4K region below 4 GB may
+; only contains few jmp instructions and data.
+;
+TIMES (0x1000 - 0x20) DB 0
 %endif
 
 applicationProcessorEntryPoint:
-- 
2.30.2.windows.1



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Re: [edk2-devel] [PATCH] REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3898 S3 Resume flow may result in executing garbage address.

2022-06-02 Thread cbduggap

HI all,
Please help to review the changes 

Thanks,
Chinni.

-Original Message-
From: devel@edk2.groups.io  On Behalf Of cbduggap
Sent: Friday, May 20, 2022 3:20 PM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Wang, Jian J 
Subject: [edk2-devel] [PATCH] 
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3898 S3 Resume flow may 
result in executing garbage address.

Cc: Ray Ni 
Cc: Jian J Wang 

Signed-off-by: cbduggap 
---
 MdeModulePkg/Core/DxeIplPeim/DxeLoad.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c 
b/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c
index 2c19f1a507..16319e2fd3 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c
@@ -288,6 +288,7 @@ DxeLoadCore (
 EFI_ERROR_CODE | EFI_ERROR_MAJOR, (EFI_SOFTWARE_PEI_MODULE | 
EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND) );+  PeiServicesResetSystem2 
(EfiResetWarm, EFI_SUCCESS, 0, NULL); }  ASSERT_EFI_ERROR (Status);-- 
2.36.0.windows.1



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[edk2-devel] [PATCH] REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3898 S3 Resume flow may result in executing garbage address.

2022-05-20 Thread cbduggap

Cc: Ray Ni 
Cc: Jian J Wang 

Signed-off-by: cbduggap 
---
 MdeModulePkg/Core/DxeIplPeim/DxeLoad.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c 
b/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c
index 2c19f1a507..16319e2fd3 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c
@@ -288,6 +288,7 @@ DxeLoadCore (
 EFI_ERROR_CODE | EFI_ERROR_MAJOR,
 (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND)
 );
+  PeiServicesResetSystem2 (EfiResetWarm, EFI_SUCCESS, 0, NULL);
 }
 
 ASSERT_EFI_ERROR (Status);
-- 
2.36.0.windows.1



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[edk2-devel] [PATCH v5 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

2022-05-17 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
Pass Input parameters using RCX.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Ashraf Ali S 
Signed-off-by: cbduggap 
---
 .../SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm   | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git 
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
 
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
index dbbf63336e..065d80d0e2 100644
--- 
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
+++ 
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
@@ -130,6 +130,9 @@ FspHeaderFound:
   mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
   add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
 
+  ; Pass Fsp T Udp pointer as Input parameter
+  mov rcx, ASM_PFX(FsptUpdDataPtr)
+
   ; Setup the hardcode stack
   mov rsp, TempRamInitStack
 
@@ -167,5 +170,4 @@ FspApiFailed:
 align 10h
 TempRamInitStack:
 DQ  TempRamInitDone
-DQ  ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams
 
-- 
2.36.0.windows.1



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[edk2-devel] [PATCH v5 1/2] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

2022-05-17 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
This API accept one parameter using RCX and this is consumed
in mutiple sub functions.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Ashraf Ali S 
Signed-off-by: cbduggap 
---
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 39 ++-
 .../Include/SaveRestoreSseAvxNasm.inc | 28 +
 2 files changed, 48 insertions(+), 19 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index a9f5f28ed7..7dd89c531a 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -114,7 +114,7 @@ endstruc
 global ASM_PFX(LoadMicrocodeDefault)
 ASM_PFX(LoadMicrocodeDefault):
; Inputs:
-   ;   rsp -> LoadMicrocodeParams pointer
+   ;   rcx -> LoadMicrocodeParams pointer
; Register Usage:
;   rsp  Preserved
;   All others destroyed
@@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
 
cmprsp, 0
jz ParamError
-   moveax, dword [rsp + 8]; Parameter pointer
-   cmpeax, 0
+   cmprcx, 0
jz ParamError
-   movesp, eax
+   movrsp, rcx
 
; skip loading Microcode if the MicrocodeCodeSize is zero
; and report error if size is less than 2k
@@ -144,14 +143,14 @@ ASM_PFX(LoadMicrocodeDefault):
jneParamError
 
; UPD structure is compliant with FSP spec 2.4
-   moveax, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
-   cmpeax, 0
+   movrax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
+   cmprax, 0
jz Exit2
-   cmpeax, 0800h
+   cmprax, 0800h
jl ParamError
 
-   movesi, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
-   cmpesi, 0
+   movrsi, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
+   cmprsi, 0
jnzCheckMainHeader
 
 ParamError:
@@ -256,7 +255,8 @@ CheckAddress:
; UPD structure is compliant with FSP spec 2.4
; Is automatic size detection ?
mov   rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
-   cmp   rax, 0h
+   mov   rcx, 0h
+   cmp   rax, rcx
jzLoadMicrocodeDefault4
 
; Address >= microcode region address + microcode region size?
@@ -321,8 +321,7 @@ ASM_PFX(EstablishStackFsp):
   ;
   ; Save parameter pointer in rdx
   ;
-  mov   rdx, qword [rsp + 8]
-
+  mov   rdx, rcx
   ;
   ; Enable FSP STACK
   ;
@@ -420,7 +419,10 @@ ASM_PFX(TempRamInitApi):
   ;
   ENABLE_SSE
   ENABLE_AVX
-
+  ;
+  ; Save Input Parameter in YMM10
+  ;
+  SAVE_RCX
   ;
   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
   ;
@@ -442,9 +444,8 @@ ASM_PFX(TempRamInitApi):
   ;
   ; Check Parameter
   ;
-  mov   rax, qword [rsp + 8]
-  cmp   rax, 0
-  mov   rax, 08002h
+  cmp   rcx, 0
+  mov   rcx, 08002h
   jzTempRamInitExit
 
   ;
@@ -455,18 +456,18 @@ ASM_PFX(TempRamInitApi):
   jnz   TempRamInitExit
 
   ; Load microcode
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(LoadMicrocodeDefault)
   SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT 0 
in YMM9 (upper 128bits).
   ; @note If return value rax is not 0, microcode did not load, but continue 
and attempt to boot.
 
   ; Call Sec CAR Init
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(SecCarInit)
   cmp   rax, 0
   jnz   TempRamInitExit
 
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(EstablishStackFsp)
   cmp   rax, 0
   jnz   TempRamInitExit
diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc 
b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
index e8bd91669d..38c807a311 100644
--- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
+++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
@@ -177,6 +177,30 @@
 LXMMN   xmm5, %1, 1
 %endmacro
 
+;
+; Upper half of YMM10 to save/restore RCX
+;
+;
+; Save RCX to YMM10[128:191]
+; Modified: XMM5 and YMM10
+;
+
+%macro SAVE_RCX 0
+LYMMN   ymm10, xmm5, 1
+SXMMN   xmm5, 0, rcx
+SYMMN   ymm10, 1, xmm5
+%endmacro
+
+;
+; Restore RCX from YMM10[128:191]
+; Modified: XMM5 and RCX
+;
+
+%macro LOAD_RCX 0
+LYMMN   ymm10, xmm5, 1
+movqrcx,  xmm5
+%endmacro
+
 ;
 ; YMM7[128:191] for calling stack
 ; arg 1:Entry
@@ -231,6 +255,7 @@ NextAddress:
 ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
 ; whether the processor supports SSE instruction.
 ;
+mov r10, rcx
 mov rax, 1
 cpuid
 bt  rdx, 25
@@ -241,6 +266,7 @@ NextAddress:
 ;
 bt  ecx, 19
 jnc SseError
+mov rcx,  r10
 
 ;
 ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
@@ -258,6 +284,7 @@ NextAddress:
 %endma

[edk2-devel] [PATCH v5 0/2] FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

2022-05-17 Thread cbduggap

cbduggap (2):
  IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling
Convention
  IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling
Convention

 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 39 ++-
 .../Include/SaveRestoreSseAvxNasm.inc | 28 +
 .../X64/SecEntry.nasm |  4 +-
 3 files changed, 51 insertions(+), 20 deletions(-)

-- 
2.36.0.windows.1



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[edk2-devel] [PATCH v4 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

2022-05-16 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
Pass Input parameters using RCX.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Ashraf Ali S 
Signed-off-by: cbduggap 
---
 .../SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm   | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git 
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
 
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
index dbbf63336e..065d80d0e2 100644
--- 
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
+++ 
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
@@ -130,6 +130,9 @@ FspHeaderFound:
   mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
   add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
 
+  ; Pass Fsp T Udp pointer as Input parameter
+  mov rcx, ASM_PFX(FsptUpdDataPtr)
+
   ; Setup the hardcode stack
   mov rsp, TempRamInitStack
 
@@ -167,5 +170,4 @@ FspApiFailed:
 align 10h
 TempRamInitStack:
 DQ  TempRamInitDone
-DQ  ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams
 
-- 
2.36.0.windows.1



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[edk2-devel] [PATCH v4 1/2] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

2022-05-16 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
This API accept one parameter using RCX and this is consumed
in mutiple sub functions.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Ashraf Ali S 
Signed-off-by: cbduggap 
---
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 39 ++-
 .../Include/SaveRestoreSseAvxNasm.inc | 28 +
 2 files changed, 48 insertions(+), 19 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index a9f5f28ed7..22dbea1fed 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -114,7 +114,7 @@ endstruc
 global ASM_PFX(LoadMicrocodeDefault)
 ASM_PFX(LoadMicrocodeDefault):
; Inputs:
-   ;   rsp -> LoadMicrocodeParams pointer
+   ;   rcx -> LoadMicrocodeParams pointer
; Register Usage:
;   rsp  Preserved
;   All others destroyed
@@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
 
cmprsp, 0
jz ParamError
-   moveax, dword [rsp + 8]; Parameter pointer
-   cmpeax, 0
+   cmprcx, 0
jz ParamError
-   movesp, eax
+   movrsp, rcx
 
; skip loading Microcode if the MicrocodeCodeSize is zero
; and report error if size is less than 2k
@@ -144,14 +143,14 @@ ASM_PFX(LoadMicrocodeDefault):
jneParamError
 
; UPD structure is compliant with FSP spec 2.4
-   moveax, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
-   cmpeax, 0
+   movrax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
+   cmprax, 0
jz Exit2
-   cmpeax, 0800h
+   cmprax, 0800h
jl ParamError
 
-   movesi, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
-   cmpesi, 0
+   movrsi, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
+   cmprsi, 0
jnzCheckMainHeader
 
 ParamError:
@@ -256,7 +255,8 @@ CheckAddress:
; UPD structure is compliant with FSP spec 2.4
; Is automatic size detection ?
mov   rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
-   cmp   rax, 0h
+   cmp   rcx, 0h
+   cmp   rax, rcx
jzLoadMicrocodeDefault4
 
; Address >= microcode region address + microcode region size?
@@ -321,8 +321,7 @@ ASM_PFX(EstablishStackFsp):
   ;
   ; Save parameter pointer in rdx
   ;
-  mov   rdx, qword [rsp + 8]
-
+  mov   rdx, rcx
   ;
   ; Enable FSP STACK
   ;
@@ -420,7 +419,10 @@ ASM_PFX(TempRamInitApi):
   ;
   ENABLE_SSE
   ENABLE_AVX
-
+  ;
+  ; Save Input Parameter in YMM10
+  ;
+  SAVE_RCX
   ;
   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
   ;
@@ -442,9 +444,8 @@ ASM_PFX(TempRamInitApi):
   ;
   ; Check Parameter
   ;
-  mov   rax, qword [rsp + 8]
-  cmp   rax, 0
-  mov   rax, 08002h
+  cmp   rcx, 0
+  mov   rcx, 08002h
   jzTempRamInitExit
 
   ;
@@ -455,18 +456,18 @@ ASM_PFX(TempRamInitApi):
   jnz   TempRamInitExit
 
   ; Load microcode
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(LoadMicrocodeDefault)
   SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT 0 
in YMM9 (upper 128bits).
   ; @note If return value rax is not 0, microcode did not load, but continue 
and attempt to boot.
 
   ; Call Sec CAR Init
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(SecCarInit)
   cmp   rax, 0
   jnz   TempRamInitExit
 
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(EstablishStackFsp)
   cmp   rax, 0
   jnz   TempRamInitExit
diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc 
b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
index e8bd91669d..38c807a311 100644
--- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
+++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
@@ -177,6 +177,30 @@
 LXMMN   xmm5, %1, 1
 %endmacro
 
+;
+; Upper half of YMM10 to save/restore RCX
+;
+;
+; Save RCX to YMM10[128:191]
+; Modified: XMM5 and YMM10
+;
+
+%macro SAVE_RCX 0
+LYMMN   ymm10, xmm5, 1
+SXMMN   xmm5, 0, rcx
+SYMMN   ymm10, 1, xmm5
+%endmacro
+
+;
+; Restore RCX from YMM10[128:191]
+; Modified: XMM5 and RCX
+;
+
+%macro LOAD_RCX 0
+LYMMN   ymm10, xmm5, 1
+movqrcx,  xmm5
+%endmacro
+
 ;
 ; YMM7[128:191] for calling stack
 ; arg 1:Entry
@@ -231,6 +255,7 @@ NextAddress:
 ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
 ; whether the processor supports SSE instruction.
 ;
+mov r10, rcx
 mov rax, 1
 cpuid
 bt  rdx, 25
@@ -241,6 +266,7 @@ NextAddress:
 ;
 bt  ecx, 19
 jnc SseError
+mov rcx,  r10
 
 ;
 ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
@@ -258,6 +284,7 @@ NextAddress:
 %endma

[edk2-devel] [PATCH v4 0/2] FSP_TEMP_RAM_INIT call must follow X64 Calling

2022-05-16 Thread cbduggap

*** BLURB HERE ***
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
FSP_TEMP_RAM_INIT consume input parameter using RCX.

cbduggap (2):
  IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling
Convention
  IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling
Convention

 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 39 ++-
 .../Include/SaveRestoreSseAvxNasm.inc | 28 +
 .../X64/SecEntry.nasm |  4 +-
 3 files changed, 51 insertions(+), 20 deletions(-)

-- 
2.36.0.windows.1



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Re: [edk2-devel] [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

2022-05-16 Thread cbduggap

HI Chasel,
Yes, we don't need to modify esp for LoadMicrocodeDefault. However, this 
function does couple of MSR Accesses in b/w that would lead to modify RCX 
anyway.
So, if not RSP, we need to use different register to save RCX and consume in 
the whole function. 

That's why I have not changed the usage of RSP to hold the input parameter.  
 


Thanks,
Chinni.

-Original Message-
From: Chiu, Chasel  
Sent: Monday, May 16, 2022 5:38 PM
To: Duggapu, Chinni B ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Zeng, Star 
; S, Ashraf Ali 
Subject: RE: [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 
Calling Convention


Thanks for correcting format and updating patch per feedbacks!
Just one more comment below inline and please also help to include patch of 
IntelFsp2WrapperPkg\Library\SecFspWrapperPlatformSecLibSample\X64\SecEntry.nasm 
for passing API parameter by RCX.
You might want to create a patch series:
[1/2] IntelFsp2Pkg patch
[2/2] IntelFsp2WrapperPkg patch

Thanks,
Chasel

> -Original Message-
> From: Duggapu, Chinni B 
> Sent: Monday, May 16, 2022 6:54 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L 
> ; Zeng, Star ; S, 
> Ashraf Ali 
> Subject: [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow
> X64 Calling Convention
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
> This API accept one parameter using RCX and this is consumed in 
> mutiple sub functions.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Star Zeng 
> Cc: Ashraf Ali S 
> Signed-off-by: cbduggap 
> ---
>  IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 -
>  .../Include/SaveRestoreSseAvxNasm.inc | 28 +++
>  2 files changed, 41 insertions(+), 13 deletions(-)
> 
> diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> index a9f5f28ed7..9504c96b81 100644
> --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> @@ -114,7 +114,7 @@ endstruc
>  global ASM_PFX(LoadMicrocodeDefault)
> ASM_PFX(LoadMicrocodeDefault):; Inputs:-   ;   rsp ->
> LoadMicrocodeParams pointer+   ;   rcx -> LoadMicrocodeParams pointer;
> Register Usage:;   rsp  Preserved;   All others destroyed@@ -130,10
> +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
>  cmprsp, 0jz ParamError-   moveax, dword [rsp + 8];
> Parameter pointer-   cmpeax, 0+   cmpecx, 0jz ParamError-   
> mov
> esp, eax+   movesp, ecx



I think we do not need to modify esp because now esp/rsp only containing return 
address initialized by caller.



 ; skip loading Microcode if the
> MicrocodeCodeSize is zero; and report error if size is less than 2k@@ -
> 321,8 +320,7 @@ ASM_PFX(EstablishStackFsp):
>;   ; Save parameter pointer in rdx   ;-  mov   rdx, qword [rsp + 8]-+ 
>  mov
> rdx, rcx   ;   ; Enable FSP STACK   ;@@ -420,7 +418,10 @@
> ASM_PFX(TempRamInitApi):
>;   ENABLE_SSE   ENABLE_AVX-+  ;+  ; Save Input Parameter in YMM10+  ;+
> SAVE_RCX   ;   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and
> YMM6   ;@@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi):
>;   ; Check Parameter   ;-  mov   rax, qword [rsp + 8]-  cmp   
> rax, 0-
> mov   rax, 08002h+  cmp   rcx, 0+  mov   rcx,
> 08002h   jzTempRamInitExit;@@ -455,18 +455,18
> @@ ASM_PFX(TempRamInitApi):
>jnz   TempRamInitExit; Load microcode-  LOAD_RSP+  LOAD_RCX
> CALL_YMM  ASM_PFX(LoadMicrocodeDefault)   SAVE_UCODE_STATUS
> rax ; Save microcode return status in SLOT 0 in YMM9 (upper
> 128bits).   ; @note If return value rax is not 0, microcode did not load, but
> continue and attempt to boot.; Call Sec CAR Init-  LOAD_RSP+  LOAD_RCX
> CALL_YMM  ASM_PFX(SecCarInit)   cmp   rax, 0   jnz   TempRamInitExit
> -  LOAD_RSP+  LOAD_RCX   CALL_YMM  ASM_PFX(EstablishStackFsp)   cmp
> rax, 0   jnz   TempRamInitExitdiff --git
> a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> index e8bd91669d..38c807a311 100644
> --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> @@ -177,6 +177,30 @@
>  LXMMN   xmm5, %1, 1 %endmacro +;+; Upper half of
> YMM10 to save/restore RCX+;+;+; Save RCX to YMM10[128:191]+;
> Modified: XMM5 and YMM10+;++%macro SAVE_RCX 0+LYMMN
> ymm10, xmm5, 1+SXMMN   xmm5, 0, rcx+SYMMN   ymm10,
> 1, xmm5+%endmacro++;+; Restore RCX from YMM10[128:191]+;
> Modified: XMM5 and RCX+;++%macro LOAD_RCX 0+LYMMN
> ymm10,

[edk2-devel] [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

2022-05-16 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
This API accept one parameter using RCX and this is consumed
in mutiple sub functions.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Ashraf Ali S 
Signed-off-by: cbduggap 
---
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 -
 .../Include/SaveRestoreSseAvxNasm.inc | 28 +++
 2 files changed, 41 insertions(+), 13 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index a9f5f28ed7..9504c96b81 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -114,7 +114,7 @@ endstruc
 global ASM_PFX(LoadMicrocodeDefault)
 ASM_PFX(LoadMicrocodeDefault):
; Inputs:
-   ;   rsp -> LoadMicrocodeParams pointer
+   ;   rcx -> LoadMicrocodeParams pointer
; Register Usage:
;   rsp  Preserved
;   All others destroyed
@@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
 
cmprsp, 0
jz ParamError
-   moveax, dword [rsp + 8]; Parameter pointer
-   cmpeax, 0
+   cmpecx, 0
jz ParamError
-   movesp, eax
+   movesp, ecx
 
; skip loading Microcode if the MicrocodeCodeSize is zero
; and report error if size is less than 2k
@@ -321,8 +320,7 @@ ASM_PFX(EstablishStackFsp):
   ;
   ; Save parameter pointer in rdx
   ;
-  mov   rdx, qword [rsp + 8]
-
+  mov   rdx, rcx
   ;
   ; Enable FSP STACK
   ;
@@ -420,7 +418,10 @@ ASM_PFX(TempRamInitApi):
   ;
   ENABLE_SSE
   ENABLE_AVX
-
+  ;
+  ; Save Input Parameter in YMM10
+  ;
+  SAVE_RCX
   ;
   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
   ;
@@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi):
   ;
   ; Check Parameter
   ;
-  mov   rax, qword [rsp + 8]
-  cmp   rax, 0
-  mov   rax, 08002h
+  cmp   rcx, 0
+  mov   rcx, 08002h
   jzTempRamInitExit
 
   ;
@@ -455,18 +455,18 @@ ASM_PFX(TempRamInitApi):
   jnz   TempRamInitExit
 
   ; Load microcode
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(LoadMicrocodeDefault)
   SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT 0 
in YMM9 (upper 128bits).
   ; @note If return value rax is not 0, microcode did not load, but continue 
and attempt to boot.
 
   ; Call Sec CAR Init
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(SecCarInit)
   cmp   rax, 0
   jnz   TempRamInitExit
 
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(EstablishStackFsp)
   cmp   rax, 0
   jnz   TempRamInitExit
diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc 
b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
index e8bd91669d..38c807a311 100644
--- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
+++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
@@ -177,6 +177,30 @@
 LXMMN   xmm5, %1, 1
 %endmacro
 
+;
+; Upper half of YMM10 to save/restore RCX
+;
+;
+; Save RCX to YMM10[128:191]
+; Modified: XMM5 and YMM10
+;
+
+%macro SAVE_RCX 0
+LYMMN   ymm10, xmm5, 1
+SXMMN   xmm5, 0, rcx
+SYMMN   ymm10, 1, xmm5
+%endmacro
+
+;
+; Restore RCX from YMM10[128:191]
+; Modified: XMM5 and RCX
+;
+
+%macro LOAD_RCX 0
+LYMMN   ymm10, xmm5, 1
+movqrcx,  xmm5
+%endmacro
+
 ;
 ; YMM7[128:191] for calling stack
 ; arg 1:Entry
@@ -231,6 +255,7 @@ NextAddress:
 ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
 ; whether the processor supports SSE instruction.
 ;
+mov r10, rcx
 mov rax, 1
 cpuid
 bt  rdx, 25
@@ -241,6 +266,7 @@ NextAddress:
 ;
 bt  ecx, 19
 jnc SseError
+mov rcx,  r10
 
 ;
 ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
@@ -258,6 +284,7 @@ NextAddress:
 %endmacro
 
 %macro ENABLE_AVX   0
+mov r10, rcx
 mov eax, 1
 cpuid
 and ecx, 1000h
@@ -280,5 +307,6 @@ EnableAvx:
 xgetbv ; result in edx:eax
 or  eax, 0006h ; Set XCR0 bit #1 and bit #2 to enable SSE 
state and AVX state
 xsetbv
+mov rcx, r10
 %endmacro
 
-- 
2.36.0.windows.1



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[edk2-devel] [PATCH v2] FSP_TEMP_RAM_INIT API call must follow X64 Calling Convention

2022-05-12 Thread cbduggap

This API accept one parameter using RCX and this is consumed
in mutiple sub functions.
Signed-off-by: cbduggap 
---
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 21 --
 .../Include/SaveRestoreSseAvxNasm.inc | 28 +++
 2 files changed, 40 insertions(+), 9 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index a9f5f28ed7..cddc41125e 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
 
cmprsp, 0
jz ParamError
-   moveax, dword [rsp + 8]; Parameter pointer
-   cmpeax, 0
+   cmpecx, 0
jz ParamError
-   movesp, eax
+   movesp, ecx
 
; skip loading Microcode if the MicrocodeCodeSize is zero
; and report error if size is less than 2k
@@ -321,8 +320,7 @@ ASM_PFX(EstablishStackFsp):
   ;
   ; Save parameter pointer in rdx
   ;
-  mov   rdx, qword [rsp + 8]
-
+  mov   rdx, rcx
   ;
   ; Enable FSP STACK
   ;
@@ -420,7 +418,10 @@ ASM_PFX(TempRamInitApi):
   ;
   ENABLE_SSE
   ENABLE_AVX
-
+  ;
+  ; Save Input Parameter in YMM10
+  ;
+  SAVE_RCX
   ;
   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
   ;
@@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi):
   ;
   ; Check Parameter
   ;
-  mov   rax, qword [rsp + 8]
-  cmp   rax, 0
-  mov   rax, 08002h
+  cmp   rcx, 0
+  mov   rcx, 08002h
   jzTempRamInitExit
 
   ;
@@ -456,17 +456,20 @@ ASM_PFX(TempRamInitApi):
 
   ; Load microcode
   LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(LoadMicrocodeDefault)
   SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT 0 
in YMM9 (upper 128bits).
   ; @note If return value rax is not 0, microcode did not load, but continue 
and attempt to boot.
 
   ; Call Sec CAR Init
   LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(SecCarInit)
   cmp   rax, 0
   jnz   TempRamInitExit
 
   LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(EstablishStackFsp)
   cmp   rax, 0
   jnz   TempRamInitExit
diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc 
b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
index e8bd91669d..38c807a311 100644
--- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
+++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
@@ -177,6 +177,30 @@
 LXMMN   xmm5, %1, 1
 %endmacro
 
+;
+; Upper half of YMM10 to save/restore RCX
+;
+;
+; Save RCX to YMM10[128:191]
+; Modified: XMM5 and YMM10
+;
+
+%macro SAVE_RCX 0
+LYMMN   ymm10, xmm5, 1
+SXMMN   xmm5, 0, rcx
+SYMMN   ymm10, 1, xmm5
+%endmacro
+
+;
+; Restore RCX from YMM10[128:191]
+; Modified: XMM5 and RCX
+;
+
+%macro LOAD_RCX 0
+LYMMN   ymm10, xmm5, 1
+movqrcx,  xmm5
+%endmacro
+
 ;
 ; YMM7[128:191] for calling stack
 ; arg 1:Entry
@@ -231,6 +255,7 @@ NextAddress:
 ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
 ; whether the processor supports SSE instruction.
 ;
+mov r10, rcx
 mov rax, 1
 cpuid
 bt  rdx, 25
@@ -241,6 +266,7 @@ NextAddress:
 ;
 bt  ecx, 19
 jnc SseError
+mov rcx,  r10
 
 ;
 ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
@@ -258,6 +284,7 @@ NextAddress:
 %endmacro
 
 %macro ENABLE_AVX   0
+mov r10, rcx
 mov eax, 1
 cpuid
 and ecx, 1000h
@@ -280,5 +307,6 @@ EnableAvx:
 xgetbv ; result in edx:eax
 or  eax, 0006h ; Set XCR0 bit #1 and bit #2 to enable SSE 
state and AVX state
 xsetbv
+mov rcx, r10
 %endmacro
 
-- 
2.36.0.windows.1



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[edk2-devel] [PATCH] FSP_TEMP_RAM_INIT API call must follow X64 Calling Convention

2022-05-11 Thread cbduggap

This API accept one parameter using RCX and this is consumed
in mutiple sub functions.
Signed-off-by: cbduggap 
---
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 23 +++---
 .../Include/SaveRestoreSseAvxNasm.inc | 82 +++
 2 files changed, 95 insertions(+), 10 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index a9f5f28ed7..4add0ef3fd 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
 
cmprsp, 0
jz ParamError
-   moveax, dword [rsp + 8]; Parameter pointer
-   cmpeax, 0
+   cmpecx, 0
jz ParamError
-   movesp, eax
+   movesp, ecx
 
; skip loading Microcode if the MicrocodeCodeSize is zero
; and report error if size is less than 2k
@@ -321,8 +320,7 @@ ASM_PFX(EstablishStackFsp):
   ;
   ; Save parameter pointer in rdx
   ;
-  mov   rdx, qword [rsp + 8]
-
+  mov   rdx, rcx
   ;
   ; Enable FSP STACK
   ;
@@ -418,9 +416,12 @@ ASM_PFX(TempRamInitApi):
   ;
   ; Ensure both SSE and AVX are enabled
   ;
-  ENABLE_SSE
+  ENABLE_SSE_X64
   ENABLE_AVX
-
+  ;
+  ; Save Input Parameter in YMM10
+  ;
+  SAVE_RCX
   ;
   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
   ;
@@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi):
   ;
   ; Check Parameter
   ;
-  mov   rax, qword [rsp + 8]
-  cmp   rax, 0
-  mov   rax, 08002h
+  cmp   rcx, 0
+  mov   rcx, 08002h
   jzTempRamInitExit
 
   ;
@@ -456,17 +456,20 @@ ASM_PFX(TempRamInitApi):
 
   ; Load microcode
   LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(LoadMicrocodeDefault)
   SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT 0 
in YMM9 (upper 128bits).
   ; @note If return value rax is not 0, microcode did not load, but continue 
and attempt to boot.
 
   ; Call Sec CAR Init
   LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(SecCarInit)
   cmp   rax, 0
   jnz   TempRamInitExit
 
   LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(EstablishStackFsp)
   cmp   rax, 0
   jnz   TempRamInitExit
diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc 
b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
index e8bd91669d..fb6df2a18b 100644
--- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
+++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
@@ -177,6 +177,30 @@
 LXMMN   xmm5, %1, 1
 %endmacro
 
+;
+; Upper half of YMM10 to save/restore RCX
+;
+;
+; Save RCX to YMM10[128:191]
+; Modified: XMM5 and YMM10
+;
+
+%macro SAVE_RCX 0
+LYMMN   ymm10, xmm5, 1
+SXMMN   xmm5, 0, rcx
+SYMMN   ymm10, 1, xmm5
+%endmacro
+
+;
+; Restore RCX from YMM10[128:191]
+; Modified: XMM5 and RCX
+;
+
+%macro LOAD_RCX 0
+LYMMN   ymm10, xmm5, 1
+movqrcx,  xmm5
+%endmacro
+
 ;
 ; YMM7[128:191] for calling stack
 ; arg 1:Entry
@@ -258,6 +282,7 @@ NextAddress:
 %endmacro
 
 %macro ENABLE_AVX   0
+mov r10, rcx
 mov eax, 1
 cpuid
 and ecx, 1000h
@@ -280,5 +305,62 @@ EnableAvx:
 xgetbv ; result in edx:eax
 or  eax, 0006h ; Set XCR0 bit #1 and bit #2 to enable SSE 
state and AVX state
 xsetbv
+mov rcx, r10
 %endmacro
 
+%macro ENABLE_SSE_X64   0
+;
+; Initialize floating point units
+;
+jmp NextAddress
+align 4
+;
+; Float control word initial value:
+; all exceptions masked, double-precision, round-to-nearest
+;
+FpuControlWord   DW  027Fh
+;
+; Multimedia-extensions control word:
+; all exceptions masked, round-to-nearest, flush to zero for 
masked underflow
+;
+MmxControlWord   DQ  01F80h
+SseError:
+;
+; Processor has to support SSE
+;
+jmp SseError
+NextAddress:
+finit
+mov rax, FpuControlWord
+fldcw [rax]
+
+;
+; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+; whether the processor supports SSE instruction.
+;
+mov r10, rcx
+mov rax, 1
+cpuid
+bt  rdx, 25
+jnc SseError
+
+;
+; SSE 4.1 support
+;
+bt  ecx, 19
+jnc SseError
+mov rcx,  r10
+;
+; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
+;
+mov rax, cr4
+or  rax, 0600h
+mov cr4, rax
+
+;
+; The processor should support SSE instruction and we

[edk2-devel] [PATCH] Bug 3898 - S3 Resume result in executing garbage address

2022-04-24 Thread cbduggap

In Release Build, Trying to execute ppi Function even after
Locate ppi failed.

Signed-off-by: cbduggap 
---
 MdeModulePkg/Core/DxeIplPeim/DxeLoad.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c 
b/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c
index 2c19f1a507..d7f02df5f5 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c
@@ -288,6 +288,7 @@ DxeLoadCore (
 EFI_ERROR_CODE | EFI_ERROR_MAJOR,
 (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND)
 );
+  CpuDeadLoop ();
 }
 
 ASSERT_EFI_ERROR (Status);
-- 
2.36.0.windows.1



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[edk2-devel] [PATCH] Bug 3898 - S3 Resume result in executing garbage address

2022-04-24 Thread cbduggap

From: yes 

In Release Build, Trying to execute ppi Function even after
Locate ppi failed.

Signed-off-by: yes 
---
 MdeModulePkg/Core/DxeIplPeim/DxeLoad.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c 
b/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c
index 2c19f1a507..d7f02df5f5 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c
@@ -288,6 +288,7 @@ DxeLoadCore (
 EFI_ERROR_CODE | EFI_ERROR_MAJOR,
 (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND)
 );
+  CpuDeadLoop ();
 }
 
 ASSERT_EFI_ERROR (Status);
-- 
2.26.2.windows.1



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[edk2-devel] [Patch V1 1/1] \Silicon\Intel\Tools\FitGen: Add extra parameter to the Fit Gen Tool to input the Higher Flash Address

2020-10-05 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2981

Add extra parameter to the Fit Gen Tool to input the Higher Address.
Default Address should be 4GB and if some one inputs new address,
tool must consume that address instead of Default address (4GB).

Signed-off-by: cbduggap 
---
 Silicon/Intel/Tools/FitGen/FitGen.c | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c 
b/Silicon/Intel/Tools/FitGen/FitGen.c
index c4006e69c8..c17a0fabc0 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -209,10 +209,12 @@ typedef struct {
 #define DEFAULT_FIT_TABLE_POINTER_OFFSET  0x40
 #define DEFAULT_FIT_ENTRY_VERSION 0x0100
 
+#define HIGHER_FLASH_ADDRESS  (gFitTableContext.HigherAddressRemapValue)
+
 #define MEMORY_TO_FLASH(FileBuffer, FvBuffer, FvSize)  \
- (UINTN)(0x1 - ((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(UINTN)(FileBuffer)))
+ (UINTN)(HIGHER_FLASH_ADDRESS - ((UINTN)(FvBuffer) + 
(UINTN)(FvSize) - (UINTN)(FileBuffer)))
 #define FLASH_TO_MEMORY(Address, FvBuffer, FvSize)  \
- (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(0x1 - (UINTN)(Address)))
+ (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(HIGHER_FLASH_ADDRESS - (UINTN)(Address)))
 
 #define FIT_TABLE_TYPE_HEADER 0
 #define FIT_TABLE_TYPE_MICROCODE  1
@@ -268,6 +270,7 @@ typedef struct {
   UINT32 MicrocodeVersion;
   FIT_TABLE_CONTEXT_ENTRYOptionalModule[MAX_OPTIONAL_ENTRY];
   FIT_TABLE_CONTEXT_ENTRYPortModule[MAX_PORT_ENTRY];
+  UINT64  HigherAddressRemapValue;
 } FIT_TABLE_CONTEXT;
 
 FIT_TABLE_CONTEXT   gFitTableContext = {0};
@@ -330,6 +333,7 @@ Returns:
   "\t[-F ] [-F ] [-V 
]\n"
   "\t[-NA]\n"
   "\t[-A ]\n"
+   "\t[-REMAP \n"
   "\t[-CLEAR]\n"
   "\t[-L  ]\n"
   "\t[-I ]\n"
@@ -986,6 +990,21 @@ Returns:
 Index += 2;
   }
 
+  if ((Index >= argc) ||
+  ((strcmp (argv[Index], "-REMAP") == 0) ||
+   (strcmp (argv[Index], "-remap") == 0)) ) {
+//
+// by pass
+//
+gFitTableContext.HigherAddressRemapValue = xtoi (argv[Index + 1]);
+Index += 2;
+  } else {
+//
+// no remapping
+//
+gFitTableContext.HigherAddressRemapValue = 0x1;
+  }
+  printf ("Higher Address Value : 0x%llx\n", 
gFitTableContext.HigherAddressRemapValue);
   //
   // 0.4 Clear FIT table related memory
   //
-- 
2.26.2.windows.1



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[edk2-devel] [Patch V4 1/1] Tools\FitGen: Add extra parameter to input the Higher Flash Address

2020-10-05 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2981

Add extra parameter to the Fit Gen Tool to input the Higher Address.
Default Address should be 4GB and if some one inputs new address,
tool must consume that address instead of Default address (4GB).

Signed-off-by: cbduggap 
Cc: Bob Feng 
Cc: Liming Gao 

Signed-off-by: cbduggap 
---
 Silicon/Intel/Tools/FitGen/FitGen.c | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c 
b/Silicon/Intel/Tools/FitGen/FitGen.c
index c4006e69c8..cb60a3c324 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -209,10 +209,12 @@ typedef struct {
 #define DEFAULT_FIT_TABLE_POINTER_OFFSET  0x40
 #define DEFAULT_FIT_ENTRY_VERSION 0x0100
 
+#define TOP_FLASH_ADDRESS  (gFitTableContext.TopFlashAddressRemapValue)
+
 #define MEMORY_TO_FLASH(FileBuffer, FvBuffer, FvSize)  \
- (UINTN)(0x1 - ((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(UINTN)(FileBuffer)))
+ (UINTN)(TOP_FLASH_ADDRESS - ((UINTN)(FvBuffer) + 
(UINTN)(FvSize) - (UINTN)(FileBuffer)))
 #define FLASH_TO_MEMORY(Address, FvBuffer, FvSize)  \
- (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(0x1 - (UINTN)(Address)))
+ (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(TOP_FLASH_ADDRESS - (UINTN)(Address)))
 
 #define FIT_TABLE_TYPE_HEADER 0
 #define FIT_TABLE_TYPE_MICROCODE  1
@@ -268,6 +270,7 @@ typedef struct {
   UINT32 MicrocodeVersion;
   FIT_TABLE_CONTEXT_ENTRYOptionalModule[MAX_OPTIONAL_ENTRY];
   FIT_TABLE_CONTEXT_ENTRYPortModule[MAX_PORT_ENTRY];
+  UINT64 TopFlashAddressRemapValue;
 } FIT_TABLE_CONTEXT;
 
 FIT_TABLE_CONTEXT   gFitTableContext = {0};
@@ -330,6 +333,7 @@ Returns:
   "\t[-F ] [-F ] [-V 
]\n"
   "\t[-NA]\n"
   "\t[-A ]\n"
+   "\t[-REMAP \n"
   "\t[-CLEAR]\n"
   "\t[-L  ]\n"
   "\t[-I ]\n"
@@ -986,6 +990,21 @@ Returns:
 Index += 2;
   }
 
+  if ((Index >= argc) ||
+  ((strcmp (argv[Index], "-REMAP") == 0) ||
+   (strcmp (argv[Index], "-remap") == 0)) ) {
+//
+// by pass
+//
+gFitTableContext.TopFlashAddressRemapValue = xtoi (argv[Index + 1]);
+Index += 2;
+  } else {
+//
+// no remapping
+//
+gFitTableContext.TopFlashAddressRemapValue = 0x1;
+  }
+  printf ("Top Flash Address Value : 0x%llx\n", 
gFitTableContext.TopFlashAddressRemapValue);
   //
   // 0.4 Clear FIT table related memory
   //
-- 
2.26.2.windows.1



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[edk2-devel] [Patch V5 1/1] Tools\FitGen: Add extra parameter to input the Top Flash Address

2020-10-05 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2981

Add extra parameter to the Fit Gen Tool to input the Top Flash Address.
Default Address should be 4GB and if some one inputs new address,
tool must consume that address instead of Default address (4GB).

Signed-off-by: cbduggap 
Cc: Bob Feng 
Cc: Liming Gao 

Signed-off-by: cbduggap 
---
 Silicon/Intel/Tools/FitGen/FitGen.c | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c 
b/Silicon/Intel/Tools/FitGen/FitGen.c
index c4006e69c8..cb60a3c324 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -209,10 +209,12 @@ typedef struct {
 #define DEFAULT_FIT_TABLE_POINTER_OFFSET  0x40
 #define DEFAULT_FIT_ENTRY_VERSION 0x0100
 
+#define TOP_FLASH_ADDRESS  (gFitTableContext.TopFlashAddressRemapValue)
+
 #define MEMORY_TO_FLASH(FileBuffer, FvBuffer, FvSize)  \
- (UINTN)(0x1 - ((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(UINTN)(FileBuffer)))
+ (UINTN)(TOP_FLASH_ADDRESS - ((UINTN)(FvBuffer) + 
(UINTN)(FvSize) - (UINTN)(FileBuffer)))
 #define FLASH_TO_MEMORY(Address, FvBuffer, FvSize)  \
- (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(0x1 - (UINTN)(Address)))
+ (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(TOP_FLASH_ADDRESS - (UINTN)(Address)))
 
 #define FIT_TABLE_TYPE_HEADER 0
 #define FIT_TABLE_TYPE_MICROCODE  1
@@ -268,6 +270,7 @@ typedef struct {
   UINT32 MicrocodeVersion;
   FIT_TABLE_CONTEXT_ENTRYOptionalModule[MAX_OPTIONAL_ENTRY];
   FIT_TABLE_CONTEXT_ENTRYPortModule[MAX_PORT_ENTRY];
+  UINT64 TopFlashAddressRemapValue;
 } FIT_TABLE_CONTEXT;
 
 FIT_TABLE_CONTEXT   gFitTableContext = {0};
@@ -330,6 +333,7 @@ Returns:
   "\t[-F ] [-F ] [-V 
]\n"
   "\t[-NA]\n"
   "\t[-A ]\n"
+   "\t[-REMAP \n"
   "\t[-CLEAR]\n"
   "\t[-L  ]\n"
   "\t[-I ]\n"
@@ -986,6 +990,21 @@ Returns:
 Index += 2;
   }
 
+  if ((Index >= argc) ||
+  ((strcmp (argv[Index], "-REMAP") == 0) ||
+   (strcmp (argv[Index], "-remap") == 0)) ) {
+//
+// by pass
+//
+gFitTableContext.TopFlashAddressRemapValue = xtoi (argv[Index + 1]);
+Index += 2;
+  } else {
+//
+// no remapping
+//
+gFitTableContext.TopFlashAddressRemapValue = 0x1;
+  }
+  printf ("Top Flash Address Value : 0x%llx\n", 
gFitTableContext.TopFlashAddressRemapValue);
   //
   // 0.4 Clear FIT table related memory
   //
-- 
2.26.2.windows.1



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[edk2-devel] [Patch V1 1/1] \Silicon\Intel\Tools\FitGen: Add extra parameter to the Fit Gen Tool to input the Higher Flash Address

2020-09-29 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2981

Add extra parameter to the Fit Gen Tool to input the Higher Address.
Default Address should be 4GB and if some one inputs new address,
tool must consume that address instead of Default address (4GB).

Signed-off-by: cbduggap 
---
 Silicon/Intel/Tools/FitGen/FitGen.c | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c 
b/Silicon/Intel/Tools/FitGen/FitGen.c
index c4006e69c8..c17a0fabc0 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -209,10 +209,12 @@ typedef struct {
 #define DEFAULT_FIT_TABLE_POINTER_OFFSET  0x40
 #define DEFAULT_FIT_ENTRY_VERSION 0x0100
 
+#define HIGHER_FLASH_ADDRESS  (gFitTableContext.HigherAddressRemapValue)
+
 #define MEMORY_TO_FLASH(FileBuffer, FvBuffer, FvSize)  \
- (UINTN)(0x1 - ((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(UINTN)(FileBuffer)))
+ (UINTN)(HIGHER_FLASH_ADDRESS - ((UINTN)(FvBuffer) + 
(UINTN)(FvSize) - (UINTN)(FileBuffer)))
 #define FLASH_TO_MEMORY(Address, FvBuffer, FvSize)  \
- (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(0x1 - (UINTN)(Address)))
+ (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(HIGHER_FLASH_ADDRESS - (UINTN)(Address)))
 
 #define FIT_TABLE_TYPE_HEADER 0
 #define FIT_TABLE_TYPE_MICROCODE  1
@@ -268,6 +270,7 @@ typedef struct {
   UINT32 MicrocodeVersion;
   FIT_TABLE_CONTEXT_ENTRYOptionalModule[MAX_OPTIONAL_ENTRY];
   FIT_TABLE_CONTEXT_ENTRYPortModule[MAX_PORT_ENTRY];
+  UINT64  HigherAddressRemapValue;
 } FIT_TABLE_CONTEXT;
 
 FIT_TABLE_CONTEXT   gFitTableContext = {0};
@@ -330,6 +333,7 @@ Returns:
   "\t[-F ] [-F ] [-V 
]\n"
   "\t[-NA]\n"
   "\t[-A ]\n"
+   "\t[-REMAP \n"
   "\t[-CLEAR]\n"
   "\t[-L  ]\n"
   "\t[-I ]\n"
@@ -986,6 +990,21 @@ Returns:
 Index += 2;
   }
 
+  if ((Index >= argc) ||
+  ((strcmp (argv[Index], "-REMAP") == 0) ||
+   (strcmp (argv[Index], "-remap") == 0)) ) {
+//
+// by pass
+//
+gFitTableContext.HigherAddressRemapValue = xtoi (argv[Index + 1]);
+Index += 2;
+  } else {
+//
+// no remapping
+//
+gFitTableContext.HigherAddressRemapValue = 0x1;
+  }
+  printf ("Higher Address Value : 0x%llx\n", 
gFitTableContext.HigherAddressRemapValue);
   //
   // 0.4 Clear FIT table related memory
   //
-- 
2.26.2.windows.1



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[edk2-devel] [Patch V4 1/1] Tools\FitGen: Add extra parameter to input the Higher Flash Address

2020-09-29 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2981

Add extra parameter to the Fit Gen Tool to input the Higher Address.
Default Address should be 4GB and if some one inputs new address,
tool must consume that address instead of Default address (4GB).

Signed-off-by: cbduggap 
Cc: Bob Feng 
Cc: Liming Gao 

Signed-off-by: cbduggap 
---
 Silicon/Intel/Tools/FitGen/FitGen.c | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c 
b/Silicon/Intel/Tools/FitGen/FitGen.c
index c4006e69c8..cb60a3c324 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -209,10 +209,12 @@ typedef struct {
 #define DEFAULT_FIT_TABLE_POINTER_OFFSET  0x40
 #define DEFAULT_FIT_ENTRY_VERSION 0x0100
 
+#define TOP_FLASH_ADDRESS  (gFitTableContext.TopFlashAddressRemapValue)
+
 #define MEMORY_TO_FLASH(FileBuffer, FvBuffer, FvSize)  \
- (UINTN)(0x1 - ((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(UINTN)(FileBuffer)))
+ (UINTN)(TOP_FLASH_ADDRESS - ((UINTN)(FvBuffer) + 
(UINTN)(FvSize) - (UINTN)(FileBuffer)))
 #define FLASH_TO_MEMORY(Address, FvBuffer, FvSize)  \
- (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(0x1 - (UINTN)(Address)))
+ (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(TOP_FLASH_ADDRESS - (UINTN)(Address)))
 
 #define FIT_TABLE_TYPE_HEADER 0
 #define FIT_TABLE_TYPE_MICROCODE  1
@@ -268,6 +270,7 @@ typedef struct {
   UINT32 MicrocodeVersion;
   FIT_TABLE_CONTEXT_ENTRYOptionalModule[MAX_OPTIONAL_ENTRY];
   FIT_TABLE_CONTEXT_ENTRYPortModule[MAX_PORT_ENTRY];
+  UINT64 TopFlashAddressRemapValue;
 } FIT_TABLE_CONTEXT;
 
 FIT_TABLE_CONTEXT   gFitTableContext = {0};
@@ -330,6 +333,7 @@ Returns:
   "\t[-F ] [-F ] [-V 
]\n"
   "\t[-NA]\n"
   "\t[-A ]\n"
+   "\t[-REMAP \n"
   "\t[-CLEAR]\n"
   "\t[-L  ]\n"
   "\t[-I ]\n"
@@ -986,6 +990,21 @@ Returns:
 Index += 2;
   }
 
+  if ((Index >= argc) ||
+  ((strcmp (argv[Index], "-REMAP") == 0) ||
+   (strcmp (argv[Index], "-remap") == 0)) ) {
+//
+// by pass
+//
+gFitTableContext.TopFlashAddressRemapValue = xtoi (argv[Index + 1]);
+Index += 2;
+  } else {
+//
+// no remapping
+//
+gFitTableContext.TopFlashAddressRemapValue = 0x1;
+  }
+  printf ("Top Flash Address Value : 0x%llx\n", 
gFitTableContext.TopFlashAddressRemapValue);
   //
   // 0.4 Clear FIT table related memory
   //
-- 
2.26.2.windows.1



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[edk2-devel] [Patch V1 1/1] \Silicon\Intel\Tools\FitGen: Add extra parameter to the Fit Gen Tool to input the Higher Flash Address

2020-09-29 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2981

Add extra parameter to the Fit Gen Tool to input the Higher Address.
Default Address should be 4GB and if some one inputs new address,
tool must consume that address instead of Default address (4GB).

Signed-off-by: cbduggap 
---
 Silicon/Intel/Tools/FitGen/FitGen.c | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c 
b/Silicon/Intel/Tools/FitGen/FitGen.c
index c4006e69c8..c17a0fabc0 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -209,10 +209,12 @@ typedef struct {
 #define DEFAULT_FIT_TABLE_POINTER_OFFSET  0x40
 #define DEFAULT_FIT_ENTRY_VERSION 0x0100
 
+#define HIGHER_FLASH_ADDRESS  (gFitTableContext.HigherAddressRemapValue)
+
 #define MEMORY_TO_FLASH(FileBuffer, FvBuffer, FvSize)  \
- (UINTN)(0x1 - ((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(UINTN)(FileBuffer)))
+ (UINTN)(HIGHER_FLASH_ADDRESS - ((UINTN)(FvBuffer) + 
(UINTN)(FvSize) - (UINTN)(FileBuffer)))
 #define FLASH_TO_MEMORY(Address, FvBuffer, FvSize)  \
- (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(0x1 - (UINTN)(Address)))
+ (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(HIGHER_FLASH_ADDRESS - (UINTN)(Address)))
 
 #define FIT_TABLE_TYPE_HEADER 0
 #define FIT_TABLE_TYPE_MICROCODE  1
@@ -268,6 +270,7 @@ typedef struct {
   UINT32 MicrocodeVersion;
   FIT_TABLE_CONTEXT_ENTRYOptionalModule[MAX_OPTIONAL_ENTRY];
   FIT_TABLE_CONTEXT_ENTRYPortModule[MAX_PORT_ENTRY];
+  UINT64  HigherAddressRemapValue;
 } FIT_TABLE_CONTEXT;
 
 FIT_TABLE_CONTEXT   gFitTableContext = {0};
@@ -330,6 +333,7 @@ Returns:
   "\t[-F ] [-F ] [-V 
]\n"
   "\t[-NA]\n"
   "\t[-A ]\n"
+   "\t[-REMAP \n"
   "\t[-CLEAR]\n"
   "\t[-L  ]\n"
   "\t[-I ]\n"
@@ -986,6 +990,21 @@ Returns:
 Index += 2;
   }
 
+  if ((Index >= argc) ||
+  ((strcmp (argv[Index], "-REMAP") == 0) ||
+   (strcmp (argv[Index], "-remap") == 0)) ) {
+//
+// by pass
+//
+gFitTableContext.HigherAddressRemapValue = xtoi (argv[Index + 1]);
+Index += 2;
+  } else {
+//
+// no remapping
+//
+gFitTableContext.HigherAddressRemapValue = 0x1;
+  }
+  printf ("Higher Address Value : 0x%llx\n", 
gFitTableContext.HigherAddressRemapValue);
   //
   // 0.4 Clear FIT table related memory
   //
-- 
2.26.2.windows.1



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[edk2-devel] [Patch V3 1/1] Tools\FitGen: Add extra parameter to input the Higher Flash Address

2020-09-29 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2981

Add extra parameter to the Fit Gen Tool to input the Higher Address.
Default Address should be 4GB and if some one inputs new address,
tool must consume that address instead of Default address (4GB).

Signed-off-by: cbduggap 
Cc: Bob Feng 
Cc: Liming Gao 

Signed-off-by: cbduggap 
---
 Silicon/Intel/Tools/FitGen/FitGen.c | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c 
b/Silicon/Intel/Tools/FitGen/FitGen.c
index c4006e69c8..3c663080c3 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -209,10 +209,12 @@ typedef struct {
 #define DEFAULT_FIT_TABLE_POINTER_OFFSET  0x40
 #define DEFAULT_FIT_ENTRY_VERSION 0x0100
 
+#define TOP_FLASH_ADDRESS  (gFitTableContext.TopFlashAddressRemapValue)
+
 #define MEMORY_TO_FLASH(FileBuffer, FvBuffer, FvSize)  \
- (UINTN)(0x1 - ((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(UINTN)(FileBuffer)))
+ (UINTN)(TOP_FLASH_ADDRESS - ((UINTN)(FvBuffer) + 
(UINTN)(FvSize) - (UINTN)(FileBuffer)))
 #define FLASH_TO_MEMORY(Address, FvBuffer, FvSize)  \
- (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(0x1 - (UINTN)(Address)))
+ (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(TOP_FLASH_ADDRESS - (UINTN)(Address)))
 
 #define FIT_TABLE_TYPE_HEADER 0
 #define FIT_TABLE_TYPE_MICROCODE  1
@@ -268,6 +270,7 @@ typedef struct {
   UINT32 MicrocodeVersion;
   FIT_TABLE_CONTEXT_ENTRYOptionalModule[MAX_OPTIONAL_ENTRY];
   FIT_TABLE_CONTEXT_ENTRYPortModule[MAX_PORT_ENTRY];
+  UINT64 TopFlashAddressRemapValue;
 } FIT_TABLE_CONTEXT;
 
 FIT_TABLE_CONTEXT   gFitTableContext = {0};
@@ -330,6 +333,7 @@ Returns:
   "\t[-F ] [-F ] [-V 
]\n"
   "\t[-NA]\n"
   "\t[-A ]\n"
+   "\t[-REMAP \n"
   "\t[-CLEAR]\n"
   "\t[-L  ]\n"
   "\t[-I ]\n"
@@ -986,6 +990,21 @@ Returns:
 Index += 2;
   }
 
+  if ((Index >= argc) ||
+  ((strcmp (argv[Index], "-REMAP") == 0) ||
+   (strcmp (argv[Index], "-remap") == 0)) ) {
+//
+// by pass
+//
+gFitTableContext.HigherAddressRemapValue = xtoi (argv[Index + 1]);
+Index += 2;
+  } else {
+//
+// no remapping
+//
+gFitTableContext.HigherAddressRemapValue = 0x1;
+  }
+  printf ("Higher Address Value : 0x%llx\n", 
gFitTableContext.HigherAddressRemapValue);
   //
   // 0.4 Clear FIT table related memory
   //
-- 
2.26.2.windows.1



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Re: [edk2-devel] 回复: [edk2-devel] [Patch V2 1/1] Tools\FitGen: Add extra parameter to input the Higher Flash Address

2020-09-29 Thread cbduggap

Use case :

For Boot from Block device feature, As Block device is not Memory mapped, we 
need some agent to load the Initial firmware to Host memory. CSE takes care of 
it by mapping CSE internal SRAM to host memory of 4GB to 4 GB – 256 KB.

*Boot from Block Configuration Host Memory Map :*

Current Implementation

Future Recommendation

POC on Current Implementation

CSE Mapped host memory

4GB to 4GB – 256 KB

4GB to 4GB – 512KB

4GB to 4GB – 256 KB

BIOS Flash Map Definition

4GB to 4GB – 256 KB à Empty Firmware volume ( *hole in flash map* )

4GB – 256KB to 4GB – 10 MB ( BIOS Firmware Volumes)

4GB to 4GB – 512KB à Empty Firmware volume ( *hole in flash map* )

4GB – 512 KB to 4GB – 10 MB ( BIOS Firmware Volumes)

*Eliminate the Empty Firmware volume /hole in flash memory.*

*(by shifting flash range by 256 KB as shown below)*

Flash Map range

4GB to 4GB – 10 MB

For 10 MB BIOS.

4GB to 4GB – 10 MB

For 10 MB BIOS.

4GB *– 256 KB* to 4GB – 10 MB *– 256 KB*

For 10 MB BIOS

Below is the usage of this addition.
@if "%BFX_BUILD%" == "TRUE" (
%WORKSPACE_PLATFORM%\%PLATFORM_FULL_PACKAGE%\Tools\FitGen_Split_Boot\FitGen.exe 
^
-D ^
%BUILD_DIR%\FV\ClientBios.fd ^
%BUILD_DIR%\FV\ClientBios.fd ^
-F 0x40 ^
-NA ^
*-REMAP 0xFFF8 ^*
-L %SLOT_SIZE% %MICROCODE_ARRAY_FFS_GUID% ^
-I %BIOS_INFO_GUID% ^
%STARTUP_AC_PARA% ^
-O 0x0C RESERVE 0x600 ^
-O 0x0B RESERVE 0x400 ^
-P 0xA 0x70 0x71 0x1 0x4 0x2a
)
%STARTUP_AC_PARA% ^
-O 0x0C RESERVE 0x600 ^
-O 0x0B RESERVE 0x400 ^
-P 0xA 0x70 0x71 0x1 0x4 0x2a


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[edk2-devel] [Patch V2 1/1] Tools\FitGen: Add extra parameter to input the Higher Flash Address

2020-09-22 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2981

Add extra parameter to the Fit Gen Tool to input the Higher Address.
Default Address should be 4GB and if some one inputs new address,
tool must consume that address instead of Default address (4GB).

Signed-off-by: cbduggap 
Cc: Bob Feng 
Cc: Liming Gao 
---
 Silicon/Intel/Tools/FitGen/FitGen.c | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c 
b/Silicon/Intel/Tools/FitGen/FitGen.c
index c4006e69c8..c17a0fabc0 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -209,10 +209,12 @@ typedef struct {
 #define DEFAULT_FIT_TABLE_POINTER_OFFSET  0x40
 #define DEFAULT_FIT_ENTRY_VERSION 0x0100
 
+#define HIGHER_FLASH_ADDRESS  (gFitTableContext.HigherAddressRemapValue)
+
 #define MEMORY_TO_FLASH(FileBuffer, FvBuffer, FvSize)  \
- (UINTN)(0x1 - ((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(UINTN)(FileBuffer)))
+ (UINTN)(HIGHER_FLASH_ADDRESS - ((UINTN)(FvBuffer) + 
(UINTN)(FvSize) - (UINTN)(FileBuffer)))
 #define FLASH_TO_MEMORY(Address, FvBuffer, FvSize)  \
- (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(0x1 - (UINTN)(Address)))
+ (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(HIGHER_FLASH_ADDRESS - (UINTN)(Address)))
 
 #define FIT_TABLE_TYPE_HEADER 0
 #define FIT_TABLE_TYPE_MICROCODE  1
@@ -268,6 +270,7 @@ typedef struct {
   UINT32 MicrocodeVersion;
   FIT_TABLE_CONTEXT_ENTRYOptionalModule[MAX_OPTIONAL_ENTRY];
   FIT_TABLE_CONTEXT_ENTRYPortModule[MAX_PORT_ENTRY];
+  UINT64  HigherAddressRemapValue;
 } FIT_TABLE_CONTEXT;
 
 FIT_TABLE_CONTEXT   gFitTableContext = {0};
@@ -330,6 +333,7 @@ Returns:
   "\t[-F ] [-F ] [-V 
]\n"
   "\t[-NA]\n"
   "\t[-A ]\n"
+   "\t[-REMAP \n"
   "\t[-CLEAR]\n"
   "\t[-L  ]\n"
   "\t[-I ]\n"
@@ -986,6 +990,21 @@ Returns:
 Index += 2;
   }
 
+  if ((Index >= argc) ||
+  ((strcmp (argv[Index], "-REMAP") == 0) ||
+   (strcmp (argv[Index], "-remap") == 0)) ) {
+//
+// by pass
+//
+gFitTableContext.HigherAddressRemapValue = xtoi (argv[Index + 1]);
+Index += 2;
+  } else {
+//
+// no remapping
+//
+gFitTableContext.HigherAddressRemapValue = 0x1;
+  }
+  printf ("Higher Address Value : 0x%llx\n", 
gFitTableContext.HigherAddressRemapValue);
   //
   // 0.4 Clear FIT table related memory
   //
-- 
2.26.2.windows.1



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[edk2-devel] [Patch V1 1/1] \Silicon\Intel\Tools\FitGen: Add extra parameter to the Fit Gen Tool to input the Higher Flash Address

2020-09-22 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2981

Add extra parameter to the Fit Gen Tool to input the Higher Address.
Default Address should be 4GB and if some one inputs new address,
tool must consume that address instead of Default address (4GB).

Signed-off-by: cbduggap 
---
 Silicon/Intel/Tools/FitGen/FitGen.c | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c 
b/Silicon/Intel/Tools/FitGen/FitGen.c
index c4006e69c8..c17a0fabc0 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -209,10 +209,12 @@ typedef struct {
 #define DEFAULT_FIT_TABLE_POINTER_OFFSET  0x40
 #define DEFAULT_FIT_ENTRY_VERSION 0x0100
 
+#define HIGHER_FLASH_ADDRESS  (gFitTableContext.HigherAddressRemapValue)
+
 #define MEMORY_TO_FLASH(FileBuffer, FvBuffer, FvSize)  \
- (UINTN)(0x1 - ((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(UINTN)(FileBuffer)))
+ (UINTN)(HIGHER_FLASH_ADDRESS - ((UINTN)(FvBuffer) + 
(UINTN)(FvSize) - (UINTN)(FileBuffer)))
 #define FLASH_TO_MEMORY(Address, FvBuffer, FvSize)  \
- (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(0x1 - (UINTN)(Address)))
+ (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(HIGHER_FLASH_ADDRESS - (UINTN)(Address)))
 
 #define FIT_TABLE_TYPE_HEADER 0
 #define FIT_TABLE_TYPE_MICROCODE  1
@@ -268,6 +270,7 @@ typedef struct {
   UINT32 MicrocodeVersion;
   FIT_TABLE_CONTEXT_ENTRYOptionalModule[MAX_OPTIONAL_ENTRY];
   FIT_TABLE_CONTEXT_ENTRYPortModule[MAX_PORT_ENTRY];
+  UINT64  HigherAddressRemapValue;
 } FIT_TABLE_CONTEXT;
 
 FIT_TABLE_CONTEXT   gFitTableContext = {0};
@@ -330,6 +333,7 @@ Returns:
   "\t[-F ] [-F ] [-V 
]\n"
   "\t[-NA]\n"
   "\t[-A ]\n"
+   "\t[-REMAP \n"
   "\t[-CLEAR]\n"
   "\t[-L  ]\n"
   "\t[-I ]\n"
@@ -986,6 +990,21 @@ Returns:
 Index += 2;
   }
 
+  if ((Index >= argc) ||
+  ((strcmp (argv[Index], "-REMAP") == 0) ||
+   (strcmp (argv[Index], "-remap") == 0)) ) {
+//
+// by pass
+//
+gFitTableContext.HigherAddressRemapValue = xtoi (argv[Index + 1]);
+Index += 2;
+  } else {
+//
+// no remapping
+//
+gFitTableContext.HigherAddressRemapValue = 0x1;
+  }
+  printf ("Higher Address Value : 0x%llx\n", 
gFitTableContext.HigherAddressRemapValue);
   //
   // 0.4 Clear FIT table related memory
   //
-- 
2.26.2.windows.1



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[edk2-devel] [Patch V1 1/1] \Silicon\Intel\Tools\FitGen: Add extra parameter to the Fit Gen Tool to input the Higher Flash Address

2020-09-22 Thread cbduggap

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2981

Add extra parameter to the Fit Gen Tool to input the Higher Address.
Default Address should be 4GB and if some one inputs new address,
tool must consume that address instead of Default address (4GB).

Signed-off-by: cbduggap 
---
 Silicon/Intel/Tools/FitGen/FitGen.c | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c 
b/Silicon/Intel/Tools/FitGen/FitGen.c
index c4006e69c8..c17a0fabc0 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -209,10 +209,12 @@ typedef struct {
 #define DEFAULT_FIT_TABLE_POINTER_OFFSET  0x40
 #define DEFAULT_FIT_ENTRY_VERSION 0x0100
 
+#define HIGHER_FLASH_ADDRESS  (gFitTableContext.HigherAddressRemapValue)
+
 #define MEMORY_TO_FLASH(FileBuffer, FvBuffer, FvSize)  \
- (UINTN)(0x1 - ((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(UINTN)(FileBuffer)))
+ (UINTN)(HIGHER_FLASH_ADDRESS - ((UINTN)(FvBuffer) + 
(UINTN)(FvSize) - (UINTN)(FileBuffer)))
 #define FLASH_TO_MEMORY(Address, FvBuffer, FvSize)  \
- (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(0x1 - (UINTN)(Address)))
+ (VOID *)(UINTN)((UINTN)(FvBuffer) + (UINTN)(FvSize) - 
(HIGHER_FLASH_ADDRESS - (UINTN)(Address)))
 
 #define FIT_TABLE_TYPE_HEADER 0
 #define FIT_TABLE_TYPE_MICROCODE  1
@@ -268,6 +270,7 @@ typedef struct {
   UINT32 MicrocodeVersion;
   FIT_TABLE_CONTEXT_ENTRYOptionalModule[MAX_OPTIONAL_ENTRY];
   FIT_TABLE_CONTEXT_ENTRYPortModule[MAX_PORT_ENTRY];
+  UINT64  HigherAddressRemapValue;
 } FIT_TABLE_CONTEXT;
 
 FIT_TABLE_CONTEXT   gFitTableContext = {0};
@@ -330,6 +333,7 @@ Returns:
   "\t[-F ] [-F ] [-V 
]\n"
   "\t[-NA]\n"
   "\t[-A ]\n"
+   "\t[-REMAP \n"
   "\t[-CLEAR]\n"
   "\t[-L  ]\n"
   "\t[-I ]\n"
@@ -986,6 +990,21 @@ Returns:
 Index += 2;
   }
 
+  if ((Index >= argc) ||
+  ((strcmp (argv[Index], "-REMAP") == 0) ||
+   (strcmp (argv[Index], "-remap") == 0)) ) {
+//
+// by pass
+//
+gFitTableContext.HigherAddressRemapValue = xtoi (argv[Index + 1]);
+Index += 2;
+  } else {
+//
+// no remapping
+//
+gFitTableContext.HigherAddressRemapValue = 0x1;
+  }
+  printf ("Higher Address Value : 0x%llx\n", 
gFitTableContext.HigherAddressRemapValue);
   //
   // 0.4 Clear FIT table related memory
   //
-- 
2.26.2.windows.1



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