Re: [edk2-devel][edk2-platforms][PATCH v4] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
Looks good to me. Please get RB by atleast one of the Pkg maintainers.
With that:
Reviewed-by: Sai Chaganty
-Original Message-
From: Kuo, Ted
Sent: Tuesday, January 2, 2024 1:41 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel
; Desimone, Nathaniel L
; Dong, Eric ; S, Ashraf
Ali ; Duggapu, Chinni B ;
Gao, Liming
Subject: [edk2-devel][edk2-platforms][PATCH v4] MinPlatformPkg: Support
SecFspWrapperPlatformSecLib in X64
https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common files to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdRevision
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Eric Dong
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Liming Gao
Signed-off-by: Ted Kuo
---
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 ++-
.../Ia32/SecEntry.nasm| 4 +-
.../SecFspWrapperPlatformSecLib.inf | 9 +-
...pWrapperPlatformSecLibResetVectorInFsp.inf | 101 +
.../SecGetPerformance.c | 11 +-
.../SecPlatformInformation.c | 8 +-
.../SecRamInitData.c | 73 +--
.../X64/PeiCoreEntry.nasm | 202 ++
.../X64/SecEntry.nasm | 71 ++
.../X64/Stack.nasm| 72 +++
.../Ia32 => Include}/Fsp.h| 6 +-
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 17 +-
12 files changed, 565 insertions(+), 34 deletions(-) create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibResetVectorInFsp.inf
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
rename
Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32
=> Include}/Fsp.h (79%)
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..24c18f25b8 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
/** @file -Copyright (c) 2017, Intel Corporation. All rights
reserved.+Copyright (c) 2017 - 2024, Intel Corporation. All rights
reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -10,6 +10,7
@@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1) +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1 /** Fsp T
Core UPD **/ typedef struct {@@ -34,6 +35,28 @@ typedef struct {
**/ UINT8 Reserved[16]; } FSPT_CORE_UPD;+#else+/** Fsp
T Core UPD+**/+typedef struct {++/** Offset 0x0040+**/+ EFI_PHYSICAL_ADDRESS
MicrocodeRegionBase;++/** Offset 0x0048+**/+ UINT64
MicrocodeRegionSize;++/** Offset 0x0050+**/+ EFI_PHYSICAL_ADDRESS
CodeRegionBase;++/** Offset 0x0058+**/+ UINT64
CodeRegionSize;+} FSPT_CORE_UPD;+#endif #pragma pack() diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..0b3f343991 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
;--
;-; Copyright (c) 2019, Intel Corporation. All rights reserved.+; Copyright
(c) 2019 - 2024, Intel Corporation. All rights reserved. ;
SPDX-License-Identifier: BSD-2-Clause-Patent ; Module Name: ;@@ -13,7 +13,7 @@
;
;--
-#include "Fsp.h"+#include SECTION .text diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 2e0d67eae4..6806e000ce 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Librar
[edk2-devel][edk2-platforms][PATCH v4] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common files to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdRevision
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Eric Dong
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Liming Gao
Signed-off-by: Ted Kuo
---
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 ++-
.../Ia32/SecEntry.nasm| 4 +-
.../SecFspWrapperPlatformSecLib.inf | 9 +-
...pWrapperPlatformSecLibResetVectorInFsp.inf | 101 +
.../SecGetPerformance.c | 11 +-
.../SecPlatformInformation.c | 8 +-
.../SecRamInitData.c | 73 +--
.../X64/PeiCoreEntry.nasm | 202 ++
.../X64/SecEntry.nasm | 71 ++
.../X64/Stack.nasm| 72 +++
.../Ia32 => Include}/Fsp.h| 6 +-
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 17 +-
12 files changed, 565 insertions(+), 34 deletions(-)
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibResetVectorInFsp.inf
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
rename
Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32
=> Include}/Fsp.h (79%)
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..24c18f25b8 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1)
+#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1
/** Fsp T Core UPD
**/
typedef struct {
@@ -34,6 +35,28 @@ typedef struct {
**/
UINT8 Reserved[16];
} FSPT_CORE_UPD;
+#else
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0040
+**/
+ EFI_PHYSICAL_ADDRESSMicrocodeRegionBase;
+
+/** Offset 0x0048
+**/
+ UINT64 MicrocodeRegionSize;
+
+/** Offset 0x0050
+**/
+ EFI_PHYSICAL_ADDRESSCodeRegionBase;
+
+/** Offset 0x0058
+**/
+ UINT64 CodeRegionSize;
+} FSPT_CORE_UPD;
+#endif
#pragma pack()
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..0b3f343991 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
;--
;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2019 - 2024, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
; Module Name:
;
@@ -13,7 +13,7 @@
;
;--
-#include "Fsp.h"
+#include
SECTION .text
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 2e0d67eae4..6806e000ce 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
@@ -1,7 +1,7 @@
## @file
-# Provide FSP wrapper platform sec related function.
+# Provide FSP wrapper platform sec related function for IA32.
#
-# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,7 +25,7 @@
#
# The following information is
