Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode
On 7/23/19 2:48 AM, Laszlo Ersek wrote:
> (+ Brijesh, and one comment below)
>
> On 07/23/19 04:05, Wu, Hao A wrote:
>>> -Original Message-
>>> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Ni,
>>> Ray
>>> Sent: Monday, July 22, 2019 4:16 PM
>>> To: devel@edk2.groups.io
>>> Cc: Dong, Eric; Laszlo Ersek
>>> Subject: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level
>>> page table for long mode
>>>
>>> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008
>>>
>>> DxeIpl is responsible to create page table for DXE phase running
>>> either in long mode or in 32bit mode with certain protection
>>> mechanism enabled (refer to ToBuildPageTable()).
>>>
>>> The patch updates DxeIpl to create 5-level page table for DXE phase
>>> running in long mode when PcdUse5LevelPageTable is TRUE and CPU
>>> supports 5-level page table.
>>>
>>> Signed-off-by: Ray Ni
>>> Cc: Eric Dong
>>> Cc: Laszlo Ersek
>>> ---
>>> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 +
>>> .../Core/DxeIplPeim/X64/VirtualMemory.c | 227 --
>>> 2 files changed, 151 insertions(+), 77 deletions(-)
>>>
>>> diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>>> b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>>> index abc3217b01..98bc17fc9d 100644
>>> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>>> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>>> @@ -110,6 +110,7 @@ [Pcd.IA32,Pcd.X64]
>>>
>>> gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask
>>> ## CONSUMES
>>> gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask
>>> ## CONSUMES
>>> gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##
>>> CONSUMES
>>> + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##
>>> SOMETIMES_CONSUMES
>>>
>>> [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
>>> gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ##
>>> SOMETIMES_CONSUMES
>>> diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
>>> b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
>>> index edc38e4525..a5bcdcc734 100644
>>> --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
>>> +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
>>> @@ -15,7 +15,7 @@
>>> 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume
>>> 2:Instruction Set Reference, Intel
>>> 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume
>>> 3:System Programmer's Guide, Intel
>>>
>>> -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
>>> +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
>>> Copyright (c) 2017, AMD Incorporated. All rights reserved.
>>>
>>> SPDX-License-Identifier: BSD-2-Clause-Patent
>>> @@ -626,14 +626,19 @@ CreateIdentityMappingPageTables (
>>> )
>>> {
>>> UINT32RegEax;
>>> + UINT32RegEbx;
>>> + UINT32RegEcx;
>>> UINT32RegEdx;
>>> UINT8 PhysicalAddressBits;
>>> EFI_PHYSICAL_ADDRESS PageAddress;
>>> + UINTN IndexOfPml5Entries;
>>> UINTN IndexOfPml4Entries;
>>> UINTN IndexOfPdpEntries;
>>> UINTN
>>> IndexOfPageDirectoryEntries;
>>> + UINT32NumberOfPml5EntriesNeeded;
>>> UINT32NumberOfPml4EntriesNeeded;
>>> UINT32NumberOfPdpEntriesNeeded;
>>> + PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel5Entry;
>>> PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel4Entry;
>>> PAGE_MAP_AND_DIRECTORY_POINTER*PageMap;
>>> PAGE_MAP_AND_DIRECTORY_POINTER
>>> *PageDirectoryPointerEntry;
>>> @@ -641,9 +646,11 @@ CreateIdentityMappingPageTables (
>>> UINTN TotalPagesNum;
>>> UINTN
Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode
Mike, Thanks for the suggestion. I will try to move Cpuid.h to MdePkg/Include/Register directory in V2 patch. Thanks, Ray > -Original Message- > From: Kinney, Michael D > Sent: Wednesday, July 24, 2019 7:54 AM > To: devel@edk2.groups.io; ler...@redhat.com; Ni, Ray ; > Kinney, Michael D > Cc: Dong, Eric > Subject: RE: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level > page table for long mode > > Laszlo, > > There already a few examples in MdePkg/Include/Library/BaseLib.h. > For example, the bit field structures for CR0, CR4, EFLAGS, > and a segment descriptor are in that .h file. These are all > within: > > #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) > . . . > #endif > > We have since used a standard way to provide .h files for > registers. Best example is in UefiCpuPkg/Include/Register. > > It may make sense to put the register definitions required > by MdePkg and MdeModulePkg in MdePkg/Include/Register, and > files that use those register types can include the > required register definition include files. > > Best regards, > > Mike > > > -Original Message- > > From: devel@edk2.groups.io > > [mailto:devel@edk2.groups.io] On Behalf Of Laszlo Ersek > > Sent: Tuesday, July 23, 2019 12:20 PM > > To: Ni, Ray ; devel@edk2.groups.io > > Cc: Dong, Eric > > Subject: Re: [edk2-devel] [PATCH 4/4] > > MdeModulePkg/DxeIpl: Create 5-level page table for long > > mode > > > > On 07/23/19 17:29, Ni, Ray wrote: > > > > > > > > >> -Original Message- > > >> From: devel@edk2.groups.io On > > Behalf Of Laszlo > > >> Ersek > > >> Sent: Tuesday, July 23, 2019 5:46 PM > > >> To: devel@edk2.groups.io; Ni, Ray > > >> Cc: Dong, Eric > > >> Subject: Re: [edk2-devel] [PATCH 4/4] > > MdeModulePkg/DxeIpl: Create > > >> 5-level page table for long mode > > >> > > >> On 07/22/19 10:15, Ni, Ray wrote: > > >>> REF: > > https://bugzilla.tianocore.org/show_bug.cgi?id=2008 > > >>> > > >>> DxeIpl is responsible to create page table for DXE > > phase running > > >>> either in long mode or in 32bit mode with certain > > protection > > >>> mechanism enabled (refer to ToBuildPageTable()). > > >>> > > >>> The patch updates DxeIpl to create 5-level page > > table for DXE phase > > >>> running in long mode when PcdUse5LevelPageTable is > > TRUE and CPU > > >>> supports 5-level page table. > > >>> > > >>> Signed-off-by: Ray Ni > > >>> Cc: Eric Dong > > >>> Cc: Laszlo Ersek > > >>> --- > > >>> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | > > 1 + > > >>> .../Core/DxeIplPeim/X64/VirtualMemory.c | > > 227 -- > > >>> 2 files changed, 151 insertions(+), 77 deletions(- > > ) > > >>> > > >>> diff --git > > a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > > >>> b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > > >>> index abc3217b01..98bc17fc9d 100644 > > >>> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > > >>> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > > >>> @@ -110,6 +110,7 @@ [Pcd.IA32,Pcd.X64] > > >>> > > gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionP > > ropertyMask## CONSUMES > > >>> > > gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask > > ## CONSUMES > > >>>gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard > > ## CONSUMES > > >>> + > > gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable > > ## SOMETIMES_CONSUMES > > >>> > > >>> [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64] > > >>>gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack > > ## SOMETIMES_CONSUMES > > >>> diff --git > > a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > > >>> b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > > >>> index edc38e4525..a5bcdcc734 100644 > > >>> --- > > a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > > >>> +++ > > b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > > >>> @@ -15,7 +15,7 @@ > > >>> 2) IA-32 Intel(R) Architecture Software > > Developer's Manual Volume 2:Instruction Set Reference, > > Intel > > >>>
Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode
Laszlo,
There already a few examples in MdePkg/Include/Library/BaseLib.h.
For example, the bit field structures for CR0, CR4, EFLAGS,
and a segment descriptor are in that .h file. These are all
within:
#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
. . .
#endif
We have since used a standard way to provide .h files for
registers. Best example is in UefiCpuPkg/Include/Register.
It may make sense to put the register definitions required
by MdePkg and MdeModulePkg in MdePkg/Include/Register, and
files that use those register types can include the
required register definition include files.
Best regards,
Mike
> -Original Message-
> From: devel@edk2.groups.io
> [mailto:devel@edk2.groups.io] On Behalf Of Laszlo Ersek
> Sent: Tuesday, July 23, 2019 12:20 PM
> To: Ni, Ray ; devel@edk2.groups.io
> Cc: Dong, Eric
> Subject: Re: [edk2-devel] [PATCH 4/4]
> MdeModulePkg/DxeIpl: Create 5-level page table for long
> mode
>
> On 07/23/19 17:29, Ni, Ray wrote:
> >
> >
> >> -Original Message-
> >> From: devel@edk2.groups.io On
> Behalf Of Laszlo
> >> Ersek
> >> Sent: Tuesday, July 23, 2019 5:46 PM
> >> To: devel@edk2.groups.io; Ni, Ray
> >> Cc: Dong, Eric
> >> Subject: Re: [edk2-devel] [PATCH 4/4]
> MdeModulePkg/DxeIpl: Create
> >> 5-level page table for long mode
> >>
> >> On 07/22/19 10:15, Ni, Ray wrote:
> >>> REF:
> https://bugzilla.tianocore.org/show_bug.cgi?id=2008
> >>>
> >>> DxeIpl is responsible to create page table for DXE
> phase running
> >>> either in long mode or in 32bit mode with certain
> protection
> >>> mechanism enabled (refer to ToBuildPageTable()).
> >>>
> >>> The patch updates DxeIpl to create 5-level page
> table for DXE phase
> >>> running in long mode when PcdUse5LevelPageTable is
> TRUE and CPU
> >>> supports 5-level page table.
> >>>
> >>> Signed-off-by: Ray Ni
> >>> Cc: Eric Dong
> >>> Cc: Laszlo Ersek
> >>> ---
> >>> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf |
> 1 +
> >>> .../Core/DxeIplPeim/X64/VirtualMemory.c |
> 227 --
> >>> 2 files changed, 151 insertions(+), 77 deletions(-
> )
> >>>
> >>> diff --git
> a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> >>> b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> >>> index abc3217b01..98bc17fc9d 100644
> >>> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> >>> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> >>> @@ -110,6 +110,7 @@ [Pcd.IA32,Pcd.X64]
> >>>
> gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionP
> ropertyMask## CONSUMES
> >>>
> gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask
> ## CONSUMES
> >>>gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> ## CONSUMES
> >>> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable
> ## SOMETIMES_CONSUMES
> >>>
> >>> [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
> >>>gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack
> ## SOMETIMES_CONSUMES
> >>> diff --git
> a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> >>> b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> >>> index edc38e4525..a5bcdcc734 100644
> >>> ---
> a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> >>> +++
> b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> >>> @@ -15,7 +15,7 @@
> >>> 2) IA-32 Intel(R) Architecture Software
> Developer's Manual Volume 2:Instruction Set Reference,
> Intel
> >>> 3) IA-32 Intel(R) Architecture Software
> Developer's Manual
> >>> Volume 3:System Programmer's Guide, Intel
> >>>
> >>> -Copyright (c) 2006 - 2018, Intel Corporation. All
> rights
> >>> reserved.
> >>> +Copyright (c) 2006 - 2019, Intel Corporation. All
> rights
> >>> +reserved.
> >>> Copyright (c) 2017, AMD Incorporated. All rights
> reserved.
> >>>
> >>> SPDX-License-Identifier: BSD-2-Clause-Patent @@ -
> 626,14 +626,19 @@
> >>> CreateIdentityMappingPageTables (
> >>>)
> >>> {
> >>>UINT32
> RegEax;
> >>> + UINT32
> RegEbx;
> >>> + UINT32
> RegEcx;
> >>>UINT32
> RegEdx;
> >>>UINT8
> PhysicalAddressBits;
> >>>EFI_PHYSICAL_ADDRESS
> PageAddress;
> >>> + UINTN
> IndexOfPml5Entries;
> >>>UINTN
Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode
On 07/23/19 17:29, Ni, Ray wrote:
>
>
>> -Original Message-
>> From: devel@edk2.groups.io On Behalf Of Laszlo Ersek
>> Sent: Tuesday, July 23, 2019 5:46 PM
>> To: devel@edk2.groups.io; Ni, Ray
>> Cc: Dong, Eric
>> Subject: Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level
>> page table for long mode
>>
>> On 07/22/19 10:15, Ni, Ray wrote:
>>> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008
>>>
>>> DxeIpl is responsible to create page table for DXE phase running
>>> either in long mode or in 32bit mode with certain protection
>>> mechanism enabled (refer to ToBuildPageTable()).
>>>
>>> The patch updates DxeIpl to create 5-level page table for DXE phase
>>> running in long mode when PcdUse5LevelPageTable is TRUE and CPU
>>> supports 5-level page table.
>>>
>>> Signed-off-by: Ray Ni
>>> Cc: Eric Dong
>>> Cc: Laszlo Ersek
>>> ---
>>> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 +
>>> .../Core/DxeIplPeim/X64/VirtualMemory.c | 227 --
>>> 2 files changed, 151 insertions(+), 77 deletions(-)
>>>
>>> diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>>> b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>>> index abc3217b01..98bc17fc9d 100644
>>> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>>> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>>> @@ -110,6 +110,7 @@ [Pcd.IA32,Pcd.X64]
>>>gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask##
>>> CONSUMES
>>>gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##
>>> CONSUMES
>>>gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##
>>> CONSUMES
>>> + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##
>>> SOMETIMES_CONSUMES
>>>
>>> [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
>>>gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ##
>>> SOMETIMES_CONSUMES
>>> diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
>>> b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
>>> index edc38e4525..a5bcdcc734 100644
>>> --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
>>> +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
>>> @@ -15,7 +15,7 @@
>>> 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume
>>> 2:Instruction Set Reference, Intel
>>> 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume
>>> 3:System Programmer's Guide, Intel
>>>
>>> -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
>>> +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
>>> Copyright (c) 2017, AMD Incorporated. All rights reserved.
>>>
>>> SPDX-License-Identifier: BSD-2-Clause-Patent
>>> @@ -626,14 +626,19 @@ CreateIdentityMappingPageTables (
>>>)
>>> {
>>>UINT32RegEax;
>>> + UINT32RegEbx;
>>> + UINT32RegEcx;
>>>UINT32RegEdx;
>>>UINT8 PhysicalAddressBits;
>>>EFI_PHYSICAL_ADDRESS PageAddress;
>>> + UINTN IndexOfPml5Entries;
>>>UINTN IndexOfPml4Entries;
>>>UINTN IndexOfPdpEntries;
>>>UINTN
>>> IndexOfPageDirectoryEntries;
>>> + UINT32NumberOfPml5EntriesNeeded;
>>>UINT32NumberOfPml4EntriesNeeded;
>>>UINT32NumberOfPdpEntriesNeeded;
>>> + PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel5Entry;
>>>PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel4Entry;
>>>PAGE_MAP_AND_DIRECTORY_POINTER*PageMap;
>>>PAGE_MAP_AND_DIRECTORY_POINTER*PageDirectoryPointerEntry;
>>> @@ -641,9 +646,11 @@ CreateIdentityMappingPageTables (
>>>UINTN TotalPagesNum;
>>>UINTN BigPageAddress;
>>>VOID *Hob;
Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Laszlo Ersek
> Sent: Tuesday, July 23, 2019 5:46 PM
> To: devel@edk2.groups.io; Ni, Ray
> Cc: Dong, Eric
> Subject: Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level
> page table for long mode
>
> On 07/22/19 10:15, Ni, Ray wrote:
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008
> >
> > DxeIpl is responsible to create page table for DXE phase running
> > either in long mode or in 32bit mode with certain protection
> > mechanism enabled (refer to ToBuildPageTable()).
> >
> > The patch updates DxeIpl to create 5-level page table for DXE phase
> > running in long mode when PcdUse5LevelPageTable is TRUE and CPU
> > supports 5-level page table.
> >
> > Signed-off-by: Ray Ni
> > Cc: Eric Dong
> > Cc: Laszlo Ersek
> > ---
> > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 +
> > .../Core/DxeIplPeim/X64/VirtualMemory.c | 227 --
> > 2 files changed, 151 insertions(+), 77 deletions(-)
> >
> > diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> > b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> > index abc3217b01..98bc17fc9d 100644
> > --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> > +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> > @@ -110,6 +110,7 @@ [Pcd.IA32,Pcd.X64]
> >gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask##
> > CONSUMES
> >gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##
> > CONSUMES
> >gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##
> > CONSUMES
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##
> > SOMETIMES_CONSUMES
> >
> > [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
> >gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ##
> > SOMETIMES_CONSUMES
> > diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> > b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> > index edc38e4525..a5bcdcc734 100644
> > --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> > +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> > @@ -15,7 +15,7 @@
> > 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume
> > 2:Instruction Set Reference, Intel
> > 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume
> > 3:System Programmer's Guide, Intel
> >
> > -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> > +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
> > Copyright (c) 2017, AMD Incorporated. All rights reserved.
> >
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> > @@ -626,14 +626,19 @@ CreateIdentityMappingPageTables (
> >)
> > {
> >UINT32RegEax;
> > + UINT32RegEbx;
> > + UINT32RegEcx;
> >UINT32RegEdx;
> >UINT8 PhysicalAddressBits;
> >EFI_PHYSICAL_ADDRESS PageAddress;
> > + UINTN IndexOfPml5Entries;
> >UINTN IndexOfPml4Entries;
> >UINTN IndexOfPdpEntries;
> >UINTN
> > IndexOfPageDirectoryEntries;
> > + UINT32NumberOfPml5EntriesNeeded;
> >UINT32NumberOfPml4EntriesNeeded;
> >UINT32NumberOfPdpEntriesNeeded;
> > + PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel5Entry;
> >PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel4Entry;
> >PAGE_MAP_AND_DIRECTORY_POINTER*PageMap;
> >PAGE_MAP_AND_DIRECTORY_POINTER*PageDirectoryPointerEntry;
> > @@ -641,9 +646,11 @@ CreateIdentityMappingPageTables (
> >UINTN TotalPagesNum;
> >UINTN BigPageAddress;
> >VOID *Hob;
> > + BOOLEAN Page5LevelSupport;
> >BOOLEAN Page1GSupport;
> >PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
> >UINT64AddressEncMask;
>
Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode
On 07/22/19 10:15, Ni, Ray wrote:
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008
>
> DxeIpl is responsible to create page table for DXE phase running
> either in long mode or in 32bit mode with certain protection
> mechanism enabled (refer to ToBuildPageTable()).
>
> The patch updates DxeIpl to create 5-level page table for DXE phase
> running in long mode when PcdUse5LevelPageTable is TRUE and CPU
> supports 5-level page table.
>
> Signed-off-by: Ray Ni
> Cc: Eric Dong
> Cc: Laszlo Ersek
> ---
> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 +
> .../Core/DxeIplPeim/X64/VirtualMemory.c | 227 --
> 2 files changed, 151 insertions(+), 77 deletions(-)
>
> diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> index abc3217b01..98bc17fc9d 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> @@ -110,6 +110,7 @@ [Pcd.IA32,Pcd.X64]
>gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask##
> CONSUMES
>gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##
> CONSUMES
>gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##
> CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##
> SOMETIMES_CONSUMES
>
> [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
>gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ##
> SOMETIMES_CONSUMES
> diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> index edc38e4525..a5bcdcc734 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> @@ -15,7 +15,7 @@
> 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume
> 2:Instruction Set Reference, Intel
> 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume
> 3:System Programmer's Guide, Intel
>
> -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
> Copyright (c) 2017, AMD Incorporated. All rights reserved.
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -626,14 +626,19 @@ CreateIdentityMappingPageTables (
>)
> {
>UINT32RegEax;
> + UINT32RegEbx;
> + UINT32RegEcx;
>UINT32RegEdx;
>UINT8 PhysicalAddressBits;
>EFI_PHYSICAL_ADDRESS PageAddress;
> + UINTN IndexOfPml5Entries;
>UINTN IndexOfPml4Entries;
>UINTN IndexOfPdpEntries;
>UINTN IndexOfPageDirectoryEntries;
> + UINT32NumberOfPml5EntriesNeeded;
>UINT32NumberOfPml4EntriesNeeded;
>UINT32NumberOfPdpEntriesNeeded;
> + PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel5Entry;
>PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel4Entry;
>PAGE_MAP_AND_DIRECTORY_POINTER*PageMap;
>PAGE_MAP_AND_DIRECTORY_POINTER*PageDirectoryPointerEntry;
> @@ -641,9 +646,11 @@ CreateIdentityMappingPageTables (
>UINTN TotalPagesNum;
>UINTN BigPageAddress;
>VOID *Hob;
> + BOOLEAN Page5LevelSupport;
>BOOLEAN Page1GSupport;
>PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
>UINT64AddressEncMask;
> + IA32_CR4 Cr4;
>
>//
>// Make sure AddressEncMask is contained to smallest supported address
> field
> @@ -677,33 +684,66 @@ CreateIdentityMappingPageTables (
> }
>}
>
> + Page5LevelSupport = FALSE;
> + if (PcdGetBool (PcdUse5LevelPageTable)) {
> +AsmCpuidEx (0x7, 0, , , , );
> +DEBUG ((DEBUG_INFO, "Cpuid(7/0): %08x/%08x/%08x/%08x\n", RegEax, RegEbx,
> RegEcx, RegEdx));
> +if ((RegEcx & BIT16) != 0) {
(1) Would it be possible to use macro names here, for Index and SubIndex
in AsmCpuidEx(), and a "better" macro name than BIT16, in the RegEcx check?
> + Page5LevelSupport = TRUE;
> +}
> + }
> +
> + DEBUG ((DEBUG_INFO, "AddressBits/5LevelPaging/1GPage = %d/%d/%d\n",
> PhysicalAddressBits, Page5LevelSupport, Page1GSupport));
> +
(2) Can we format this log message as:
AddressBits=%d 5LevelPaging=%d 1GPage=%d
?
>//
> - // IA-32e paging translates 48-bit
Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode
(+ Brijesh, and one comment below)
On 07/23/19 04:05, Wu, Hao A wrote:
>> -Original Message-
>> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Ni,
>> Ray
>> Sent: Monday, July 22, 2019 4:16 PM
>> To: devel@edk2.groups.io
>> Cc: Dong, Eric; Laszlo Ersek
>> Subject: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level
>> page table for long mode
>>
>> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008
>>
>> DxeIpl is responsible to create page table for DXE phase running
>> either in long mode or in 32bit mode with certain protection
>> mechanism enabled (refer to ToBuildPageTable()).
>>
>> The patch updates DxeIpl to create 5-level page table for DXE phase
>> running in long mode when PcdUse5LevelPageTable is TRUE and CPU
>> supports 5-level page table.
>>
>> Signed-off-by: Ray Ni
>> Cc: Eric Dong
>> Cc: Laszlo Ersek
>> ---
>> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 +
>> .../Core/DxeIplPeim/X64/VirtualMemory.c | 227 --
>> 2 files changed, 151 insertions(+), 77 deletions(-)
>>
>> diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>> b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>> index abc3217b01..98bc17fc9d 100644
>> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>> @@ -110,6 +110,7 @@ [Pcd.IA32,Pcd.X64]
>>
>> gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask
>> ## CONSUMES
>>gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask
>> ## CONSUMES
>>gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##
>> CONSUMES
>> + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##
>> SOMETIMES_CONSUMES
>>
>> [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
>>gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ##
>> SOMETIMES_CONSUMES
>> diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
>> b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
>> index edc38e4525..a5bcdcc734 100644
>> --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
>> +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
>> @@ -15,7 +15,7 @@
>> 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume
>> 2:Instruction Set Reference, Intel
>> 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume
>> 3:System Programmer's Guide, Intel
>>
>> -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
>> +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
>> Copyright (c) 2017, AMD Incorporated. All rights reserved.
>>
>> SPDX-License-Identifier: BSD-2-Clause-Patent
>> @@ -626,14 +626,19 @@ CreateIdentityMappingPageTables (
>>)
>> {
>>UINT32RegEax;
>> + UINT32RegEbx;
>> + UINT32RegEcx;
>>UINT32RegEdx;
>>UINT8 PhysicalAddressBits;
>>EFI_PHYSICAL_ADDRESS PageAddress;
>> + UINTN IndexOfPml5Entries;
>>UINTN IndexOfPml4Entries;
>>UINTN IndexOfPdpEntries;
>>UINTN IndexOfPageDirectoryEntries;
>> + UINT32NumberOfPml5EntriesNeeded;
>>UINT32NumberOfPml4EntriesNeeded;
>>UINT32NumberOfPdpEntriesNeeded;
>> + PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel5Entry;
>>PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel4Entry;
>>PAGE_MAP_AND_DIRECTORY_POINTER*PageMap;
>>PAGE_MAP_AND_DIRECTORY_POINTER
>> *PageDirectoryPointerEntry;
>> @@ -641,9 +646,11 @@ CreateIdentityMappingPageTables (
>>UINTN TotalPagesNum;
>>UINTN BigPageAddress;
>>VOID *Hob;
>> + BOOLEAN Page5LevelSupport;
>>BOOLEAN Page1GSupport;
>>PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
>>UINT64AddressEncMask;
>> + IA32_CR4
Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode
> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Ni,
> Ray
> Sent: Monday, July 22, 2019 4:16 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric; Laszlo Ersek
> Subject: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level
> page table for long mode
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008
>
> DxeIpl is responsible to create page table for DXE phase running
> either in long mode or in 32bit mode with certain protection
> mechanism enabled (refer to ToBuildPageTable()).
>
> The patch updates DxeIpl to create 5-level page table for DXE phase
> running in long mode when PcdUse5LevelPageTable is TRUE and CPU
> supports 5-level page table.
>
> Signed-off-by: Ray Ni
> Cc: Eric Dong
> Cc: Laszlo Ersek
> ---
> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 +
> .../Core/DxeIplPeim/X64/VirtualMemory.c | 227 --
> 2 files changed, 151 insertions(+), 77 deletions(-)
>
> diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> index abc3217b01..98bc17fc9d 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> @@ -110,6 +110,7 @@ [Pcd.IA32,Pcd.X64]
>
> gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask
> ## CONSUMES
>gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask
> ## CONSUMES
>gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##
> CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##
> SOMETIMES_CONSUMES
>
> [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
>gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ##
> SOMETIMES_CONSUMES
> diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> index edc38e4525..a5bcdcc734 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> @@ -15,7 +15,7 @@
> 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume
> 2:Instruction Set Reference, Intel
> 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume
> 3:System Programmer's Guide, Intel
>
> -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
> Copyright (c) 2017, AMD Incorporated. All rights reserved.
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -626,14 +626,19 @@ CreateIdentityMappingPageTables (
>)
> {
>UINT32RegEax;
> + UINT32RegEbx;
> + UINT32RegEcx;
>UINT32RegEdx;
>UINT8 PhysicalAddressBits;
>EFI_PHYSICAL_ADDRESS PageAddress;
> + UINTN IndexOfPml5Entries;
>UINTN IndexOfPml4Entries;
>UINTN IndexOfPdpEntries;
>UINTN IndexOfPageDirectoryEntries;
> + UINT32NumberOfPml5EntriesNeeded;
>UINT32NumberOfPml4EntriesNeeded;
>UINT32NumberOfPdpEntriesNeeded;
> + PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel5Entry;
>PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel4Entry;
>PAGE_MAP_AND_DIRECTORY_POINTER*PageMap;
>PAGE_MAP_AND_DIRECTORY_POINTER
> *PageDirectoryPointerEntry;
> @@ -641,9 +646,11 @@ CreateIdentityMappingPageTables (
>UINTN TotalPagesNum;
>UINTN BigPageAddress;
>VOID *Hob;
> + BOOLEAN Page5LevelSupport;
>BOOLEAN Page1GSupport;
>PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
>UINT64AddressEncMask;
> + IA32_CR4 Cr4;
>
>//
>// Make sure AddressEncMask is contained to smallest supported address
> field
> @@ -677,33 +684,66 @@ CreateIdentityMappingPageTables (
> }
>}
>
> + Page5LevelSupport = FALSE;
> + if (PcdGetBool (PcdUse5LevelPageTable)) {
> +AsmCpuidEx (0x7, 0, , , , );
> +DEBUG ((DEBUG_INFO, "Cpuid(7/0): %08x/%08x/%08x/%08x\n&qu
Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode
Forgot to include MdeModulePkg maintainers for review.
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Ni, Ray
> Sent: Monday, July 22, 2019 4:16 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Laszlo Ersek
> Subject: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level
> page table for long mode
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008
>
> DxeIpl is responsible to create page table for DXE phase running either in
> long mode or in 32bit mode with certain protection mechanism enabled
> (refer to ToBuildPageTable()).
>
> The patch updates DxeIpl to create 5-level page table for DXE phase running
> in long mode when PcdUse5LevelPageTable is TRUE and CPU supports 5-
> level page table.
>
> Signed-off-by: Ray Ni
> Cc: Eric Dong
> Cc: Laszlo Ersek
> ---
> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 +
> .../Core/DxeIplPeim/X64/VirtualMemory.c | 227 --
> 2 files changed, 151 insertions(+), 77 deletions(-)
>
> diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> index abc3217b01..98bc17fc9d 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> @@ -110,6 +110,7 @@ [Pcd.IA32,Pcd.X64]
>
> gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask
> ## CONSUMES
>gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask
> ## CONSUMES
>gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##
> CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##
> SOMETIMES_CONSUMES
>
> [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
>gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ##
> SOMETIMES_CONSUMES
> diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> index edc38e4525..a5bcdcc734 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> @@ -15,7 +15,7 @@
> 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume
> 2:Instruction Set Reference, Intel
> 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume
> 3:System Programmer's Guide, Intel
>
> -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
> Copyright (c) 2017, AMD Incorporated. All rights reserved.
>
> SPDX-License-Identifier: BSD-2-Clause-Patent @@ -626,14 +626,19 @@
> CreateIdentityMappingPageTables (
>)
> {
>UINT32RegEax;
> + UINT32RegEbx;
> + UINT32RegEcx;
>UINT32RegEdx;
>UINT8 PhysicalAddressBits;
>EFI_PHYSICAL_ADDRESS PageAddress;
> + UINTN IndexOfPml5Entries;
>UINTN IndexOfPml4Entries;
>UINTN IndexOfPdpEntries;
>UINTN IndexOfPageDirectoryEntries;
> + UINT32NumberOfPml5EntriesNeeded;
>UINT32NumberOfPml4EntriesNeeded;
>UINT32NumberOfPdpEntriesNeeded;
> + PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel5Entry;
>PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel4Entry;
>PAGE_MAP_AND_DIRECTORY_POINTER*PageMap;
>PAGE_MAP_AND_DIRECTORY_POINTER
> *PageDirectoryPointerEntry;
> @@ -641,9 +646,11 @@ CreateIdentityMappingPageTables (
>UINTN TotalPagesNum;
>UINTN BigPageAddress;
>VOID *Hob;
> + BOOLEAN Page5LevelSupport;
>BOOLEAN Page1GSupport;
>PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
>UINT64AddressEncMask;
> + IA32_CR4 Cr4;
>
>//
>// Make sure AddressEncMask is contained to smallest supported address
> field @@ -677,33 +684,66 @@ CreateIdentityMappingPageTables (
> }
>}
>
> + Page5LevelSupport = FALSE;
> + if (PcdGetBool (PcdUse5LevelPageTable)) {
> +AsmCpuidEx (0x7, 0, , , , );
> +DEBUG ((DEBUG_INFO, "Cpuid(7/0): %08x/%08x
[edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008
DxeIpl is responsible to create page table for DXE phase running
either in long mode or in 32bit mode with certain protection
mechanism enabled (refer to ToBuildPageTable()).
The patch updates DxeIpl to create 5-level page table for DXE phase
running in long mode when PcdUse5LevelPageTable is TRUE and CPU
supports 5-level page table.
Signed-off-by: Ray Ni
Cc: Eric Dong
Cc: Laszlo Ersek
---
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 +
.../Core/DxeIplPeim/X64/VirtualMemory.c | 227 --
2 files changed, 151 insertions(+), 77 deletions(-)
diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
index abc3217b01..98bc17fc9d 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -110,6 +110,7 @@ [Pcd.IA32,Pcd.X64]
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask##
CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##
CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##
CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##
SOMETIMES_CONSUMES
[Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ##
SOMETIMES_CONSUMES
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index edc38e4525..a5bcdcc734 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -15,7 +15,7 @@
2) IA-32 Intel(R) Architecture Software Developer's Manual Volume
2:Instruction Set Reference, Intel
3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System
Programmer's Guide, Intel
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -626,14 +626,19 @@ CreateIdentityMappingPageTables (
)
{
UINT32RegEax;
+ UINT32RegEbx;
+ UINT32RegEcx;
UINT32RegEdx;
UINT8 PhysicalAddressBits;
EFI_PHYSICAL_ADDRESS PageAddress;
+ UINTN IndexOfPml5Entries;
UINTN IndexOfPml4Entries;
UINTN IndexOfPdpEntries;
UINTN IndexOfPageDirectoryEntries;
+ UINT32NumberOfPml5EntriesNeeded;
UINT32NumberOfPml4EntriesNeeded;
UINT32NumberOfPdpEntriesNeeded;
+ PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel5Entry;
PAGE_MAP_AND_DIRECTORY_POINTER*PageMapLevel4Entry;
PAGE_MAP_AND_DIRECTORY_POINTER*PageMap;
PAGE_MAP_AND_DIRECTORY_POINTER*PageDirectoryPointerEntry;
@@ -641,9 +646,11 @@ CreateIdentityMappingPageTables (
UINTN TotalPagesNum;
UINTN BigPageAddress;
VOID *Hob;
+ BOOLEAN Page5LevelSupport;
BOOLEAN Page1GSupport;
PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
UINT64AddressEncMask;
+ IA32_CR4 Cr4;
//
// Make sure AddressEncMask is contained to smallest supported address field
@@ -677,33 +684,66 @@ CreateIdentityMappingPageTables (
}
}
+ Page5LevelSupport = FALSE;
+ if (PcdGetBool (PcdUse5LevelPageTable)) {
+AsmCpuidEx (0x7, 0, , , , );
+DEBUG ((DEBUG_INFO, "Cpuid(7/0): %08x/%08x/%08x/%08x\n", RegEax, RegEbx,
RegEcx, RegEdx));
+if ((RegEcx & BIT16) != 0) {
+ Page5LevelSupport = TRUE;
+}
+ }
+
+ DEBUG ((DEBUG_INFO, "AddressBits/5LevelPaging/1GPage = %d/%d/%d\n",
PhysicalAddressBits, Page5LevelSupport, Page1GSupport));
+
//
- // IA-32e paging translates 48-bit linear addresses to 52-bit physical
addresses.
+ // IA-32e paging translates 48-bit linear addresses to 52-bit physical
addresses
+ // when 5-Level Paging is disabled,
+ // due to either unsupported by HW, or disabled by PCD.
//
ASSERT (PhysicalAddressBits <= 52);
- if (PhysicalAddressBits > 48) {
+ if (!Page5LevelSupport && PhysicalAddressBits > 48) {
PhysicalAddressBits = 48;
}
//
// Calculate the table entries needed.
//
- if
