Re: [edk2-devel] [Patch] PcAtChipsetPkg: Fix spelling errors

2019-10-21 Thread Philippe Mathieu-Daudé 

On 10/18/19 9:34 PM, Michael D Kinney wrote:

From: Sean Brogan 

https://bugzilla.tianocore.org/show_bug.cgi?id=2263

Cc: Ray Ni 
Signed-off-by: Michael D Kinney 
---
  PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c  | 12 ++--
  PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf |  2 +-
  PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni |  2 +-
  PcAtChipsetPkg/Include/Library/IoApicLib.h   |  2 +-
  PcAtChipsetPkg/Include/Register/Hpet.h   |  6 +++---
  PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c |  2 +-
  PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c   |  8 
  PcAtChipsetPkg/PcAtChipsetPkg.dec|  2 +-
  PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c   |  4 ++--
  PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h   |  8 
  .../PcatRealTimeClockRuntimeDxe/PcRtcEntry.c |  2 +-
  11 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c 
b/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
index ded3b53619..cbe986ebfd 100644
--- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
+++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
@@ -1,5 +1,5 @@
  /** @file
-  Timer Architectural Protocol module using High Precesion Event Timer (HPET)
+  Timer Architectural Protocol module using High Precision Event Timer (HPET)
  
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -246,7 +246,7 @@ HpetRead (
  /**
Write a 64-bit HPET register.
  
-  @param  Offset  Specifies the ofsfert of the HPET register to write.

+  @param  Offset  Specifies the offset of the HPET register to write.
@param  Value   Specifies the value to write to the HPET register specified 
by Offset.
  
@return  The 64-bit value written to HPET register specified by Offset.

@@ -530,7 +530,7 @@ TimerDriverSetTimerPeriod (
  // If TimerPeriod is 0, then mask HPET Timer interrupts
  //
  
-if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {

+if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet 
(PcdHpetMsiEnable)) {


Ah, this changes are not present in the previous patch version 
(https://edk2.groups.io/g/devel/message/43354) so I now realize we had 2 
person doing the same work, and failed at noticing because we kinda 
ignored the previous patches :|



//
// Disable HPET MSI interrupt generation
//
@@ -576,7 +576,7 @@ TimerDriverSetTimerPeriod (
  //
  // Enable HPET Timer interrupt generation
  //
-if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet 
(PcdHpetMsiEnable)) {
+if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet 
(PcdHpetMsiEnable)) {
//
// Program MSI Address and MSI Data values in the selected HPET Timer
// Program HPET register with APIC ID of current BSP in case BSP has 
been switched
@@ -834,7 +834,7 @@ TimerDriverInitialize (
  //
  // Check to see if this HPET Timer supports MSI
  //
-if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0) {
+if (mTimerConfiguration.Bits.MsiInterruptCapability != 0) {
//
// Save the index of the first HPET Timer that supports MSI interrupts
//
@@ -959,7 +959,7 @@ TimerDriverInitialize (
// Show state of enabled HPET timer
//
DEBUG_CODE (
-if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet 
(PcdHpetMsiEnable)) {
+if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet 
(PcdHpetMsiEnable)) {
DEBUG ((DEBUG_INFO, "HPET Interrupt Mode MSI\n"));
  } else {
DEBUG ((DEBUG_INFO, "HPET Interrupt Mode I/O APIC\n"));
diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf 
b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
index ba2e075118..125eea0aab 100644
--- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
@@ -1,5 +1,5 @@
  ## @file
-# Timer Architectural Protocol module using High Precesion Event Timer (HPET).
+# Timer Architectural Protocol module using High Precision Event Timer (HPET).
  #
  # Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
  # SPDX-License-Identifier: BSD-2-Clause-Patent
diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni 
b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
index e2320653b6..7d1797b1df 100644
--- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
+++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
@@ -1,5 +1,5 @@
  // /** @file
-// Timer Architectural Protocol module using High Precesion Event Timer (HPET).
+// Timer Architectural Protocol module using High Precision Event Timer (HPET).
  //
  // Timer Architectural Protocol module using High Precision Event Timer 
(HPET).
  //
diff --git a/PcAtChipsetPkg/Include/Library/IoApicLib.h 
b/PcAtChipsetPkg/Include/Library/IoApicLib.h
index

Re: [edk2-devel] [Patch] PcAtChipsetPkg: Fix spelling errors

2019-10-20 Thread Ni, Ray 
Reviewed-by: Ray Ni 

> -Original Message-
> From: Kinney, Michael D 
> Sent: Saturday, October 19, 2019 3:35 AM
> To: devel@edk2.groups.io
> Cc: Sean Brogan ; Ni, Ray 
> Subject: [Patch] PcAtChipsetPkg: Fix spelling errors
> 
> From: Sean Brogan 
> 
> https://bugzilla.tianocore.org/show_bug.cgi?id=2263
> 
> Cc: Ray Ni 
> Signed-off-by: Michael D Kinney 
> ---
>  PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c  | 12 ++--
>  PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf |  2 +-
>  PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni |  2 +-
>  PcAtChipsetPkg/Include/Library/IoApicLib.h   |  2 +-
>  PcAtChipsetPkg/Include/Register/Hpet.h   |  6 +++---
>  PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c |  2 +-
>  PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c   |  8 
>  PcAtChipsetPkg/PcAtChipsetPkg.dec|  2 +-
>  PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c   |  4 ++--
>  PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h   |  8 
>  .../PcatRealTimeClockRuntimeDxe/PcRtcEntry.c |  2 +-
>  11 files changed, 25 insertions(+), 25 deletions(-)
> 
> diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
> b/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
> index ded3b53619..cbe986ebfd 100644
> --- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
> +++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
> @@ -1,5 +1,5 @@
>  /** @file
> -  Timer Architectural Protocol module using High Precesion Event Timer
> (HPET)
> +  Timer Architectural Protocol module using High Precision Event Timer
> (HPET)
> 
>Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
>SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -246,7 +246,7 @@ HpetRead (
>  /**
>Write a 64-bit HPET register.
> 
> -  @param  Offset  Specifies the ofsfert of the HPET register to write.
> +  @param  Offset  Specifies the offset of the HPET register to write.
>@param  Value   Specifies the value to write to the HPET register specified
> by Offset.
> 
>@return  The 64-bit value written to HPET register specified by Offset.
> @@ -530,7 +530,7 @@ TimerDriverSetTimerPeriod (
>  // If TimerPeriod is 0, then mask HPET Timer interrupts
>  //
> 
> -if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 &&
> FeaturePcdGet (PcdHpetMsiEnable)) {
> +if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 &&
> FeaturePcdGet (PcdHpetMsiEnable)) {
>//
>// Disable HPET MSI interrupt generation
>//
> @@ -576,7 +576,7 @@ TimerDriverSetTimerPeriod (
>  //
>  // Enable HPET Timer interrupt generation
>  //
> -if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 &&
> FeaturePcdGet (PcdHpetMsiEnable)) {
> +if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 &&
> FeaturePcdGet (PcdHpetMsiEnable)) {
>//
>// Program MSI Address and MSI Data values in the selected HPET Timer
>// Program HPET register with APIC ID of current BSP in case BSP has 
> been
> switched
> @@ -834,7 +834,7 @@ TimerDriverInitialize (
>  //
>  // Check to see if this HPET Timer supports MSI
>  //
> -if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0) {
> +if (mTimerConfiguration.Bits.MsiInterruptCapability != 0) {
>//
>// Save the index of the first HPET Timer that supports MSI interrupts
>//
> @@ -959,7 +959,7 @@ TimerDriverInitialize (
>// Show state of enabled HPET timer
>//
>DEBUG_CODE (
> -if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 &&
> FeaturePcdGet (PcdHpetMsiEnable)) {
> +if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 &&
> FeaturePcdGet (PcdHpetMsiEnable)) {
>DEBUG ((DEBUG_INFO, "HPET Interrupt Mode MSI\n"));
>  } else {
>DEBUG ((DEBUG_INFO, "HPET Interrupt Mode I/O APIC\n"));
> diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
> b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
> index ba2e075118..125eea0aab 100644
> --- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
> +++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
> @@ -1,5 +1,5 @@
>  ## @file
> -# Timer Architectural Protocol module using High Precesion Event Timer
> (HPET).
> +# Timer Architectural Protocol module using High Precision Event Timer
> (HPET).
>  #
>  # Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
> diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
> b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
> index e2320653b6..7d1797b1df 100644
> --- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
> +++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
> @@ -1,5 +1,5 @@
>  // /** @file
> -// Timer Architectural Protocol module using High Precesion Event Timer
> (HPET).
> +// Timer Architectural Protocol module using High Precision Event Timer
> (HPET).
>  //
>  // Timer Architectural Protocol module using High Precision Event Timer
> (HPET).
>  //
>

[edk2-devel] [Patch] PcAtChipsetPkg: Fix spelling errors

2019-10-18 Thread Michael D Kinney 
From: Sean Brogan 

https://bugzilla.tianocore.org/show_bug.cgi?id=2263

Cc: Ray Ni 
Signed-off-by: Michael D Kinney 
---
 PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c  | 12 ++--
 PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf |  2 +-
 PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni |  2 +-
 PcAtChipsetPkg/Include/Library/IoApicLib.h   |  2 +-
 PcAtChipsetPkg/Include/Register/Hpet.h   |  6 +++---
 PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c |  2 +-
 PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c   |  8 
 PcAtChipsetPkg/PcAtChipsetPkg.dec|  2 +-
 PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c   |  4 ++--
 PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h   |  8 
 .../PcatRealTimeClockRuntimeDxe/PcRtcEntry.c |  2 +-
 11 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c 
b/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
index ded3b53619..cbe986ebfd 100644
--- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
+++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
@@ -1,5 +1,5 @@
 /** @file
-  Timer Architectural Protocol module using High Precesion Event Timer (HPET)
+  Timer Architectural Protocol module using High Precision Event Timer (HPET)
 
   Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -246,7 +246,7 @@ HpetRead (
 /**
   Write a 64-bit HPET register.
 
-  @param  Offset  Specifies the ofsfert of the HPET register to write.
+  @param  Offset  Specifies the offset of the HPET register to write.
   @param  Value   Specifies the value to write to the HPET register specified 
by Offset.
 
   @return  The 64-bit value written to HPET register specified by Offset.
@@ -530,7 +530,7 @@ TimerDriverSetTimerPeriod (
 // If TimerPeriod is 0, then mask HPET Timer interrupts
 //
 
-if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet 
(PcdHpetMsiEnable)) {
+if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet 
(PcdHpetMsiEnable)) {
   //
   // Disable HPET MSI interrupt generation
   //
@@ -576,7 +576,7 @@ TimerDriverSetTimerPeriod (
 //
 // Enable HPET Timer interrupt generation
 //
-if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet 
(PcdHpetMsiEnable)) {
+if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet 
(PcdHpetMsiEnable)) {
   //
   // Program MSI Address and MSI Data values in the selected HPET Timer
   // Program HPET register with APIC ID of current BSP in case BSP has 
been switched
@@ -834,7 +834,7 @@ TimerDriverInitialize (
 //
 // Check to see if this HPET Timer supports MSI
 //
-if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0) {
+if (mTimerConfiguration.Bits.MsiInterruptCapability != 0) {
   //
   // Save the index of the first HPET Timer that supports MSI interrupts
   //
@@ -959,7 +959,7 @@ TimerDriverInitialize (
   // Show state of enabled HPET timer
   //
   DEBUG_CODE (
-if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet 
(PcdHpetMsiEnable)) {
+if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet 
(PcdHpetMsiEnable)) {
   DEBUG ((DEBUG_INFO, "HPET Interrupt Mode MSI\n"));
 } else {
   DEBUG ((DEBUG_INFO, "HPET Interrupt Mode I/O APIC\n"));
diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf 
b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
index ba2e075118..125eea0aab 100644
--- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
@@ -1,5 +1,5 @@
 ## @file
-# Timer Architectural Protocol module using High Precesion Event Timer (HPET).
+# Timer Architectural Protocol module using High Precision Event Timer (HPET).
 #
 # Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni 
b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
index e2320653b6..7d1797b1df 100644
--- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
+++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
@@ -1,5 +1,5 @@
 // /** @file
-// Timer Architectural Protocol module using High Precesion Event Timer (HPET).
+// Timer Architectural Protocol module using High Precision Event Timer (HPET).
 //
 // Timer Architectural Protocol module using High Precision Event Timer (HPET).
 //
diff --git a/PcAtChipsetPkg/Include/Library/IoApicLib.h 
b/PcAtChipsetPkg/Include/Library/IoApicLib.h
index 200ef731fb..4ee092c0f2 100644
--- a/PcAtChipsetPkg/Include/Library/IoApicLib.h
+++ b/PcAtChipsetPkg/Include/Library/IoApicLib.h
@@ -63,7 +63,7 @@ IoApicEnableInterrupt (
   Configures an I/O APIC interrupt.
 
   Configure an I/O APIC Redirection Table Entry to deliver an interrupt in 
physical
-  mode to the Local APIC of the currntly executing CPU.