Re: [edk2-devel] [edk2-platforms: PATCH v2 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation
On Fri, 24 May 2019 at 17:43, Marcin Wojtas wrote: > > pt., 24 maj 2019 o 17:32 Leif Lindholm napisał(a): > > > > > > Looking forward to your feedback. Other than that - do you have any > > > > remarks to the rest of the patches in v2? > > > > > > The rest looks fine. > > > > And I'm happy that all of my comments on v1 have been addressed. > > > > Great, thanks. Ok, with PciSegmentLib it's still working. Should I > resubmit the whole patchset? > Yes, please. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41348): https://edk2.groups.io/g/devel/message/41348 Mute This Topic: https://groups.io/mt/31686572/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms: PATCH v2 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation
pt., 24 maj 2019 o 17:32 Leif Lindholm napisał(a): > > > > Looking forward to your feedback. Other than that - do you have any > > > remarks to the rest of the patches in v2? > > > > The rest looks fine. > > And I'm happy that all of my comments on v1 have been addressed. > Great, thanks. Ok, with PciSegmentLib it's still working. Should I resubmit the whole patchset? Best regards, Marcin -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41347): https://edk2.groups.io/g/devel/message/41347 Mute This Topic: https://groups.io/mt/31686572/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms: PATCH v2 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation
> > Looking forward to your feedback. Other than that - do you have any > > remarks to the rest of the patches in v2? > > The rest looks fine. And I'm happy that all of my comments on v1 have been addressed. / Leif -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41346): https://edk2.groups.io/g/devel/message/41346 Mute This Topic: https://groups.io/mt/31686572/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms: PATCH v2 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation
On Fri, 24 May 2019 at 16:28, Marcin Wojtas wrote: > > pt., 24 maj 2019 o 15:08 Ard Biesheuvel > napisał(a): > > > > On Fri, 24 May 2019 at 15:03, Marcin Wojtas wrote: > > > > > > pt., 24 maj 2019 o 14:50 Ard Biesheuvel > > > napisał(a): > > > > > > > > On Mon, 20 May 2019 at 17:27, Marcin Wojtas wrote: > > > > > > > > > > From: Ard Biesheuvel > > > > > > > > > > Implement a special version of PciExpressLib that takes the quirky > > > > > nature of the Synopsys Designware PCIe IP into account. In particular, > > > > > we need to ignore config space accesses to all devices on the first > > > > > bus except device 0, because the broadcast nature of type 0 > > > > > configuration > > > > > cycles will result in whatever device is in the slot to appear at each > > > > > of the 32 device positions. > > > > > > > > > > > > > I never bothered to implement multisegment support for this SoC, since > > > > MacchiatoBin has only one segment wired up, but since your interest is > > > > in generic support, it might make sense to drop this patch and > > > > implement PciSegmentLib instead (without depending on any of the other > > > > library classes that the generic PciExpressLib depends on) > > > > > > > > > > This was (and still is) my plan, but I've been having some serious > > > time shortages for extra development. In order not to postpone this > > > support any longer I prefer to get merged, what I have and possibly > > > rework on top. > > > > > > About depending on a generic PciExpressLib - do you mean I can filter > > > out devices from bus0 in PciSegmentLib? > > > > > > > Yes, please look at > > Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib > > > > If you follow the same approach, you no longer need PciLib or > > PciExpressLib, it is all flattened into PciSegmentLib. > > For PciLib I use MdePkg implementation, but if that could be dropped > that's good. I saw your library and it would be perfect for reusing on > Armada, with one difference: PciSegmentLibGetConfigBase. > > 1. As a first step I could reuse Synquacer library using single base > in PciSegmentLibGetConfigBase (PcdPciExpressBaseAddress) as a stub, > for extending later. > > 2. Afterwards (i.e. in some next patchset) I'd like to use my board > description infrastructure for obtaining config space base addresses. > How about following solution: > - add PciSegmentLib constructor routine, where I'd create a global > array with config space addesses > - add dispatching for it in PciSegmentLibGetConfigBase? > This sounds like a reasonable approach, yes. > Looking forward to your feedback. Other than that - do you have any > remarks to the rest of the patches in v2? > The rest looks fine. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41344): https://edk2.groups.io/g/devel/message/41344 Mute This Topic: https://groups.io/mt/31686572/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms: PATCH v2 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation
pt., 24 maj 2019 o 15:08 Ard Biesheuvel napisał(a): > > On Fri, 24 May 2019 at 15:03, Marcin Wojtas wrote: > > > > pt., 24 maj 2019 o 14:50 Ard Biesheuvel > > napisał(a): > > > > > > On Mon, 20 May 2019 at 17:27, Marcin Wojtas wrote: > > > > > > > > From: Ard Biesheuvel > > > > > > > > Implement a special version of PciExpressLib that takes the quirky > > > > nature of the Synopsys Designware PCIe IP into account. In particular, > > > > we need to ignore config space accesses to all devices on the first > > > > bus except device 0, because the broadcast nature of type 0 > > > > configuration > > > > cycles will result in whatever device is in the slot to appear at each > > > > of the 32 device positions. > > > > > > > > > > I never bothered to implement multisegment support for this SoC, since > > > MacchiatoBin has only one segment wired up, but since your interest is > > > in generic support, it might make sense to drop this patch and > > > implement PciSegmentLib instead (without depending on any of the other > > > library classes that the generic PciExpressLib depends on) > > > > > > > This was (and still is) my plan, but I've been having some serious > > time shortages for extra development. In order not to postpone this > > support any longer I prefer to get merged, what I have and possibly > > rework on top. > > > > About depending on a generic PciExpressLib - do you mean I can filter > > out devices from bus0 in PciSegmentLib? > > > > Yes, please look at Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib > > If you follow the same approach, you no longer need PciLib or > PciExpressLib, it is all flattened into PciSegmentLib. For PciLib I use MdePkg implementation, but if that could be dropped that's good. I saw your library and it would be perfect for reusing on Armada, with one difference: PciSegmentLibGetConfigBase. 1. As a first step I could reuse Synquacer library using single base in PciSegmentLibGetConfigBase (PcdPciExpressBaseAddress) as a stub, for extending later. 2. Afterwards (i.e. in some next patchset) I'd like to use my board description infrastructure for obtaining config space base addresses. How about following solution: - add PciSegmentLib constructor routine, where I'd create a global array with config space addesses - add dispatching for it in PciSegmentLibGetConfigBase? Looking forward to your feedback. Other than that - do you have any remarks to the rest of the patches in v2? Thanks, Marcin -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41335): https://edk2.groups.io/g/devel/message/41335 Mute This Topic: https://groups.io/mt/31686572/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms: PATCH v2 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation
On Fri, 24 May 2019 at 15:03, Marcin Wojtas wrote: > > pt., 24 maj 2019 o 14:50 Ard Biesheuvel > napisał(a): > > > > On Mon, 20 May 2019 at 17:27, Marcin Wojtas wrote: > > > > > > From: Ard Biesheuvel > > > > > > Implement a special version of PciExpressLib that takes the quirky > > > nature of the Synopsys Designware PCIe IP into account. In particular, > > > we need to ignore config space accesses to all devices on the first > > > bus except device 0, because the broadcast nature of type 0 configuration > > > cycles will result in whatever device is in the slot to appear at each > > > of the 32 device positions. > > > > > > > I never bothered to implement multisegment support for this SoC, since > > MacchiatoBin has only one segment wired up, but since your interest is > > in generic support, it might make sense to drop this patch and > > implement PciSegmentLib instead (without depending on any of the other > > library classes that the generic PciExpressLib depends on) > > > > This was (and still is) my plan, but I've been having some serious > time shortages for extra development. In order not to postpone this > support any longer I prefer to get merged, what I have and possibly > rework on top. > > About depending on a generic PciExpressLib - do you mean I can filter > out devices from bus0 in PciSegmentLib? > Yes, please look at Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib If you follow the same approach, you no longer need PciLib or PciExpressLib, it is all flattened into PciSegmentLib. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41331): https://edk2.groups.io/g/devel/message/41331 Mute This Topic: https://groups.io/mt/31686572/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms: PATCH v2 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation
pt., 24 maj 2019 o 14:50 Ard Biesheuvel napisał(a): > > On Mon, 20 May 2019 at 17:27, Marcin Wojtas wrote: > > > > From: Ard Biesheuvel > > > > Implement a special version of PciExpressLib that takes the quirky > > nature of the Synopsys Designware PCIe IP into account. In particular, > > we need to ignore config space accesses to all devices on the first > > bus except device 0, because the broadcast nature of type 0 configuration > > cycles will result in whatever device is in the slot to appear at each > > of the 32 device positions. > > > > I never bothered to implement multisegment support for this SoC, since > MacchiatoBin has only one segment wired up, but since your interest is > in generic support, it might make sense to drop this patch and > implement PciSegmentLib instead (without depending on any of the other > library classes that the generic PciExpressLib depends on) > This was (and still is) my plan, but I've been having some serious time shortages for extra development. In order not to postpone this support any longer I prefer to get merged, what I have and possibly rework on top. About depending on a generic PciExpressLib - do you mean I can filter out devices from bus0 in PciSegmentLib? Thanks, Marcin > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Marcin Wojtas > > --- > > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > > | 42 + > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > > | 1531 > > 2 files changed, 1573 insertions(+) > > create mode 100644 > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > > create mode 100644 > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > > > > diff --git > > a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > > > > b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > > new file mode 100644 > > index 000..a66ef28 > > --- /dev/null > > +++ > > b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > > @@ -0,0 +1,42 @@ > > +## @file > > +# > > +# Copyright (c) 2017, Linaro, Ltd. All rights reserved. > > +# Copyright (c) 2019, Marvell International Ltd. All rights reserved. > > +# > > +# This program and the accompanying materials > > +# are licensed and made available under the terms and conditions of the > > BSD License > > +# which accompanies this distribution. The full text of the license may > > be found at > > +# http://opensource.org/licenses/bsd-license.php. > > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > > IMPLIED. > > +# > > +# > > +## > > + > > +[Defines] > > + INF_VERSION= 0x0001001B > > + BASE_NAME = Armada7k8kPciExpressLib > > + FILE_GUID = f0926204-3061-40ed-8261-2aeccc7914c9 > > + MODULE_TYPE= BASE > > + VERSION_STRING = 1.0 > > + LIBRARY_CLASS = PciExpressLib > > + > > +[Sources] > > + PciExpressLib.c > > + > > +[Packages] > > + ArmPkg/ArmPkg.dec > > + MdePkg/MdePkg.dec > > + > > +[LibraryClasses] > > + BaseLib > > + DebugLib > > + IoLib > > + PcdLib > > + > > +[Pcd] > > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES > > + > > +[FixedPcd] > > + gArmTokenSpaceGuid.PcdPciBusMin > > + gArmTokenSpaceGuid.PcdPciBusMax > > diff --git > > a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > > > > b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > > new file mode 100644 > > index 000..e88cc7b > > --- /dev/null > > +++ > > b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > > @@ -0,0 +1,1531 @@ > > +/** @file > > + > > + Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved. > > + Copyright (c) 2017, Linaro, Ltd. All rights reserved. > > + Copyright (c) 2019, Marvell International Ltd. All rights reserved. > > + > > + This program and the accompanying materials > > + are licensed and made available under the terms and conditions of the > > BSD License > > + which accompanies this distribution. The full text of the license may > > be found at > > + http://opensource.org/licenses/bsd-license.php. > > + > > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > > IMPLIED. > > + > > +**/ > > + > > + > > +#include > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/** > > + Assert the validity of a PCI address. A valid PCI address should contain > > 1's > > + only in the low 28 bits. > > + > > + @param A The address to validate. > > + > > +**/ > > +#define
Re: [edk2-devel] [edk2-platforms: PATCH v2 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation
On Mon, 20 May 2019 at 17:27, Marcin Wojtas wrote: > > From: Ard Biesheuvel > > Implement a special version of PciExpressLib that takes the quirky > nature of the Synopsys Designware PCIe IP into account. In particular, > we need to ignore config space accesses to all devices on the first > bus except device 0, because the broadcast nature of type 0 configuration > cycles will result in whatever device is in the slot to appear at each > of the 32 device positions. > I never bothered to implement multisegment support for this SoC, since MacchiatoBin has only one segment wired up, but since your interest is in generic support, it might make sense to drop this patch and implement PciSegmentLib instead (without depending on any of the other library classes that the generic PciExpressLib depends on) > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > | 42 + > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > | 1531 > 2 files changed, 1573 insertions(+) > create mode 100644 > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > create mode 100644 > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > > diff --git > a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > > b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > new file mode 100644 > index 000..a66ef28 > --- /dev/null > +++ > b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > @@ -0,0 +1,42 @@ > +## @file > +# > +# Copyright (c) 2017, Linaro, Ltd. All rights reserved. > +# Copyright (c) 2019, Marvell International Ltd. All rights reserved. > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD > License > +# which accompanies this distribution. The full text of the license may be > found at > +# http://opensource.org/licenses/bsd-license.php. > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > IMPLIED. > +# > +# > +## > + > +[Defines] > + INF_VERSION= 0x0001001B > + BASE_NAME = Armada7k8kPciExpressLib > + FILE_GUID = f0926204-3061-40ed-8261-2aeccc7914c9 > + MODULE_TYPE= BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = PciExpressLib > + > +[Sources] > + PciExpressLib.c > + > +[Packages] > + ArmPkg/ArmPkg.dec > + MdePkg/MdePkg.dec > + > +[LibraryClasses] > + BaseLib > + DebugLib > + IoLib > + PcdLib > + > +[Pcd] > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdPciBusMin > + gArmTokenSpaceGuid.PcdPciBusMax > diff --git > a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > new file mode 100644 > index 000..e88cc7b > --- /dev/null > +++ > b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > @@ -0,0 +1,1531 @@ > +/** @file > + > + Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved. > + Copyright (c) 2017, Linaro, Ltd. All rights reserved. > + Copyright (c) 2019, Marvell International Ltd. All rights reserved. > + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD > License > + which accompanies this distribution. The full text of the license may be > found at > + http://opensource.org/licenses/bsd-license.php. > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > IMPLIED. > + > +**/ > + > + > +#include > + > +#include > +#include > +#include > +#include > +#include > + > +/** > + Assert the validity of a PCI address. A valid PCI address should contain > 1's > + only in the low 28 bits. > + > + @param A The address to validate. > + > +**/ > +#define ASSERT_INVALID_PCI_ADDRESS(A) \ > + ASSERT (((A) & ~0xfff) == 0) > + > +/** > + Registers a PCI device so PCI configuration registers may be accessed after > + SetVirtualAddressMap(). > + > + Registers the PCI device specified by Address so all the PCI configuration > + registers associated with that PCI device may be accessed after > SetVirtualAddressMap() > + is called. > + > + If Address > 0x0FFF, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + > + @retval RETURN_SUCCESS The PCI device was registered for runtime > access. > + @retval
[edk2-devel] [edk2-platforms: PATCH v2 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation
From: Ard Biesheuvel
Implement a special version of PciExpressLib that takes the quirky
nature of the Synopsys Designware PCIe IP into account. In particular,
we need to ignore config space accesses to all devices on the first
bus except device 0, because the broadcast nature of type 0 configuration
cycles will result in whatever device is in the slot to appear at each
of the 32 device positions.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas
---
Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf |
42 +
Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c |
1531
2 files changed, 1573 insertions(+)
create mode 100644
Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf
create mode 100644
Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c
diff --git
a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf
b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf
new file mode 100644
index 000..a66ef28
--- /dev/null
+++
b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf
@@ -0,0 +1,42 @@
+## @file
+#
+# Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD
License
+# which accompanies this distribution. The full text of the license may be
found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION= 0x0001001B
+ BASE_NAME = Armada7k8kPciExpressLib
+ FILE_GUID = f0926204-3061-40ed-8261-2aeccc7914c9
+ MODULE_TYPE= BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciExpressLib
+
+[Sources]
+ PciExpressLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
diff --git
a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c
b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c
new file mode 100644
index 000..e88cc7b
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c
@@ -0,0 +1,1531 @@
+/** @file
+
+ Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Assert the validity of a PCI address. A valid PCI address should contain 1's
+ only in the low 28 bits.
+
+ @param A The address to validate.
+
+**/
+#define ASSERT_INVALID_PCI_ADDRESS(A) \
+ ASSERT (((A) & ~0xfff) == 0)
+
+/**
+ Registers a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ Registers the PCI device specified by Address so all the PCI configuration
+ registers associated with that PCI device may be accessed after
SetVirtualAddressMap()
+ is called.
+
+ If Address > 0x0FFF, then ASSERT().
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime
access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI
device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciExpressRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return RETURN_UNSUPPORTED;
+}
+
+#define ECAM_BUS_SIZE SIZE_1MB
+#define ECAM_DEV_SIZE SIZE_32KB
+
+STATIC
+BOOLEAN
